1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
9 #include <rte_string_fns.h>
11 #include "qede_ethdev.h"
12 /* ######### DEBUG ###########*/
13 #include "qede_debug.h"
16 #define QEDE_ALARM_TIMEOUT_US 100000
18 /* Global variable to hold absolute path of fw file */
19 char qede_fw_file[PATH_MAX];
21 static const char * const QEDE_DEFAULT_FIRMWARE =
22 "/lib/firmware/qed/qed_init_values-8.40.33.0.bin";
25 qed_update_pf_params(struct ecore_dev *edev, struct ecore_pf_params *params)
29 for (i = 0; i < edev->num_hwfns; i++) {
30 struct ecore_hwfn *p_hwfn = &edev->hwfns[i];
31 p_hwfn->pf_params = *params;
35 static void qed_init_pci(struct ecore_dev *edev, struct rte_pci_device *pci_dev)
37 edev->regview = pci_dev->mem_resource[0].addr;
38 edev->doorbells = pci_dev->mem_resource[2].addr;
39 edev->db_size = pci_dev->mem_resource[2].len;
40 edev->pci_dev = pci_dev;
44 qed_probe(struct ecore_dev *edev, struct rte_pci_device *pci_dev,
45 uint32_t dp_module, uint8_t dp_level, bool is_vf)
47 struct ecore_hw_prepare_params hw_prepare_params;
50 ecore_init_struct(edev);
51 edev->drv_type = DRV_ID_DRV_TYPE_LINUX;
52 /* Protocol type is always fixed to PROTOCOL_ETH */
57 ecore_init_dp(edev, dp_module, dp_level, NULL);
58 qed_init_pci(edev, pci_dev);
60 memset(&hw_prepare_params, 0, sizeof(hw_prepare_params));
63 hw_prepare_params.acquire_retry_cnt = ECORE_VF_ACQUIRE_THRESH;
65 hw_prepare_params.personality = ECORE_PCI_ETH;
66 hw_prepare_params.drv_resc_alloc = false;
67 hw_prepare_params.chk_reg_fifo = false;
68 hw_prepare_params.initiate_pf_flr = true;
69 hw_prepare_params.allow_mdump = false;
70 hw_prepare_params.b_en_pacing = false;
71 hw_prepare_params.epoch = OSAL_GET_EPOCH(ECORE_LEADING_HWFN(edev));
72 rc = ecore_hw_prepare(edev, &hw_prepare_params);
74 DP_ERR(edev, "hw prepare failed\n");
81 static int qed_nic_setup(struct ecore_dev *edev)
85 rc = ecore_resc_alloc(edev);
89 DP_INFO(edev, "Allocated qed resources\n");
90 ecore_resc_setup(edev);
95 #ifdef CONFIG_ECORE_ZIPPED_FW
96 static int qed_alloc_stream_mem(struct ecore_dev *edev)
100 for_each_hwfn(edev, i) {
101 struct ecore_hwfn *p_hwfn = &edev->hwfns[i];
103 p_hwfn->stream = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
104 sizeof(*p_hwfn->stream));
112 static void qed_free_stream_mem(struct ecore_dev *edev)
116 for_each_hwfn(edev, i) {
117 struct ecore_hwfn *p_hwfn = &edev->hwfns[i];
122 OSAL_FREE(p_hwfn->p_dev, p_hwfn->stream);
127 #ifdef CONFIG_ECORE_BINARY_FW
128 static int qed_load_firmware_data(struct ecore_dev *edev)
132 const char *fw = RTE_LIBRTE_QEDE_FW;
134 if (strcmp(fw, "") == 0)
135 strcpy(qede_fw_file, QEDE_DEFAULT_FIRMWARE);
137 strcpy(qede_fw_file, fw);
139 fd = open(qede_fw_file, O_RDONLY);
141 DP_ERR(edev, "Can't open firmware file\n");
145 if (fstat(fd, &st) < 0) {
146 DP_ERR(edev, "Can't stat firmware file\n");
151 edev->firmware = rte_zmalloc("qede_fw", st.st_size,
152 RTE_CACHE_LINE_SIZE);
153 if (!edev->firmware) {
154 DP_ERR(edev, "Can't allocate memory for firmware\n");
159 if (read(fd, edev->firmware, st.st_size) != st.st_size) {
160 DP_ERR(edev, "Can't read firmware data\n");
165 edev->fw_len = st.st_size;
166 if (edev->fw_len < 104) {
167 DP_ERR(edev, "Invalid fw size: %" PRIu64 "\n",
178 static void qed_handle_bulletin_change(struct ecore_hwfn *hwfn)
180 uint8_t mac[ETH_ALEN], is_mac_exist, is_mac_forced;
182 is_mac_exist = ecore_vf_bulletin_get_forced_mac(hwfn, mac,
184 if (is_mac_exist && is_mac_forced)
185 rte_memcpy(hwfn->hw_info.hw_mac_addr, mac, ETH_ALEN);
187 /* Always update link configuration according to bulletin */
188 qed_link_update(hwfn);
191 static void qede_vf_task(void *arg)
193 struct ecore_hwfn *p_hwfn = arg;
196 /* Read the bulletin board, and re-schedule the task */
197 ecore_vf_read_bulletin(p_hwfn, &change);
199 qed_handle_bulletin_change(p_hwfn);
201 rte_eal_alarm_set(QEDE_ALARM_TIMEOUT_US, qede_vf_task, p_hwfn);
204 static void qed_start_iov_task(struct ecore_dev *edev)
206 struct ecore_hwfn *p_hwfn;
209 for_each_hwfn(edev, i) {
210 p_hwfn = &edev->hwfns[i];
212 rte_eal_alarm_set(QEDE_ALARM_TIMEOUT_US, qede_vf_task,
217 static void qed_stop_iov_task(struct ecore_dev *edev)
219 struct ecore_hwfn *p_hwfn;
222 for_each_hwfn(edev, i) {
223 p_hwfn = &edev->hwfns[i];
225 rte_eal_alarm_cancel(qede_vf_task, p_hwfn);
228 static int qed_slowpath_start(struct ecore_dev *edev,
229 struct qed_slowpath_params *params)
231 struct ecore_drv_load_params drv_load_params;
232 struct ecore_hw_init_params hw_init_params;
233 struct ecore_mcp_drv_version drv_version;
234 const uint8_t *data = NULL;
235 struct ecore_hwfn *hwfn;
236 struct ecore_ptt *p_ptt;
240 #ifdef CONFIG_ECORE_BINARY_FW
241 rc = qed_load_firmware_data(edev);
243 DP_ERR(edev, "Failed to find fw file %s\n",
248 hwfn = ECORE_LEADING_HWFN(edev);
249 if (edev->num_hwfns == 1) { /* skip aRFS for 100G device */
250 p_ptt = ecore_ptt_acquire(hwfn);
252 ECORE_LEADING_HWFN(edev)->p_arfs_ptt = p_ptt;
254 DP_ERR(edev, "Failed to acquire PTT for flowdir\n");
261 rc = qed_nic_setup(edev);
265 /* set int_coalescing_mode */
266 edev->int_coalescing_mode = ECORE_COAL_MODE_ENABLE;
268 #ifdef CONFIG_ECORE_ZIPPED_FW
270 /* Allocate stream for unzipping */
271 rc = qed_alloc_stream_mem(edev);
273 DP_ERR(edev, "Failed to allocate stream memory\n");
279 qed_start_iov_task(edev);
281 #ifdef CONFIG_ECORE_BINARY_FW
283 data = (const uint8_t *)edev->firmware + sizeof(u32);
285 /* ############### DEBUG ################## */
286 qed_dbg_pf_init(edev);
291 /* Start the slowpath */
292 memset(&hw_init_params, 0, sizeof(hw_init_params));
293 hw_init_params.b_hw_start = true;
294 hw_init_params.int_mode = params->int_mode;
295 hw_init_params.allow_npar_tx_switch = true;
296 hw_init_params.bin_fw_data = data;
298 memset(&drv_load_params, 0, sizeof(drv_load_params));
299 drv_load_params.mfw_timeout_val = ECORE_LOAD_REQ_LOCK_TO_DEFAULT;
300 drv_load_params.avoid_eng_reset = false;
301 drv_load_params.override_force_load = ECORE_OVERRIDE_FORCE_LOAD_ALWAYS;
302 hw_init_params.avoid_eng_affin = false;
303 hw_init_params.p_drv_load_params = &drv_load_params;
305 rc = ecore_hw_init(edev, &hw_init_params);
307 DP_ERR(edev, "ecore_hw_init failed\n");
311 DP_INFO(edev, "HW inited and function started\n");
314 hwfn = ECORE_LEADING_HWFN(edev);
315 drv_version.version = (params->drv_major << 24) |
316 (params->drv_minor << 16) |
317 (params->drv_rev << 8) | (params->drv_eng);
318 strlcpy((char *)drv_version.name, (const char *)params->name,
319 sizeof(drv_version.name));
320 rc = ecore_mcp_send_drv_version(hwfn, hwfn->p_main_ptt,
323 DP_ERR(edev, "Failed sending drv version command\n");
328 ecore_reset_vport_stats(edev);
335 qed_stop_iov_task(edev);
336 #ifdef CONFIG_ECORE_ZIPPED_FW
337 qed_free_stream_mem(edev);
340 ecore_resc_free(edev);
342 #ifdef CONFIG_ECORE_BINARY_FW
345 rte_free(edev->firmware);
346 edev->firmware = NULL;
349 qed_stop_iov_task(edev);
355 qed_fill_dev_info(struct ecore_dev *edev, struct qed_dev_info *dev_info)
357 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(edev);
358 struct ecore_ptt *ptt = NULL;
359 struct ecore_tunnel_info *tun = &edev->tunnel;
361 memset(dev_info, 0, sizeof(struct qed_dev_info));
363 if (tun->vxlan.tun_cls == ECORE_TUNN_CLSS_MAC_VLAN &&
364 tun->vxlan.b_mode_enabled)
365 dev_info->vxlan_enable = true;
367 if (tun->l2_gre.b_mode_enabled && tun->ip_gre.b_mode_enabled &&
368 tun->l2_gre.tun_cls == ECORE_TUNN_CLSS_MAC_VLAN &&
369 tun->ip_gre.tun_cls == ECORE_TUNN_CLSS_MAC_VLAN)
370 dev_info->gre_enable = true;
372 if (tun->l2_geneve.b_mode_enabled && tun->ip_geneve.b_mode_enabled &&
373 tun->l2_geneve.tun_cls == ECORE_TUNN_CLSS_MAC_VLAN &&
374 tun->ip_geneve.tun_cls == ECORE_TUNN_CLSS_MAC_VLAN)
375 dev_info->geneve_enable = true;
377 dev_info->num_hwfns = edev->num_hwfns;
378 dev_info->is_mf_default = IS_MF_DEFAULT(&edev->hwfns[0]);
379 dev_info->mtu = ECORE_LEADING_HWFN(edev)->hw_info.mtu;
380 dev_info->dev_type = edev->type;
382 rte_memcpy(&dev_info->hw_mac, &edev->hwfns[0].hw_info.hw_mac_addr,
385 dev_info->fw_major = FW_MAJOR_VERSION;
386 dev_info->fw_minor = FW_MINOR_VERSION;
387 dev_info->fw_rev = FW_REVISION_VERSION;
388 dev_info->fw_eng = FW_ENGINEERING_VERSION;
391 dev_info->b_inter_pf_switch =
392 OSAL_GET_BIT(ECORE_MF_INTER_PF_SWITCH, &edev->mf_bits);
393 if (!OSAL_GET_BIT(ECORE_MF_DISABLE_ARFS, &edev->mf_bits))
394 dev_info->b_arfs_capable = true;
395 dev_info->tx_switching = false;
397 dev_info->smart_an = ecore_mcp_is_smart_an_supported(p_hwfn);
399 ptt = ecore_ptt_acquire(ECORE_LEADING_HWFN(edev));
401 ecore_mcp_get_mfw_ver(ECORE_LEADING_HWFN(edev), ptt,
402 &dev_info->mfw_rev, NULL);
404 ecore_mcp_get_mbi_ver(ECORE_LEADING_HWFN(edev), ptt,
405 &dev_info->mbi_version);
407 ecore_mcp_get_flash_size(ECORE_LEADING_HWFN(edev), ptt,
408 &dev_info->flash_size);
410 /* Workaround to allow PHY-read commands for
413 if (ECORE_IS_BB_B0(edev))
414 dev_info->flash_size = 0xffffffff;
416 ecore_ptt_release(ECORE_LEADING_HWFN(edev), ptt);
419 ecore_mcp_get_mfw_ver(ECORE_LEADING_HWFN(edev), ptt,
420 &dev_info->mfw_rev, NULL);
427 qed_fill_eth_dev_info(struct ecore_dev *edev, struct qed_dev_eth_info *info)
432 memset(info, 0, sizeof(*info));
434 info->num_tc = 1 /* @@@TBD aelior MULTI_COS */;
437 int max_vf_vlan_filters = 0;
439 info->num_queues = 0;
440 for_each_hwfn(edev, i)
442 FEAT_NUM(&edev->hwfns[i], ECORE_PF_L2_QUE);
444 if (IS_ECORE_SRIOV(edev))
445 max_vf_vlan_filters = edev->p_iov_info->total_vfs *
446 ECORE_ETH_VF_NUM_VLAN_FILTERS;
447 info->num_vlan_filters = RESC_NUM(&edev->hwfns[0], ECORE_VLAN) -
450 rte_memcpy(&info->port_mac, &edev->hwfns[0].hw_info.hw_mac_addr,
453 ecore_vf_get_num_rxqs(ECORE_LEADING_HWFN(edev),
455 if (ECORE_IS_CMT(edev)) {
456 ecore_vf_get_num_rxqs(&edev->hwfns[1], &queues);
457 info->num_queues += queues;
460 ecore_vf_get_num_vlan_filters(&edev->hwfns[0],
461 (u8 *)&info->num_vlan_filters);
463 ecore_vf_get_port_mac(&edev->hwfns[0],
464 (uint8_t *)&info->port_mac);
466 info->is_legacy = ecore_vf_get_pre_fp_hsi(&edev->hwfns[0]);
469 qed_fill_dev_info(edev, &info->common);
472 memset(&info->common.hw_mac, 0, RTE_ETHER_ADDR_LEN);
477 static void qed_set_name(struct ecore_dev *edev, char name[NAME_SIZE])
481 rte_memcpy(edev->name, name, NAME_SIZE);
482 for_each_hwfn(edev, i) {
483 snprintf(edev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i);
488 qed_sb_init(struct ecore_dev *edev, struct ecore_sb_info *sb_info,
489 void *sb_virt_addr, dma_addr_t sb_phy_addr, uint16_t sb_id)
491 struct ecore_hwfn *p_hwfn;
494 uint8_t n_hwfns = edev->num_hwfns;
497 hwfn_index = sb_id % n_hwfns;
498 p_hwfn = &edev->hwfns[hwfn_index];
499 rel_sb_id = sb_id / n_hwfns;
501 DP_INFO(edev, "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
502 hwfn_index, rel_sb_id, sb_id);
504 rc = ecore_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info,
505 sb_virt_addr, sb_phy_addr, rel_sb_id);
510 static void qed_fill_link(struct ecore_hwfn *hwfn,
511 __rte_unused struct ecore_ptt *ptt,
512 struct qed_link_output *if_link)
514 struct ecore_mcp_link_params params;
515 struct ecore_mcp_link_state link;
516 struct ecore_mcp_link_capabilities link_caps;
519 memset(if_link, 0, sizeof(*if_link));
521 /* Prepare source inputs */
522 if (IS_PF(hwfn->p_dev)) {
523 rte_memcpy(¶ms, ecore_mcp_get_link_params(hwfn),
525 rte_memcpy(&link, ecore_mcp_get_link_state(hwfn), sizeof(link));
526 rte_memcpy(&link_caps, ecore_mcp_get_link_capabilities(hwfn),
529 ecore_vf_read_bulletin(hwfn, &change);
530 ecore_vf_get_link_params(hwfn, ¶ms);
531 ecore_vf_get_link_state(hwfn, &link);
532 ecore_vf_get_link_caps(hwfn, &link_caps);
535 /* Set the link parameters to pass to protocol driver */
537 if_link->link_up = true;
540 if_link->speed = link.speed;
542 if_link->duplex = QEDE_DUPLEX_FULL;
544 /* Fill up the native advertised speed cap mask */
545 if_link->adv_speed = params.speed.advertised_speeds;
547 if (params.speed.autoneg)
548 if_link->supported_caps |= QEDE_SUPPORTED_AUTONEG;
550 if (params.pause.autoneg || params.pause.forced_rx ||
551 params.pause.forced_tx)
552 if_link->supported_caps |= QEDE_SUPPORTED_PAUSE;
554 if (params.pause.autoneg)
555 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
557 if (params.pause.forced_rx)
558 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE;
560 if (params.pause.forced_tx)
561 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE;
563 if (link_caps.default_eee == ECORE_MCP_EEE_UNSUPPORTED) {
564 if_link->eee_supported = false;
566 if_link->eee_supported = true;
567 if_link->eee_active = link.eee_active;
568 if_link->sup_caps = link_caps.eee_speed_caps;
569 /* MFW clears adv_caps on eee disable; use configured value */
570 if_link->eee.adv_caps = link.eee_adv_caps ? link.eee_adv_caps :
572 if_link->eee.lp_adv_caps = link.eee_lp_adv_caps;
573 if_link->eee.enable = params.eee.enable;
574 if_link->eee.tx_lpi_enable = params.eee.tx_lpi_enable;
575 if_link->eee.tx_lpi_timer = params.eee.tx_lpi_timer;
580 qed_get_current_link(struct ecore_dev *edev, struct qed_link_output *if_link)
582 struct ecore_hwfn *hwfn;
583 struct ecore_ptt *ptt;
585 hwfn = &edev->hwfns[0];
587 ptt = ecore_ptt_acquire(hwfn);
589 DP_NOTICE(hwfn, true, "Failed to fill link; No PTT\n");
591 qed_fill_link(hwfn, ptt, if_link);
594 ecore_ptt_release(hwfn, ptt);
596 qed_fill_link(hwfn, NULL, if_link);
600 static int qed_set_link(struct ecore_dev *edev, struct qed_link_params *params)
602 struct ecore_hwfn *hwfn;
603 struct ecore_ptt *ptt;
604 struct ecore_mcp_link_params *link_params;
610 /* The link should be set only once per PF */
611 hwfn = &edev->hwfns[0];
613 ptt = ecore_ptt_acquire(hwfn);
617 link_params = ecore_mcp_get_link_params(hwfn);
618 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG)
619 link_params->speed.autoneg = params->autoneg;
621 if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) {
622 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
623 link_params->pause.autoneg = true;
625 link_params->pause.autoneg = false;
626 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE)
627 link_params->pause.forced_rx = true;
629 link_params->pause.forced_rx = false;
630 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE)
631 link_params->pause.forced_tx = true;
633 link_params->pause.forced_tx = false;
636 if (params->override_flags & QED_LINK_OVERRIDE_EEE_CONFIG)
637 memcpy(&link_params->eee, ¶ms->eee,
638 sizeof(link_params->eee));
640 rc = ecore_mcp_set_link(hwfn, ptt, params->link_up);
642 ecore_ptt_release(hwfn, ptt);
647 void qed_link_update(struct ecore_hwfn *hwfn)
649 struct ecore_dev *edev = hwfn->p_dev;
650 struct qede_dev *qdev = (struct qede_dev *)edev;
651 struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
653 if (!qede_link_update(dev, 0))
654 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
657 static int qed_drain(struct ecore_dev *edev)
659 struct ecore_hwfn *hwfn;
660 struct ecore_ptt *ptt;
666 for_each_hwfn(edev, i) {
667 hwfn = &edev->hwfns[i];
668 ptt = ecore_ptt_acquire(hwfn);
670 DP_ERR(hwfn, "Failed to drain NIG; No PTT\n");
673 rc = ecore_mcp_drain(hwfn, ptt);
676 ecore_ptt_release(hwfn, ptt);
682 static int qed_nic_stop(struct ecore_dev *edev)
686 rc = ecore_hw_stop(edev);
687 for (i = 0; i < edev->num_hwfns; i++) {
688 struct ecore_hwfn *p_hwfn = &edev->hwfns[i];
690 if (p_hwfn->b_sp_dpc_enabled)
691 p_hwfn->b_sp_dpc_enabled = false;
696 static int qed_slowpath_stop(struct ecore_dev *edev)
698 #ifdef CONFIG_QED_SRIOV
706 #ifdef CONFIG_ECORE_ZIPPED_FW
707 qed_free_stream_mem(edev);
710 #ifdef CONFIG_QED_SRIOV
711 if (IS_QED_ETH_IF(edev))
712 qed_sriov_disable(edev, true);
718 ecore_resc_free(edev);
719 qed_stop_iov_task(edev);
724 static void qed_remove(struct ecore_dev *edev)
729 ecore_hw_remove(edev);
732 static int qed_send_drv_state(struct ecore_dev *edev, bool active)
734 struct ecore_hwfn *hwfn = ECORE_LEADING_HWFN(edev);
735 struct ecore_ptt *ptt;
738 ptt = ecore_ptt_acquire(hwfn);
742 status = ecore_mcp_ov_update_driver_state(hwfn, ptt, active ?
743 ECORE_OV_DRIVER_STATE_ACTIVE :
744 ECORE_OV_DRIVER_STATE_DISABLED);
746 ecore_ptt_release(hwfn, ptt);
751 static int qed_get_sb_info(struct ecore_dev *edev, struct ecore_sb_info *sb,
752 u16 qid, struct ecore_sb_info_dbg *sb_dbg)
754 struct ecore_hwfn *hwfn = &edev->hwfns[qid % edev->num_hwfns];
755 struct ecore_ptt *ptt;
761 ptt = ecore_ptt_acquire(hwfn);
763 DP_ERR(hwfn, "Can't acquire PTT\n");
767 memset(sb_dbg, 0, sizeof(*sb_dbg));
768 rc = ecore_int_get_sb_dbg(hwfn, ptt, sb, sb_dbg);
770 ecore_ptt_release(hwfn, ptt);
774 const struct qed_common_ops qed_common_ops_pass = {
775 INIT_STRUCT_FIELD(probe, &qed_probe),
776 INIT_STRUCT_FIELD(update_pf_params, &qed_update_pf_params),
777 INIT_STRUCT_FIELD(slowpath_start, &qed_slowpath_start),
778 INIT_STRUCT_FIELD(set_name, &qed_set_name),
779 INIT_STRUCT_FIELD(chain_alloc, &ecore_chain_alloc),
780 INIT_STRUCT_FIELD(chain_free, &ecore_chain_free),
781 INIT_STRUCT_FIELD(sb_init, &qed_sb_init),
782 INIT_STRUCT_FIELD(get_sb_info, &qed_get_sb_info),
783 INIT_STRUCT_FIELD(get_link, &qed_get_current_link),
784 INIT_STRUCT_FIELD(set_link, &qed_set_link),
785 INIT_STRUCT_FIELD(drain, &qed_drain),
786 INIT_STRUCT_FIELD(slowpath_stop, &qed_slowpath_stop),
787 INIT_STRUCT_FIELD(remove, &qed_remove),
788 INIT_STRUCT_FIELD(send_drv_state, &qed_send_drv_state),
789 /* ############### DEBUG ####################*/
791 INIT_STRUCT_FIELD(dbg_get_debug_engine, &qed_get_debug_engine),
792 INIT_STRUCT_FIELD(dbg_set_debug_engine, &qed_set_debug_engine),
794 INIT_STRUCT_FIELD(dbg_protection_override,
795 &qed_dbg_protection_override),
796 INIT_STRUCT_FIELD(dbg_protection_override_size,
797 &qed_dbg_protection_override_size),
799 INIT_STRUCT_FIELD(dbg_grc, &qed_dbg_grc),
800 INIT_STRUCT_FIELD(dbg_grc_size, &qed_dbg_grc_size),
802 INIT_STRUCT_FIELD(dbg_idle_chk, &qed_dbg_idle_chk),
803 INIT_STRUCT_FIELD(dbg_idle_chk_size, &qed_dbg_idle_chk_size),
805 INIT_STRUCT_FIELD(dbg_mcp_trace, &qed_dbg_mcp_trace),
806 INIT_STRUCT_FIELD(dbg_mcp_trace_size, &qed_dbg_mcp_trace_size),
808 INIT_STRUCT_FIELD(dbg_fw_asserts, &qed_dbg_fw_asserts),
809 INIT_STRUCT_FIELD(dbg_fw_asserts_size, &qed_dbg_fw_asserts_size),
811 INIT_STRUCT_FIELD(dbg_ilt, &qed_dbg_ilt),
812 INIT_STRUCT_FIELD(dbg_ilt_size, &qed_dbg_ilt_size),
814 INIT_STRUCT_FIELD(dbg_reg_fifo_size, &qed_dbg_reg_fifo_size),
815 INIT_STRUCT_FIELD(dbg_reg_fifo, &qed_dbg_reg_fifo),
817 INIT_STRUCT_FIELD(dbg_igu_fifo_size, &qed_dbg_igu_fifo_size),
818 INIT_STRUCT_FIELD(dbg_igu_fifo, &qed_dbg_igu_fifo),
821 const struct qed_eth_ops qed_eth_ops_pass = {
822 INIT_STRUCT_FIELD(common, &qed_common_ops_pass),
823 INIT_STRUCT_FIELD(fill_dev_info, &qed_fill_eth_dev_info),
826 const struct qed_eth_ops *qed_get_eth_ops(void)
828 return &qed_eth_ops_pass;