drivers/net/qede/qede_rxtx.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_rxtx.h"
  10
  11 static bool gro_disable = 1;    /* mod_param */
  12
  13 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
  14 {
  15         struct rte_mbuf *new_mb = NULL;
  16         struct eth_rx_bd *rx_bd;
  17         dma_addr_t mapping;
  18         uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
  19
  20         new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
  21         if (unlikely(!new_mb)) {
  22                 PMD_RX_LOG(ERR, rxq,
  23                            "Failed to allocate rx buffer "
  24                            "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
  25                            idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
  26                            rte_mempool_avail_count(rxq->mb_pool),
  27                            rte_mempool_in_use_count(rxq->mb_pool));
  28                 return -ENOMEM;
  29         }
  30         rxq->sw_rx_ring[idx].mbuf = new_mb;
  31         rxq->sw_rx_ring[idx].page_offset = 0;
  32         mapping = rte_mbuf_data_dma_addr_default(new_mb);
  33         /* Advance PROD and get BD pointer */
  34         rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
  35         rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
  36         rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
  37         rxq->sw_rx_prod++;
  38         return 0;
  39 }
  40
  41 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
  42 {
  43         uint16_t i;
  44
  45         if (rxq->sw_rx_ring != NULL) {
  46                 for (i = 0; i < rxq->nb_rx_desc; i++) {
  47                         if (rxq->sw_rx_ring[i].mbuf != NULL) {
  48                                 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
  49                                 rxq->sw_rx_ring[i].mbuf = NULL;
  50                         }
  51                 }
  52         }
  53 }
  54
  55 void qede_rx_queue_release(void *rx_queue)
  56 {
  57         struct qede_rx_queue *rxq = rx_queue;
  58
  59         if (rxq != NULL) {
  60                 qede_rx_queue_release_mbufs(rxq);
  61                 rte_free(rxq->sw_rx_ring);
  62                 rxq->sw_rx_ring = NULL;
  63                 rte_free(rxq);
  64                 rxq = NULL;
  65         }
  66 }
  67
  68 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
  69 {
  70         unsigned int i;
  71
  72         PMD_TX_LOG(DEBUG, txq, "releasing %u mbufs", txq->nb_tx_desc);
  73
  74         if (txq->sw_tx_ring) {
  75                 for (i = 0; i < txq->nb_tx_desc; i++) {
  76                         if (txq->sw_tx_ring[i].mbuf) {
  77                                 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf);
  78                                 txq->sw_tx_ring[i].mbuf = NULL;
  79                         }
  80                 }
  81         }
  82 }
  83
  84 int
  85 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  86                     uint16_t nb_desc, unsigned int socket_id,
  87                     const struct rte_eth_rxconf *rx_conf,
  88                     struct rte_mempool *mp)
  89 {
  90         struct qede_dev *qdev = dev->data->dev_private;
  91         struct ecore_dev *edev = &qdev->edev;
  92         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  93         struct qede_rx_queue *rxq;
  94         uint16_t max_rx_pkt_len;
  95         uint16_t bufsz;
  96         size_t size;
  97         int rc;
  98         int i;
  99
 100         PMD_INIT_FUNC_TRACE(edev);
 101
 102         /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
 103         if (!rte_is_power_of_2(nb_desc)) {
 104                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 105                           nb_desc);
 106                 return -EINVAL;
 107         }
 108
 109         /* Free memory prior to re-allocation if needed... */
 110         if (dev->data->rx_queues[queue_idx] != NULL) {
 111                 qede_rx_queue_release(dev->data->rx_queues[queue_idx]);
 112                 dev->data->rx_queues[queue_idx] = NULL;
 113         }
 114
 115         /* First allocate the rx queue data structure */
 116         rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
 117                                  RTE_CACHE_LINE_SIZE, socket_id);
 118
 119         if (!rxq) {
 120                 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
 121                           socket_id);
 122                 return -ENOMEM;
 123         }
 124
 125         rxq->qdev = qdev;
 126         rxq->mb_pool = mp;
 127         rxq->nb_rx_desc = nb_desc;
 128         rxq->queue_id = queue_idx;
 129         rxq->port_id = dev->data->port_id;
 130         max_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len;
 131         qdev->mtu = max_rx_pkt_len;
 132
 133         /* Fix up RX buffer size */
 134         bufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 135         if ((rxmode->enable_scatter)                    ||
 136             (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {
 137                 if (!dev->data->scattered_rx) {
 138                         DP_INFO(edev, "Forcing scatter-gather mode\n");
 139                         dev->data->scattered_rx = 1;
 140                 }
 141         }
 142         if (dev->data->scattered_rx)
 143                 rxq->rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
 144         else
 145                 rxq->rx_buf_size = qdev->mtu + QEDE_ETH_OVERHEAD;
 146         /* Align to cache-line size if needed */
 147         rxq->rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rxq->rx_buf_size);
 148
 149         DP_INFO(edev, "mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\n",
 150                 qdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);
 151
 152         /* Allocate the parallel driver ring for Rx buffers */
 153         size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
 154         rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
 155                                              RTE_CACHE_LINE_SIZE, socket_id);
 156         if (!rxq->sw_rx_ring) {
 157                 DP_NOTICE(edev, false,
 158                           "Unable to alloc memory for sw_rx_ring on socket %u\n",
 159                           socket_id);
 160                 rte_free(rxq);
 161                 rxq = NULL;
 162                 return -ENOMEM;
 163         }
 164
 165         /* Allocate FW Rx ring  */
 166         rc = qdev->ops->common->chain_alloc(edev,
 167                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 168                                             ECORE_CHAIN_MODE_NEXT_PTR,
 169                                             ECORE_CHAIN_CNT_TYPE_U16,
 170                                             rxq->nb_rx_desc,
 171                                             sizeof(struct eth_rx_bd),
 172                                             &rxq->rx_bd_ring,
 173                                             NULL);
 174
 175         if (rc != ECORE_SUCCESS) {
 176                 DP_NOTICE(edev, false,
 177                           "Unable to alloc memory for rxbd ring on socket %u\n",
 178                           socket_id);
 179                 rte_free(rxq->sw_rx_ring);
 180                 rxq->sw_rx_ring = NULL;
 181                 rte_free(rxq);
 182                 rxq = NULL;
 183                 return -ENOMEM;
 184         }
 185
 186         /* Allocate FW completion ring */
 187         rc = qdev->ops->common->chain_alloc(edev,
 188                                             ECORE_CHAIN_USE_TO_CONSUME,
 189                                             ECORE_CHAIN_MODE_PBL,
 190                                             ECORE_CHAIN_CNT_TYPE_U16,
 191                                             rxq->nb_rx_desc,
 192                                             sizeof(union eth_rx_cqe),
 193                                             &rxq->rx_comp_ring,
 194                                             NULL);
 195
 196         if (rc != ECORE_SUCCESS) {
 197                 DP_NOTICE(edev, false,
 198                           "Unable to alloc memory for cqe ring on socket %u\n",
 199                           socket_id);
 200                 /* TBD: Freeing RX BD ring */
 201                 rte_free(rxq->sw_rx_ring);
 202                 rxq->sw_rx_ring = NULL;
 203                 rte_free(rxq);
 204                 return -ENOMEM;
 205         }
 206
 207         /* Allocate buffers for the Rx ring */
 208         for (i = 0; i < rxq->nb_rx_desc; i++) {
 209                 rc = qede_alloc_rx_buffer(rxq);
 210                 if (rc) {
 211                         DP_NOTICE(edev, false,
 212                                   "RX buffer allocation failed at idx=%d\n", i);
 213                         goto err4;
 214                 }
 215         }
 216
 217         dev->data->rx_queues[queue_idx] = rxq;
 218
 219         DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
 220                   queue_idx, nb_desc, qdev->mtu, socket_id);
 221
 222         return 0;
 223 err4:
 224         qede_rx_queue_release(rxq);
 225         return -ENOMEM;
 226 }
 227
 228 void qede_tx_queue_release(void *tx_queue)
 229 {
 230         struct qede_tx_queue *txq = tx_queue;
 231
 232         if (txq != NULL) {
 233                 qede_tx_queue_release_mbufs(txq);
 234                 if (txq->sw_tx_ring) {
 235                         rte_free(txq->sw_tx_ring);
 236                         txq->sw_tx_ring = NULL;
 237                 }
 238                 rte_free(txq);
 239         }
 240         txq = NULL;
 241 }
 242
 243 int
 244 qede_tx_queue_setup(struct rte_eth_dev *dev,
 245                     uint16_t queue_idx,
 246                     uint16_t nb_desc,
 247                     unsigned int socket_id,
 248                     const struct rte_eth_txconf *tx_conf)
 249 {
 250         struct qede_dev *qdev = dev->data->dev_private;
 251         struct ecore_dev *edev = &qdev->edev;
 252         struct qede_tx_queue *txq;
 253         int rc;
 254
 255         PMD_INIT_FUNC_TRACE(edev);
 256
 257         if (!rte_is_power_of_2(nb_desc)) {
 258                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 259                        nb_desc);
 260                 return -EINVAL;
 261         }
 262
 263         /* Free memory prior to re-allocation if needed... */
 264         if (dev->data->tx_queues[queue_idx] != NULL) {
 265                 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
 266                 dev->data->tx_queues[queue_idx] = NULL;
 267         }
 268
 269         txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
 270                                  RTE_CACHE_LINE_SIZE, socket_id);
 271
 272         if (txq == NULL) {
 273                 DP_ERR(edev,
 274                        "Unable to allocate memory for txq on socket %u",
 275                        socket_id);
 276                 return -ENOMEM;
 277         }
 278
 279         txq->nb_tx_desc = nb_desc;
 280         txq->qdev = qdev;
 281         txq->port_id = dev->data->port_id;
 282
 283         rc = qdev->ops->common->chain_alloc(edev,
 284                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 285                                             ECORE_CHAIN_MODE_PBL,
 286                                             ECORE_CHAIN_CNT_TYPE_U16,
 287                                             txq->nb_tx_desc,
 288                                             sizeof(union eth_tx_bd_types),
 289                                             &txq->tx_pbl,
 290                                             NULL);
 291         if (rc != ECORE_SUCCESS) {
 292                 DP_ERR(edev,
 293                        "Unable to allocate memory for txbd ring on socket %u",
 294                        socket_id);
 295                 qede_tx_queue_release(txq);
 296                 return -ENOMEM;
 297         }
 298
 299         /* Allocate software ring */
 300         txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
 301                                              (sizeof(struct qede_tx_entry) *
 302                                               txq->nb_tx_desc),
 303                                              RTE_CACHE_LINE_SIZE, socket_id);
 304
 305         if (!txq->sw_tx_ring) {
 306                 DP_ERR(edev,
 307                        "Unable to allocate memory for txbd ring on socket %u",
 308                        socket_id);
 309                 qede_tx_queue_release(txq);
 310                 return -ENOMEM;
 311         }
 312
 313         txq->queue_id = queue_idx;
 314
 315         txq->nb_tx_avail = txq->nb_tx_desc;
 316
 317         txq->tx_free_thresh =
 318             tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
 319             (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
 320
 321         dev->data->tx_queues[queue_idx] = txq;
 322
 323         DP_INFO(edev,
 324                   "txq %u num_desc %u tx_free_thresh %u socket %u\n",
 325                   queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
 326
 327         return 0;
 328 }
 329
 330 /* This function inits fp content and resets the SB, RXQ and TXQ arrays */
 331 static void qede_init_fp(struct qede_dev *qdev)
 332 {
 333         struct qede_fastpath *fp;
 334         uint8_t i, rss_id, tc;
 335         int fp_rx = qdev->fp_num_rx, rxq = 0, txq = 0;
 336
 337         memset((void *)qdev->fp_array, 0, (QEDE_QUEUE_CNT(qdev) *
 338                                            sizeof(*qdev->fp_array)));
 339         memset((void *)qdev->sb_array, 0, (QEDE_QUEUE_CNT(qdev) *
 340                                            sizeof(*qdev->sb_array)));
 341         for_each_queue(i) {
 342                 fp = &qdev->fp_array[i];
 343                 if (fp_rx) {
 344                         fp->type = QEDE_FASTPATH_RX;
 345                         fp_rx--;
 346                 } else{
 347                         fp->type = QEDE_FASTPATH_TX;
 348                 }
 349                 fp->qdev = qdev;
 350                 fp->id = i;
 351                 fp->sb_info = &qdev->sb_array[i];
 352                 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d", "qdev", i);
 353         }
 354
 355         qdev->gro_disable = gro_disable;
 356 }
 357
 358 void qede_free_fp_arrays(struct qede_dev *qdev)
 359 {
 360         /* It asseumes qede_free_mem_load() is called before */
 361         if (qdev->fp_array != NULL) {
 362                 rte_free(qdev->fp_array);
 363                 qdev->fp_array = NULL;
 364         }
 365
 366         if (qdev->sb_array != NULL) {
 367                 rte_free(qdev->sb_array);
 368                 qdev->sb_array = NULL;
 369         }
 370 }
 371
 372 int qede_alloc_fp_array(struct qede_dev *qdev)
 373 {
 374         struct qede_fastpath *fp;
 375         struct ecore_dev *edev = &qdev->edev;
 376         int i;
 377
 378         qdev->fp_array = rte_calloc("fp", QEDE_QUEUE_CNT(qdev),
 379                                     sizeof(*qdev->fp_array),
 380                                     RTE_CACHE_LINE_SIZE);
 381
 382         if (!qdev->fp_array) {
 383                 DP_ERR(edev, "fp array allocation failed\n");
 384                 return -ENOMEM;
 385         }
 386
 387         qdev->sb_array = rte_calloc("sb", QEDE_QUEUE_CNT(qdev),
 388                                     sizeof(*qdev->sb_array),
 389                                     RTE_CACHE_LINE_SIZE);
 390
 391         if (!qdev->sb_array) {
 392                 DP_ERR(edev, "sb array allocation failed\n");
 393                 rte_free(qdev->fp_array);
 394                 return -ENOMEM;
 395         }
 396
 397         return 0;
 398 }
 399
 400 /* This function allocates fast-path status block memory */
 401 static int
 402 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
 403                   uint16_t sb_id)
 404 {
 405         struct ecore_dev *edev = &qdev->edev;
 406         struct status_block *sb_virt;
 407         dma_addr_t sb_phys;
 408         int rc;
 409
 410         sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys, sizeof(*sb_virt));
 411
 412         if (!sb_virt) {
 413                 DP_ERR(edev, "Status block allocation failed\n");
 414                 return -ENOMEM;
 415         }
 416
 417         rc = qdev->ops->common->sb_init(edev, sb_info,
 418                                         sb_virt, sb_phys, sb_id,
 419                                         QED_SB_TYPE_L2_QUEUE);
 420         if (rc) {
 421                 DP_ERR(edev, "Status block initialization failed\n");
 422                 /* TBD: No dma_free_coherent possible */
 423                 return rc;
 424         }
 425
 426         return 0;
 427 }
 428
 429 int qede_alloc_fp_resc(struct qede_dev *qdev)
 430 {
 431         struct ecore_dev *edev = &qdev->edev;
 432         struct qede_fastpath *fp;
 433         uint32_t num_sbs;
 434         uint16_t i;
 435         uint16_t sb_idx;
 436         int rc;
 437
 438         if (IS_VF(edev))
 439                 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
 440         else
 441                 num_sbs = ecore_cxt_get_proto_cid_count
 442                           (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL);
 443
 444         if (num_sbs == 0) {
 445                 DP_ERR(edev, "No status blocks available\n");
 446                 return -EINVAL;
 447         }
 448
 449         if (qdev->fp_array)
 450                 qede_free_fp_arrays(qdev);
 451
 452         rc = qede_alloc_fp_array(qdev);
 453         if (rc != 0)
 454                 return rc;
 455
 456         qede_init_fp(qdev);
 457
 458         for (i = 0; i < QEDE_QUEUE_CNT(qdev); i++) {
 459                 fp = &qdev->fp_array[i];
 460                 if (IS_VF(edev))
 461                         sb_idx = i % num_sbs;
 462                 else
 463                         sb_idx = i;
 464                 if (qede_alloc_mem_sb(qdev, fp->sb_info, sb_idx)) {
 465                         qede_free_fp_arrays(qdev);
 466                         return -ENOMEM;
 467                 }
 468         }
 469
 470         return 0;
 471 }
 472
 473 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
 474 {
 475         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 476
 477         qede_free_mem_load(eth_dev);
 478         qede_free_fp_arrays(qdev);
 479 }
 480
 481 static inline void
 482 qede_update_rx_prod(struct qede_dev *edev, struct qede_rx_queue *rxq)
 483 {
 484         uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
 485         uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
 486         struct eth_rx_prod_data rx_prods = { 0 };
 487
 488         /* Update producers */
 489         rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
 490         rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
 491
 492         /* Make sure that the BD and SGE data is updated before updating the
 493          * producers since FW might read the BD/SGE right after the producer
 494          * is updated.
 495          */
 496         rte_wmb();
 497
 498         internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
 499                         (uint32_t *)&rx_prods);
 500
 501         /* mmiowb is needed to synchronize doorbell writes from more than one
 502          * processor. It guarantees that the write arrives to the device before
 503          * the napi lock is released and another qede_poll is called (possibly
 504          * on another CPU). Without this barrier, the next doorbell can bypass
 505          * this doorbell. This is applicable to IA64/Altix systems.
 506          */
 507         rte_wmb();
 508
 509         PMD_RX_LOG(DEBUG, rxq, "bd_prod %u  cqe_prod %u", bd_prod, cqe_prod);
 510 }
 511
 512 static int qede_start_queues(struct rte_eth_dev *eth_dev, bool clear_stats)
 513 {
 514         struct qede_dev *qdev = eth_dev->data->dev_private;
 515         struct ecore_dev *edev = &qdev->edev;
 516         struct ecore_queue_start_common_params q_params;
 517         struct qed_dev_info *qed_info = &qdev->dev_info.common;
 518         struct qed_update_vport_params vport_update_params;
 519         struct qede_tx_queue *txq;
 520         struct qede_fastpath *fp;
 521         dma_addr_t p_phys_table;
 522         int txq_index;
 523         uint16_t page_cnt;
 524         int vlan_removal_en = 1;
 525         int rc, tc, i;
 526
 527         for_each_queue(i) {
 528                 fp = &qdev->fp_array[i];
 529                 if (fp->type & QEDE_FASTPATH_RX) {
 530                         p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->
 531                                                                 rx_comp_ring);
 532                         page_cnt = ecore_chain_get_page_cnt(&fp->rxq->
 533                                                                 rx_comp_ring);
 534
 535                         memset(&q_params, 0, sizeof(q_params));
 536                         q_params.queue_id = i;
 537                         q_params.vport_id = 0;
 538                         q_params.sb = fp->sb_info->igu_sb_id;
 539                         q_params.sb_idx = RX_PI;
 540
 541                         ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
 542
 543                         rc = qdev->ops->q_rx_start(edev, i, &q_params,
 544                                            fp->rxq->rx_buf_size,
 545                                            fp->rxq->rx_bd_ring.p_phys_addr,
 546                                            p_phys_table,
 547                                            page_cnt,
 548                                            &fp->rxq->hw_rxq_prod_addr);
 549                         if (rc) {
 550                                 DP_ERR(edev, "Start rxq #%d failed %d\n",
 551                                        fp->rxq->queue_id, rc);
 552                                 return rc;
 553                         }
 554
 555                         fp->rxq->hw_cons_ptr =
 556                                         &fp->sb_info->sb_virt->pi_array[RX_PI];
 557
 558                         qede_update_rx_prod(qdev, fp->rxq);
 559                 }
 560
 561                 if (!(fp->type & QEDE_FASTPATH_TX))
 562                         continue;
 563                 for (tc = 0; tc < qdev->num_tc; tc++) {
 564                         txq = fp->txqs[tc];
 565                         txq_index = tc * QEDE_RSS_COUNT(qdev) + i;
 566
 567                         p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
 568                         page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
 569
 570                         memset(&q_params, 0, sizeof(q_params));
 571                         q_params.queue_id = txq->queue_id;
 572                         q_params.vport_id = 0;
 573                         q_params.sb = fp->sb_info->igu_sb_id;
 574                         q_params.sb_idx = TX_PI(tc);
 575
 576                         rc = qdev->ops->q_tx_start(edev, i, &q_params,
 577                                                    p_phys_table,
 578                                                    page_cnt, /* **pp_doorbell */
 579                                                    &txq->doorbell_addr);
 580                         if (rc) {
 581                                 DP_ERR(edev, "Start txq %u failed %d\n",
 582                                        txq_index, rc);
 583                                 return rc;
 584                         }
 585
 586                         txq->hw_cons_ptr =
 587                             &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
 588                         SET_FIELD(txq->tx_db.data.params,
 589                                   ETH_DB_DATA_DEST, DB_DEST_XCM);
 590                         SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
 591                                   DB_AGG_CMD_SET);
 592                         SET_FIELD(txq->tx_db.data.params,
 593                                   ETH_DB_DATA_AGG_VAL_SEL,
 594                                   DQ_XCM_ETH_TX_BD_PROD_CMD);
 595
 596                         txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
 597                 }
 598         }
 599
 600         /* Prepare and send the vport enable */
 601         memset(&vport_update_params, 0, sizeof(vport_update_params));
 602         /* Update MTU via vport update */
 603         vport_update_params.mtu = qdev->mtu;
 604         vport_update_params.vport_id = 0;
 605         vport_update_params.update_vport_active_flg = 1;
 606         vport_update_params.vport_active_flg = 1;
 607
 608         /* @DPDK */
 609         if (qed_info->mf_mode == MF_NPAR && qed_info->tx_switching) {
 610                 /* TBD: Check SRIOV enabled for VF */
 611                 vport_update_params.update_tx_switching_flg = 1;
 612                 vport_update_params.tx_switching_flg = 1;
 613         }
 614
 615         rc = qdev->ops->vport_update(edev, &vport_update_params);
 616         if (rc) {
 617                 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
 618                 return rc;
 619         }
 620
 621         return 0;
 622 }
 623
 624 static bool qede_tunn_exist(uint16_t flag)
 625 {
 626         return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
 627                     PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
 628 }
 629
 630 /*
 631  * qede_check_tunn_csum_l4:
 632  * Returns:
 633  * 1 : If L4 csum is enabled AND if the validation has failed.
 634  * 0 : Otherwise
 635  */
 636 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
 637 {
 638         if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
 639              PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
 640                 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
 641                         PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
 642
 643         return 0;
 644 }
 645
 646 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
 647 {
 648         if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
 649              PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
 650                 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
 651                            PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
 652
 653         return 0;
 654 }
 655
 656 static inline uint8_t
 657 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
 658 {
 659         struct ipv4_hdr *ip;
 660         uint16_t pkt_csum;
 661         uint16_t calc_csum;
 662         uint16_t val;
 663
 664         val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
 665                 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
 666
 667         if (unlikely(val)) {
 668                 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
 669                 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
 670                         ip = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
 671                                            sizeof(struct ether_hdr));
 672                         pkt_csum = ip->hdr_checksum;
 673                         ip->hdr_checksum = 0;
 674                         calc_csum = rte_ipv4_cksum(ip);
 675                         ip->hdr_checksum = pkt_csum;
 676                         return (calc_csum != pkt_csum);
 677                 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
 678                         return 1;
 679                 }
 680         }
 681         return 0;
 682 }
 683
 684 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
 685 {
 686         ecore_chain_consume(&rxq->rx_bd_ring);
 687         rxq->sw_rx_cons++;
 688 }
 689
 690 static inline void
 691 qede_reuse_page(struct qede_dev *qdev,
 692                 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
 693 {
 694         struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
 695         uint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 696         struct qede_rx_entry *curr_prod;
 697         dma_addr_t new_mapping;
 698
 699         curr_prod = &rxq->sw_rx_ring[idx];
 700         *curr_prod = *curr_cons;
 701
 702         new_mapping = rte_mbuf_data_dma_addr_default(curr_prod->mbuf) +
 703                       curr_prod->page_offset;
 704
 705         rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
 706         rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
 707
 708         rxq->sw_rx_prod++;
 709 }
 710
 711 static inline void
 712 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
 713                         struct qede_dev *qdev, uint8_t count)
 714 {
 715         struct qede_rx_entry *curr_cons;
 716
 717         for (; count > 0; count--) {
 718                 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
 719                 qede_reuse_page(qdev, rxq, curr_cons);
 720                 qede_rx_bd_ring_consume(rxq);
 721         }
 722 }
 723
 724 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
 725 {
 726         uint16_t val;
 727
 728         /* Lookup table */
 729         static const uint32_t
 730         ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
 731                 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4,
 732                 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6,
 733                 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
 734                 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
 735                 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
 736                 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
 737         };
 738
 739         /* Bits (0..3) provides L3/L4 protocol type */
 740         val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
 741                PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
 742                (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
 743                 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT)) & flags;
 744
 745         if (val < QEDE_PKT_TYPE_MAX)
 746                 return ptype_lkup_tbl[val] | RTE_PTYPE_L2_ETHER;
 747         else
 748                 return RTE_PTYPE_UNKNOWN;
 749 }
 750
 751 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
 752 {
 753         uint32_t val;
 754
 755         /* Lookup table */
 756         static const uint32_t
 757         ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
 758                 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
 759                 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
 760                 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
 761                 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
 762                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
 763                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
 764                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
 765                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
 766                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
 767                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
 768                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
 769                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
 770                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
 771                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
 772                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
 773                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
 774                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
 775                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
 776                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
 777                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
 778                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
 779                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
 780                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
 781                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
 782                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
 783                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
 784                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
 785                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
 786                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
 787                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
 788                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
 789                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
 790                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
 791                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
 792                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
 793                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
 794                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
 795                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
 796                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
 797                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
 798         };
 799
 800         /* Cover bits[4-0] to include tunn_type and next protocol */
 801         val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
 802                 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
 803                 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
 804                 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
 805
 806         if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
 807                 return ptype_tunn_lkup_tbl[val];
 808         else
 809                 return RTE_PTYPE_UNKNOWN;
 810 }
 811
 812 static inline int
 813 qede_process_sg_pkts(void *p_rxq,  struct rte_mbuf *rx_mb,
 814                      uint8_t num_segs, uint16_t pkt_len)
 815 {
 816         struct qede_rx_queue *rxq = p_rxq;
 817         struct qede_dev *qdev = rxq->qdev;
 818         struct ecore_dev *edev = &qdev->edev;
 819         register struct rte_mbuf *seg1 = NULL;
 820         register struct rte_mbuf *seg2 = NULL;
 821         uint16_t sw_rx_index;
 822         uint16_t cur_size;
 823
 824         seg1 = rx_mb;
 825         while (num_segs) {
 826                 cur_size = pkt_len > rxq->rx_buf_size ? rxq->rx_buf_size :
 827                                                         pkt_len;
 828                 if (unlikely(!cur_size)) {
 829                         PMD_RX_LOG(ERR, rxq, "Length is 0 while %u BDs"
 830                                    " left for mapping jumbo", num_segs);
 831                         qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
 832                         return -EINVAL;
 833                 }
 834                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 835                 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
 836                 qede_rx_bd_ring_consume(rxq);
 837                 pkt_len -= cur_size;
 838                 seg2->data_len = cur_size;
 839                 seg1->next = seg2;
 840                 seg1 = seg1->next;
 841                 num_segs--;
 842                 rxq->rx_segs++;
 843         }
 844
 845         return 0;
 846 }
 847
 848 uint16_t
 849 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 850 {
 851         struct qede_rx_queue *rxq = p_rxq;
 852         struct qede_dev *qdev = rxq->qdev;
 853         struct ecore_dev *edev = &qdev->edev;
 854         struct qede_fastpath *fp = &qdev->fp_array[rxq->queue_id];
 855         uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
 856         uint16_t rx_pkt = 0;
 857         union eth_rx_cqe *cqe;
 858         struct eth_fast_path_rx_reg_cqe *fp_cqe;
 859         register struct rte_mbuf *rx_mb = NULL;
 860         register struct rte_mbuf *seg1 = NULL;
 861         enum eth_rx_cqe_type cqe_type;
 862         uint16_t pkt_len; /* Sum of all BD segments */
 863         uint16_t len; /* Length of first BD */
 864         uint8_t num_segs = 1;
 865         uint16_t pad;
 866         uint16_t preload_idx;
 867         uint8_t csum_flag;
 868         uint16_t parse_flag;
 869         enum rss_hash_type htype;
 870         uint8_t tunn_parse_flag;
 871         uint8_t j;
 872
 873         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
 874         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
 875
 876         rte_rmb();
 877
 878         if (hw_comp_cons == sw_comp_cons)
 879                 return 0;
 880
 881         while (sw_comp_cons != hw_comp_cons) {
 882                 /* Get the CQE from the completion ring */
 883                 cqe =
 884                     (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
 885                 cqe_type = cqe->fast_path_regular.type;
 886
 887                 if (unlikely(cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH)) {
 888                         PMD_RX_LOG(DEBUG, rxq, "Got a slowath CQE");
 889
 890                         qdev->ops->eth_cqe_completion(edev, fp->id,
 891                                 (struct eth_slow_path_rx_cqe *)cqe);
 892                         goto next_cqe;
 893                 }
 894
 895                 /* Get the data from the SW ring */
 896                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 897                 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
 898                 assert(rx_mb != NULL);
 899
 900                 /* non GRO */
 901                 fp_cqe = &cqe->fast_path_regular;
 902
 903                 len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
 904                 pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
 905                 pad = fp_cqe->placement_offset;
 906                 assert((len + pad) <= rx_mb->buf_len);
 907
 908                 PMD_RX_LOG(DEBUG, rxq,
 909                            "CQE type = 0x%x, flags = 0x%x, vlan = 0x%x"
 910                            " len = %u, parsing_flags = %d",
 911                            cqe_type, fp_cqe->bitfields,
 912                            rte_le_to_cpu_16(fp_cqe->vlan_tag),
 913                            len, rte_le_to_cpu_16(fp_cqe->pars_flags.flags));
 914
 915                 /* If this is an error packet then drop it */
 916                 parse_flag =
 917                     rte_le_to_cpu_16(cqe->fast_path_regular.pars_flags.flags);
 918
 919                 rx_mb->ol_flags = 0;
 920
 921                 if (qede_tunn_exist(parse_flag)) {
 922                         PMD_RX_LOG(DEBUG, rxq, "Rx tunneled packet");
 923                         if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
 924                                 PMD_RX_LOG(ERR, rxq,
 925                                             "L4 csum failed, flags = 0x%x",
 926                                             parse_flag);
 927                                 rxq->rx_hw_errors++;
 928                                 rx_mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
 929                         } else {
 930                                 tunn_parse_flag =
 931                                                 fp_cqe->tunnel_pars_flags.flags;
 932                                 rx_mb->packet_type =
 933                                         qede_rx_cqe_to_tunn_pkt_type(
 934                                                         tunn_parse_flag);
 935                         }
 936                 } else {
 937                         PMD_RX_LOG(DEBUG, rxq, "Rx non-tunneled packet");
 938                         if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
 939                                 PMD_RX_LOG(ERR, rxq,
 940                                             "L4 csum failed, flags = 0x%x",
 941                                             parse_flag);
 942                                 rxq->rx_hw_errors++;
 943                                 rx_mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
 944                         } else if (unlikely(qede_check_notunn_csum_l3(rx_mb,
 945                                                         parse_flag))) {
 946                                 PMD_RX_LOG(ERR, rxq,
 947                                            "IP csum failed, flags = 0x%x",
 948                                            parse_flag);
 949                                 rxq->rx_hw_errors++;
 950                                 rx_mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
 951                         } else {
 952                                 rx_mb->packet_type =
 953                                         qede_rx_cqe_to_pkt_type(parse_flag);
 954                         }
 955                 }
 956
 957                 PMD_RX_LOG(INFO, rxq, "packet_type 0x%x", rx_mb->packet_type);
 958
 959                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
 960                         PMD_RX_LOG(ERR, rxq,
 961                                    "New buffer allocation failed,"
 962                                    "dropping incoming packet");
 963                         qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
 964                         rte_eth_devices[rxq->port_id].
 965                             data->rx_mbuf_alloc_failed++;
 966                         rxq->rx_alloc_errors++;
 967                         break;
 968                 }
 969                 qede_rx_bd_ring_consume(rxq);
 970                 if (fp_cqe->bd_num > 1) {
 971                         PMD_RX_LOG(DEBUG, rxq, "Jumbo-over-BD packet: %02x BDs"
 972                                    " len on first: %04x Total Len: %04x",
 973                                    fp_cqe->bd_num, len, pkt_len);
 974                         num_segs = fp_cqe->bd_num - 1;
 975                         seg1 = rx_mb;
 976                         if (qede_process_sg_pkts(p_rxq, seg1, num_segs,
 977                                                  pkt_len - len))
 978                                 goto next_cqe;
 979                         for (j = 0; j < num_segs; j++) {
 980                                 if (qede_alloc_rx_buffer(rxq)) {
 981                                         PMD_RX_LOG(ERR, rxq,
 982                                                 "Buffer allocation failed");
 983                                         rte_eth_devices[rxq->port_id].
 984                                                 data->rx_mbuf_alloc_failed++;
 985                                         rxq->rx_alloc_errors++;
 986                                         break;
 987                                 }
 988                                 rxq->rx_segs++;
 989                         }
 990                 }
 991                 rxq->rx_segs++; /* for the first segment */
 992
 993                 /* Prefetch next mbuf while processing current one. */
 994                 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 995                 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
 996
 997                 /* Update rest of the MBUF fields */
 998                 rx_mb->data_off = pad + RTE_PKTMBUF_HEADROOM;
 999                 rx_mb->nb_segs = fp_cqe->bd_num;
1000                 rx_mb->data_len = len;
1001                 rx_mb->pkt_len = pkt_len;
1002                 rx_mb->port = rxq->port_id;
1003
1004                 htype = (uint8_t)GET_FIELD(fp_cqe->bitfields,
1005                                 ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
1006                 if (qdev->rss_enable && htype) {
1007                         rx_mb->ol_flags |= PKT_RX_RSS_HASH;
1008                         rx_mb->hash.rss = rte_le_to_cpu_32(fp_cqe->rss_hash);
1009                         PMD_RX_LOG(DEBUG, rxq, "Hash result 0x%x",
1010                                    rx_mb->hash.rss);
1011                 }
1012
1013                 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
1014
1015                 if (CQE_HAS_VLAN(parse_flag)) {
1016                         rx_mb->vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1017                         rx_mb->ol_flags |= PKT_RX_VLAN_PKT;
1018                 }
1019
1020                 if (CQE_HAS_OUTER_VLAN(parse_flag)) {
1021                         /* FW does not provide indication of Outer VLAN tag,
1022                          * which is always stripped, so vlan_tci_outer is set
1023                          * to 0. Here vlan_tag represents inner VLAN tag.
1024                          */
1025                         rx_mb->vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1026                         rx_mb->ol_flags |= PKT_RX_QINQ_PKT;
1027                         rx_mb->vlan_tci_outer = 0;
1028                 }
1029
1030                 rx_pkts[rx_pkt] = rx_mb;
1031                 rx_pkt++;
1032 next_cqe:
1033                 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1034                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1035                 if (rx_pkt == nb_pkts) {
1036                         PMD_RX_LOG(DEBUG, rxq,
1037                                    "Budget reached nb_pkts=%u received=%u",
1038                                    rx_pkt, nb_pkts);
1039                         break;
1040                 }
1041         }
1042
1043         qede_update_rx_prod(qdev, rxq);
1044
1045         rxq->rcv_pkts += rx_pkt;
1046
1047         PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
1048
1049         return rx_pkt;
1050 }
1051
1052 static inline int
1053 qede_free_tx_pkt(struct ecore_dev *edev, struct qede_tx_queue *txq)
1054 {
1055         uint16_t nb_segs, idx = TX_CONS(txq);
1056         struct eth_tx_bd *tx_data_bd;
1057         struct rte_mbuf *mbuf = txq->sw_tx_ring[idx].mbuf;
1058
1059         if (unlikely(!mbuf)) {
1060                 PMD_TX_LOG(ERR, txq, "null mbuf");
1061                 PMD_TX_LOG(ERR, txq,
1062                            "tx_desc %u tx_avail %u tx_cons %u tx_prod %u",
1063                            txq->nb_tx_desc, txq->nb_tx_avail, idx,
1064                            TX_PROD(txq));
1065                 return -1;
1066         }
1067
1068         nb_segs = mbuf->nb_segs;
1069         while (nb_segs) {
1070                 /* It's like consuming rxbuf in recv() */
1071                 ecore_chain_consume(&txq->tx_pbl);
1072                 txq->nb_tx_avail++;
1073                 nb_segs--;
1074         }
1075         rte_pktmbuf_free(mbuf);
1076         txq->sw_tx_ring[idx].mbuf = NULL;
1077
1078         return 0;
1079 }
1080
1081 static inline uint16_t
1082 qede_process_tx_compl(struct ecore_dev *edev, struct qede_tx_queue *txq)
1083 {
1084         uint16_t tx_compl = 0;
1085         uint16_t hw_bd_cons;
1086
1087         hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
1088         rte_compiler_barrier();
1089
1090         while (hw_bd_cons != ecore_chain_get_cons_idx(&txq->tx_pbl)) {
1091                 if (qede_free_tx_pkt(edev, txq)) {
1092                         PMD_TX_LOG(ERR, txq,
1093                                    "hw_bd_cons = %u, chain_cons = %u",
1094                                    hw_bd_cons,
1095                                    ecore_chain_get_cons_idx(&txq->tx_pbl));
1096                         break;
1097                 }
1098                 txq->sw_tx_cons++;      /* Making TXD available */
1099                 tx_compl++;
1100         }
1101
1102         PMD_TX_LOG(DEBUG, txq, "Tx compl %u sw_tx_cons %u avail %u",
1103                    tx_compl, txq->sw_tx_cons, txq->nb_tx_avail);
1104         return tx_compl;
1105 }
1106
1107 /* Populate scatter gather buffer descriptor fields */
1108 static inline uint8_t
1109 qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg,
1110                   struct eth_tx_1st_bd *bd1)
1111 {
1112         struct qede_tx_queue *txq = p_txq;
1113         struct eth_tx_2nd_bd *bd2 = NULL;
1114         struct eth_tx_3rd_bd *bd3 = NULL;
1115         struct eth_tx_bd *tx_bd = NULL;
1116         dma_addr_t mapping;
1117         uint8_t nb_segs = 1; /* min one segment per packet */
1118
1119         /* Check for scattered buffers */
1120         while (m_seg) {
1121                 if (nb_segs == 1) {
1122                         bd2 = (struct eth_tx_2nd_bd *)
1123                                 ecore_chain_produce(&txq->tx_pbl);
1124                         memset(bd2, 0, sizeof(*bd2));
1125                         mapping = rte_mbuf_data_dma_addr(m_seg);
1126                         QEDE_BD_SET_ADDR_LEN(bd2, mapping, m_seg->data_len);
1127                         PMD_TX_LOG(DEBUG, txq, "BD2 len %04x",
1128                                    m_seg->data_len);
1129                 } else if (nb_segs == 2) {
1130                         bd3 = (struct eth_tx_3rd_bd *)
1131                                 ecore_chain_produce(&txq->tx_pbl);
1132                         memset(bd3, 0, sizeof(*bd3));
1133                         mapping = rte_mbuf_data_dma_addr(m_seg);
1134                         QEDE_BD_SET_ADDR_LEN(bd3, mapping, m_seg->data_len);
1135                         PMD_TX_LOG(DEBUG, txq, "BD3 len %04x",
1136                                    m_seg->data_len);
1137                 } else {
1138                         tx_bd = (struct eth_tx_bd *)
1139                                 ecore_chain_produce(&txq->tx_pbl);
1140                         memset(tx_bd, 0, sizeof(*tx_bd));
1141                         mapping = rte_mbuf_data_dma_addr(m_seg);
1142                         QEDE_BD_SET_ADDR_LEN(tx_bd, mapping, m_seg->data_len);
1143                         PMD_TX_LOG(DEBUG, txq, "BD len %04x",
1144                                    m_seg->data_len);
1145                 }
1146                 nb_segs++;
1147                 m_seg = m_seg->next;
1148         }
1149
1150         /* Return total scattered buffers */
1151         return nb_segs;
1152 }
1153
1154 uint16_t
1155 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1156 {
1157         struct qede_tx_queue *txq = p_txq;
1158         struct qede_dev *qdev = txq->qdev;
1159         struct ecore_dev *edev = &qdev->edev;
1160         struct qede_fastpath *fp;
1161         struct eth_tx_1st_bd *bd1;
1162         struct rte_mbuf *mbuf;
1163         struct rte_mbuf *m_seg = NULL;
1164         uint16_t nb_tx_pkts;
1165         uint16_t bd_prod;
1166         uint16_t idx;
1167         uint16_t tx_count;
1168         uint16_t nb_frags;
1169         uint16_t nb_pkt_sent = 0;
1170
1171         fp = &qdev->fp_array[QEDE_RSS_COUNT(qdev) + txq->queue_id];
1172
1173         if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
1174                 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
1175                            nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
1176                 (void)qede_process_tx_compl(edev, txq);
1177         }
1178
1179         nb_tx_pkts = RTE_MIN(nb_pkts, (txq->nb_tx_avail /
1180                         ETH_TX_MAX_BDS_PER_NON_LSO_PACKET));
1181         if (unlikely(nb_tx_pkts == 0)) {
1182                 PMD_TX_LOG(DEBUG, txq, "Out of BDs nb_pkts=%u avail=%u",
1183                            nb_pkts, txq->nb_tx_avail);
1184                 return 0;
1185         }
1186
1187         tx_count = nb_tx_pkts;
1188         while (nb_tx_pkts--) {
1189                 /* Fill the entry in the SW ring and the BDs in the FW ring */
1190                 idx = TX_PROD(txq);
1191                 mbuf = *tx_pkts++;
1192                 txq->sw_tx_ring[idx].mbuf = mbuf;
1193                 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
1194                 bd1->data.bd_flags.bitfields =
1195                         1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
1196                 /* FW 8.10.x specific change */
1197                 bd1->data.bitfields =
1198                         (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
1199                                 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
1200                 /* Map MBUF linear data for DMA and set in the first BD */
1201                 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_dma_addr(mbuf),
1202                                      mbuf->data_len);
1203                 PMD_TX_LOG(INFO, txq, "BD1 len %04x", mbuf->data_len);
1204
1205                 if (RTE_ETH_IS_TUNNEL_PKT(mbuf->packet_type)) {
1206                         PMD_TX_LOG(INFO, txq, "Tx tunnel packet");
1207                         /* First indicate its a tunnel pkt */
1208                         bd1->data.bd_flags.bitfields |=
1209                                 ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
1210                                 ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1211
1212                         /* Legacy FW had flipped behavior in regard to this bit
1213                          * i.e. it needed to set to prevent FW from touching
1214                          * encapsulated packets when it didn't need to.
1215                          */
1216                         if (unlikely(txq->is_legacy))
1217                                 bd1->data.bitfields ^=
1218                                         1 << ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1219
1220                         /* Outer IP checksum offload */
1221                         if (mbuf->ol_flags & PKT_TX_OUTER_IP_CKSUM) {
1222                                 PMD_TX_LOG(INFO, txq, "OuterIP csum offload");
1223                                 bd1->data.bd_flags.bitfields |=
1224                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
1225                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
1226                         }
1227
1228                         /* Outer UDP checksum offload */
1229                         bd1->data.bd_flags.bitfields |=
1230                                 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
1231                                 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
1232                 }
1233
1234                 /* Descriptor based VLAN insertion */
1235                 if (mbuf->ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1236                         PMD_TX_LOG(INFO, txq, "Insert VLAN 0x%x",
1237                                    mbuf->vlan_tci);
1238                         bd1->data.vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
1239                         bd1->data.bd_flags.bitfields |=
1240                             1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
1241                 }
1242
1243                 /* Offload the IP checksum in the hardware */
1244                 if (mbuf->ol_flags & PKT_TX_IP_CKSUM) {
1245                         PMD_TX_LOG(INFO, txq, "IP csum offload");
1246                         bd1->data.bd_flags.bitfields |=
1247                             1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1248                 }
1249
1250                 /* L4 checksum offload (tcp or udp) */
1251                 if (mbuf->ol_flags & (PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
1252                         PMD_TX_LOG(INFO, txq, "L4 csum offload");
1253                         bd1->data.bd_flags.bitfields |=
1254                             1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1255                         /* IPv6 + extn. -> later */
1256                 }
1257
1258                 /* Handle fragmented MBUF */
1259                 m_seg = mbuf->next;
1260                 /* Encode scatter gather buffer descriptors if required */
1261                 nb_frags = qede_encode_sg_bd(txq, m_seg, bd1);
1262                 bd1->data.nbds = nb_frags;
1263                 txq->nb_tx_avail -= nb_frags;
1264                 txq->sw_tx_prod++;
1265                 rte_prefetch0(txq->sw_tx_ring[TX_PROD(txq)].mbuf);
1266                 bd_prod =
1267                     rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1268                 nb_pkt_sent++;
1269                 txq->xmit_pkts++;
1270                 PMD_TX_LOG(INFO, txq, "nbds = %d pkt_len = %04x",
1271                            bd1->data.nbds, mbuf->pkt_len);
1272         }
1273
1274         /* Write value of prod idx into bd_prod */
1275         txq->tx_db.data.bd_prod = bd_prod;
1276         rte_wmb();
1277         rte_compiler_barrier();
1278         DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
1279         rte_wmb();
1280
1281         /* Check again for Tx completions */
1282         (void)qede_process_tx_compl(edev, txq);
1283
1284         PMD_TX_LOG(DEBUG, txq, "to_send=%u can_send=%u sent=%u core=%d",
1285                    nb_pkts, tx_count, nb_pkt_sent, rte_lcore_id());
1286
1287         return nb_pkt_sent;
1288 }
1289
1290 static void qede_init_fp_queue(struct rte_eth_dev *eth_dev)
1291 {
1292         struct qede_dev *qdev = eth_dev->data->dev_private;
1293         struct qede_fastpath *fp;
1294         uint8_t i, rss_id, txq_index, tc;
1295         int rxq = 0, txq = 0;
1296
1297         for_each_queue(i) {
1298                 fp = &qdev->fp_array[i];
1299                 if (fp->type & QEDE_FASTPATH_RX) {
1300                         fp->rxq = eth_dev->data->rx_queues[i];
1301                         fp->rxq->queue_id = rxq++;
1302                 }
1303
1304                 if (fp->type & QEDE_FASTPATH_TX) {
1305                         for (tc = 0; tc < qdev->num_tc; tc++) {
1306                                 txq_index = tc * QEDE_TSS_COUNT(qdev) + txq;
1307                                 fp->txqs[tc] =
1308                                         eth_dev->data->tx_queues[txq_index];
1309                                 fp->txqs[tc]->queue_id = txq_index;
1310                                 if (qdev->dev_info.is_legacy)
1311                                         fp->txqs[tc]->is_legacy = true;
1312                         }
1313                         txq++;
1314                 }
1315         }
1316 }
1317
1318 int qede_dev_start(struct rte_eth_dev *eth_dev)
1319 {
1320         struct qede_dev *qdev = eth_dev->data->dev_private;
1321         struct ecore_dev *edev = &qdev->edev;
1322         struct qed_link_output link_output;
1323         struct qede_fastpath *fp;
1324         int rc;
1325
1326         DP_INFO(edev, "Device state is %d\n", qdev->state);
1327
1328         if (qdev->state == QEDE_DEV_START) {
1329                 DP_INFO(edev, "Port is already started\n");
1330                 return 0;
1331         }
1332
1333         if (qdev->state == QEDE_DEV_CONFIG)
1334                 qede_init_fp_queue(eth_dev);
1335
1336         rc = qede_start_queues(eth_dev, true);
1337         if (rc) {
1338                 DP_ERR(edev, "Failed to start queues\n");
1339                 /* TBD: free */
1340                 return rc;
1341         }
1342
1343         /* Bring-up the link */
1344         qede_dev_set_link_state(eth_dev, true);
1345
1346         /* Reset ring */
1347         if (qede_reset_fp_rings(qdev))
1348                 return -ENOMEM;
1349
1350         /* Start/resume traffic */
1351         qdev->ops->fastpath_start(edev);
1352
1353         qdev->state = QEDE_DEV_START;
1354
1355         DP_INFO(edev, "dev_state is QEDE_DEV_START\n");
1356
1357         return 0;
1358 }
1359
1360 static int qede_drain_txq(struct qede_dev *qdev,
1361                           struct qede_tx_queue *txq, bool allow_drain)
1362 {
1363         struct ecore_dev *edev = &qdev->edev;
1364         int rc, cnt = 1000;
1365
1366         while (txq->sw_tx_cons != txq->sw_tx_prod) {
1367                 qede_process_tx_compl(edev, txq);
1368                 if (!cnt) {
1369                         if (allow_drain) {
1370                                 DP_NOTICE(edev, false,
1371                                           "Tx queue[%u] is stuck,"
1372                                           "requesting MCP to drain\n",
1373                                           txq->queue_id);
1374                                 rc = qdev->ops->common->drain(edev);
1375                                 if (rc)
1376                                         return rc;
1377                                 return qede_drain_txq(qdev, txq, false);
1378                         }
1379
1380                         DP_NOTICE(edev, false,
1381                                   "Timeout waiting for tx queue[%d]:"
1382                                   "PROD=%d, CONS=%d\n",
1383                                   txq->queue_id, txq->sw_tx_prod,
1384                                   txq->sw_tx_cons);
1385                         return -ENODEV;
1386                 }
1387                 cnt--;
1388                 DELAY(1000);
1389                 rte_compiler_barrier();
1390         }
1391
1392         /* FW finished processing, wait for HW to transmit all tx packets */
1393         DELAY(2000);
1394
1395         return 0;
1396 }
1397
1398 static int qede_stop_queues(struct qede_dev *qdev)
1399 {
1400         struct qed_update_vport_params vport_update_params;
1401         struct ecore_dev *edev = &qdev->edev;
1402         int rc, tc, i;
1403
1404         /* Disable the vport */
1405         memset(&vport_update_params, 0, sizeof(vport_update_params));
1406         vport_update_params.vport_id = 0;
1407         vport_update_params.update_vport_active_flg = 1;
1408         vport_update_params.vport_active_flg = 0;
1409         vport_update_params.update_rss_flg = 0;
1410
1411         DP_INFO(edev, "Deactivate vport\n");
1412
1413         rc = qdev->ops->vport_update(edev, &vport_update_params);
1414         if (rc) {
1415                 DP_ERR(edev, "Failed to update vport\n");
1416                 return rc;
1417         }
1418
1419         DP_INFO(edev, "Flushing tx queues\n");
1420
1421         /* Flush Tx queues. If needed, request drain from MCP */
1422         for_each_queue(i) {
1423                 struct qede_fastpath *fp = &qdev->fp_array[i];
1424
1425                 if (fp->type & QEDE_FASTPATH_TX) {
1426                         for (tc = 0; tc < qdev->num_tc; tc++) {
1427                                 struct qede_tx_queue *txq = fp->txqs[tc];
1428
1429                                 rc = qede_drain_txq(qdev, txq, true);
1430                                 if (rc)
1431                                         return rc;
1432                         }
1433                 }
1434         }
1435
1436         /* Stop all Queues in reverse order */
1437         for (i = QEDE_QUEUE_CNT(qdev) - 1; i >= 0; i--) {
1438                 struct qed_stop_rxq_params rx_params;
1439
1440                 /* Stop the Tx Queue(s) */
1441                 if (qdev->fp_array[i].type & QEDE_FASTPATH_TX) {
1442                         for (tc = 0; tc < qdev->num_tc; tc++) {
1443                                 struct qed_stop_txq_params tx_params;
1444                                 u8 val;
1445
1446                                 tx_params.rss_id = i;
1447                                 val = qdev->fp_array[i].txqs[tc]->queue_id;
1448                                 tx_params.tx_queue_id = val;
1449
1450                                 DP_INFO(edev, "Stopping tx queues\n");
1451                                 rc = qdev->ops->q_tx_stop(edev, &tx_params);
1452                                 if (rc) {
1453                                         DP_ERR(edev, "Failed to stop TXQ #%d\n",
1454                                                tx_params.tx_queue_id);
1455                                         return rc;
1456                                 }
1457                         }
1458                 }
1459
1460                 /* Stop the Rx Queue */
1461                 if (qdev->fp_array[i].type & QEDE_FASTPATH_RX) {
1462                         memset(&rx_params, 0, sizeof(rx_params));
1463                         rx_params.rss_id = i;
1464                         rx_params.rx_queue_id = qdev->fp_array[i].rxq->queue_id;
1465                         rx_params.eq_completion_only = 1;
1466
1467                         DP_INFO(edev, "Stopping rx queues\n");
1468
1469                         rc = qdev->ops->q_rx_stop(edev, &rx_params);
1470                         if (rc) {
1471                                 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
1472                                 return rc;
1473                         }
1474                 }
1475         }
1476
1477         return 0;
1478 }
1479
1480 int qede_reset_fp_rings(struct qede_dev *qdev)
1481 {
1482         struct qede_fastpath *fp;
1483         struct qede_tx_queue *txq;
1484         uint8_t tc;
1485         uint16_t id, i;
1486
1487         for_each_queue(id) {
1488                 fp = &qdev->fp_array[id];
1489
1490                 if (fp->type & QEDE_FASTPATH_RX) {
1491                         DP_INFO(&qdev->edev,
1492                                 "Reset FP chain for RSS %u\n", id);
1493                         qede_rx_queue_release_mbufs(fp->rxq);
1494                         ecore_chain_reset(&fp->rxq->rx_bd_ring);
1495                         ecore_chain_reset(&fp->rxq->rx_comp_ring);
1496                         fp->rxq->sw_rx_prod = 0;
1497                         fp->rxq->sw_rx_cons = 0;
1498                         *fp->rxq->hw_cons_ptr = 0;
1499                         for (i = 0; i < fp->rxq->nb_rx_desc; i++) {
1500                                 if (qede_alloc_rx_buffer(fp->rxq)) {
1501                                         DP_ERR(&qdev->edev,
1502                                                "RX buffer allocation failed\n");
1503                                         return -ENOMEM;
1504                                 }
1505                         }
1506                 }
1507                 if (fp->type & QEDE_FASTPATH_TX) {
1508                         for (tc = 0; tc < qdev->num_tc; tc++) {
1509                                 txq = fp->txqs[tc];
1510                                 qede_tx_queue_release_mbufs(txq);
1511                                 ecore_chain_reset(&txq->tx_pbl);
1512                                 txq->sw_tx_cons = 0;
1513                                 txq->sw_tx_prod = 0;
1514                                 *txq->hw_cons_ptr = 0;
1515                         }
1516                 }
1517         }
1518
1519         return 0;
1520 }
1521
1522 /* This function frees all memory of a single fp */
1523 void qede_free_mem_load(struct rte_eth_dev *eth_dev)
1524 {
1525         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1526         struct qede_fastpath *fp;
1527         uint16_t txq_idx;
1528         uint8_t id;
1529         uint8_t tc;
1530
1531         for_each_queue(id) {
1532                 fp = &qdev->fp_array[id];
1533                 if (fp->type & QEDE_FASTPATH_RX) {
1534                         if (!fp->rxq)
1535                                 continue;
1536                         qede_rx_queue_release(fp->rxq);
1537                         eth_dev->data->rx_queues[id] = NULL;
1538                 } else {
1539                         for (tc = 0; tc < qdev->num_tc; tc++) {
1540                                 if (!fp->txqs[tc])
1541                                         continue;
1542                                 txq_idx = fp->txqs[tc]->queue_id;
1543                                 qede_tx_queue_release(fp->txqs[tc]);
1544                                 eth_dev->data->tx_queues[txq_idx] = NULL;
1545                         }
1546                 }
1547         }
1548 }
1549
1550 void qede_dev_stop(struct rte_eth_dev *eth_dev)
1551 {
1552         struct qede_dev *qdev = eth_dev->data->dev_private;
1553         struct ecore_dev *edev = &qdev->edev;
1554
1555         DP_INFO(edev, "port %u\n", eth_dev->data->port_id);
1556
1557         if (qdev->state != QEDE_DEV_START) {
1558                 DP_INFO(edev, "Device not yet started\n");
1559                 return;
1560         }
1561
1562         if (qede_stop_queues(qdev))
1563                 DP_ERR(edev, "Didn't succeed to close queues\n");
1564
1565         DP_INFO(edev, "Stopped queues\n");
1566
1567         qdev->ops->fastpath_stop(edev);
1568
1569         /* Bring the link down */
1570         qede_dev_set_link_state(eth_dev, false);
1571
1572         qdev->state = QEDE_DEV_STOP;
1573
1574         DP_INFO(edev, "dev_state is QEDE_DEV_STOP\n");
1575 }