1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
10 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
12 struct rte_mbuf *new_mb = NULL;
13 struct eth_rx_bd *rx_bd;
15 uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
17 new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
18 if (unlikely(!new_mb)) {
20 "Failed to allocate rx buffer "
21 "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
22 idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
23 rte_mempool_avail_count(rxq->mb_pool),
24 rte_mempool_in_use_count(rxq->mb_pool));
27 rxq->sw_rx_ring[idx].mbuf = new_mb;
28 rxq->sw_rx_ring[idx].page_offset = 0;
29 mapping = rte_mbuf_data_iova_default(new_mb);
30 /* Advance PROD and get BD pointer */
31 rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
32 rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
33 rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
38 /* Criterias for calculating Rx buffer size -
39 * 1) rx_buf_size should not exceed the size of mbuf
40 * 2) In scattered_rx mode - minimum rx_buf_size should be
41 * (MTU + Maximum L2 Header Size + 2) / ETH_RX_MAX_BUFF_PER_PKT
42 * 3) In regular mode - minimum rx_buf_size should be
43 * (MTU + Maximum L2 Header Size + 2)
44 * In above cases +2 corrosponds to 2 bytes padding in front of L2
46 * 4) rx_buf_size should be cacheline-size aligned. So considering
47 * criteria 1, we need to adjust the size to floor instead of ceil,
48 * so that we don't exceed mbuf size while ceiling rx_buf_size.
51 qede_calc_rx_buf_size(struct rte_eth_dev *dev, uint16_t mbufsz,
52 uint16_t max_frame_size)
54 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
55 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
58 if (dev->data->scattered_rx) {
59 /* per HW limitation, only ETH_RX_MAX_BUFF_PER_PKT number of
60 * bufferes can be used for single packet. So need to make sure
61 * mbuf size is sufficient enough for this.
63 if ((mbufsz * ETH_RX_MAX_BUFF_PER_PKT) <
64 (max_frame_size + QEDE_ETH_OVERHEAD)) {
65 DP_ERR(edev, "mbuf %d size is not enough to hold max fragments (%d) for max rx packet length (%d)\n",
66 mbufsz, ETH_RX_MAX_BUFF_PER_PKT, max_frame_size);
70 rx_buf_size = RTE_MAX(mbufsz,
71 (max_frame_size + QEDE_ETH_OVERHEAD) /
72 ETH_RX_MAX_BUFF_PER_PKT);
74 rx_buf_size = max_frame_size + QEDE_ETH_OVERHEAD;
77 /* Align to cache-line size if needed */
78 return QEDE_FLOOR_TO_CACHE_LINE_SIZE(rx_buf_size);
82 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
83 uint16_t nb_desc, unsigned int socket_id,
84 __rte_unused const struct rte_eth_rxconf *rx_conf,
85 struct rte_mempool *mp)
87 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
88 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
89 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
90 struct qede_rx_queue *rxq;
91 uint16_t max_rx_pkt_len;
96 PMD_INIT_FUNC_TRACE(edev);
98 /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
99 if (!rte_is_power_of_2(nb_desc)) {
100 DP_ERR(edev, "Ring size %u is not power of 2\n",
105 /* Free memory prior to re-allocation if needed... */
106 if (dev->data->rx_queues[queue_idx] != NULL) {
107 qede_rx_queue_release(dev->data->rx_queues[queue_idx]);
108 dev->data->rx_queues[queue_idx] = NULL;
111 /* First allocate the rx queue data structure */
112 rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
113 RTE_CACHE_LINE_SIZE, socket_id);
116 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
123 rxq->nb_rx_desc = nb_desc;
124 rxq->queue_id = queue_idx;
125 rxq->port_id = dev->data->port_id;
127 max_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len;
129 /* Fix up RX buffer size */
130 bufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
131 /* cache align the mbuf size to simplfy rx_buf_size calculation */
132 bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
133 if ((rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) ||
134 (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {
135 if (!dev->data->scattered_rx) {
136 DP_INFO(edev, "Forcing scatter-gather mode\n");
137 dev->data->scattered_rx = 1;
141 rc = qede_calc_rx_buf_size(dev, bufsz, max_rx_pkt_len);
147 rxq->rx_buf_size = rc;
149 DP_INFO(edev, "mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\n",
150 qdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);
152 /* Allocate the parallel driver ring for Rx buffers */
153 size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
154 rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
155 RTE_CACHE_LINE_SIZE, socket_id);
156 if (!rxq->sw_rx_ring) {
157 DP_ERR(edev, "Memory allocation fails for sw_rx_ring on"
158 " socket %u\n", socket_id);
163 /* Allocate FW Rx ring */
164 rc = qdev->ops->common->chain_alloc(edev,
165 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
166 ECORE_CHAIN_MODE_NEXT_PTR,
167 ECORE_CHAIN_CNT_TYPE_U16,
169 sizeof(struct eth_rx_bd),
173 if (rc != ECORE_SUCCESS) {
174 DP_ERR(edev, "Memory allocation fails for RX BD ring"
175 " on socket %u\n", socket_id);
176 rte_free(rxq->sw_rx_ring);
181 /* Allocate FW completion ring */
182 rc = qdev->ops->common->chain_alloc(edev,
183 ECORE_CHAIN_USE_TO_CONSUME,
184 ECORE_CHAIN_MODE_PBL,
185 ECORE_CHAIN_CNT_TYPE_U16,
187 sizeof(union eth_rx_cqe),
191 if (rc != ECORE_SUCCESS) {
192 DP_ERR(edev, "Memory allocation fails for RX CQE ring"
193 " on socket %u\n", socket_id);
194 qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);
195 rte_free(rxq->sw_rx_ring);
200 dev->data->rx_queues[queue_idx] = rxq;
201 qdev->fp_array[queue_idx].rxq = rxq;
203 DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
204 queue_idx, nb_desc, rxq->rx_buf_size, socket_id);
210 qede_rx_queue_reset(__rte_unused struct qede_dev *qdev,
211 struct qede_rx_queue *rxq)
213 DP_INFO(&qdev->edev, "Reset RX queue %u\n", rxq->queue_id);
214 ecore_chain_reset(&rxq->rx_bd_ring);
215 ecore_chain_reset(&rxq->rx_comp_ring);
218 *rxq->hw_cons_ptr = 0;
221 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
225 if (rxq->sw_rx_ring) {
226 for (i = 0; i < rxq->nb_rx_desc; i++) {
227 if (rxq->sw_rx_ring[i].mbuf) {
228 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
229 rxq->sw_rx_ring[i].mbuf = NULL;
235 void qede_rx_queue_release(void *rx_queue)
237 struct qede_rx_queue *rxq = rx_queue;
238 struct qede_dev *qdev;
239 struct ecore_dev *edev;
243 edev = QEDE_INIT_EDEV(qdev);
244 PMD_INIT_FUNC_TRACE(edev);
245 qede_rx_queue_release_mbufs(rxq);
246 qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);
247 qdev->ops->common->chain_free(edev, &rxq->rx_comp_ring);
248 rte_free(rxq->sw_rx_ring);
253 /* Stops a given RX queue in the HW */
254 static int qede_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
256 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
257 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
258 struct ecore_hwfn *p_hwfn;
259 struct qede_rx_queue *rxq;
263 if (rx_queue_id < eth_dev->data->nb_rx_queues) {
264 rxq = eth_dev->data->rx_queues[rx_queue_id];
265 hwfn_index = rx_queue_id % edev->num_hwfns;
266 p_hwfn = &edev->hwfns[hwfn_index];
267 rc = ecore_eth_rx_queue_stop(p_hwfn, rxq->handle,
269 if (rc != ECORE_SUCCESS) {
270 DP_ERR(edev, "RX queue %u stop fails\n", rx_queue_id);
273 qede_rx_queue_release_mbufs(rxq);
274 qede_rx_queue_reset(qdev, rxq);
275 eth_dev->data->rx_queue_state[rx_queue_id] =
276 RTE_ETH_QUEUE_STATE_STOPPED;
277 DP_INFO(edev, "RX queue %u stopped\n", rx_queue_id);
279 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
287 qede_tx_queue_setup(struct rte_eth_dev *dev,
290 unsigned int socket_id,
291 const struct rte_eth_txconf *tx_conf)
293 struct qede_dev *qdev = dev->data->dev_private;
294 struct ecore_dev *edev = &qdev->edev;
295 struct qede_tx_queue *txq;
298 PMD_INIT_FUNC_TRACE(edev);
300 if (!rte_is_power_of_2(nb_desc)) {
301 DP_ERR(edev, "Ring size %u is not power of 2\n",
306 /* Free memory prior to re-allocation if needed... */
307 if (dev->data->tx_queues[queue_idx] != NULL) {
308 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
309 dev->data->tx_queues[queue_idx] = NULL;
312 txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
313 RTE_CACHE_LINE_SIZE, socket_id);
317 "Unable to allocate memory for txq on socket %u",
322 txq->nb_tx_desc = nb_desc;
324 txq->port_id = dev->data->port_id;
326 rc = qdev->ops->common->chain_alloc(edev,
327 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
328 ECORE_CHAIN_MODE_PBL,
329 ECORE_CHAIN_CNT_TYPE_U16,
331 sizeof(union eth_tx_bd_types),
334 if (rc != ECORE_SUCCESS) {
336 "Unable to allocate memory for txbd ring on socket %u",
338 qede_tx_queue_release(txq);
342 /* Allocate software ring */
343 txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
344 (sizeof(struct qede_tx_entry) *
346 RTE_CACHE_LINE_SIZE, socket_id);
348 if (!txq->sw_tx_ring) {
350 "Unable to allocate memory for txbd ring on socket %u",
352 qdev->ops->common->chain_free(edev, &txq->tx_pbl);
353 qede_tx_queue_release(txq);
357 txq->queue_id = queue_idx;
359 txq->nb_tx_avail = txq->nb_tx_desc;
361 txq->tx_free_thresh =
362 tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
363 (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
365 dev->data->tx_queues[queue_idx] = txq;
366 qdev->fp_array[queue_idx].txq = txq;
369 "txq %u num_desc %u tx_free_thresh %u socket %u\n",
370 queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
376 qede_tx_queue_reset(__rte_unused struct qede_dev *qdev,
377 struct qede_tx_queue *txq)
379 DP_INFO(&qdev->edev, "Reset TX queue %u\n", txq->queue_id);
380 ecore_chain_reset(&txq->tx_pbl);
383 *txq->hw_cons_ptr = 0;
386 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
390 if (txq->sw_tx_ring) {
391 for (i = 0; i < txq->nb_tx_desc; i++) {
392 if (txq->sw_tx_ring[i].mbuf) {
393 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf);
394 txq->sw_tx_ring[i].mbuf = NULL;
400 void qede_tx_queue_release(void *tx_queue)
402 struct qede_tx_queue *txq = tx_queue;
403 struct qede_dev *qdev;
404 struct ecore_dev *edev;
408 edev = QEDE_INIT_EDEV(qdev);
409 PMD_INIT_FUNC_TRACE(edev);
410 qede_tx_queue_release_mbufs(txq);
411 qdev->ops->common->chain_free(edev, &txq->tx_pbl);
412 rte_free(txq->sw_tx_ring);
417 /* This function allocates fast-path status block memory */
419 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
422 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
423 struct status_block_e4 *sb_virt;
427 sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys,
428 sizeof(struct status_block_e4));
430 DP_ERR(edev, "Status block allocation failed\n");
433 rc = qdev->ops->common->sb_init(edev, sb_info, sb_virt,
436 DP_ERR(edev, "Status block initialization failed\n");
437 OSAL_DMA_FREE_COHERENT(edev, sb_virt, sb_phys,
438 sizeof(struct status_block_e4));
445 int qede_alloc_fp_resc(struct qede_dev *qdev)
447 struct ecore_dev *edev = &qdev->edev;
448 struct qede_fastpath *fp;
453 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
455 num_sbs = ecore_cxt_get_proto_cid_count
456 (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL);
459 DP_ERR(edev, "No status blocks available\n");
463 qdev->fp_array = rte_calloc("fp", QEDE_RXTX_MAX(qdev),
464 sizeof(*qdev->fp_array), RTE_CACHE_LINE_SIZE);
466 if (!qdev->fp_array) {
467 DP_ERR(edev, "fp array allocation failed\n");
471 memset((void *)qdev->fp_array, 0, QEDE_RXTX_MAX(qdev) *
472 sizeof(*qdev->fp_array));
474 for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
475 fp = &qdev->fp_array[sb_idx];
478 fp->sb_info = rte_calloc("sb", 1, sizeof(struct ecore_sb_info),
479 RTE_CACHE_LINE_SIZE);
481 DP_ERR(edev, "FP sb_info allocation fails\n");
484 if (qede_alloc_mem_sb(qdev, fp->sb_info, sb_idx)) {
485 DP_ERR(edev, "FP status block allocation fails\n");
488 DP_INFO(edev, "sb_info idx 0x%x initialized\n",
489 fp->sb_info->igu_sb_id);
495 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
497 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
498 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
499 struct qede_fastpath *fp;
503 PMD_INIT_FUNC_TRACE(edev);
505 for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
506 fp = &qdev->fp_array[sb_idx];
509 DP_INFO(edev, "Free sb_info index 0x%x\n",
510 fp->sb_info->igu_sb_id);
512 OSAL_DMA_FREE_COHERENT(edev, fp->sb_info->sb_virt,
513 fp->sb_info->sb_phys,
514 sizeof(struct status_block_e4));
515 rte_free(fp->sb_info);
520 /* Free packet buffers and ring memories */
521 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
522 if (eth_dev->data->rx_queues[i]) {
523 qede_rx_queue_release(eth_dev->data->rx_queues[i]);
524 eth_dev->data->rx_queues[i] = NULL;
528 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
529 if (eth_dev->data->tx_queues[i]) {
530 qede_tx_queue_release(eth_dev->data->tx_queues[i]);
531 eth_dev->data->tx_queues[i] = NULL;
536 rte_free(qdev->fp_array);
537 qdev->fp_array = NULL;
541 qede_update_rx_prod(__rte_unused struct qede_dev *edev,
542 struct qede_rx_queue *rxq)
544 uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
545 uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
546 struct eth_rx_prod_data rx_prods = { 0 };
548 /* Update producers */
549 rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
550 rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
552 /* Make sure that the BD and SGE data is updated before updating the
553 * producers since FW might read the BD/SGE right after the producer
558 internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
559 (uint32_t *)&rx_prods);
561 /* mmiowb is needed to synchronize doorbell writes from more than one
562 * processor. It guarantees that the write arrives to the device before
563 * the napi lock is released and another qede_poll is called (possibly
564 * on another CPU). Without this barrier, the next doorbell can bypass
565 * this doorbell. This is applicable to IA64/Altix systems.
569 PMD_RX_LOG(DEBUG, rxq, "bd_prod %u cqe_prod %u", bd_prod, cqe_prod);
572 /* Starts a given RX queue in HW */
574 qede_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
576 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
577 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
578 struct ecore_queue_start_common_params params;
579 struct ecore_rxq_start_ret_params ret_params;
580 struct qede_rx_queue *rxq;
581 struct qede_fastpath *fp;
582 struct ecore_hwfn *p_hwfn;
583 dma_addr_t p_phys_table;
589 if (rx_queue_id < eth_dev->data->nb_rx_queues) {
590 fp = &qdev->fp_array[rx_queue_id];
591 rxq = eth_dev->data->rx_queues[rx_queue_id];
592 /* Allocate buffers for the Rx ring */
593 for (j = 0; j < rxq->nb_rx_desc; j++) {
594 rc = qede_alloc_rx_buffer(rxq);
596 DP_ERR(edev, "RX buffer allocation failed"
597 " for rxq = %u\n", rx_queue_id);
601 /* disable interrupts */
602 ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
604 memset(¶ms, 0, sizeof(params));
605 params.queue_id = rx_queue_id / edev->num_hwfns;
607 params.stats_id = params.vport_id;
608 params.p_sb = fp->sb_info;
609 DP_INFO(edev, "rxq %u igu_sb_id 0x%x\n",
610 fp->rxq->queue_id, fp->sb_info->igu_sb_id);
611 params.sb_idx = RX_PI;
612 hwfn_index = rx_queue_id % edev->num_hwfns;
613 p_hwfn = &edev->hwfns[hwfn_index];
614 p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->rx_comp_ring);
615 page_cnt = ecore_chain_get_page_cnt(&fp->rxq->rx_comp_ring);
616 memset(&ret_params, 0, sizeof(ret_params));
617 rc = ecore_eth_rx_queue_start(p_hwfn,
618 p_hwfn->hw_info.opaque_fid,
619 ¶ms, fp->rxq->rx_buf_size,
620 fp->rxq->rx_bd_ring.p_phys_addr,
621 p_phys_table, page_cnt,
624 DP_ERR(edev, "RX queue %u could not be started, rc = %d\n",
628 /* Update with the returned parameters */
629 fp->rxq->hw_rxq_prod_addr = ret_params.p_prod;
630 fp->rxq->handle = ret_params.p_handle;
632 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[RX_PI];
633 qede_update_rx_prod(qdev, fp->rxq);
634 eth_dev->data->rx_queue_state[rx_queue_id] =
635 RTE_ETH_QUEUE_STATE_STARTED;
636 DP_INFO(edev, "RX queue %u started\n", rx_queue_id);
638 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
646 qede_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
648 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
649 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
650 struct ecore_queue_start_common_params params;
651 struct ecore_txq_start_ret_params ret_params;
652 struct ecore_hwfn *p_hwfn;
653 dma_addr_t p_phys_table;
654 struct qede_tx_queue *txq;
655 struct qede_fastpath *fp;
660 if (tx_queue_id < eth_dev->data->nb_tx_queues) {
661 txq = eth_dev->data->tx_queues[tx_queue_id];
662 fp = &qdev->fp_array[tx_queue_id];
663 memset(¶ms, 0, sizeof(params));
664 params.queue_id = tx_queue_id / edev->num_hwfns;
666 params.stats_id = params.vport_id;
667 params.p_sb = fp->sb_info;
668 DP_INFO(edev, "txq %u igu_sb_id 0x%x\n",
669 fp->txq->queue_id, fp->sb_info->igu_sb_id);
670 params.sb_idx = TX_PI(0); /* tc = 0 */
671 p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
672 page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
673 hwfn_index = tx_queue_id % edev->num_hwfns;
674 p_hwfn = &edev->hwfns[hwfn_index];
675 if (qdev->dev_info.is_legacy)
676 fp->txq->is_legacy = true;
677 rc = ecore_eth_tx_queue_start(p_hwfn,
678 p_hwfn->hw_info.opaque_fid,
680 p_phys_table, page_cnt,
682 if (rc != ECORE_SUCCESS) {
683 DP_ERR(edev, "TX queue %u couldn't be started, rc=%d\n",
687 txq->doorbell_addr = ret_params.p_doorbell;
688 txq->handle = ret_params.p_handle;
690 txq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[TX_PI(0)];
691 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_DEST,
693 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
695 SET_FIELD(txq->tx_db.data.params,
696 ETH_DB_DATA_AGG_VAL_SEL,
697 DQ_XCM_ETH_TX_BD_PROD_CMD);
698 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
699 eth_dev->data->tx_queue_state[tx_queue_id] =
700 RTE_ETH_QUEUE_STATE_STARTED;
701 DP_INFO(edev, "TX queue %u started\n", tx_queue_id);
703 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
711 qede_free_tx_pkt(struct qede_tx_queue *txq)
713 struct rte_mbuf *mbuf;
718 mbuf = txq->sw_tx_ring[idx].mbuf;
720 nb_segs = mbuf->nb_segs;
721 PMD_TX_LOG(DEBUG, txq, "nb_segs to free %u\n", nb_segs);
723 /* It's like consuming rxbuf in recv() */
724 ecore_chain_consume(&txq->tx_pbl);
728 rte_pktmbuf_free(mbuf);
729 txq->sw_tx_ring[idx].mbuf = NULL;
731 PMD_TX_LOG(DEBUG, txq, "Freed tx packet\n");
733 ecore_chain_consume(&txq->tx_pbl);
739 qede_process_tx_compl(__rte_unused struct ecore_dev *edev,
740 struct qede_tx_queue *txq)
743 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
747 rte_compiler_barrier();
748 hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
749 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
750 sw_tx_cons = ecore_chain_get_cons_idx(&txq->tx_pbl);
751 PMD_TX_LOG(DEBUG, txq, "Tx Completions = %u\n",
752 abs(hw_bd_cons - sw_tx_cons));
754 while (hw_bd_cons != ecore_chain_get_cons_idx(&txq->tx_pbl))
755 qede_free_tx_pkt(txq);
758 static int qede_drain_txq(struct qede_dev *qdev,
759 struct qede_tx_queue *txq, bool allow_drain)
761 struct ecore_dev *edev = &qdev->edev;
764 while (txq->sw_tx_cons != txq->sw_tx_prod) {
765 qede_process_tx_compl(edev, txq);
768 DP_ERR(edev, "Tx queue[%u] is stuck,"
769 "requesting MCP to drain\n",
771 rc = qdev->ops->common->drain(edev);
774 return qede_drain_txq(qdev, txq, false);
776 DP_ERR(edev, "Timeout waiting for tx queue[%d]:"
777 "PROD=%d, CONS=%d\n",
778 txq->queue_id, txq->sw_tx_prod,
784 rte_compiler_barrier();
787 /* FW finished processing, wait for HW to transmit all tx packets */
793 /* Stops a given TX queue in the HW */
794 static int qede_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
796 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
797 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
798 struct ecore_hwfn *p_hwfn;
799 struct qede_tx_queue *txq;
803 if (tx_queue_id < eth_dev->data->nb_tx_queues) {
804 txq = eth_dev->data->tx_queues[tx_queue_id];
806 if (qede_drain_txq(qdev, txq, true))
807 return -1; /* For the lack of retcodes */
809 hwfn_index = tx_queue_id % edev->num_hwfns;
810 p_hwfn = &edev->hwfns[hwfn_index];
811 rc = ecore_eth_tx_queue_stop(p_hwfn, txq->handle);
812 if (rc != ECORE_SUCCESS) {
813 DP_ERR(edev, "TX queue %u stop fails\n", tx_queue_id);
816 qede_tx_queue_release_mbufs(txq);
817 qede_tx_queue_reset(qdev, txq);
818 eth_dev->data->tx_queue_state[tx_queue_id] =
819 RTE_ETH_QUEUE_STATE_STOPPED;
820 DP_INFO(edev, "TX queue %u stopped\n", tx_queue_id);
822 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
829 int qede_start_queues(struct rte_eth_dev *eth_dev)
831 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
836 rc = qede_rx_queue_start(eth_dev, id);
837 if (rc != ECORE_SUCCESS)
842 rc = qede_tx_queue_start(eth_dev, id);
843 if (rc != ECORE_SUCCESS)
850 void qede_stop_queues(struct rte_eth_dev *eth_dev)
852 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
855 /* Stopping RX/TX queues */
857 qede_tx_queue_stop(eth_dev, id);
861 qede_rx_queue_stop(eth_dev, id);
865 static inline bool qede_tunn_exist(uint16_t flag)
867 return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
868 PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
871 static inline uint8_t qede_check_tunn_csum_l3(uint16_t flag)
873 return !!((PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
874 PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT) & flag);
878 * qede_check_tunn_csum_l4:
880 * 1 : If L4 csum is enabled AND if the validation has failed.
883 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
885 if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
886 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
887 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
888 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
893 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
895 if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
896 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
897 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
898 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
903 /* Returns outer L2, L3 and L4 packet_type for tunneled packets */
904 static inline uint32_t qede_rx_cqe_to_pkt_type_outer(struct rte_mbuf *m)
906 uint32_t packet_type = RTE_PTYPE_UNKNOWN;
907 struct ether_hdr *eth_hdr;
908 struct ipv4_hdr *ipv4_hdr;
909 struct ipv6_hdr *ipv6_hdr;
910 struct vlan_hdr *vlan_hdr;
912 bool vlan_tagged = 0;
915 eth_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *);
916 len = sizeof(struct ether_hdr);
917 ethertype = rte_cpu_to_be_16(eth_hdr->ether_type);
919 /* Note: Valid only if VLAN stripping is disabled */
920 if (ethertype == ETHER_TYPE_VLAN) {
922 vlan_hdr = (struct vlan_hdr *)(eth_hdr + 1);
923 len += sizeof(struct vlan_hdr);
924 ethertype = rte_cpu_to_be_16(vlan_hdr->eth_proto);
927 if (ethertype == ETHER_TYPE_IPv4) {
928 packet_type |= RTE_PTYPE_L3_IPV4;
929 ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *, len);
930 if (ipv4_hdr->next_proto_id == IPPROTO_TCP)
931 packet_type |= RTE_PTYPE_L4_TCP;
932 else if (ipv4_hdr->next_proto_id == IPPROTO_UDP)
933 packet_type |= RTE_PTYPE_L4_UDP;
934 } else if (ethertype == ETHER_TYPE_IPv6) {
935 packet_type |= RTE_PTYPE_L3_IPV6;
936 ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct ipv6_hdr *, len);
937 if (ipv6_hdr->proto == IPPROTO_TCP)
938 packet_type |= RTE_PTYPE_L4_TCP;
939 else if (ipv6_hdr->proto == IPPROTO_UDP)
940 packet_type |= RTE_PTYPE_L4_UDP;
944 packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
946 packet_type |= RTE_PTYPE_L2_ETHER;
951 static inline uint32_t qede_rx_cqe_to_pkt_type_inner(uint16_t flags)
956 static const uint32_t
957 ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
958 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_INNER_L3_IPV4 |
959 RTE_PTYPE_INNER_L2_ETHER,
960 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_INNER_L3_IPV6 |
961 RTE_PTYPE_INNER_L2_ETHER,
962 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_INNER_L3_IPV4 |
963 RTE_PTYPE_INNER_L4_TCP |
964 RTE_PTYPE_INNER_L2_ETHER,
965 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_INNER_L3_IPV6 |
966 RTE_PTYPE_INNER_L4_TCP |
967 RTE_PTYPE_INNER_L2_ETHER,
968 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_INNER_L3_IPV4 |
969 RTE_PTYPE_INNER_L4_UDP |
970 RTE_PTYPE_INNER_L2_ETHER,
971 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_INNER_L3_IPV6 |
972 RTE_PTYPE_INNER_L4_UDP |
973 RTE_PTYPE_INNER_L2_ETHER,
974 /* Frags with no VLAN */
975 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_INNER_L3_IPV4 |
976 RTE_PTYPE_INNER_L4_FRAG |
977 RTE_PTYPE_INNER_L2_ETHER,
978 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_INNER_L3_IPV6 |
979 RTE_PTYPE_INNER_L4_FRAG |
980 RTE_PTYPE_INNER_L2_ETHER,
982 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
983 RTE_PTYPE_INNER_L2_ETHER_VLAN,
984 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
985 RTE_PTYPE_INNER_L2_ETHER_VLAN,
986 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
987 RTE_PTYPE_INNER_L4_TCP |
988 RTE_PTYPE_INNER_L2_ETHER_VLAN,
989 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
990 RTE_PTYPE_INNER_L4_TCP |
991 RTE_PTYPE_INNER_L2_ETHER_VLAN,
992 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
993 RTE_PTYPE_INNER_L4_UDP |
994 RTE_PTYPE_INNER_L2_ETHER_VLAN,
995 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
996 RTE_PTYPE_INNER_L4_UDP |
997 RTE_PTYPE_INNER_L2_ETHER_VLAN,
998 /* Frags with VLAN */
999 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV4 |
1000 RTE_PTYPE_INNER_L4_FRAG |
1001 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1002 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV6 |
1003 RTE_PTYPE_INNER_L4_FRAG |
1004 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1007 /* Bits (0..3) provides L3/L4 protocol type */
1008 /* Bits (4,5) provides frag and VLAN info */
1009 val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
1010 PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
1011 (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
1012 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) |
1013 (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1014 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) |
1015 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK <<
1016 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags;
1018 if (val < QEDE_PKT_TYPE_MAX)
1019 return ptype_lkup_tbl[val];
1021 return RTE_PTYPE_UNKNOWN;
1024 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
1029 static const uint32_t
1030 ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
1031 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L2_ETHER,
1032 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L2_ETHER,
1033 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4 |
1036 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6 |
1039 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4 |
1042 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6 |
1045 /* Frags with no VLAN */
1046 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_L3_IPV4 |
1049 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_L3_IPV6 |
1053 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_L3_IPV4 |
1054 RTE_PTYPE_L2_ETHER_VLAN,
1055 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_L3_IPV6 |
1056 RTE_PTYPE_L2_ETHER_VLAN,
1057 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_L3_IPV4 |
1059 RTE_PTYPE_L2_ETHER_VLAN,
1060 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_L3_IPV6 |
1062 RTE_PTYPE_L2_ETHER_VLAN,
1063 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_L3_IPV4 |
1065 RTE_PTYPE_L2_ETHER_VLAN,
1066 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_L3_IPV6 |
1068 RTE_PTYPE_L2_ETHER_VLAN,
1069 /* Frags with VLAN */
1070 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_L3_IPV4 |
1072 RTE_PTYPE_L2_ETHER_VLAN,
1073 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_L3_IPV6 |
1075 RTE_PTYPE_L2_ETHER_VLAN,
1078 /* Bits (0..3) provides L3/L4 protocol type */
1079 /* Bits (4,5) provides frag and VLAN info */
1080 val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
1081 PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
1082 (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
1083 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) |
1084 (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1085 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) |
1086 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK <<
1087 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags;
1089 if (val < QEDE_PKT_TYPE_MAX)
1090 return ptype_lkup_tbl[val];
1092 return RTE_PTYPE_UNKNOWN;
1095 static inline uint8_t
1096 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
1098 struct ipv4_hdr *ip;
1103 val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1104 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
1106 if (unlikely(val)) {
1107 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
1108 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
1109 ip = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1110 sizeof(struct ether_hdr));
1111 pkt_csum = ip->hdr_checksum;
1112 ip->hdr_checksum = 0;
1113 calc_csum = rte_ipv4_cksum(ip);
1114 ip->hdr_checksum = pkt_csum;
1115 return (calc_csum != pkt_csum);
1116 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
1123 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
1125 ecore_chain_consume(&rxq->rx_bd_ring);
1130 qede_reuse_page(__rte_unused struct qede_dev *qdev,
1131 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
1133 struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
1134 uint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1135 struct qede_rx_entry *curr_prod;
1136 dma_addr_t new_mapping;
1138 curr_prod = &rxq->sw_rx_ring[idx];
1139 *curr_prod = *curr_cons;
1141 new_mapping = rte_mbuf_data_iova_default(curr_prod->mbuf) +
1142 curr_prod->page_offset;
1144 rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
1145 rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
1151 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
1152 struct qede_dev *qdev, uint8_t count)
1154 struct qede_rx_entry *curr_cons;
1156 for (; count > 0; count--) {
1157 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
1158 qede_reuse_page(qdev, rxq, curr_cons);
1159 qede_rx_bd_ring_consume(rxq);
1164 qede_rx_process_tpa_cmn_cont_end_cqe(__rte_unused struct qede_dev *qdev,
1165 struct qede_rx_queue *rxq,
1166 uint8_t agg_index, uint16_t len)
1168 struct qede_agg_info *tpa_info;
1169 struct rte_mbuf *curr_frag; /* Pointer to currently filled TPA seg */
1172 /* Under certain conditions it is possible that FW may not consume
1173 * additional or new BD. So decision to consume the BD must be made
1174 * based on len_list[0].
1176 if (rte_le_to_cpu_16(len)) {
1177 tpa_info = &rxq->tpa_info[agg_index];
1178 cons_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1179 curr_frag = rxq->sw_rx_ring[cons_idx].mbuf;
1181 curr_frag->nb_segs = 1;
1182 curr_frag->pkt_len = rte_le_to_cpu_16(len);
1183 curr_frag->data_len = curr_frag->pkt_len;
1184 tpa_info->tpa_tail->next = curr_frag;
1185 tpa_info->tpa_tail = curr_frag;
1186 qede_rx_bd_ring_consume(rxq);
1187 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1188 PMD_RX_LOG(ERR, rxq, "mbuf allocation fails\n");
1189 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1190 rxq->rx_alloc_errors++;
1196 qede_rx_process_tpa_cont_cqe(struct qede_dev *qdev,
1197 struct qede_rx_queue *rxq,
1198 struct eth_fast_path_rx_tpa_cont_cqe *cqe)
1200 PMD_RX_LOG(INFO, rxq, "TPA cont[%d] - len [%d]\n",
1201 cqe->tpa_agg_index, rte_le_to_cpu_16(cqe->len_list[0]));
1202 /* only len_list[0] will have value */
1203 qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
1208 qede_rx_process_tpa_end_cqe(struct qede_dev *qdev,
1209 struct qede_rx_queue *rxq,
1210 struct eth_fast_path_rx_tpa_end_cqe *cqe)
1212 struct rte_mbuf *rx_mb; /* Pointer to head of the chained agg */
1214 qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
1216 /* Update total length and frags based on end TPA */
1217 rx_mb = rxq->tpa_info[cqe->tpa_agg_index].tpa_head;
1218 /* TODO: Add Sanity Checks */
1219 rx_mb->nb_segs = cqe->num_of_bds;
1220 rx_mb->pkt_len = cqe->total_packet_len;
1222 PMD_RX_LOG(INFO, rxq, "TPA End[%d] reason %d cqe_len %d nb_segs %d"
1223 " pkt_len %d\n", cqe->tpa_agg_index, cqe->end_reason,
1224 rte_le_to_cpu_16(cqe->len_list[0]), rx_mb->nb_segs,
1228 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
1233 static const uint32_t
1234 ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
1235 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
1236 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
1237 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
1238 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
1239 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
1240 RTE_PTYPE_TUNNEL_GENEVE,
1241 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
1242 RTE_PTYPE_TUNNEL_GRE,
1243 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
1244 RTE_PTYPE_TUNNEL_VXLAN,
1245 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
1246 RTE_PTYPE_TUNNEL_GENEVE,
1247 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
1248 RTE_PTYPE_TUNNEL_GRE,
1249 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
1250 RTE_PTYPE_TUNNEL_VXLAN,
1251 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
1252 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1253 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
1254 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1255 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
1256 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1257 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
1258 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1259 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
1260 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1261 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
1262 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1263 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
1264 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1265 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
1266 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1267 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
1268 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1269 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
1270 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1271 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
1272 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1273 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
1274 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1277 /* Cover bits[4-0] to include tunn_type and next protocol */
1278 val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
1279 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
1280 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
1281 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
1283 if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
1284 return ptype_tunn_lkup_tbl[val];
1286 return RTE_PTYPE_UNKNOWN;
1290 qede_process_sg_pkts(void *p_rxq, struct rte_mbuf *rx_mb,
1291 uint8_t num_segs, uint16_t pkt_len)
1293 struct qede_rx_queue *rxq = p_rxq;
1294 struct qede_dev *qdev = rxq->qdev;
1295 register struct rte_mbuf *seg1 = NULL;
1296 register struct rte_mbuf *seg2 = NULL;
1297 uint16_t sw_rx_index;
1302 cur_size = pkt_len > rxq->rx_buf_size ? rxq->rx_buf_size :
1304 if (unlikely(!cur_size)) {
1305 PMD_RX_LOG(ERR, rxq, "Length is 0 while %u BDs"
1306 " left for mapping jumbo\n", num_segs);
1307 qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
1310 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1311 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
1312 qede_rx_bd_ring_consume(rxq);
1313 pkt_len -= cur_size;
1314 seg2->data_len = cur_size;
1324 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1326 print_rx_bd_info(struct rte_mbuf *m, struct qede_rx_queue *rxq,
1329 PMD_RX_LOG(INFO, rxq,
1330 "len 0x%04x bf 0x%04x hash_val 0x%x"
1331 " ol_flags 0x%04lx l2=%s l3=%s l4=%s tunn=%s"
1332 " inner_l2=%s inner_l3=%s inner_l4=%s\n",
1333 m->data_len, bitfield, m->hash.rss,
1334 (unsigned long)m->ol_flags,
1335 rte_get_ptype_l2_name(m->packet_type),
1336 rte_get_ptype_l3_name(m->packet_type),
1337 rte_get_ptype_l4_name(m->packet_type),
1338 rte_get_ptype_tunnel_name(m->packet_type),
1339 rte_get_ptype_inner_l2_name(m->packet_type),
1340 rte_get_ptype_inner_l3_name(m->packet_type),
1341 rte_get_ptype_inner_l4_name(m->packet_type));
1346 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1348 struct qede_rx_queue *rxq = p_rxq;
1349 struct qede_dev *qdev = rxq->qdev;
1350 struct ecore_dev *edev = &qdev->edev;
1351 uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
1352 uint16_t rx_pkt = 0;
1353 union eth_rx_cqe *cqe;
1354 struct eth_fast_path_rx_reg_cqe *fp_cqe = NULL;
1355 register struct rte_mbuf *rx_mb = NULL;
1356 register struct rte_mbuf *seg1 = NULL;
1357 enum eth_rx_cqe_type cqe_type;
1358 uint16_t pkt_len = 0; /* Sum of all BD segments */
1359 uint16_t len; /* Length of first BD */
1360 uint8_t num_segs = 1;
1361 uint16_t preload_idx;
1362 uint16_t parse_flag;
1363 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1364 uint8_t bitfield_val;
1366 uint8_t tunn_parse_flag;
1368 struct eth_fast_path_rx_tpa_start_cqe *cqe_start_tpa;
1370 uint32_t packet_type;
1373 uint8_t offset, tpa_agg_idx, flags;
1374 struct qede_agg_info *tpa_info = NULL;
1377 hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
1378 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1382 if (hw_comp_cons == sw_comp_cons)
1385 while (sw_comp_cons != hw_comp_cons) {
1387 packet_type = RTE_PTYPE_UNKNOWN;
1389 tpa_start_flg = false;
1392 /* Get the CQE from the completion ring */
1394 (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
1395 cqe_type = cqe->fast_path_regular.type;
1396 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type);
1399 case ETH_RX_CQE_TYPE_REGULAR:
1400 fp_cqe = &cqe->fast_path_regular;
1402 case ETH_RX_CQE_TYPE_TPA_START:
1403 cqe_start_tpa = &cqe->fast_path_tpa_start;
1404 tpa_info = &rxq->tpa_info[cqe_start_tpa->tpa_agg_index];
1405 tpa_start_flg = true;
1406 /* Mark it as LRO packet */
1407 ol_flags |= PKT_RX_LRO;
1408 /* In split mode, seg_len is same as len_on_first_bd
1409 * and ext_bd_len_list will be empty since there are
1410 * no additional buffers
1412 PMD_RX_LOG(INFO, rxq,
1413 "TPA start[%d] - len_on_first_bd %d header %d"
1414 " [bd_list[0] %d], [seg_len %d]\n",
1415 cqe_start_tpa->tpa_agg_index,
1416 rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd),
1417 cqe_start_tpa->header_len,
1418 rte_le_to_cpu_16(cqe_start_tpa->ext_bd_len_list[0]),
1419 rte_le_to_cpu_16(cqe_start_tpa->seg_len));
1422 case ETH_RX_CQE_TYPE_TPA_CONT:
1423 qede_rx_process_tpa_cont_cqe(qdev, rxq,
1424 &cqe->fast_path_tpa_cont);
1426 case ETH_RX_CQE_TYPE_TPA_END:
1427 qede_rx_process_tpa_end_cqe(qdev, rxq,
1428 &cqe->fast_path_tpa_end);
1429 tpa_agg_idx = cqe->fast_path_tpa_end.tpa_agg_index;
1430 tpa_info = &rxq->tpa_info[tpa_agg_idx];
1431 rx_mb = rxq->tpa_info[tpa_agg_idx].tpa_head;
1433 case ETH_RX_CQE_TYPE_SLOW_PATH:
1434 PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n");
1435 ecore_eth_cqe_completion(
1436 &edev->hwfns[rxq->queue_id % edev->num_hwfns],
1437 (struct eth_slow_path_rx_cqe *)cqe);
1443 /* Get the data from the SW ring */
1444 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1445 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
1446 assert(rx_mb != NULL);
1448 /* Handle regular CQE or TPA start CQE */
1449 if (!tpa_start_flg) {
1450 parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);
1451 offset = fp_cqe->placement_offset;
1452 len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
1453 pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1454 vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1455 rss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash);
1456 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1457 bitfield_val = fp_cqe->bitfields;
1461 rte_le_to_cpu_16(cqe_start_tpa->pars_flags.flags);
1462 offset = cqe_start_tpa->placement_offset;
1463 /* seg_len = len_on_first_bd */
1464 len = rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd);
1465 vlan_tci = rte_le_to_cpu_16(cqe_start_tpa->vlan_tag);
1466 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1467 bitfield_val = cqe_start_tpa->bitfields;
1469 rss_hash = rte_le_to_cpu_32(cqe_start_tpa->rss_hash);
1471 if (qede_tunn_exist(parse_flag)) {
1472 PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n");
1473 if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1474 PMD_RX_LOG(ERR, rxq,
1475 "L4 csum failed, flags = 0x%x\n",
1477 rxq->rx_hw_errors++;
1478 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1480 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1483 if (unlikely(qede_check_tunn_csum_l3(parse_flag))) {
1484 PMD_RX_LOG(ERR, rxq,
1485 "Outer L3 csum failed, flags = 0x%x\n",
1487 rxq->rx_hw_errors++;
1488 ol_flags |= PKT_RX_EIP_CKSUM_BAD;
1490 ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1494 flags = cqe_start_tpa->tunnel_pars_flags.flags;
1496 flags = fp_cqe->tunnel_pars_flags.flags;
1497 tunn_parse_flag = flags;
1501 qede_rx_cqe_to_tunn_pkt_type(tunn_parse_flag);
1505 qede_rx_cqe_to_pkt_type_inner(parse_flag);
1507 /* Outer L3/L4 types is not available in CQE */
1508 packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1510 /* Outer L3/L4 types is not available in CQE.
1511 * Need to add offset to parse correctly,
1513 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1514 packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1516 packet_type |= qede_rx_cqe_to_pkt_type(parse_flag);
1519 /* Common handling for non-tunnel packets and for inner
1520 * headers in the case of tunnel.
1522 if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1523 PMD_RX_LOG(ERR, rxq,
1524 "L4 csum failed, flags = 0x%x\n",
1526 rxq->rx_hw_errors++;
1527 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1529 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1531 if (unlikely(qede_check_notunn_csum_l3(rx_mb, parse_flag))) {
1532 PMD_RX_LOG(ERR, rxq, "IP csum failed, flags = 0x%x\n",
1534 rxq->rx_hw_errors++;
1535 ol_flags |= PKT_RX_IP_CKSUM_BAD;
1537 ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1540 if (CQE_HAS_VLAN(parse_flag) ||
1541 CQE_HAS_OUTER_VLAN(parse_flag)) {
1542 /* Note: FW doesn't indicate Q-in-Q packet */
1543 ol_flags |= PKT_RX_VLAN;
1544 if (qdev->vlan_strip_flg) {
1545 ol_flags |= PKT_RX_VLAN_STRIPPED;
1546 rx_mb->vlan_tci = vlan_tci;
1551 if (qdev->rss_enable) {
1552 ol_flags |= PKT_RX_RSS_HASH;
1553 rx_mb->hash.rss = rss_hash;
1556 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1557 PMD_RX_LOG(ERR, rxq,
1558 "New buffer allocation failed,"
1559 "dropping incoming packet\n");
1560 qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
1561 rte_eth_devices[rxq->port_id].
1562 data->rx_mbuf_alloc_failed++;
1563 rxq->rx_alloc_errors++;
1566 qede_rx_bd_ring_consume(rxq);
1568 if (!tpa_start_flg && fp_cqe->bd_num > 1) {
1569 PMD_RX_LOG(DEBUG, rxq, "Jumbo-over-BD packet: %02x BDs"
1570 " len on first: %04x Total Len: %04x",
1571 fp_cqe->bd_num, len, pkt_len);
1572 num_segs = fp_cqe->bd_num - 1;
1574 if (qede_process_sg_pkts(p_rxq, seg1, num_segs,
1577 for (j = 0; j < num_segs; j++) {
1578 if (qede_alloc_rx_buffer(rxq)) {
1579 PMD_RX_LOG(ERR, rxq,
1580 "Buffer allocation failed");
1581 rte_eth_devices[rxq->port_id].
1582 data->rx_mbuf_alloc_failed++;
1583 rxq->rx_alloc_errors++;
1589 rxq->rx_segs++; /* for the first segment */
1591 /* Prefetch next mbuf while processing current one. */
1592 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1593 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1595 /* Update rest of the MBUF fields */
1596 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1597 rx_mb->port = rxq->port_id;
1598 rx_mb->ol_flags = ol_flags;
1599 rx_mb->data_len = len;
1600 rx_mb->packet_type = packet_type;
1601 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1602 print_rx_bd_info(rx_mb, rxq, bitfield_val);
1604 if (!tpa_start_flg) {
1605 rx_mb->nb_segs = fp_cqe->bd_num;
1606 rx_mb->pkt_len = pkt_len;
1608 /* store ref to the updated mbuf */
1609 tpa_info->tpa_head = rx_mb;
1610 tpa_info->tpa_tail = tpa_info->tpa_head;
1612 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
1614 if (!tpa_start_flg) {
1615 rx_pkts[rx_pkt] = rx_mb;
1619 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1620 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1621 if (rx_pkt == nb_pkts) {
1622 PMD_RX_LOG(DEBUG, rxq,
1623 "Budget reached nb_pkts=%u received=%u",
1629 qede_update_rx_prod(qdev, rxq);
1631 rxq->rcv_pkts += rx_pkt;
1633 PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
1639 /* Populate scatter gather buffer descriptor fields */
1640 static inline uint16_t
1641 qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg,
1642 struct eth_tx_2nd_bd **bd2, struct eth_tx_3rd_bd **bd3,
1645 struct qede_tx_queue *txq = p_txq;
1646 struct eth_tx_bd *tx_bd = NULL;
1648 uint16_t nb_segs = 0;
1650 /* Check for scattered buffers */
1652 if (start_seg == 0) {
1654 *bd2 = (struct eth_tx_2nd_bd *)
1655 ecore_chain_produce(&txq->tx_pbl);
1656 memset(*bd2, 0, sizeof(struct eth_tx_2nd_bd));
1659 mapping = rte_mbuf_data_iova(m_seg);
1660 QEDE_BD_SET_ADDR_LEN(*bd2, mapping, m_seg->data_len);
1661 PMD_TX_LOG(DEBUG, txq, "BD2 len %04x", m_seg->data_len);
1662 } else if (start_seg == 1) {
1664 *bd3 = (struct eth_tx_3rd_bd *)
1665 ecore_chain_produce(&txq->tx_pbl);
1666 memset(*bd3, 0, sizeof(struct eth_tx_3rd_bd));
1669 mapping = rte_mbuf_data_iova(m_seg);
1670 QEDE_BD_SET_ADDR_LEN(*bd3, mapping, m_seg->data_len);
1671 PMD_TX_LOG(DEBUG, txq, "BD3 len %04x", m_seg->data_len);
1673 tx_bd = (struct eth_tx_bd *)
1674 ecore_chain_produce(&txq->tx_pbl);
1675 memset(tx_bd, 0, sizeof(*tx_bd));
1677 mapping = rte_mbuf_data_iova(m_seg);
1678 QEDE_BD_SET_ADDR_LEN(tx_bd, mapping, m_seg->data_len);
1679 PMD_TX_LOG(DEBUG, txq, "BD len %04x", m_seg->data_len);
1682 m_seg = m_seg->next;
1685 /* Return total scattered buffers */
1689 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1691 print_tx_bd_info(struct qede_tx_queue *txq,
1692 struct eth_tx_1st_bd *bd1,
1693 struct eth_tx_2nd_bd *bd2,
1694 struct eth_tx_3rd_bd *bd3,
1695 uint64_t tx_ol_flags)
1697 char ol_buf[256] = { 0 }; /* for verbose prints */
1700 PMD_TX_LOG(INFO, txq,
1701 "BD1: nbytes=0x%04x nbds=0x%04x bd_flags=0x%04x bf=0x%04x",
1702 rte_cpu_to_le_16(bd1->nbytes), bd1->data.nbds,
1703 bd1->data.bd_flags.bitfields,
1704 rte_cpu_to_le_16(bd1->data.bitfields));
1706 PMD_TX_LOG(INFO, txq,
1707 "BD2: nbytes=0x%04x bf1=0x%04x bf2=0x%04x tunn_ip=0x%04x\n",
1708 rte_cpu_to_le_16(bd2->nbytes), bd2->data.bitfields1,
1709 bd2->data.bitfields2, bd2->data.tunn_ip_size);
1711 PMD_TX_LOG(INFO, txq,
1712 "BD3: nbytes=0x%04x bf=0x%04x MSS=0x%04x "
1713 "tunn_l4_hdr_start_offset_w=0x%04x tunn_hdr_size=0x%04x\n",
1714 rte_cpu_to_le_16(bd3->nbytes),
1715 rte_cpu_to_le_16(bd3->data.bitfields),
1716 rte_cpu_to_le_16(bd3->data.lso_mss),
1717 bd3->data.tunn_l4_hdr_start_offset_w,
1718 bd3->data.tunn_hdr_size_w);
1720 rte_get_tx_ol_flag_list(tx_ol_flags, ol_buf, sizeof(ol_buf));
1721 PMD_TX_LOG(INFO, txq, "TX offloads = %s\n", ol_buf);
1725 /* TX prepare to check packets meets TX conditions */
1727 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1728 qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
1731 struct qede_tx_queue *txq = p_txq;
1733 qede_xmit_prep_pkts(__rte_unused void *p_txq, struct rte_mbuf **tx_pkts,
1740 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1744 for (i = 0; i < nb_pkts; i++) {
1746 ol_flags = m->ol_flags;
1747 if (ol_flags & PKT_TX_TCP_SEG) {
1748 if (m->nb_segs >= ETH_TX_MAX_BDS_PER_LSO_PACKET) {
1749 rte_errno = -EINVAL;
1752 /* TBD: confirm its ~9700B for both ? */
1753 if (m->tso_segsz > ETH_TX_MAX_NON_LSO_PKT_LEN) {
1754 rte_errno = -EINVAL;
1758 if (m->nb_segs >= ETH_TX_MAX_BDS_PER_NON_LSO_PACKET) {
1759 rte_errno = -EINVAL;
1763 if (ol_flags & QEDE_TX_OFFLOAD_NOTSUP_MASK) {
1764 /* We support only limited tunnel protocols */
1765 if (ol_flags & PKT_TX_TUNNEL_MASK) {
1768 temp = ol_flags & PKT_TX_TUNNEL_MASK;
1769 if (temp == PKT_TX_TUNNEL_VXLAN ||
1770 temp == PKT_TX_TUNNEL_GENEVE ||
1771 temp == PKT_TX_TUNNEL_MPLSINUDP ||
1772 temp == PKT_TX_TUNNEL_GRE)
1776 rte_errno = -ENOTSUP;
1780 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1781 ret = rte_validate_tx_offload(m);
1789 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1790 if (unlikely(i != nb_pkts))
1791 PMD_TX_LOG(ERR, txq, "TX prepare failed for %u\n",
1797 #define MPLSINUDP_HDR_SIZE (12)
1799 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1801 qede_mpls_tunn_tx_sanity_check(struct rte_mbuf *mbuf,
1802 struct qede_tx_queue *txq)
1804 if (((mbuf->outer_l2_len + mbuf->outer_l3_len) / 2) > 0xff)
1805 PMD_TX_LOG(ERR, txq, "tunn_l4_hdr_start_offset overflow\n");
1806 if (((mbuf->outer_l2_len + mbuf->outer_l3_len +
1807 MPLSINUDP_HDR_SIZE) / 2) > 0xff)
1808 PMD_TX_LOG(ERR, txq, "tunn_hdr_size overflow\n");
1809 if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE) / 2) >
1810 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK)
1811 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
1812 if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2) >
1813 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
1814 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
1819 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1821 struct qede_tx_queue *txq = p_txq;
1822 struct qede_dev *qdev = txq->qdev;
1823 struct ecore_dev *edev = &qdev->edev;
1824 struct rte_mbuf *mbuf;
1825 struct rte_mbuf *m_seg = NULL;
1826 uint16_t nb_tx_pkts;
1830 uint16_t nb_pkt_sent = 0;
1834 __rte_unused bool tunn_flg;
1835 bool tunn_ipv6_ext_flg;
1836 struct eth_tx_1st_bd *bd1;
1837 struct eth_tx_2nd_bd *bd2;
1838 struct eth_tx_3rd_bd *bd3;
1839 uint64_t tx_ol_flags;
1843 uint8_t bd1_bd_flags_bf;
1852 uint8_t tunn_l4_hdr_start_offset;
1853 uint8_t tunn_hdr_size;
1854 uint8_t inner_l2_hdr_size;
1855 uint16_t inner_l4_hdr_offset;
1857 if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
1858 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
1859 nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
1860 qede_process_tx_compl(edev, txq);
1863 nb_tx_pkts = nb_pkts;
1864 bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1865 while (nb_tx_pkts--) {
1866 /* Init flags/values */
1876 bd1_bd_flags_bf = 0;
1881 mplsoudp_flg = false;
1882 tunn_ipv6_ext_flg = false;
1884 tunn_l4_hdr_start_offset = 0;
1889 /* Check minimum TX BDS availability against available BDs */
1890 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs))
1893 tx_ol_flags = mbuf->ol_flags;
1894 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
1896 /* TX prepare would have already checked supported tunnel Tx
1897 * offloads. Don't rely on pkt_type marked by Rx, instead use
1898 * tx_ol_flags to decide.
1900 tunn_flg = !!(tx_ol_flags & PKT_TX_TUNNEL_MASK);
1903 /* Check against max which is Tunnel IPv6 + ext */
1904 if (unlikely(txq->nb_tx_avail <
1905 ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT))
1908 /* First indicate its a tunnel pkt */
1909 bd1_bf |= ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
1910 ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1911 /* Legacy FW had flipped behavior in regard to this bit
1912 * i.e. it needed to set to prevent FW from touching
1913 * encapsulated packets when it didn't need to.
1915 if (unlikely(txq->is_legacy)) {
1917 ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1920 /* Outer IP checksum offload */
1921 if (tx_ol_flags & (PKT_TX_OUTER_IP_CKSUM |
1922 PKT_TX_OUTER_IPV4)) {
1924 ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
1925 ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
1929 * Currently, only inner checksum offload in MPLS-in-UDP
1930 * tunnel with one MPLS label is supported. Both outer
1931 * and inner layers lengths need to be provided in
1934 if ((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
1935 PKT_TX_TUNNEL_MPLSINUDP) {
1936 mplsoudp_flg = true;
1937 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1938 qede_mpls_tunn_tx_sanity_check(mbuf, txq);
1940 /* Outer L4 offset in two byte words */
1941 tunn_l4_hdr_start_offset =
1942 (mbuf->outer_l2_len + mbuf->outer_l3_len) / 2;
1943 /* Tunnel header size in two byte words */
1944 tunn_hdr_size = (mbuf->outer_l2_len +
1945 mbuf->outer_l3_len +
1946 MPLSINUDP_HDR_SIZE) / 2;
1947 /* Inner L2 header size in two byte words */
1948 inner_l2_hdr_size = (mbuf->l2_len -
1949 MPLSINUDP_HDR_SIZE) / 2;
1950 /* Inner L4 header offset from the beggining
1951 * of inner packet in two byte words
1953 inner_l4_hdr_offset = (mbuf->l2_len -
1954 MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2;
1956 /* Inner L2 size and address type */
1957 bd2_bf1 |= (inner_l2_hdr_size &
1958 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK) <<
1959 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT;
1960 bd2_bf1 |= (UNICAST_ADDRESS &
1961 ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK) <<
1962 ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT;
1963 /* Treated as IPv6+Ext */
1965 1 << ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT;
1967 /* Mark inner IPv6 if present */
1968 if (tx_ol_flags & PKT_TX_IPV6)
1970 1 << ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT;
1972 /* Inner L4 offsets */
1973 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
1974 (tx_ol_flags & (PKT_TX_UDP_CKSUM |
1975 PKT_TX_TCP_CKSUM))) {
1976 /* Determines if BD3 is needed */
1977 tunn_ipv6_ext_flg = true;
1978 if ((tx_ol_flags & PKT_TX_L4_MASK) ==
1981 1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
1984 /* TODO other pseudo checksum modes are
1988 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
1989 ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT;
1990 bd2_bf2 |= (inner_l4_hdr_offset &
1991 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK) <<
1992 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
1994 } /* End MPLSoUDP */
1995 } /* End Tunnel handling */
1997 if (tx_ol_flags & PKT_TX_TCP_SEG) {
1999 if (unlikely(txq->nb_tx_avail <
2000 ETH_TX_MIN_BDS_PER_LSO_PKT))
2002 /* For LSO, packet header and payload must reside on
2003 * buffers pointed by different BDs. Using BD1 for HDR
2004 * and BD2 onwards for data.
2006 hdr_size = mbuf->l2_len + mbuf->l3_len + mbuf->l4_len;
2008 hdr_size += mbuf->outer_l2_len +
2011 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT;
2013 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
2014 /* PKT_TX_TCP_SEG implies PKT_TX_TCP_CKSUM */
2016 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
2017 mss = rte_cpu_to_le_16(mbuf->tso_segsz);
2018 /* Using one header BD */
2019 bd3_bf |= rte_cpu_to_le_16(1 <<
2020 ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
2022 if (unlikely(txq->nb_tx_avail <
2023 ETH_TX_MIN_BDS_PER_NON_LSO_PKT))
2026 (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
2027 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
2030 /* Descriptor based VLAN insertion */
2031 if (tx_ol_flags & PKT_TX_VLAN_PKT) {
2032 vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
2034 1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
2037 /* Offload the IP checksum in the hardware */
2038 if (tx_ol_flags & PKT_TX_IP_CKSUM) {
2040 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
2041 /* There's no DPDK flag to request outer-L4 csum
2042 * offload. But in the case of tunnel if inner L3 or L4
2043 * csum offload is requested then we need to force
2044 * recalculation of L4 tunnel header csum also.
2046 if (tunn_flg && ((tx_ol_flags & PKT_TX_TUNNEL_MASK) !=
2047 PKT_TX_TUNNEL_GRE)) {
2049 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
2050 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
2054 /* L4 checksum offload (tcp or udp) */
2055 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
2056 (tx_ol_flags & (PKT_TX_UDP_CKSUM | PKT_TX_TCP_CKSUM))) {
2058 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
2059 /* There's no DPDK flag to request outer-L4 csum
2060 * offload. But in the case of tunnel if inner L3 or L4
2061 * csum offload is requested then we need to force
2062 * recalculation of L4 tunnel header csum also.
2066 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
2067 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
2071 /* Fill the entry in the SW ring and the BDs in the FW ring */
2073 txq->sw_tx_ring[idx].mbuf = mbuf;
2076 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
2077 memset(bd1, 0, sizeof(struct eth_tx_1st_bd));
2080 /* Map MBUF linear data for DMA and set in the BD1 */
2081 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2083 bd1->data.bitfields = rte_cpu_to_le_16(bd1_bf);
2084 bd1->data.bd_flags.bitfields = bd1_bd_flags_bf;
2085 bd1->data.vlan = vlan;
2087 if (lso_flg || mplsoudp_flg) {
2088 bd2 = (struct eth_tx_2nd_bd *)ecore_chain_produce
2090 memset(bd2, 0, sizeof(struct eth_tx_2nd_bd));
2094 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2097 QEDE_BD_SET_ADDR_LEN(bd2, (hdr_size +
2098 rte_mbuf_data_iova(mbuf)),
2099 mbuf->data_len - hdr_size);
2100 bd2->data.bitfields1 = rte_cpu_to_le_16(bd2_bf1);
2102 bd2->data.bitfields2 =
2103 rte_cpu_to_le_16(bd2_bf2);
2105 bd2->data.tunn_ip_size =
2106 rte_cpu_to_le_16(mbuf->outer_l3_len);
2109 if (lso_flg || (mplsoudp_flg && tunn_ipv6_ext_flg)) {
2110 bd3 = (struct eth_tx_3rd_bd *)
2111 ecore_chain_produce(&txq->tx_pbl);
2112 memset(bd3, 0, sizeof(struct eth_tx_3rd_bd));
2114 bd3->data.bitfields = rte_cpu_to_le_16(bd3_bf);
2116 bd3->data.lso_mss = mss;
2118 bd3->data.tunn_l4_hdr_start_offset_w =
2119 tunn_l4_hdr_start_offset;
2120 bd3->data.tunn_hdr_size_w =
2126 /* Handle fragmented MBUF */
2129 /* Encode scatter gather buffer descriptors if required */
2130 nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3, nbds - 1);
2131 bd1->data.nbds = nbds + nb_frags;
2133 txq->nb_tx_avail -= bd1->data.nbds;
2135 rte_prefetch0(txq->sw_tx_ring[TX_PROD(txq)].mbuf);
2137 rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2138 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2139 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);
2145 /* Write value of prod idx into bd_prod */
2146 txq->tx_db.data.bd_prod = bd_prod;
2148 rte_compiler_barrier();
2149 DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
2152 /* Check again for Tx completions */
2153 qede_process_tx_compl(edev, txq);
2155 PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d",
2156 nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());
2162 qede_rxtx_pkts_dummy(__rte_unused void *p_rxq,
2163 __rte_unused struct rte_mbuf **pkts,
2164 __rte_unused uint16_t nb_pkts)
2170 /* this function does a fake walk through over completion queue
2171 * to calculate number of BDs used by HW.
2172 * At the end, it restores the state of completion queue.
2175 qede_parse_fp_cqe(struct qede_rx_queue *rxq)
2177 uint16_t hw_comp_cons, sw_comp_cons, bd_count = 0;
2178 union eth_rx_cqe *cqe, *orig_cqe = NULL;
2180 hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
2181 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
2183 if (hw_comp_cons == sw_comp_cons)
2186 /* Get the CQE from the completion ring */
2187 cqe = (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
2190 while (sw_comp_cons != hw_comp_cons) {
2191 switch (cqe->fast_path_regular.type) {
2192 case ETH_RX_CQE_TYPE_REGULAR:
2193 bd_count += cqe->fast_path_regular.bd_num;
2195 case ETH_RX_CQE_TYPE_TPA_END:
2196 bd_count += cqe->fast_path_tpa_end.num_of_bds;
2203 (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
2204 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
2207 /* revert comp_ring to original state */
2208 ecore_chain_set_cons(&rxq->rx_comp_ring, sw_comp_cons, orig_cqe);
2214 qede_rx_descriptor_status(void *p_rxq, uint16_t offset)
2216 uint16_t hw_bd_cons, sw_bd_cons, sw_bd_prod;
2217 uint16_t produced, consumed;
2218 struct qede_rx_queue *rxq = p_rxq;
2220 if (offset > rxq->nb_rx_desc)
2223 sw_bd_cons = ecore_chain_get_cons_idx(&rxq->rx_bd_ring);
2224 sw_bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
2226 /* find BDs used by HW from completion queue elements */
2227 hw_bd_cons = sw_bd_cons + qede_parse_fp_cqe(rxq);
2229 if (hw_bd_cons < sw_bd_cons)
2230 /* wraparound case */
2231 consumed = (0xffff - sw_bd_cons) + hw_bd_cons;
2233 consumed = hw_bd_cons - sw_bd_cons;
2235 if (offset <= consumed)
2236 return RTE_ETH_RX_DESC_DONE;
2238 if (sw_bd_prod < sw_bd_cons)
2239 /* wraparound case */
2240 produced = (0xffff - sw_bd_cons) + sw_bd_prod;
2242 produced = sw_bd_prod - sw_bd_cons;
2244 if (offset <= produced)
2245 return RTE_ETH_RX_DESC_AVAIL;
2247 return RTE_ETH_RX_DESC_UNAVAIL;