drivers/net/qede/qede_rxtx.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_rxtx.h"
  10
  11 static bool gro_disable = 1;    /* mod_param */
  12
  13 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
  14 {
  15         struct rte_mbuf *new_mb = NULL;
  16         struct eth_rx_bd *rx_bd;
  17         dma_addr_t mapping;
  18         uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
  19
  20         new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
  21         if (unlikely(!new_mb)) {
  22                 PMD_RX_LOG(ERR, rxq,
  23                            "Failed to allocate rx buffer "
  24                            "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
  25                            idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
  26                            rte_mempool_avail_count(rxq->mb_pool),
  27                            rte_mempool_in_use_count(rxq->mb_pool));
  28                 return -ENOMEM;
  29         }
  30         rxq->sw_rx_ring[idx].mbuf = new_mb;
  31         rxq->sw_rx_ring[idx].page_offset = 0;
  32         mapping = rte_mbuf_data_dma_addr_default(new_mb);
  33         /* Advance PROD and get BD pointer */
  34         rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
  35         rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
  36         rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
  37         rxq->sw_rx_prod++;
  38         return 0;
  39 }
  40
  41 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
  42 {
  43         uint16_t i;
  44
  45         if (rxq->sw_rx_ring != NULL) {
  46                 for (i = 0; i < rxq->nb_rx_desc; i++) {
  47                         if (rxq->sw_rx_ring[i].mbuf != NULL) {
  48                                 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
  49                                 rxq->sw_rx_ring[i].mbuf = NULL;
  50                         }
  51                 }
  52         }
  53 }
  54
  55 void qede_rx_queue_release(void *rx_queue)
  56 {
  57         struct qede_rx_queue *rxq = rx_queue;
  58
  59         if (rxq != NULL) {
  60                 qede_rx_queue_release_mbufs(rxq);
  61                 rte_free(rxq->sw_rx_ring);
  62                 rxq->sw_rx_ring = NULL;
  63                 rte_free(rxq);
  64                 rxq = NULL;
  65         }
  66 }
  67
  68 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
  69 {
  70         unsigned int i;
  71
  72         PMD_TX_LOG(DEBUG, txq, "releasing %u mbufs\n", txq->nb_tx_desc);
  73
  74         if (txq->sw_tx_ring) {
  75                 for (i = 0; i < txq->nb_tx_desc; i++) {
  76                         if (txq->sw_tx_ring[i].mbuf) {
  77                                 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf);
  78                                 txq->sw_tx_ring[i].mbuf = NULL;
  79                         }
  80                 }
  81         }
  82 }
  83
  84 int
  85 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  86                     uint16_t nb_desc, unsigned int socket_id,
  87                     const struct rte_eth_rxconf *rx_conf,
  88                     struct rte_mempool *mp)
  89 {
  90         struct qede_dev *qdev = dev->data->dev_private;
  91         struct ecore_dev *edev = &qdev->edev;
  92         struct rte_eth_dev_data *eth_data = dev->data;
  93         struct qede_rx_queue *rxq;
  94         uint16_t pkt_len = (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len;
  95         size_t size;
  96         uint16_t data_size;
  97         int rc;
  98         int i;
  99
 100         PMD_INIT_FUNC_TRACE(edev);
 101
 102         /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
 103         if (!rte_is_power_of_2(nb_desc)) {
 104                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 105                           nb_desc);
 106                 return -EINVAL;
 107         }
 108
 109         /* Free memory prior to re-allocation if needed... */
 110         if (dev->data->rx_queues[queue_idx] != NULL) {
 111                 qede_rx_queue_release(dev->data->rx_queues[queue_idx]);
 112                 dev->data->rx_queues[queue_idx] = NULL;
 113         }
 114
 115         /* First allocate the rx queue data structure */
 116         rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
 117                                  RTE_CACHE_LINE_SIZE, socket_id);
 118
 119         if (!rxq) {
 120                 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
 121                           socket_id);
 122                 return -ENOMEM;
 123         }
 124
 125         rxq->qdev = qdev;
 126         rxq->mb_pool = mp;
 127         rxq->nb_rx_desc = nb_desc;
 128         rxq->queue_id = queue_idx;
 129         rxq->port_id = dev->data->port_id;
 130
 131         /* Sanity check */
 132         data_size = (uint16_t)rte_pktmbuf_data_room_size(mp) -
 133                                 RTE_PKTMBUF_HEADROOM;
 134
 135         if (pkt_len > data_size && !dev->data->scattered_rx) {
 136                 DP_ERR(edev, "MTU %u should not exceed dataroom %u\n",
 137                        pkt_len, data_size);
 138                 rte_free(rxq);
 139                 return -EINVAL;
 140         }
 141
 142         if (dev->data->scattered_rx)
 143                 rxq->rx_buf_size = data_size;
 144         else
 145                 rxq->rx_buf_size = pkt_len + QEDE_ETH_OVERHEAD;
 146
 147         qdev->mtu = pkt_len;
 148
 149         DP_INFO(edev, "MTU = %u ; RX buffer = %u\n",
 150                 qdev->mtu, rxq->rx_buf_size);
 151
 152         if (pkt_len > ETHER_MAX_LEN) {
 153                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
 154                 DP_NOTICE(edev, false, "jumbo frame enabled\n");
 155         } else {
 156                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
 157         }
 158
 159         /* Allocate the parallel driver ring for Rx buffers */
 160         size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
 161         rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
 162                                              RTE_CACHE_LINE_SIZE, socket_id);
 163         if (!rxq->sw_rx_ring) {
 164                 DP_NOTICE(edev, false,
 165                           "Unable to alloc memory for sw_rx_ring on socket %u\n",
 166                           socket_id);
 167                 rte_free(rxq);
 168                 rxq = NULL;
 169                 return -ENOMEM;
 170         }
 171
 172         /* Allocate FW Rx ring  */
 173         rc = qdev->ops->common->chain_alloc(edev,
 174                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 175                                             ECORE_CHAIN_MODE_NEXT_PTR,
 176                                             ECORE_CHAIN_CNT_TYPE_U16,
 177                                             rxq->nb_rx_desc,
 178                                             sizeof(struct eth_rx_bd),
 179                                             &rxq->rx_bd_ring);
 180
 181         if (rc != ECORE_SUCCESS) {
 182                 DP_NOTICE(edev, false,
 183                           "Unable to alloc memory for rxbd ring on socket %u\n",
 184                           socket_id);
 185                 rte_free(rxq->sw_rx_ring);
 186                 rxq->sw_rx_ring = NULL;
 187                 rte_free(rxq);
 188                 rxq = NULL;
 189                 return -ENOMEM;
 190         }
 191
 192         /* Allocate FW completion ring */
 193         rc = qdev->ops->common->chain_alloc(edev,
 194                                             ECORE_CHAIN_USE_TO_CONSUME,
 195                                             ECORE_CHAIN_MODE_PBL,
 196                                             ECORE_CHAIN_CNT_TYPE_U16,
 197                                             rxq->nb_rx_desc,
 198                                             sizeof(union eth_rx_cqe),
 199                                             &rxq->rx_comp_ring);
 200
 201         if (rc != ECORE_SUCCESS) {
 202                 DP_NOTICE(edev, false,
 203                           "Unable to alloc memory for cqe ring on socket %u\n",
 204                           socket_id);
 205                 /* TBD: Freeing RX BD ring */
 206                 rte_free(rxq->sw_rx_ring);
 207                 rxq->sw_rx_ring = NULL;
 208                 rte_free(rxq);
 209                 return -ENOMEM;
 210         }
 211
 212         /* Allocate buffers for the Rx ring */
 213         for (i = 0; i < rxq->nb_rx_desc; i++) {
 214                 rc = qede_alloc_rx_buffer(rxq);
 215                 if (rc) {
 216                         DP_NOTICE(edev, false,
 217                                   "RX buffer allocation failed at idx=%d\n", i);
 218                         goto err4;
 219                 }
 220         }
 221
 222         dev->data->rx_queues[queue_idx] = rxq;
 223
 224         DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
 225                   queue_idx, nb_desc, qdev->mtu, socket_id);
 226
 227         return 0;
 228 err4:
 229         qede_rx_queue_release(rxq);
 230         return -ENOMEM;
 231 }
 232
 233 void qede_tx_queue_release(void *tx_queue)
 234 {
 235         struct qede_tx_queue *txq = tx_queue;
 236
 237         if (txq != NULL) {
 238                 qede_tx_queue_release_mbufs(txq);
 239                 if (txq->sw_tx_ring) {
 240                         rte_free(txq->sw_tx_ring);
 241                         txq->sw_tx_ring = NULL;
 242                 }
 243                 rte_free(txq);
 244         }
 245         txq = NULL;
 246 }
 247
 248 int
 249 qede_tx_queue_setup(struct rte_eth_dev *dev,
 250                     uint16_t queue_idx,
 251                     uint16_t nb_desc,
 252                     unsigned int socket_id,
 253                     const struct rte_eth_txconf *tx_conf)
 254 {
 255         struct qede_dev *qdev = dev->data->dev_private;
 256         struct ecore_dev *edev = &qdev->edev;
 257         struct qede_tx_queue *txq;
 258         int rc;
 259
 260         PMD_INIT_FUNC_TRACE(edev);
 261
 262         if (!rte_is_power_of_2(nb_desc)) {
 263                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 264                        nb_desc);
 265                 return -EINVAL;
 266         }
 267
 268         /* Free memory prior to re-allocation if needed... */
 269         if (dev->data->tx_queues[queue_idx] != NULL) {
 270                 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
 271                 dev->data->tx_queues[queue_idx] = NULL;
 272         }
 273
 274         txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
 275                                  RTE_CACHE_LINE_SIZE, socket_id);
 276
 277         if (txq == NULL) {
 278                 DP_ERR(edev,
 279                        "Unable to allocate memory for txq on socket %u",
 280                        socket_id);
 281                 return -ENOMEM;
 282         }
 283
 284         txq->nb_tx_desc = nb_desc;
 285         txq->qdev = qdev;
 286         txq->port_id = dev->data->port_id;
 287
 288         rc = qdev->ops->common->chain_alloc(edev,
 289                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 290                                             ECORE_CHAIN_MODE_PBL,
 291                                             ECORE_CHAIN_CNT_TYPE_U16,
 292                                             txq->nb_tx_desc,
 293                                             sizeof(union eth_tx_bd_types),
 294                                             &txq->tx_pbl);
 295         if (rc != ECORE_SUCCESS) {
 296                 DP_ERR(edev,
 297                        "Unable to allocate memory for txbd ring on socket %u",
 298                        socket_id);
 299                 qede_tx_queue_release(txq);
 300                 return -ENOMEM;
 301         }
 302
 303         /* Allocate software ring */
 304         txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
 305                                              (sizeof(struct qede_tx_entry) *
 306                                               txq->nb_tx_desc),
 307                                              RTE_CACHE_LINE_SIZE, socket_id);
 308
 309         if (!txq->sw_tx_ring) {
 310                 DP_ERR(edev,
 311                        "Unable to allocate memory for txbd ring on socket %u",
 312                        socket_id);
 313                 qede_tx_queue_release(txq);
 314                 return -ENOMEM;
 315         }
 316
 317         txq->queue_id = queue_idx;
 318
 319         txq->nb_tx_avail = txq->nb_tx_desc;
 320
 321         txq->tx_free_thresh =
 322             tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
 323             (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
 324
 325         dev->data->tx_queues[queue_idx] = txq;
 326
 327         DP_INFO(edev,
 328                   "txq %u num_desc %u tx_free_thresh %u socket %u\n",
 329                   queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
 330
 331         return 0;
 332 }
 333
 334 /* This function inits fp content and resets the SB, RXQ and TXQ arrays */
 335 static void qede_init_fp(struct qede_dev *qdev)
 336 {
 337         struct qede_fastpath *fp;
 338         uint8_t i, rss_id, tc;
 339         int fp_rx = qdev->fp_num_rx, rxq = 0, txq = 0;
 340
 341         memset((void *)qdev->fp_array, 0, (QEDE_QUEUE_CNT(qdev) *
 342                                            sizeof(*qdev->fp_array)));
 343         memset((void *)qdev->sb_array, 0, (QEDE_QUEUE_CNT(qdev) *
 344                                            sizeof(*qdev->sb_array)));
 345         for_each_queue(i) {
 346                 fp = &qdev->fp_array[i];
 347                 if (fp_rx) {
 348                         fp->type = QEDE_FASTPATH_RX;
 349                         fp_rx--;
 350                 } else{
 351                         fp->type = QEDE_FASTPATH_TX;
 352                 }
 353                 fp->qdev = qdev;
 354                 fp->id = i;
 355                 fp->sb_info = &qdev->sb_array[i];
 356                 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d", "qdev", i);
 357         }
 358
 359         qdev->gro_disable = gro_disable;
 360 }
 361
 362 void qede_free_fp_arrays(struct qede_dev *qdev)
 363 {
 364         /* It asseumes qede_free_mem_load() is called before */
 365         if (qdev->fp_array != NULL) {
 366                 rte_free(qdev->fp_array);
 367                 qdev->fp_array = NULL;
 368         }
 369
 370         if (qdev->sb_array != NULL) {
 371                 rte_free(qdev->sb_array);
 372                 qdev->sb_array = NULL;
 373         }
 374 }
 375
 376 int qede_alloc_fp_array(struct qede_dev *qdev)
 377 {
 378         struct qede_fastpath *fp;
 379         struct ecore_dev *edev = &qdev->edev;
 380         int i;
 381
 382         qdev->fp_array = rte_calloc("fp", QEDE_QUEUE_CNT(qdev),
 383                                     sizeof(*qdev->fp_array),
 384                                     RTE_CACHE_LINE_SIZE);
 385
 386         if (!qdev->fp_array) {
 387                 DP_ERR(edev, "fp array allocation failed\n");
 388                 return -ENOMEM;
 389         }
 390
 391         qdev->sb_array = rte_calloc("sb", QEDE_QUEUE_CNT(qdev),
 392                                     sizeof(*qdev->sb_array),
 393                                     RTE_CACHE_LINE_SIZE);
 394
 395         if (!qdev->sb_array) {
 396                 DP_ERR(edev, "sb array allocation failed\n");
 397                 rte_free(qdev->fp_array);
 398                 return -ENOMEM;
 399         }
 400
 401         return 0;
 402 }
 403
 404 /* This function allocates fast-path status block memory */
 405 static int
 406 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
 407                   uint16_t sb_id)
 408 {
 409         struct ecore_dev *edev = &qdev->edev;
 410         struct status_block *sb_virt;
 411         dma_addr_t sb_phys;
 412         int rc;
 413
 414         sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys, sizeof(*sb_virt));
 415
 416         if (!sb_virt) {
 417                 DP_ERR(edev, "Status block allocation failed\n");
 418                 return -ENOMEM;
 419         }
 420
 421         rc = qdev->ops->common->sb_init(edev, sb_info,
 422                                         sb_virt, sb_phys, sb_id,
 423                                         QED_SB_TYPE_L2_QUEUE);
 424         if (rc) {
 425                 DP_ERR(edev, "Status block initialization failed\n");
 426                 /* TBD: No dma_free_coherent possible */
 427                 return rc;
 428         }
 429
 430         return 0;
 431 }
 432
 433 int qede_alloc_fp_resc(struct qede_dev *qdev)
 434 {
 435         struct ecore_dev *edev = &qdev->edev;
 436         struct qede_fastpath *fp;
 437         uint32_t num_sbs;
 438         int rc, i;
 439
 440         if (IS_VF(edev))
 441                 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
 442         else
 443                 num_sbs = (ecore_cxt_get_proto_cid_count
 444                           (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL)) / 2;
 445
 446         if (num_sbs == 0) {
 447                 DP_ERR(edev, "No status blocks available\n");
 448                 return -EINVAL;
 449         }
 450
 451         if (qdev->fp_array)
 452                 qede_free_fp_arrays(qdev);
 453
 454         rc = qede_alloc_fp_array(qdev);
 455         if (rc != 0)
 456                 return rc;
 457
 458         qede_init_fp(qdev);
 459
 460         for (i = 0; i < QEDE_QUEUE_CNT(qdev); i++) {
 461                 fp = &qdev->fp_array[i];
 462                 if (qede_alloc_mem_sb(qdev, fp->sb_info, i % num_sbs)) {
 463                         qede_free_fp_arrays(qdev);
 464                         return -ENOMEM;
 465                 }
 466         }
 467
 468         return 0;
 469 }
 470
 471 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
 472 {
 473         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 474
 475         qede_free_mem_load(eth_dev);
 476         qede_free_fp_arrays(qdev);
 477 }
 478
 479 static inline void
 480 qede_update_rx_prod(struct qede_dev *edev, struct qede_rx_queue *rxq)
 481 {
 482         uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
 483         uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
 484         struct eth_rx_prod_data rx_prods = { 0 };
 485
 486         /* Update producers */
 487         rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
 488         rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
 489
 490         /* Make sure that the BD and SGE data is updated before updating the
 491          * producers since FW might read the BD/SGE right after the producer
 492          * is updated.
 493          */
 494         rte_wmb();
 495
 496         internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
 497                         (uint32_t *)&rx_prods);
 498
 499         /* mmiowb is needed to synchronize doorbell writes from more than one
 500          * processor. It guarantees that the write arrives to the device before
 501          * the napi lock is released and another qede_poll is called (possibly
 502          * on another CPU). Without this barrier, the next doorbell can bypass
 503          * this doorbell. This is applicable to IA64/Altix systems.
 504          */
 505         rte_wmb();
 506
 507         PMD_RX_LOG(DEBUG, rxq, "bd_prod %u  cqe_prod %u\n", bd_prod, cqe_prod);
 508 }
 509
 510 static int qede_start_queues(struct rte_eth_dev *eth_dev, bool clear_stats)
 511 {
 512         struct qede_dev *qdev = eth_dev->data->dev_private;
 513         struct ecore_dev *edev = &qdev->edev;
 514         struct ecore_queue_start_common_params q_params;
 515         struct qed_dev_info *qed_info = &qdev->dev_info.common;
 516         struct qed_update_vport_params vport_update_params;
 517         struct qede_tx_queue *txq;
 518         struct qede_fastpath *fp;
 519         dma_addr_t p_phys_table;
 520         int txq_index;
 521         uint16_t page_cnt;
 522         int vlan_removal_en = 1;
 523         int rc, tc, i;
 524
 525         for_each_queue(i) {
 526                 fp = &qdev->fp_array[i];
 527                 if (fp->type & QEDE_FASTPATH_RX) {
 528                         p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->
 529                                                                 rx_comp_ring);
 530                         page_cnt = ecore_chain_get_page_cnt(&fp->rxq->
 531                                                                 rx_comp_ring);
 532
 533                         memset(&q_params, 0, sizeof(q_params));
 534                         q_params.queue_id = i;
 535                         q_params.vport_id = 0;
 536                         q_params.sb = fp->sb_info->igu_sb_id;
 537                         q_params.sb_idx = RX_PI;
 538
 539                         ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
 540
 541                         rc = qdev->ops->q_rx_start(edev, i, &q_params,
 542                                            fp->rxq->rx_buf_size,
 543                                            fp->rxq->rx_bd_ring.p_phys_addr,
 544                                            p_phys_table,
 545                                            page_cnt,
 546                                            &fp->rxq->hw_rxq_prod_addr);
 547                         if (rc) {
 548                                 DP_ERR(edev, "Start rxq #%d failed %d\n",
 549                                        fp->rxq->queue_id, rc);
 550                                 return rc;
 551                         }
 552
 553                         fp->rxq->hw_cons_ptr =
 554                                         &fp->sb_info->sb_virt->pi_array[RX_PI];
 555
 556                         qede_update_rx_prod(qdev, fp->rxq);
 557                 }
 558
 559                 if (!(fp->type & QEDE_FASTPATH_TX))
 560                         continue;
 561                 for (tc = 0; tc < qdev->num_tc; tc++) {
 562                         txq = fp->txqs[tc];
 563                         txq_index = tc * QEDE_RSS_COUNT(qdev) + i;
 564
 565                         p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
 566                         page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
 567
 568                         memset(&q_params, 0, sizeof(q_params));
 569                         q_params.queue_id = txq->queue_id;
 570                         q_params.vport_id = 0;
 571                         q_params.sb = fp->sb_info->igu_sb_id;
 572                         q_params.sb_idx = TX_PI(tc);
 573
 574                         rc = qdev->ops->q_tx_start(edev, i, &q_params,
 575                                                    p_phys_table,
 576                                                    page_cnt, /* **pp_doorbell */
 577                                                    &txq->doorbell_addr);
 578                         if (rc) {
 579                                 DP_ERR(edev, "Start txq %u failed %d\n",
 580                                        txq_index, rc);
 581                                 return rc;
 582                         }
 583
 584                         txq->hw_cons_ptr =
 585                             &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
 586                         SET_FIELD(txq->tx_db.data.params,
 587                                   ETH_DB_DATA_DEST, DB_DEST_XCM);
 588                         SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
 589                                   DB_AGG_CMD_SET);
 590                         SET_FIELD(txq->tx_db.data.params,
 591                                   ETH_DB_DATA_AGG_VAL_SEL,
 592                                   DQ_XCM_ETH_TX_BD_PROD_CMD);
 593
 594                         txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
 595                 }
 596         }
 597
 598         /* Prepare and send the vport enable */
 599         memset(&vport_update_params, 0, sizeof(vport_update_params));
 600         /* Update MTU via vport update */
 601         vport_update_params.mtu = qdev->mtu;
 602         vport_update_params.vport_id = 0;
 603         vport_update_params.update_vport_active_flg = 1;
 604         vport_update_params.vport_active_flg = 1;
 605
 606         /* @DPDK */
 607         if (qed_info->mf_mode == MF_NPAR && qed_info->tx_switching) {
 608                 /* TBD: Check SRIOV enabled for VF */
 609                 vport_update_params.update_tx_switching_flg = 1;
 610                 vport_update_params.tx_switching_flg = 1;
 611         }
 612
 613         rc = qdev->ops->vport_update(edev, &vport_update_params);
 614         if (rc) {
 615                 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
 616                 return rc;
 617         }
 618
 619         return 0;
 620 }
 621
 622 static bool qede_tunn_exist(uint16_t flag)
 623 {
 624         return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
 625                     PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
 626 }
 627
 628 /*
 629  * qede_check_tunn_csum_l4:
 630  * Returns:
 631  * 1 : If L4 csum is enabled AND if the validation has failed.
 632  * 0 : Otherwise
 633  */
 634 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
 635 {
 636         if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
 637              PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
 638                 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
 639                         PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
 640
 641         return 0;
 642 }
 643
 644 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
 645 {
 646         if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
 647              PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
 648                 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
 649                            PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
 650
 651         return 0;
 652 }
 653
 654 static inline uint8_t
 655 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
 656 {
 657         struct ipv4_hdr *ip;
 658         uint16_t pkt_csum;
 659         uint16_t calc_csum;
 660         uint16_t val;
 661
 662         val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
 663                 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
 664
 665         if (unlikely(val)) {
 666                 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
 667                 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
 668                         ip = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
 669                                            sizeof(struct ether_hdr));
 670                         pkt_csum = ip->hdr_checksum;
 671                         ip->hdr_checksum = 0;
 672                         calc_csum = rte_ipv4_cksum(ip);
 673                         ip->hdr_checksum = pkt_csum;
 674                         return (calc_csum != pkt_csum);
 675                 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
 676                         return 1;
 677                 }
 678         }
 679         return 0;
 680 }
 681
 682 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
 683 {
 684         ecore_chain_consume(&rxq->rx_bd_ring);
 685         rxq->sw_rx_cons++;
 686 }
 687
 688 static inline void
 689 qede_reuse_page(struct qede_dev *qdev,
 690                 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
 691 {
 692         struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
 693         uint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 694         struct qede_rx_entry *curr_prod;
 695         dma_addr_t new_mapping;
 696
 697         curr_prod = &rxq->sw_rx_ring[idx];
 698         *curr_prod = *curr_cons;
 699
 700         new_mapping = rte_mbuf_data_dma_addr_default(curr_prod->mbuf) +
 701                       curr_prod->page_offset;
 702
 703         rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
 704         rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
 705
 706         rxq->sw_rx_prod++;
 707 }
 708
 709 static inline void
 710 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
 711                         struct qede_dev *qdev, uint8_t count)
 712 {
 713         struct qede_rx_entry *curr_cons;
 714
 715         for (; count > 0; count--) {
 716                 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
 717                 qede_reuse_page(qdev, rxq, curr_cons);
 718                 qede_rx_bd_ring_consume(rxq);
 719         }
 720 }
 721
 722 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
 723 {
 724         uint16_t val;
 725
 726         /* Lookup table */
 727         static const uint32_t
 728         ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
 729                 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4,
 730                 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6,
 731                 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
 732                 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
 733                 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
 734                 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
 735         };
 736
 737         /* Bits (0..3) provides L3/L4 protocol type */
 738         val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
 739                PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
 740                (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
 741                 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT)) & flags;
 742
 743         if (val < QEDE_PKT_TYPE_MAX)
 744                 return ptype_lkup_tbl[val] | RTE_PTYPE_L2_ETHER;
 745         else
 746                 return RTE_PTYPE_UNKNOWN;
 747 }
 748
 749 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
 750 {
 751         uint32_t val;
 752
 753         /* Lookup table */
 754         static const uint32_t
 755         ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
 756                 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
 757                 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
 758                 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
 759                 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
 760                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
 761                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
 762                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
 763                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
 764                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
 765                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
 766                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
 767                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
 768                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
 769                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
 770                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
 771                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
 772                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
 773                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
 774                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
 775                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
 776                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
 777                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
 778                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
 779                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
 780                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
 781                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
 782                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
 783                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
 784                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
 785                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
 786                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
 787                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
 788                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
 789                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
 790                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
 791                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
 792                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
 793                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
 794                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
 795                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
 796         };
 797
 798         /* Cover bits[4-0] to include tunn_type and next protocol */
 799         val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
 800                 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
 801                 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
 802                 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
 803
 804         if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
 805                 return ptype_tunn_lkup_tbl[val];
 806         else
 807                 return RTE_PTYPE_UNKNOWN;
 808 }
 809
 810
 811 int qede_process_sg_pkts(void *p_rxq,  struct rte_mbuf *rx_mb,
 812                          int num_segs, uint16_t pkt_len)
 813 {
 814         struct qede_rx_queue *rxq = p_rxq;
 815         struct qede_dev *qdev = rxq->qdev;
 816         struct ecore_dev *edev = &qdev->edev;
 817         uint16_t sw_rx_index, cur_size;
 818
 819         register struct rte_mbuf *seg1 = NULL;
 820         register struct rte_mbuf *seg2 = NULL;
 821
 822         seg1 = rx_mb;
 823         while (num_segs) {
 824                 cur_size = pkt_len > rxq->rx_buf_size ?
 825                                 rxq->rx_buf_size : pkt_len;
 826                 if (!cur_size) {
 827                         PMD_RX_LOG(DEBUG, rxq,
 828                                    "SG packet, len and num BD mismatch\n");
 829                         qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
 830                         return -EINVAL;
 831                 }
 832
 833                 if (qede_alloc_rx_buffer(rxq)) {
 834                         uint8_t index;
 835
 836                         PMD_RX_LOG(DEBUG, rxq, "Buffer allocation failed\n");
 837                         index = rxq->port_id;
 838                         rte_eth_devices[index].data->rx_mbuf_alloc_failed++;
 839                         rxq->rx_alloc_errors++;
 840                         return -ENOMEM;
 841                 }
 842
 843                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 844                 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
 845                 qede_rx_bd_ring_consume(rxq);
 846                 pkt_len -= cur_size;
 847                 seg2->data_len = cur_size;
 848                 seg1->next = seg2;
 849                 seg1 = seg1->next;
 850                 num_segs--;
 851                 rxq->rx_segs++;
 852                 continue;
 853         }
 854         seg1 = NULL;
 855
 856         if (pkt_len)
 857                 PMD_RX_LOG(DEBUG, rxq,
 858                            "Mapped all BDs of jumbo, but still have %d bytes\n",
 859                            pkt_len);
 860
 861         return ECORE_SUCCESS;
 862 }
 863
 864 uint16_t
 865 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 866 {
 867         struct qede_rx_queue *rxq = p_rxq;
 868         struct qede_dev *qdev = rxq->qdev;
 869         struct ecore_dev *edev = &qdev->edev;
 870         struct qede_fastpath *fp = &qdev->fp_array[rxq->queue_id];
 871         uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
 872         uint16_t rx_pkt = 0;
 873         union eth_rx_cqe *cqe;
 874         struct eth_fast_path_rx_reg_cqe *fp_cqe;
 875         register struct rte_mbuf *rx_mb = NULL;
 876         register struct rte_mbuf *seg1 = NULL;
 877         enum eth_rx_cqe_type cqe_type;
 878         uint16_t len, pad, preload_idx, pkt_len, parse_flag;
 879         uint8_t csum_flag, num_segs;
 880         enum rss_hash_type htype;
 881         uint8_t tunn_parse_flag;
 882         int ret;
 883
 884         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
 885         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
 886
 887         rte_rmb();
 888
 889         if (hw_comp_cons == sw_comp_cons)
 890                 return 0;
 891
 892         while (sw_comp_cons != hw_comp_cons) {
 893                 /* Get the CQE from the completion ring */
 894                 cqe =
 895                     (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
 896                 cqe_type = cqe->fast_path_regular.type;
 897
 898                 if (unlikely(cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH)) {
 899                         PMD_RX_LOG(DEBUG, rxq, "Got a slowath CQE\n");
 900
 901                         qdev->ops->eth_cqe_completion(edev, fp->id,
 902                                 (struct eth_slow_path_rx_cqe *)cqe);
 903                         goto next_cqe;
 904                 }
 905
 906                 /* Get the data from the SW ring */
 907                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 908                 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
 909                 assert(rx_mb != NULL);
 910
 911                 /* non GRO */
 912                 fp_cqe = &cqe->fast_path_regular;
 913
 914                 len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
 915                 pad = fp_cqe->placement_offset;
 916                 assert((len + pad) <= rx_mb->buf_len);
 917
 918                 PMD_RX_LOG(DEBUG, rxq,
 919                            "CQE type = 0x%x, flags = 0x%x, vlan = 0x%x"
 920                            " len = %u, parsing_flags = %d\n",
 921                            cqe_type, fp_cqe->bitfields,
 922                            rte_le_to_cpu_16(fp_cqe->vlan_tag),
 923                            len, rte_le_to_cpu_16(fp_cqe->pars_flags.flags));
 924
 925                 /* If this is an error packet then drop it */
 926                 parse_flag =
 927                     rte_le_to_cpu_16(cqe->fast_path_regular.pars_flags.flags);
 928
 929                 rx_mb->ol_flags = 0;
 930
 931                 if (qede_tunn_exist(parse_flag)) {
 932                         PMD_RX_LOG(DEBUG, rxq, "Rx tunneled packet\n");
 933                         if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
 934                                 PMD_RX_LOG(ERR, rxq,
 935                                             "L4 csum failed, flags = 0x%x\n",
 936                                             parse_flag);
 937                                 rxq->rx_hw_errors++;
 938                                 rx_mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
 939                         } else {
 940                                 tunn_parse_flag =
 941                                                 fp_cqe->tunnel_pars_flags.flags;
 942                                 rx_mb->packet_type =
 943                                         qede_rx_cqe_to_tunn_pkt_type(
 944                                                         tunn_parse_flag);
 945                         }
 946                 } else {
 947                         PMD_RX_LOG(DEBUG, rxq, "Rx non-tunneled packet\n");
 948                         if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
 949                                 PMD_RX_LOG(ERR, rxq,
 950                                             "L4 csum failed, flags = 0x%x\n",
 951                                             parse_flag);
 952                                 rxq->rx_hw_errors++;
 953                                 rx_mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
 954                         } else if (unlikely(qede_check_notunn_csum_l3(rx_mb,
 955                                                         parse_flag))) {
 956                                 PMD_RX_LOG(ERR, rxq,
 957                                            "IP csum failed, flags = 0x%x\n",
 958                                            parse_flag);
 959                                 rxq->rx_hw_errors++;
 960                                 rx_mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
 961                         } else {
 962                                 rx_mb->packet_type =
 963                                         qede_rx_cqe_to_pkt_type(parse_flag);
 964                         }
 965                 }
 966
 967                 PMD_RX_LOG(INFO, rxq, "packet_type 0x%x\n", rx_mb->packet_type);
 968
 969                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
 970                         PMD_RX_LOG(ERR, rxq,
 971                                    "New buffer allocation failed,"
 972                                    "dropping incoming packet\n");
 973                         qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
 974                         rte_eth_devices[rxq->port_id].
 975                             data->rx_mbuf_alloc_failed++;
 976                         rxq->rx_alloc_errors++;
 977                         break;
 978                 }
 979
 980                 qede_rx_bd_ring_consume(rxq);
 981
 982                 if (fp_cqe->bd_num > 1) {
 983                         pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
 984                         num_segs = fp_cqe->bd_num - 1;
 985
 986                         rxq->rx_segs++;
 987
 988                         pkt_len -= len;
 989                         seg1 = rx_mb;
 990                         ret = qede_process_sg_pkts(p_rxq, seg1, num_segs,
 991                                                    pkt_len);
 992                         if (ret != ECORE_SUCCESS) {
 993                                 qede_recycle_rx_bd_ring(rxq, qdev,
 994                                                         fp_cqe->bd_num);
 995                                 goto next_cqe;
 996                         }
 997                 }
 998
 999                 /* Prefetch next mbuf while processing current one. */
1000                 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1001                 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1002
1003                 /* Update rest of the MBUF fields */
1004                 rx_mb->data_off = pad + RTE_PKTMBUF_HEADROOM;
1005                 rx_mb->nb_segs = fp_cqe->bd_num;
1006                 rx_mb->data_len = len;
1007                 rx_mb->pkt_len = fp_cqe->pkt_len;
1008                 rx_mb->port = rxq->port_id;
1009
1010                 htype = (uint8_t)GET_FIELD(fp_cqe->bitfields,
1011                                 ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
1012                 if (qdev->rss_enable && htype) {
1013                         rx_mb->ol_flags |= PKT_RX_RSS_HASH;
1014                         rx_mb->hash.rss = rte_le_to_cpu_32(fp_cqe->rss_hash);
1015                         PMD_RX_LOG(DEBUG, rxq, "Hash result 0x%x\n",
1016                                    rx_mb->hash.rss);
1017                 }
1018
1019                 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
1020
1021                 if (CQE_HAS_VLAN(parse_flag)) {
1022                         rx_mb->vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1023                         rx_mb->ol_flags |= PKT_RX_VLAN_PKT;
1024                 }
1025
1026                 if (CQE_HAS_OUTER_VLAN(parse_flag)) {
1027                         /* FW does not provide indication of Outer VLAN tag,
1028                          * which is always stripped, so vlan_tci_outer is set
1029                          * to 0. Here vlan_tag represents inner VLAN tag.
1030                          */
1031                         rx_mb->vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1032                         rx_mb->ol_flags |= PKT_RX_QINQ_PKT;
1033                         rx_mb->vlan_tci_outer = 0;
1034                 }
1035
1036                 rx_pkts[rx_pkt] = rx_mb;
1037                 rx_pkt++;
1038 next_cqe:
1039                 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1040                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1041                 if (rx_pkt == nb_pkts) {
1042                         PMD_RX_LOG(DEBUG, rxq,
1043                                    "Budget reached nb_pkts=%u received=%u\n",
1044                                    rx_pkt, nb_pkts);
1045                         break;
1046                 }
1047         }
1048
1049         qede_update_rx_prod(qdev, rxq);
1050
1051         rxq->rcv_pkts += rx_pkt;
1052
1053         PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d\n", rx_pkt, rte_lcore_id());
1054
1055         return rx_pkt;
1056 }
1057
1058 static inline int
1059 qede_free_tx_pkt(struct ecore_dev *edev, struct qede_tx_queue *txq)
1060 {
1061         uint16_t nb_segs, idx = TX_CONS(txq);
1062         struct eth_tx_bd *tx_data_bd;
1063         struct rte_mbuf *mbuf = txq->sw_tx_ring[idx].mbuf;
1064
1065         if (unlikely(!mbuf)) {
1066                 PMD_TX_LOG(ERR, txq, "null mbuf\n");
1067                 PMD_TX_LOG(ERR, txq,
1068                            "tx_desc %u tx_avail %u tx_cons %u tx_prod %u\n",
1069                            txq->nb_tx_desc, txq->nb_tx_avail, idx,
1070                            TX_PROD(txq));
1071                 return -1;
1072         }
1073
1074         nb_segs = mbuf->nb_segs;
1075         while (nb_segs) {
1076                 /* It's like consuming rxbuf in recv() */
1077                 ecore_chain_consume(&txq->tx_pbl);
1078                 txq->nb_tx_avail++;
1079                 nb_segs--;
1080         }
1081         rte_pktmbuf_free(mbuf);
1082         txq->sw_tx_ring[idx].mbuf = NULL;
1083
1084         return 0;
1085 }
1086
1087 static inline uint16_t
1088 qede_process_tx_compl(struct ecore_dev *edev, struct qede_tx_queue *txq)
1089 {
1090         uint16_t tx_compl = 0;
1091         uint16_t hw_bd_cons;
1092
1093         hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
1094         rte_compiler_barrier();
1095
1096         while (hw_bd_cons != ecore_chain_get_cons_idx(&txq->tx_pbl)) {
1097                 if (qede_free_tx_pkt(edev, txq)) {
1098                         PMD_TX_LOG(ERR, txq,
1099                                    "hw_bd_cons = %u, chain_cons = %u\n",
1100                                    hw_bd_cons,
1101                                    ecore_chain_get_cons_idx(&txq->tx_pbl));
1102                         break;
1103                 }
1104                 txq->sw_tx_cons++;      /* Making TXD available */
1105                 tx_compl++;
1106         }
1107
1108         PMD_TX_LOG(DEBUG, txq, "Tx compl %u sw_tx_cons %u avail %u\n",
1109                    tx_compl, txq->sw_tx_cons, txq->nb_tx_avail);
1110         return tx_compl;
1111 }
1112
1113 /* Populate scatter gather buffer descriptor fields */
1114 static inline uint16_t qede_encode_sg_bd(struct qede_tx_queue *p_txq,
1115                                          struct rte_mbuf *m_seg,
1116                                          uint16_t count,
1117                                          struct eth_tx_1st_bd *bd1)
1118 {
1119         struct qede_tx_queue *txq = p_txq;
1120         struct eth_tx_2nd_bd *bd2 = NULL;
1121         struct eth_tx_3rd_bd *bd3 = NULL;
1122         struct eth_tx_bd *tx_bd = NULL;
1123         uint16_t nb_segs = count;
1124         dma_addr_t mapping;
1125
1126         /* Check for scattered buffers */
1127         while (m_seg) {
1128                 if (nb_segs == 1) {
1129                         bd2 = (struct eth_tx_2nd_bd *)
1130                                 ecore_chain_produce(&txq->tx_pbl);
1131                         memset(bd2, 0, sizeof(*bd2));
1132                         mapping = rte_mbuf_data_dma_addr(m_seg);
1133                         bd2->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
1134                         bd2->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
1135                         bd2->nbytes = rte_cpu_to_le_16(m_seg->data_len);
1136                 } else if (nb_segs == 2) {
1137                         bd3 = (struct eth_tx_3rd_bd *)
1138                                 ecore_chain_produce(&txq->tx_pbl);
1139                         memset(bd3, 0, sizeof(*bd3));
1140                         mapping = rte_mbuf_data_dma_addr(m_seg);
1141                         bd3->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
1142                         bd3->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
1143                         bd3->nbytes = rte_cpu_to_le_16(m_seg->data_len);
1144                 } else {
1145                         tx_bd = (struct eth_tx_bd *)
1146                                 ecore_chain_produce(&txq->tx_pbl);
1147                         memset(tx_bd, 0, sizeof(*tx_bd));
1148                         mapping = rte_mbuf_data_dma_addr(m_seg);
1149                         tx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
1150                         tx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
1151                         tx_bd->nbytes = rte_cpu_to_le_16(m_seg->data_len);
1152                 }
1153                 nb_segs++;
1154                 bd1->data.nbds = nb_segs;
1155                 m_seg = m_seg->next;
1156         }
1157
1158         /* Return total scattered buffers */
1159         return nb_segs;
1160 }
1161
1162 uint16_t
1163 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1164 {
1165         struct qede_tx_queue *txq = p_txq;
1166         struct qede_dev *qdev = txq->qdev;
1167         struct ecore_dev *edev = &qdev->edev;
1168         struct qede_fastpath *fp;
1169         struct eth_tx_1st_bd *bd1;
1170         struct rte_mbuf *m_seg = NULL;
1171         uint16_t nb_tx_pkts;
1172         uint16_t nb_pkt_sent = 0;
1173         uint16_t bd_prod;
1174         uint16_t idx;
1175         uint16_t tx_count;
1176         uint16_t nb_segs = 0;
1177
1178         fp = &qdev->fp_array[QEDE_RSS_COUNT(qdev) + txq->queue_id];
1179
1180         if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
1181                 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u\n",
1182                            nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
1183                 (void)qede_process_tx_compl(edev, txq);
1184         }
1185
1186         nb_tx_pkts = RTE_MIN(nb_pkts, (txq->nb_tx_avail /
1187                         ETH_TX_MAX_BDS_PER_NON_LSO_PACKET));
1188         if (unlikely(nb_tx_pkts == 0)) {
1189                 PMD_TX_LOG(DEBUG, txq, "Out of BDs nb_pkts=%u avail=%u\n",
1190                            nb_pkts, txq->nb_tx_avail);
1191                 return 0;
1192         }
1193
1194         tx_count = nb_tx_pkts;
1195         while (nb_tx_pkts--) {
1196                 /* Fill the entry in the SW ring and the BDs in the FW ring */
1197                 idx = TX_PROD(txq);
1198                 struct rte_mbuf *mbuf = *tx_pkts++;
1199
1200                 txq->sw_tx_ring[idx].mbuf = mbuf;
1201                 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
1202                 /* Zero init struct fields */
1203                 bd1->data.bd_flags.bitfields = 0;
1204                 bd1->data.bitfields = 0;
1205
1206                 bd1->data.bd_flags.bitfields =
1207                         1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
1208                 /* Map MBUF linear data for DMA and set in the first BD */
1209                 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_dma_addr(mbuf),
1210                                      mbuf->pkt_len);
1211
1212                 if (RTE_ETH_IS_TUNNEL_PKT(mbuf->packet_type)) {
1213                         PMD_TX_LOG(INFO, txq, "Tx tunnel packet\n");
1214                         /* First indicate its a tunnel pkt */
1215                         bd1->data.bd_flags.bitfields |=
1216                                 ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
1217                                 ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1218
1219                         /* Legacy FW had flipped behavior in regard to this bit
1220                          * i.e. it needed to set to prevent FW from touching
1221                          * encapsulated packets when it didn't need to.
1222                          */
1223                         if (unlikely(txq->is_legacy))
1224                                 bd1->data.bitfields ^=
1225                                         1 << ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1226
1227                         /* Outer IP checksum offload */
1228                         if (mbuf->ol_flags & PKT_TX_OUTER_IP_CKSUM) {
1229                                 PMD_TX_LOG(INFO, txq, "OuterIP csum offload\n");
1230                                 bd1->data.bd_flags.bitfields |=
1231                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
1232                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
1233                         }
1234
1235                         /* Outer UDP checksum offload */
1236                         bd1->data.bd_flags.bitfields |=
1237                                 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
1238                                 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
1239                 }
1240
1241                 /* Descriptor based VLAN insertion */
1242                 if (mbuf->ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1243                         PMD_TX_LOG(INFO, txq, "Insert VLAN 0x%x\n",
1244                                    mbuf->vlan_tci);
1245                         bd1->data.vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
1246                         bd1->data.bd_flags.bitfields |=
1247                             1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
1248                 }
1249
1250                 /* Offload the IP checksum in the hardware */
1251                 if (mbuf->ol_flags & PKT_TX_IP_CKSUM) {
1252                         PMD_TX_LOG(INFO, txq, "IP csum offload\n");
1253                         bd1->data.bd_flags.bitfields |=
1254                             1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1255                 }
1256
1257                 /* L4 checksum offload (tcp or udp) */
1258                 if (mbuf->ol_flags & (PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
1259                         PMD_TX_LOG(INFO, txq, "L4 csum offload\n");
1260                         bd1->data.bd_flags.bitfields |=
1261                             1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1262                         /* IPv6 + extn. -> later */
1263                 }
1264
1265                 /* Handle fragmented MBUF */
1266                 m_seg = mbuf->next;
1267                 nb_segs++;
1268                 bd1->data.nbds = nb_segs;
1269                 /* Encode scatter gather buffer descriptors if required */
1270                 nb_segs = qede_encode_sg_bd(txq, m_seg, nb_segs, bd1);
1271                 txq->nb_tx_avail = txq->nb_tx_avail - nb_segs;
1272                 nb_segs = 0;
1273                 txq->sw_tx_prod++;
1274                 rte_prefetch0(txq->sw_tx_ring[TX_PROD(txq)].mbuf);
1275                 bd_prod =
1276                     rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1277                 nb_pkt_sent++;
1278                 txq->xmit_pkts++;
1279         }
1280
1281         /* Write value of prod idx into bd_prod */
1282         txq->tx_db.data.bd_prod = bd_prod;
1283         rte_wmb();
1284         rte_compiler_barrier();
1285         DIRECT_REG_WR(edev, txq->doorbell_addr, txq->tx_db.raw);
1286         rte_wmb();
1287
1288         /* Check again for Tx completions */
1289         (void)qede_process_tx_compl(edev, txq);
1290
1291         PMD_TX_LOG(DEBUG, txq, "to_send=%u can_send=%u sent=%u core=%d\n",
1292                    nb_pkts, tx_count, nb_pkt_sent, rte_lcore_id());
1293
1294         return nb_pkt_sent;
1295 }
1296
1297 static void qede_init_fp_queue(struct rte_eth_dev *eth_dev)
1298 {
1299         struct qede_dev *qdev = eth_dev->data->dev_private;
1300         struct qede_fastpath *fp;
1301         uint8_t i, rss_id, txq_index, tc;
1302         int rxq = 0, txq = 0;
1303
1304         for_each_queue(i) {
1305                 fp = &qdev->fp_array[i];
1306                 if (fp->type & QEDE_FASTPATH_RX) {
1307                         fp->rxq = eth_dev->data->rx_queues[i];
1308                         fp->rxq->queue_id = rxq++;
1309                 }
1310
1311                 if (fp->type & QEDE_FASTPATH_TX) {
1312                         for (tc = 0; tc < qdev->num_tc; tc++) {
1313                                 txq_index = tc * QEDE_TSS_COUNT(qdev) + txq;
1314                                 fp->txqs[tc] =
1315                                         eth_dev->data->tx_queues[txq_index];
1316                                 fp->txqs[tc]->queue_id = txq_index;
1317                                 if (qdev->dev_info.is_legacy)
1318                                         fp->txqs[tc]->is_legacy = true;
1319                         }
1320                         txq++;
1321                 }
1322         }
1323 }
1324
1325 int qede_dev_start(struct rte_eth_dev *eth_dev)
1326 {
1327         struct qede_dev *qdev = eth_dev->data->dev_private;
1328         struct ecore_dev *edev = &qdev->edev;
1329         struct qed_link_output link_output;
1330         struct qede_fastpath *fp;
1331         int rc;
1332
1333         DP_INFO(edev, "Device state is %d\n", qdev->state);
1334
1335         if (qdev->state == QEDE_DEV_START) {
1336                 DP_INFO(edev, "Port is already started\n");
1337                 return 0;
1338         }
1339
1340         if (qdev->state == QEDE_DEV_CONFIG)
1341                 qede_init_fp_queue(eth_dev);
1342
1343         rc = qede_start_queues(eth_dev, true);
1344         if (rc) {
1345                 DP_ERR(edev, "Failed to start queues\n");
1346                 /* TBD: free */
1347                 return rc;
1348         }
1349
1350         /* Bring-up the link */
1351         qede_dev_set_link_state(eth_dev, true);
1352
1353         /* Reset ring */
1354         if (qede_reset_fp_rings(qdev))
1355                 return -ENOMEM;
1356
1357         /* Start/resume traffic */
1358         qdev->ops->fastpath_start(edev);
1359
1360         qdev->state = QEDE_DEV_START;
1361
1362         DP_INFO(edev, "dev_state is QEDE_DEV_START\n");
1363
1364         return 0;
1365 }
1366
1367 static int qede_drain_txq(struct qede_dev *qdev,
1368                           struct qede_tx_queue *txq, bool allow_drain)
1369 {
1370         struct ecore_dev *edev = &qdev->edev;
1371         int rc, cnt = 1000;
1372
1373         while (txq->sw_tx_cons != txq->sw_tx_prod) {
1374                 qede_process_tx_compl(edev, txq);
1375                 if (!cnt) {
1376                         if (allow_drain) {
1377                                 DP_NOTICE(edev, false,
1378                                           "Tx queue[%u] is stuck,"
1379                                           "requesting MCP to drain\n",
1380                                           txq->queue_id);
1381                                 rc = qdev->ops->common->drain(edev);
1382                                 if (rc)
1383                                         return rc;
1384                                 return qede_drain_txq(qdev, txq, false);
1385                         }
1386
1387                         DP_NOTICE(edev, false,
1388                                   "Timeout waiting for tx queue[%d]:"
1389                                   "PROD=%d, CONS=%d\n",
1390                                   txq->queue_id, txq->sw_tx_prod,
1391                                   txq->sw_tx_cons);
1392                         return -ENODEV;
1393                 }
1394                 cnt--;
1395                 DELAY(1000);
1396                 rte_compiler_barrier();
1397         }
1398
1399         /* FW finished processing, wait for HW to transmit all tx packets */
1400         DELAY(2000);
1401
1402         return 0;
1403 }
1404
1405 static int qede_stop_queues(struct qede_dev *qdev)
1406 {
1407         struct qed_update_vport_params vport_update_params;
1408         struct ecore_dev *edev = &qdev->edev;
1409         int rc, tc, i;
1410
1411         /* Disable the vport */
1412         memset(&vport_update_params, 0, sizeof(vport_update_params));
1413         vport_update_params.vport_id = 0;
1414         vport_update_params.update_vport_active_flg = 1;
1415         vport_update_params.vport_active_flg = 0;
1416         vport_update_params.update_rss_flg = 0;
1417
1418         DP_INFO(edev, "Deactivate vport\n");
1419
1420         rc = qdev->ops->vport_update(edev, &vport_update_params);
1421         if (rc) {
1422                 DP_ERR(edev, "Failed to update vport\n");
1423                 return rc;
1424         }
1425
1426         DP_INFO(edev, "Flushing tx queues\n");
1427
1428         /* Flush Tx queues. If needed, request drain from MCP */
1429         for_each_queue(i) {
1430                 struct qede_fastpath *fp = &qdev->fp_array[i];
1431
1432                 if (fp->type & QEDE_FASTPATH_TX) {
1433                         for (tc = 0; tc < qdev->num_tc; tc++) {
1434                                 struct qede_tx_queue *txq = fp->txqs[tc];
1435
1436                                 rc = qede_drain_txq(qdev, txq, true);
1437                                 if (rc)
1438                                         return rc;
1439                         }
1440                 }
1441         }
1442
1443         /* Stop all Queues in reverse order */
1444         for (i = QEDE_QUEUE_CNT(qdev) - 1; i >= 0; i--) {
1445                 struct qed_stop_rxq_params rx_params;
1446
1447                 /* Stop the Tx Queue(s) */
1448                 if (qdev->fp_array[i].type & QEDE_FASTPATH_TX) {
1449                         for (tc = 0; tc < qdev->num_tc; tc++) {
1450                                 struct qed_stop_txq_params tx_params;
1451                                 u8 val;
1452
1453                                 tx_params.rss_id = i;
1454                                 val = qdev->fp_array[i].txqs[tc]->queue_id;
1455                                 tx_params.tx_queue_id = val;
1456
1457                                 DP_INFO(edev, "Stopping tx queues\n");
1458                                 rc = qdev->ops->q_tx_stop(edev, &tx_params);
1459                                 if (rc) {
1460                                         DP_ERR(edev, "Failed to stop TXQ #%d\n",
1461                                                tx_params.tx_queue_id);
1462                                         return rc;
1463                                 }
1464                         }
1465                 }
1466
1467                 /* Stop the Rx Queue */
1468                 if (qdev->fp_array[i].type & QEDE_FASTPATH_RX) {
1469                         memset(&rx_params, 0, sizeof(rx_params));
1470                         rx_params.rss_id = i;
1471                         rx_params.rx_queue_id = qdev->fp_array[i].rxq->queue_id;
1472                         rx_params.eq_completion_only = 1;
1473
1474                         DP_INFO(edev, "Stopping rx queues\n");
1475
1476                         rc = qdev->ops->q_rx_stop(edev, &rx_params);
1477                         if (rc) {
1478                                 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
1479                                 return rc;
1480                         }
1481                 }
1482         }
1483
1484         return 0;
1485 }
1486
1487 int qede_reset_fp_rings(struct qede_dev *qdev)
1488 {
1489         struct qede_fastpath *fp;
1490         struct qede_tx_queue *txq;
1491         uint8_t tc;
1492         uint16_t id, i;
1493
1494         for_each_queue(id) {
1495                 fp = &qdev->fp_array[id];
1496
1497                 if (fp->type & QEDE_FASTPATH_RX) {
1498                         DP_INFO(&qdev->edev,
1499                                 "Reset FP chain for RSS %u\n", id);
1500                         qede_rx_queue_release_mbufs(fp->rxq);
1501                         ecore_chain_reset(&fp->rxq->rx_bd_ring);
1502                         ecore_chain_reset(&fp->rxq->rx_comp_ring);
1503                         fp->rxq->sw_rx_prod = 0;
1504                         fp->rxq->sw_rx_cons = 0;
1505                         *fp->rxq->hw_cons_ptr = 0;
1506                         for (i = 0; i < fp->rxq->nb_rx_desc; i++) {
1507                                 if (qede_alloc_rx_buffer(fp->rxq)) {
1508                                         DP_ERR(&qdev->edev,
1509                                                "RX buffer allocation failed\n");
1510                                         return -ENOMEM;
1511                                 }
1512                         }
1513                 }
1514                 if (fp->type & QEDE_FASTPATH_TX) {
1515                         for (tc = 0; tc < qdev->num_tc; tc++) {
1516                                 txq = fp->txqs[tc];
1517                                 qede_tx_queue_release_mbufs(txq);
1518                                 ecore_chain_reset(&txq->tx_pbl);
1519                                 txq->sw_tx_cons = 0;
1520                                 txq->sw_tx_prod = 0;
1521                                 *txq->hw_cons_ptr = 0;
1522                         }
1523                 }
1524         }
1525
1526         return 0;
1527 }
1528
1529 /* This function frees all memory of a single fp */
1530 void qede_free_mem_load(struct rte_eth_dev *eth_dev)
1531 {
1532         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1533         struct qede_fastpath *fp;
1534         uint16_t txq_idx;
1535         uint8_t id;
1536         uint8_t tc;
1537
1538         for_each_queue(id) {
1539                 fp = &qdev->fp_array[id];
1540                 if (fp->type & QEDE_FASTPATH_RX) {
1541                         if (!fp->rxq)
1542                                 continue;
1543                         qede_rx_queue_release(fp->rxq);
1544                         eth_dev->data->rx_queues[id] = NULL;
1545                 } else {
1546                         for (tc = 0; tc < qdev->num_tc; tc++) {
1547                                 if (!fp->txqs[tc])
1548                                         continue;
1549                                 txq_idx = fp->txqs[tc]->queue_id;
1550                                 qede_tx_queue_release(fp->txqs[tc]);
1551                                 eth_dev->data->tx_queues[txq_idx] = NULL;
1552                         }
1553                 }
1554         }
1555 }
1556
1557 void qede_dev_stop(struct rte_eth_dev *eth_dev)
1558 {
1559         struct qede_dev *qdev = eth_dev->data->dev_private;
1560         struct ecore_dev *edev = &qdev->edev;
1561
1562         DP_INFO(edev, "port %u\n", eth_dev->data->port_id);
1563
1564         if (qdev->state != QEDE_DEV_START) {
1565                 DP_INFO(edev, "Device not yet started\n");
1566                 return;
1567         }
1568
1569         if (qede_stop_queues(qdev))
1570                 DP_ERR(edev, "Didn't succeed to close queues\n");
1571
1572         DP_INFO(edev, "Stopped queues\n");
1573
1574         qdev->ops->fastpath_stop(edev);
1575
1576         /* Bring the link down */
1577         qede_dev_set_link_state(eth_dev, false);
1578
1579         qdev->state = QEDE_DEV_STOP;
1580
1581         DP_INFO(edev, "dev_state is QEDE_DEV_STOP\n");
1582 }