2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
10 #include "qede_rxtx.h"
12 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
14 struct rte_mbuf *new_mb = NULL;
15 struct eth_rx_bd *rx_bd;
17 uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
19 new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
20 if (unlikely(!new_mb)) {
22 "Failed to allocate rx buffer "
23 "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
24 idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
25 rte_mempool_avail_count(rxq->mb_pool),
26 rte_mempool_in_use_count(rxq->mb_pool));
29 rxq->sw_rx_ring[idx].mbuf = new_mb;
30 rxq->sw_rx_ring[idx].page_offset = 0;
31 mapping = rte_mbuf_data_iova_default(new_mb);
32 /* Advance PROD and get BD pointer */
33 rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
34 rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
35 rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
41 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
42 uint16_t nb_desc, unsigned int socket_id,
43 __rte_unused const struct rte_eth_rxconf *rx_conf,
44 struct rte_mempool *mp)
46 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
47 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
48 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
49 struct qede_rx_queue *rxq;
50 uint16_t max_rx_pkt_len;
55 PMD_INIT_FUNC_TRACE(edev);
57 /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
58 if (!rte_is_power_of_2(nb_desc)) {
59 DP_ERR(edev, "Ring size %u is not power of 2\n",
64 /* Free memory prior to re-allocation if needed... */
65 if (dev->data->rx_queues[queue_idx] != NULL) {
66 qede_rx_queue_release(dev->data->rx_queues[queue_idx]);
67 dev->data->rx_queues[queue_idx] = NULL;
70 /* First allocate the rx queue data structure */
71 rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
72 RTE_CACHE_LINE_SIZE, socket_id);
75 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
82 rxq->nb_rx_desc = nb_desc;
83 rxq->queue_id = queue_idx;
84 rxq->port_id = dev->data->port_id;
86 max_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len;
87 qdev->mtu = max_rx_pkt_len;
89 /* Fix up RX buffer size */
90 bufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
91 if ((rxmode->enable_scatter) ||
92 (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {
93 if (!dev->data->scattered_rx) {
94 DP_INFO(edev, "Forcing scatter-gather mode\n");
95 dev->data->scattered_rx = 1;
99 if (dev->data->scattered_rx)
100 rxq->rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
102 rxq->rx_buf_size = qdev->mtu + QEDE_ETH_OVERHEAD;
103 /* Align to cache-line size if needed */
104 rxq->rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rxq->rx_buf_size);
106 DP_INFO(edev, "mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\n",
107 qdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);
109 /* Allocate the parallel driver ring for Rx buffers */
110 size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
111 rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
112 RTE_CACHE_LINE_SIZE, socket_id);
113 if (!rxq->sw_rx_ring) {
114 DP_ERR(edev, "Memory allocation fails for sw_rx_ring on"
115 " socket %u\n", socket_id);
120 /* Allocate FW Rx ring */
121 rc = qdev->ops->common->chain_alloc(edev,
122 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
123 ECORE_CHAIN_MODE_NEXT_PTR,
124 ECORE_CHAIN_CNT_TYPE_U16,
126 sizeof(struct eth_rx_bd),
130 if (rc != ECORE_SUCCESS) {
131 DP_ERR(edev, "Memory allocation fails for RX BD ring"
132 " on socket %u\n", socket_id);
133 rte_free(rxq->sw_rx_ring);
138 /* Allocate FW completion ring */
139 rc = qdev->ops->common->chain_alloc(edev,
140 ECORE_CHAIN_USE_TO_CONSUME,
141 ECORE_CHAIN_MODE_PBL,
142 ECORE_CHAIN_CNT_TYPE_U16,
144 sizeof(union eth_rx_cqe),
148 if (rc != ECORE_SUCCESS) {
149 DP_ERR(edev, "Memory allocation fails for RX CQE ring"
150 " on socket %u\n", socket_id);
151 qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);
152 rte_free(rxq->sw_rx_ring);
157 dev->data->rx_queues[queue_idx] = rxq;
158 qdev->fp_array[queue_idx].rxq = rxq;
160 DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
161 queue_idx, nb_desc, qdev->mtu, socket_id);
167 qede_rx_queue_reset(__rte_unused struct qede_dev *qdev,
168 struct qede_rx_queue *rxq)
170 DP_INFO(&qdev->edev, "Reset RX queue %u\n", rxq->queue_id);
171 ecore_chain_reset(&rxq->rx_bd_ring);
172 ecore_chain_reset(&rxq->rx_comp_ring);
175 *rxq->hw_cons_ptr = 0;
178 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
182 if (rxq->sw_rx_ring) {
183 for (i = 0; i < rxq->nb_rx_desc; i++) {
184 if (rxq->sw_rx_ring[i].mbuf) {
185 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
186 rxq->sw_rx_ring[i].mbuf = NULL;
192 void qede_rx_queue_release(void *rx_queue)
194 struct qede_rx_queue *rxq = rx_queue;
197 qede_rx_queue_release_mbufs(rxq);
198 rte_free(rxq->sw_rx_ring);
203 /* Stops a given RX queue in the HW */
204 static int qede_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
206 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
207 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
208 struct ecore_hwfn *p_hwfn;
209 struct qede_rx_queue *rxq;
213 if (rx_queue_id < eth_dev->data->nb_rx_queues) {
214 rxq = eth_dev->data->rx_queues[rx_queue_id];
215 hwfn_index = rx_queue_id % edev->num_hwfns;
216 p_hwfn = &edev->hwfns[hwfn_index];
217 rc = ecore_eth_rx_queue_stop(p_hwfn, rxq->handle,
219 if (rc != ECORE_SUCCESS) {
220 DP_ERR(edev, "RX queue %u stop fails\n", rx_queue_id);
223 qede_rx_queue_release_mbufs(rxq);
224 qede_rx_queue_reset(qdev, rxq);
225 eth_dev->data->rx_queue_state[rx_queue_id] =
226 RTE_ETH_QUEUE_STATE_STOPPED;
227 DP_INFO(edev, "RX queue %u stopped\n", rx_queue_id);
229 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
237 qede_tx_queue_setup(struct rte_eth_dev *dev,
240 unsigned int socket_id,
241 const struct rte_eth_txconf *tx_conf)
243 struct qede_dev *qdev = dev->data->dev_private;
244 struct ecore_dev *edev = &qdev->edev;
245 struct qede_tx_queue *txq;
248 PMD_INIT_FUNC_TRACE(edev);
250 if (!rte_is_power_of_2(nb_desc)) {
251 DP_ERR(edev, "Ring size %u is not power of 2\n",
256 /* Free memory prior to re-allocation if needed... */
257 if (dev->data->tx_queues[queue_idx] != NULL) {
258 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
259 dev->data->tx_queues[queue_idx] = NULL;
262 txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
263 RTE_CACHE_LINE_SIZE, socket_id);
267 "Unable to allocate memory for txq on socket %u",
272 txq->nb_tx_desc = nb_desc;
274 txq->port_id = dev->data->port_id;
276 rc = qdev->ops->common->chain_alloc(edev,
277 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
278 ECORE_CHAIN_MODE_PBL,
279 ECORE_CHAIN_CNT_TYPE_U16,
281 sizeof(union eth_tx_bd_types),
284 if (rc != ECORE_SUCCESS) {
286 "Unable to allocate memory for txbd ring on socket %u",
288 qede_tx_queue_release(txq);
292 /* Allocate software ring */
293 txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
294 (sizeof(struct qede_tx_entry) *
296 RTE_CACHE_LINE_SIZE, socket_id);
298 if (!txq->sw_tx_ring) {
300 "Unable to allocate memory for txbd ring on socket %u",
302 qdev->ops->common->chain_free(edev, &txq->tx_pbl);
303 qede_tx_queue_release(txq);
307 txq->queue_id = queue_idx;
309 txq->nb_tx_avail = txq->nb_tx_desc;
311 txq->tx_free_thresh =
312 tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
313 (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
315 dev->data->tx_queues[queue_idx] = txq;
316 qdev->fp_array[queue_idx].txq = txq;
319 "txq %u num_desc %u tx_free_thresh %u socket %u\n",
320 queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
326 qede_tx_queue_reset(__rte_unused struct qede_dev *qdev,
327 struct qede_tx_queue *txq)
329 DP_INFO(&qdev->edev, "Reset TX queue %u\n", txq->queue_id);
330 ecore_chain_reset(&txq->tx_pbl);
333 *txq->hw_cons_ptr = 0;
336 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
340 if (txq->sw_tx_ring) {
341 for (i = 0; i < txq->nb_tx_desc; i++) {
342 if (txq->sw_tx_ring[i].mbuf) {
343 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf);
344 txq->sw_tx_ring[i].mbuf = NULL;
350 void qede_tx_queue_release(void *tx_queue)
352 struct qede_tx_queue *txq = tx_queue;
355 qede_tx_queue_release_mbufs(txq);
356 rte_free(txq->sw_tx_ring);
361 /* This function allocates fast-path status block memory */
363 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
366 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
367 struct status_block_e4 *sb_virt;
371 sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys,
372 sizeof(struct status_block_e4));
374 DP_ERR(edev, "Status block allocation failed\n");
377 rc = qdev->ops->common->sb_init(edev, sb_info, sb_virt,
380 DP_ERR(edev, "Status block initialization failed\n");
381 OSAL_DMA_FREE_COHERENT(edev, sb_virt, sb_phys,
382 sizeof(struct status_block_e4));
389 int qede_alloc_fp_resc(struct qede_dev *qdev)
391 struct ecore_dev *edev = &qdev->edev;
392 struct qede_fastpath *fp;
397 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
399 num_sbs = ecore_cxt_get_proto_cid_count
400 (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL);
403 DP_ERR(edev, "No status blocks available\n");
407 qdev->fp_array = rte_calloc("fp", QEDE_RXTX_MAX(qdev),
408 sizeof(*qdev->fp_array), RTE_CACHE_LINE_SIZE);
410 if (!qdev->fp_array) {
411 DP_ERR(edev, "fp array allocation failed\n");
415 memset((void *)qdev->fp_array, 0, QEDE_RXTX_MAX(qdev) *
416 sizeof(*qdev->fp_array));
418 for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
419 fp = &qdev->fp_array[sb_idx];
420 fp->sb_info = rte_calloc("sb", 1, sizeof(struct ecore_sb_info),
421 RTE_CACHE_LINE_SIZE);
423 DP_ERR(edev, "FP sb_info allocation fails\n");
426 if (qede_alloc_mem_sb(qdev, fp->sb_info, sb_idx)) {
427 DP_ERR(edev, "FP status block allocation fails\n");
430 DP_INFO(edev, "sb_info idx 0x%x initialized\n",
431 fp->sb_info->igu_sb_id);
437 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
439 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
440 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
441 struct qede_fastpath *fp;
442 struct qede_rx_queue *rxq;
443 struct qede_tx_queue *txq;
447 PMD_INIT_FUNC_TRACE(edev);
449 for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
450 fp = &qdev->fp_array[sb_idx];
451 DP_INFO(edev, "Free sb_info index 0x%x\n",
452 fp->sb_info->igu_sb_id);
454 OSAL_DMA_FREE_COHERENT(edev, fp->sb_info->sb_virt,
455 fp->sb_info->sb_phys,
456 sizeof(struct status_block_e4));
457 rte_free(fp->sb_info);
462 /* Free packet buffers and ring memories */
463 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
464 if (eth_dev->data->rx_queues[i]) {
465 qede_rx_queue_release(eth_dev->data->rx_queues[i]);
466 rxq = eth_dev->data->rx_queues[i];
467 qdev->ops->common->chain_free(edev,
469 qdev->ops->common->chain_free(edev,
471 eth_dev->data->rx_queues[i] = NULL;
475 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
476 if (eth_dev->data->tx_queues[i]) {
477 txq = eth_dev->data->tx_queues[i];
478 qede_tx_queue_release(eth_dev->data->tx_queues[i]);
479 qdev->ops->common->chain_free(edev,
481 eth_dev->data->tx_queues[i] = NULL;
486 rte_free(qdev->fp_array);
487 qdev->fp_array = NULL;
491 qede_update_rx_prod(__rte_unused struct qede_dev *edev,
492 struct qede_rx_queue *rxq)
494 uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
495 uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
496 struct eth_rx_prod_data rx_prods = { 0 };
498 /* Update producers */
499 rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
500 rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
502 /* Make sure that the BD and SGE data is updated before updating the
503 * producers since FW might read the BD/SGE right after the producer
508 internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
509 (uint32_t *)&rx_prods);
511 /* mmiowb is needed to synchronize doorbell writes from more than one
512 * processor. It guarantees that the write arrives to the device before
513 * the napi lock is released and another qede_poll is called (possibly
514 * on another CPU). Without this barrier, the next doorbell can bypass
515 * this doorbell. This is applicable to IA64/Altix systems.
519 PMD_RX_LOG(DEBUG, rxq, "bd_prod %u cqe_prod %u", bd_prod, cqe_prod);
522 /* Starts a given RX queue in HW */
524 qede_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
526 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
527 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
528 struct ecore_queue_start_common_params params;
529 struct ecore_rxq_start_ret_params ret_params;
530 struct qede_rx_queue *rxq;
531 struct qede_fastpath *fp;
532 struct ecore_hwfn *p_hwfn;
533 dma_addr_t p_phys_table;
539 if (rx_queue_id < eth_dev->data->nb_rx_queues) {
540 fp = &qdev->fp_array[rx_queue_id];
541 rxq = eth_dev->data->rx_queues[rx_queue_id];
542 /* Allocate buffers for the Rx ring */
543 for (j = 0; j < rxq->nb_rx_desc; j++) {
544 rc = qede_alloc_rx_buffer(rxq);
546 DP_ERR(edev, "RX buffer allocation failed"
547 " for rxq = %u\n", rx_queue_id);
551 /* disable interrupts */
552 ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
554 memset(¶ms, 0, sizeof(params));
555 params.queue_id = rx_queue_id / edev->num_hwfns;
557 params.stats_id = params.vport_id;
558 params.p_sb = fp->sb_info;
559 DP_INFO(edev, "rxq %u igu_sb_id 0x%x\n",
560 fp->rxq->queue_id, fp->sb_info->igu_sb_id);
561 params.sb_idx = RX_PI;
562 hwfn_index = rx_queue_id % edev->num_hwfns;
563 p_hwfn = &edev->hwfns[hwfn_index];
564 p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->rx_comp_ring);
565 page_cnt = ecore_chain_get_page_cnt(&fp->rxq->rx_comp_ring);
566 memset(&ret_params, 0, sizeof(ret_params));
567 rc = ecore_eth_rx_queue_start(p_hwfn,
568 p_hwfn->hw_info.opaque_fid,
569 ¶ms, fp->rxq->rx_buf_size,
570 fp->rxq->rx_bd_ring.p_phys_addr,
571 p_phys_table, page_cnt,
574 DP_ERR(edev, "RX queue %u could not be started, rc = %d\n",
578 /* Update with the returned parameters */
579 fp->rxq->hw_rxq_prod_addr = ret_params.p_prod;
580 fp->rxq->handle = ret_params.p_handle;
582 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[RX_PI];
583 qede_update_rx_prod(qdev, fp->rxq);
584 eth_dev->data->rx_queue_state[rx_queue_id] =
585 RTE_ETH_QUEUE_STATE_STARTED;
586 DP_INFO(edev, "RX queue %u started\n", rx_queue_id);
588 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
596 qede_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
598 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
599 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
600 struct ecore_queue_start_common_params params;
601 struct ecore_txq_start_ret_params ret_params;
602 struct ecore_hwfn *p_hwfn;
603 dma_addr_t p_phys_table;
604 struct qede_tx_queue *txq;
605 struct qede_fastpath *fp;
610 if (tx_queue_id < eth_dev->data->nb_tx_queues) {
611 txq = eth_dev->data->tx_queues[tx_queue_id];
612 fp = &qdev->fp_array[tx_queue_id];
613 memset(¶ms, 0, sizeof(params));
614 params.queue_id = tx_queue_id / edev->num_hwfns;
616 params.stats_id = params.vport_id;
617 params.p_sb = fp->sb_info;
618 DP_INFO(edev, "txq %u igu_sb_id 0x%x\n",
619 fp->txq->queue_id, fp->sb_info->igu_sb_id);
620 params.sb_idx = TX_PI(0); /* tc = 0 */
621 p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
622 page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
623 hwfn_index = tx_queue_id % edev->num_hwfns;
624 p_hwfn = &edev->hwfns[hwfn_index];
625 if (qdev->dev_info.is_legacy)
626 fp->txq->is_legacy = true;
627 rc = ecore_eth_tx_queue_start(p_hwfn,
628 p_hwfn->hw_info.opaque_fid,
630 p_phys_table, page_cnt,
632 if (rc != ECORE_SUCCESS) {
633 DP_ERR(edev, "TX queue %u couldn't be started, rc=%d\n",
637 txq->doorbell_addr = ret_params.p_doorbell;
638 txq->handle = ret_params.p_handle;
640 txq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[TX_PI(0)];
641 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_DEST,
643 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
645 SET_FIELD(txq->tx_db.data.params,
646 ETH_DB_DATA_AGG_VAL_SEL,
647 DQ_XCM_ETH_TX_BD_PROD_CMD);
648 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
649 eth_dev->data->tx_queue_state[tx_queue_id] =
650 RTE_ETH_QUEUE_STATE_STARTED;
651 DP_INFO(edev, "TX queue %u started\n", tx_queue_id);
653 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
661 qede_free_tx_pkt(struct qede_tx_queue *txq)
663 struct rte_mbuf *mbuf;
668 mbuf = txq->sw_tx_ring[idx].mbuf;
670 nb_segs = mbuf->nb_segs;
671 PMD_TX_LOG(DEBUG, txq, "nb_segs to free %u\n", nb_segs);
673 /* It's like consuming rxbuf in recv() */
674 ecore_chain_consume(&txq->tx_pbl);
678 rte_pktmbuf_free(mbuf);
679 txq->sw_tx_ring[idx].mbuf = NULL;
681 PMD_TX_LOG(DEBUG, txq, "Freed tx packet\n");
683 ecore_chain_consume(&txq->tx_pbl);
689 qede_process_tx_compl(__rte_unused struct ecore_dev *edev,
690 struct qede_tx_queue *txq)
693 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
697 rte_compiler_barrier();
698 hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
699 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
700 sw_tx_cons = ecore_chain_get_cons_idx(&txq->tx_pbl);
701 PMD_TX_LOG(DEBUG, txq, "Tx Completions = %u\n",
702 abs(hw_bd_cons - sw_tx_cons));
704 while (hw_bd_cons != ecore_chain_get_cons_idx(&txq->tx_pbl))
705 qede_free_tx_pkt(txq);
708 static int qede_drain_txq(struct qede_dev *qdev,
709 struct qede_tx_queue *txq, bool allow_drain)
711 struct ecore_dev *edev = &qdev->edev;
714 while (txq->sw_tx_cons != txq->sw_tx_prod) {
715 qede_process_tx_compl(edev, txq);
718 DP_ERR(edev, "Tx queue[%u] is stuck,"
719 "requesting MCP to drain\n",
721 rc = qdev->ops->common->drain(edev);
724 return qede_drain_txq(qdev, txq, false);
726 DP_ERR(edev, "Timeout waiting for tx queue[%d]:"
727 "PROD=%d, CONS=%d\n",
728 txq->queue_id, txq->sw_tx_prod,
734 rte_compiler_barrier();
737 /* FW finished processing, wait for HW to transmit all tx packets */
743 /* Stops a given TX queue in the HW */
744 static int qede_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
746 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
747 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
748 struct ecore_hwfn *p_hwfn;
749 struct qede_tx_queue *txq;
753 if (tx_queue_id < eth_dev->data->nb_tx_queues) {
754 txq = eth_dev->data->tx_queues[tx_queue_id];
756 if (qede_drain_txq(qdev, txq, true))
757 return -1; /* For the lack of retcodes */
759 hwfn_index = tx_queue_id % edev->num_hwfns;
760 p_hwfn = &edev->hwfns[hwfn_index];
761 rc = ecore_eth_tx_queue_stop(p_hwfn, txq->handle);
762 if (rc != ECORE_SUCCESS) {
763 DP_ERR(edev, "TX queue %u stop fails\n", tx_queue_id);
766 qede_tx_queue_release_mbufs(txq);
767 qede_tx_queue_reset(qdev, txq);
768 eth_dev->data->tx_queue_state[tx_queue_id] =
769 RTE_ETH_QUEUE_STATE_STOPPED;
770 DP_INFO(edev, "TX queue %u stopped\n", tx_queue_id);
772 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
779 int qede_start_queues(struct rte_eth_dev *eth_dev)
781 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
786 rc = qede_rx_queue_start(eth_dev, id);
787 if (rc != ECORE_SUCCESS)
792 rc = qede_tx_queue_start(eth_dev, id);
793 if (rc != ECORE_SUCCESS)
800 void qede_stop_queues(struct rte_eth_dev *eth_dev)
802 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
805 /* Stopping RX/TX queues */
807 qede_tx_queue_stop(eth_dev, id);
811 qede_rx_queue_stop(eth_dev, id);
815 static inline bool qede_tunn_exist(uint16_t flag)
817 return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
818 PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
821 static inline uint8_t qede_check_tunn_csum_l3(uint16_t flag)
823 return !!((PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
824 PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT) & flag);
828 * qede_check_tunn_csum_l4:
830 * 1 : If L4 csum is enabled AND if the validation has failed.
833 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
835 if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
836 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
837 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
838 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
843 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
845 if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
846 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
847 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
848 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
853 /* Returns outer L2, L3 and L4 packet_type for tunneled packets */
854 static inline uint32_t qede_rx_cqe_to_pkt_type_outer(struct rte_mbuf *m)
856 uint32_t packet_type = RTE_PTYPE_UNKNOWN;
857 struct ether_hdr *eth_hdr;
858 struct ipv4_hdr *ipv4_hdr;
859 struct ipv6_hdr *ipv6_hdr;
860 struct vlan_hdr *vlan_hdr;
862 bool vlan_tagged = 0;
865 eth_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *);
866 len = sizeof(struct ether_hdr);
867 ethertype = rte_cpu_to_be_16(eth_hdr->ether_type);
869 /* Note: Valid only if VLAN stripping is disabled */
870 if (ethertype == ETHER_TYPE_VLAN) {
872 vlan_hdr = (struct vlan_hdr *)(eth_hdr + 1);
873 len += sizeof(struct vlan_hdr);
874 ethertype = rte_cpu_to_be_16(vlan_hdr->eth_proto);
877 if (ethertype == ETHER_TYPE_IPv4) {
878 packet_type |= RTE_PTYPE_L3_IPV4;
879 ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *, len);
880 if (ipv4_hdr->next_proto_id == IPPROTO_TCP)
881 packet_type |= RTE_PTYPE_L4_TCP;
882 else if (ipv4_hdr->next_proto_id == IPPROTO_UDP)
883 packet_type |= RTE_PTYPE_L4_UDP;
884 } else if (ethertype == ETHER_TYPE_IPv6) {
885 packet_type |= RTE_PTYPE_L3_IPV6;
886 ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct ipv6_hdr *, len);
887 if (ipv6_hdr->proto == IPPROTO_TCP)
888 packet_type |= RTE_PTYPE_L4_TCP;
889 else if (ipv6_hdr->proto == IPPROTO_UDP)
890 packet_type |= RTE_PTYPE_L4_UDP;
894 packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
896 packet_type |= RTE_PTYPE_L2_ETHER;
901 static inline uint32_t qede_rx_cqe_to_pkt_type_inner(uint16_t flags)
906 static const uint32_t
907 ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
908 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_INNER_L3_IPV4 |
909 RTE_PTYPE_INNER_L2_ETHER,
910 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_INNER_L3_IPV6 |
911 RTE_PTYPE_INNER_L2_ETHER,
912 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_INNER_L3_IPV4 |
913 RTE_PTYPE_INNER_L4_TCP |
914 RTE_PTYPE_INNER_L2_ETHER,
915 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_INNER_L3_IPV6 |
916 RTE_PTYPE_INNER_L4_TCP |
917 RTE_PTYPE_INNER_L2_ETHER,
918 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_INNER_L3_IPV4 |
919 RTE_PTYPE_INNER_L4_UDP |
920 RTE_PTYPE_INNER_L2_ETHER,
921 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_INNER_L3_IPV6 |
922 RTE_PTYPE_INNER_L4_UDP |
923 RTE_PTYPE_INNER_L2_ETHER,
924 /* Frags with no VLAN */
925 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_INNER_L3_IPV4 |
926 RTE_PTYPE_INNER_L4_FRAG |
927 RTE_PTYPE_INNER_L2_ETHER,
928 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_INNER_L3_IPV6 |
929 RTE_PTYPE_INNER_L4_FRAG |
930 RTE_PTYPE_INNER_L2_ETHER,
932 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
933 RTE_PTYPE_INNER_L2_ETHER_VLAN,
934 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
935 RTE_PTYPE_INNER_L2_ETHER_VLAN,
936 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
937 RTE_PTYPE_INNER_L4_TCP |
938 RTE_PTYPE_INNER_L2_ETHER_VLAN,
939 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
940 RTE_PTYPE_INNER_L4_TCP |
941 RTE_PTYPE_INNER_L2_ETHER_VLAN,
942 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
943 RTE_PTYPE_INNER_L4_UDP |
944 RTE_PTYPE_INNER_L2_ETHER_VLAN,
945 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
946 RTE_PTYPE_INNER_L4_UDP |
947 RTE_PTYPE_INNER_L2_ETHER_VLAN,
948 /* Frags with VLAN */
949 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV4 |
950 RTE_PTYPE_INNER_L4_FRAG |
951 RTE_PTYPE_INNER_L2_ETHER_VLAN,
952 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV6 |
953 RTE_PTYPE_INNER_L4_FRAG |
954 RTE_PTYPE_INNER_L2_ETHER_VLAN,
957 /* Bits (0..3) provides L3/L4 protocol type */
958 /* Bits (4,5) provides frag and VLAN info */
959 val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
960 PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
961 (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
962 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) |
963 (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
964 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) |
965 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK <<
966 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags;
968 if (val < QEDE_PKT_TYPE_MAX)
969 return ptype_lkup_tbl[val];
971 return RTE_PTYPE_UNKNOWN;
974 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
979 static const uint32_t
980 ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
981 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L2_ETHER,
982 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L2_ETHER,
983 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4 |
986 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6 |
989 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4 |
992 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6 |
995 /* Frags with no VLAN */
996 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_L3_IPV4 |
999 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_L3_IPV6 |
1003 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_L3_IPV4 |
1004 RTE_PTYPE_L2_ETHER_VLAN,
1005 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_L3_IPV6 |
1006 RTE_PTYPE_L2_ETHER_VLAN,
1007 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_L3_IPV4 |
1009 RTE_PTYPE_L2_ETHER_VLAN,
1010 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_L3_IPV6 |
1012 RTE_PTYPE_L2_ETHER_VLAN,
1013 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_L3_IPV4 |
1015 RTE_PTYPE_L2_ETHER_VLAN,
1016 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_L3_IPV6 |
1018 RTE_PTYPE_L2_ETHER_VLAN,
1019 /* Frags with VLAN */
1020 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_L3_IPV4 |
1022 RTE_PTYPE_L2_ETHER_VLAN,
1023 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_L3_IPV6 |
1025 RTE_PTYPE_L2_ETHER_VLAN,
1028 /* Bits (0..3) provides L3/L4 protocol type */
1029 /* Bits (4,5) provides frag and VLAN info */
1030 val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
1031 PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
1032 (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
1033 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) |
1034 (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1035 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) |
1036 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK <<
1037 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags;
1039 if (val < QEDE_PKT_TYPE_MAX)
1040 return ptype_lkup_tbl[val];
1042 return RTE_PTYPE_UNKNOWN;
1045 static inline uint8_t
1046 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
1048 struct ipv4_hdr *ip;
1053 val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1054 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
1056 if (unlikely(val)) {
1057 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
1058 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
1059 ip = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1060 sizeof(struct ether_hdr));
1061 pkt_csum = ip->hdr_checksum;
1062 ip->hdr_checksum = 0;
1063 calc_csum = rte_ipv4_cksum(ip);
1064 ip->hdr_checksum = pkt_csum;
1065 return (calc_csum != pkt_csum);
1066 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
1073 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
1075 ecore_chain_consume(&rxq->rx_bd_ring);
1080 qede_reuse_page(__rte_unused struct qede_dev *qdev,
1081 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
1083 struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
1084 uint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1085 struct qede_rx_entry *curr_prod;
1086 dma_addr_t new_mapping;
1088 curr_prod = &rxq->sw_rx_ring[idx];
1089 *curr_prod = *curr_cons;
1091 new_mapping = rte_mbuf_data_iova_default(curr_prod->mbuf) +
1092 curr_prod->page_offset;
1094 rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
1095 rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
1101 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
1102 struct qede_dev *qdev, uint8_t count)
1104 struct qede_rx_entry *curr_cons;
1106 for (; count > 0; count--) {
1107 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
1108 qede_reuse_page(qdev, rxq, curr_cons);
1109 qede_rx_bd_ring_consume(rxq);
1114 qede_rx_process_tpa_cmn_cont_end_cqe(__rte_unused struct qede_dev *qdev,
1115 struct qede_rx_queue *rxq,
1116 uint8_t agg_index, uint16_t len)
1118 struct qede_agg_info *tpa_info;
1119 struct rte_mbuf *curr_frag; /* Pointer to currently filled TPA seg */
1122 /* Under certain conditions it is possible that FW may not consume
1123 * additional or new BD. So decision to consume the BD must be made
1124 * based on len_list[0].
1126 if (rte_le_to_cpu_16(len)) {
1127 tpa_info = &rxq->tpa_info[agg_index];
1128 cons_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1129 curr_frag = rxq->sw_rx_ring[cons_idx].mbuf;
1131 curr_frag->nb_segs = 1;
1132 curr_frag->pkt_len = rte_le_to_cpu_16(len);
1133 curr_frag->data_len = curr_frag->pkt_len;
1134 tpa_info->tpa_tail->next = curr_frag;
1135 tpa_info->tpa_tail = curr_frag;
1136 qede_rx_bd_ring_consume(rxq);
1137 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1138 PMD_RX_LOG(ERR, rxq, "mbuf allocation fails\n");
1139 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1140 rxq->rx_alloc_errors++;
1146 qede_rx_process_tpa_cont_cqe(struct qede_dev *qdev,
1147 struct qede_rx_queue *rxq,
1148 struct eth_fast_path_rx_tpa_cont_cqe *cqe)
1150 PMD_RX_LOG(INFO, rxq, "TPA cont[%d] - len [%d]\n",
1151 cqe->tpa_agg_index, rte_le_to_cpu_16(cqe->len_list[0]));
1152 /* only len_list[0] will have value */
1153 qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
1158 qede_rx_process_tpa_end_cqe(struct qede_dev *qdev,
1159 struct qede_rx_queue *rxq,
1160 struct eth_fast_path_rx_tpa_end_cqe *cqe)
1162 struct rte_mbuf *rx_mb; /* Pointer to head of the chained agg */
1164 qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
1166 /* Update total length and frags based on end TPA */
1167 rx_mb = rxq->tpa_info[cqe->tpa_agg_index].tpa_head;
1168 /* TODO: Add Sanity Checks */
1169 rx_mb->nb_segs = cqe->num_of_bds;
1170 rx_mb->pkt_len = cqe->total_packet_len;
1172 PMD_RX_LOG(INFO, rxq, "TPA End[%d] reason %d cqe_len %d nb_segs %d"
1173 " pkt_len %d\n", cqe->tpa_agg_index, cqe->end_reason,
1174 rte_le_to_cpu_16(cqe->len_list[0]), rx_mb->nb_segs,
1178 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
1183 static const uint32_t
1184 ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
1185 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
1186 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
1187 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
1188 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
1189 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
1190 RTE_PTYPE_TUNNEL_GENEVE,
1191 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
1192 RTE_PTYPE_TUNNEL_GRE,
1193 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
1194 RTE_PTYPE_TUNNEL_VXLAN,
1195 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
1196 RTE_PTYPE_TUNNEL_GENEVE,
1197 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
1198 RTE_PTYPE_TUNNEL_GRE,
1199 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
1200 RTE_PTYPE_TUNNEL_VXLAN,
1201 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
1202 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1203 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
1204 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1205 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
1206 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1207 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
1208 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1209 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
1210 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1211 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
1212 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1213 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
1214 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1215 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
1216 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1217 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
1218 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1219 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
1220 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1221 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
1222 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1223 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
1224 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1227 /* Cover bits[4-0] to include tunn_type and next protocol */
1228 val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
1229 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
1230 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
1231 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
1233 if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
1234 return ptype_tunn_lkup_tbl[val];
1236 return RTE_PTYPE_UNKNOWN;
1240 qede_process_sg_pkts(void *p_rxq, struct rte_mbuf *rx_mb,
1241 uint8_t num_segs, uint16_t pkt_len)
1243 struct qede_rx_queue *rxq = p_rxq;
1244 struct qede_dev *qdev = rxq->qdev;
1245 register struct rte_mbuf *seg1 = NULL;
1246 register struct rte_mbuf *seg2 = NULL;
1247 uint16_t sw_rx_index;
1252 cur_size = pkt_len > rxq->rx_buf_size ? rxq->rx_buf_size :
1254 if (unlikely(!cur_size)) {
1255 PMD_RX_LOG(ERR, rxq, "Length is 0 while %u BDs"
1256 " left for mapping jumbo\n", num_segs);
1257 qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
1260 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1261 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
1262 qede_rx_bd_ring_consume(rxq);
1263 pkt_len -= cur_size;
1264 seg2->data_len = cur_size;
1274 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1276 print_rx_bd_info(struct rte_mbuf *m, struct qede_rx_queue *rxq,
1279 PMD_RX_LOG(INFO, rxq,
1280 "len 0x%04x bf 0x%04x hash_val 0x%x"
1281 " ol_flags 0x%04lx l2=%s l3=%s l4=%s tunn=%s"
1282 " inner_l2=%s inner_l3=%s inner_l4=%s\n",
1283 m->data_len, bitfield, m->hash.rss,
1284 (unsigned long)m->ol_flags,
1285 rte_get_ptype_l2_name(m->packet_type),
1286 rte_get_ptype_l3_name(m->packet_type),
1287 rte_get_ptype_l4_name(m->packet_type),
1288 rte_get_ptype_tunnel_name(m->packet_type),
1289 rte_get_ptype_inner_l2_name(m->packet_type),
1290 rte_get_ptype_inner_l3_name(m->packet_type),
1291 rte_get_ptype_inner_l4_name(m->packet_type));
1296 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1298 struct qede_rx_queue *rxq = p_rxq;
1299 struct qede_dev *qdev = rxq->qdev;
1300 struct ecore_dev *edev = &qdev->edev;
1301 uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
1302 uint16_t rx_pkt = 0;
1303 union eth_rx_cqe *cqe;
1304 struct eth_fast_path_rx_reg_cqe *fp_cqe = NULL;
1305 register struct rte_mbuf *rx_mb = NULL;
1306 register struct rte_mbuf *seg1 = NULL;
1307 enum eth_rx_cqe_type cqe_type;
1308 uint16_t pkt_len = 0; /* Sum of all BD segments */
1309 uint16_t len; /* Length of first BD */
1310 uint8_t num_segs = 1;
1311 uint16_t preload_idx;
1312 uint16_t parse_flag;
1313 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1314 uint8_t bitfield_val;
1316 uint8_t tunn_parse_flag;
1318 struct eth_fast_path_rx_tpa_start_cqe *cqe_start_tpa;
1320 uint32_t packet_type;
1323 uint8_t offset, tpa_agg_idx, flags;
1324 struct qede_agg_info *tpa_info = NULL;
1327 hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
1328 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1332 if (hw_comp_cons == sw_comp_cons)
1335 while (sw_comp_cons != hw_comp_cons) {
1337 packet_type = RTE_PTYPE_UNKNOWN;
1339 tpa_start_flg = false;
1342 /* Get the CQE from the completion ring */
1344 (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
1345 cqe_type = cqe->fast_path_regular.type;
1346 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type);
1349 case ETH_RX_CQE_TYPE_REGULAR:
1350 fp_cqe = &cqe->fast_path_regular;
1352 case ETH_RX_CQE_TYPE_TPA_START:
1353 cqe_start_tpa = &cqe->fast_path_tpa_start;
1354 tpa_info = &rxq->tpa_info[cqe_start_tpa->tpa_agg_index];
1355 tpa_start_flg = true;
1356 /* Mark it as LRO packet */
1357 ol_flags |= PKT_RX_LRO;
1358 /* In split mode, seg_len is same as len_on_first_bd
1359 * and ext_bd_len_list will be empty since there are
1360 * no additional buffers
1362 PMD_RX_LOG(INFO, rxq,
1363 "TPA start[%d] - len_on_first_bd %d header %d"
1364 " [bd_list[0] %d], [seg_len %d]\n",
1365 cqe_start_tpa->tpa_agg_index,
1366 rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd),
1367 cqe_start_tpa->header_len,
1368 rte_le_to_cpu_16(cqe_start_tpa->ext_bd_len_list[0]),
1369 rte_le_to_cpu_16(cqe_start_tpa->seg_len));
1372 case ETH_RX_CQE_TYPE_TPA_CONT:
1373 qede_rx_process_tpa_cont_cqe(qdev, rxq,
1374 &cqe->fast_path_tpa_cont);
1376 case ETH_RX_CQE_TYPE_TPA_END:
1377 qede_rx_process_tpa_end_cqe(qdev, rxq,
1378 &cqe->fast_path_tpa_end);
1379 tpa_agg_idx = cqe->fast_path_tpa_end.tpa_agg_index;
1380 tpa_info = &rxq->tpa_info[tpa_agg_idx];
1381 rx_mb = rxq->tpa_info[tpa_agg_idx].tpa_head;
1383 case ETH_RX_CQE_TYPE_SLOW_PATH:
1384 PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n");
1385 ecore_eth_cqe_completion(
1386 &edev->hwfns[rxq->queue_id % edev->num_hwfns],
1387 (struct eth_slow_path_rx_cqe *)cqe);
1393 /* Get the data from the SW ring */
1394 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1395 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
1396 assert(rx_mb != NULL);
1398 /* Handle regular CQE or TPA start CQE */
1399 if (!tpa_start_flg) {
1400 parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);
1401 offset = fp_cqe->placement_offset;
1402 len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
1403 pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1404 vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1405 rss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash);
1406 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1407 bitfield_val = fp_cqe->bitfields;
1411 rte_le_to_cpu_16(cqe_start_tpa->pars_flags.flags);
1412 offset = cqe_start_tpa->placement_offset;
1413 /* seg_len = len_on_first_bd */
1414 len = rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd);
1415 vlan_tci = rte_le_to_cpu_16(cqe_start_tpa->vlan_tag);
1416 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1417 bitfield_val = cqe_start_tpa->bitfields;
1419 rss_hash = rte_le_to_cpu_32(cqe_start_tpa->rss_hash);
1421 if (qede_tunn_exist(parse_flag)) {
1422 PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n");
1423 if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1424 PMD_RX_LOG(ERR, rxq,
1425 "L4 csum failed, flags = 0x%x\n",
1427 rxq->rx_hw_errors++;
1428 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1430 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1433 if (unlikely(qede_check_tunn_csum_l3(parse_flag))) {
1434 PMD_RX_LOG(ERR, rxq,
1435 "Outer L3 csum failed, flags = 0x%x\n",
1437 rxq->rx_hw_errors++;
1438 ol_flags |= PKT_RX_EIP_CKSUM_BAD;
1440 ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1444 flags = cqe_start_tpa->tunnel_pars_flags.flags;
1446 flags = fp_cqe->tunnel_pars_flags.flags;
1447 tunn_parse_flag = flags;
1451 qede_rx_cqe_to_tunn_pkt_type(tunn_parse_flag);
1455 qede_rx_cqe_to_pkt_type_inner(parse_flag);
1457 /* Outer L3/L4 types is not available in CQE */
1458 packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1460 /* Outer L3/L4 types is not available in CQE.
1461 * Need to add offset to parse correctly,
1463 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1464 packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1467 /* Common handling for non-tunnel packets and for inner
1468 * headers in the case of tunnel.
1470 if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1471 PMD_RX_LOG(ERR, rxq,
1472 "L4 csum failed, flags = 0x%x\n",
1474 rxq->rx_hw_errors++;
1475 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1477 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1479 if (unlikely(qede_check_notunn_csum_l3(rx_mb, parse_flag))) {
1480 PMD_RX_LOG(ERR, rxq, "IP csum failed, flags = 0x%x\n",
1482 rxq->rx_hw_errors++;
1483 ol_flags |= PKT_RX_IP_CKSUM_BAD;
1485 ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1486 packet_type |= qede_rx_cqe_to_pkt_type(parse_flag);
1489 if (CQE_HAS_VLAN(parse_flag) ||
1490 CQE_HAS_OUTER_VLAN(parse_flag)) {
1491 /* Note: FW doesn't indicate Q-in-Q packet */
1492 ol_flags |= PKT_RX_VLAN;
1493 if (qdev->vlan_strip_flg) {
1494 ol_flags |= PKT_RX_VLAN_STRIPPED;
1495 rx_mb->vlan_tci = vlan_tci;
1500 if (qdev->rss_enable) {
1501 ol_flags |= PKT_RX_RSS_HASH;
1502 rx_mb->hash.rss = rss_hash;
1505 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1506 PMD_RX_LOG(ERR, rxq,
1507 "New buffer allocation failed,"
1508 "dropping incoming packet\n");
1509 qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
1510 rte_eth_devices[rxq->port_id].
1511 data->rx_mbuf_alloc_failed++;
1512 rxq->rx_alloc_errors++;
1515 qede_rx_bd_ring_consume(rxq);
1517 if (!tpa_start_flg && fp_cqe->bd_num > 1) {
1518 PMD_RX_LOG(DEBUG, rxq, "Jumbo-over-BD packet: %02x BDs"
1519 " len on first: %04x Total Len: %04x",
1520 fp_cqe->bd_num, len, pkt_len);
1521 num_segs = fp_cqe->bd_num - 1;
1523 if (qede_process_sg_pkts(p_rxq, seg1, num_segs,
1526 for (j = 0; j < num_segs; j++) {
1527 if (qede_alloc_rx_buffer(rxq)) {
1528 PMD_RX_LOG(ERR, rxq,
1529 "Buffer allocation failed");
1530 rte_eth_devices[rxq->port_id].
1531 data->rx_mbuf_alloc_failed++;
1532 rxq->rx_alloc_errors++;
1538 rxq->rx_segs++; /* for the first segment */
1540 /* Prefetch next mbuf while processing current one. */
1541 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1542 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1544 /* Update rest of the MBUF fields */
1545 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1546 rx_mb->port = rxq->port_id;
1547 rx_mb->ol_flags = ol_flags;
1548 rx_mb->data_len = len;
1549 rx_mb->packet_type = packet_type;
1550 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1551 print_rx_bd_info(rx_mb, rxq, bitfield_val);
1553 if (!tpa_start_flg) {
1554 rx_mb->nb_segs = fp_cqe->bd_num;
1555 rx_mb->pkt_len = pkt_len;
1557 /* store ref to the updated mbuf */
1558 tpa_info->tpa_head = rx_mb;
1559 tpa_info->tpa_tail = tpa_info->tpa_head;
1561 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
1563 if (!tpa_start_flg) {
1564 rx_pkts[rx_pkt] = rx_mb;
1568 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1569 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1570 if (rx_pkt == nb_pkts) {
1571 PMD_RX_LOG(DEBUG, rxq,
1572 "Budget reached nb_pkts=%u received=%u",
1578 qede_update_rx_prod(qdev, rxq);
1580 rxq->rcv_pkts += rx_pkt;
1582 PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
1588 /* Populate scatter gather buffer descriptor fields */
1589 static inline uint16_t
1590 qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg,
1591 struct eth_tx_2nd_bd **bd2, struct eth_tx_3rd_bd **bd3)
1593 struct qede_tx_queue *txq = p_txq;
1594 struct eth_tx_bd *tx_bd = NULL;
1596 uint16_t nb_segs = 0;
1598 /* Check for scattered buffers */
1602 *bd2 = (struct eth_tx_2nd_bd *)
1603 ecore_chain_produce(&txq->tx_pbl);
1604 memset(*bd2, 0, sizeof(struct eth_tx_2nd_bd));
1607 mapping = rte_mbuf_data_iova(m_seg);
1608 QEDE_BD_SET_ADDR_LEN(*bd2, mapping, m_seg->data_len);
1609 PMD_TX_LOG(DEBUG, txq, "BD2 len %04x", m_seg->data_len);
1610 } else if (nb_segs == 1) {
1612 *bd3 = (struct eth_tx_3rd_bd *)
1613 ecore_chain_produce(&txq->tx_pbl);
1614 memset(*bd3, 0, sizeof(struct eth_tx_3rd_bd));
1617 mapping = rte_mbuf_data_iova(m_seg);
1618 QEDE_BD_SET_ADDR_LEN(*bd3, mapping, m_seg->data_len);
1619 PMD_TX_LOG(DEBUG, txq, "BD3 len %04x", m_seg->data_len);
1621 tx_bd = (struct eth_tx_bd *)
1622 ecore_chain_produce(&txq->tx_pbl);
1623 memset(tx_bd, 0, sizeof(*tx_bd));
1625 mapping = rte_mbuf_data_iova(m_seg);
1626 QEDE_BD_SET_ADDR_LEN(tx_bd, mapping, m_seg->data_len);
1627 PMD_TX_LOG(DEBUG, txq, "BD len %04x", m_seg->data_len);
1629 m_seg = m_seg->next;
1632 /* Return total scattered buffers */
1636 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1638 print_tx_bd_info(struct qede_tx_queue *txq,
1639 struct eth_tx_1st_bd *bd1,
1640 struct eth_tx_2nd_bd *bd2,
1641 struct eth_tx_3rd_bd *bd3,
1642 uint64_t tx_ol_flags)
1644 char ol_buf[256] = { 0 }; /* for verbose prints */
1647 PMD_TX_LOG(INFO, txq,
1648 "BD1: nbytes=%u nbds=%u bd_flags=%04x bf=%04x",
1649 rte_cpu_to_le_16(bd1->nbytes), bd1->data.nbds,
1650 bd1->data.bd_flags.bitfields,
1651 rte_cpu_to_le_16(bd1->data.bitfields));
1653 PMD_TX_LOG(INFO, txq,
1654 "BD2: nbytes=%u bf=%04x\n",
1655 rte_cpu_to_le_16(bd2->nbytes), bd2->data.bitfields1);
1657 PMD_TX_LOG(INFO, txq,
1658 "BD3: nbytes=%u bf=%04x mss=%u\n",
1659 rte_cpu_to_le_16(bd3->nbytes),
1660 rte_cpu_to_le_16(bd3->data.bitfields),
1661 rte_cpu_to_le_16(bd3->data.lso_mss));
1663 rte_get_tx_ol_flag_list(tx_ol_flags, ol_buf, sizeof(ol_buf));
1664 PMD_TX_LOG(INFO, txq, "TX offloads = %s\n", ol_buf);
1668 /* TX prepare to check packets meets TX conditions */
1670 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1671 qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
1674 struct qede_tx_queue *txq = p_txq;
1676 qede_xmit_prep_pkts(__rte_unused void *p_txq, struct rte_mbuf **tx_pkts,
1683 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1687 for (i = 0; i < nb_pkts; i++) {
1689 ol_flags = m->ol_flags;
1690 if (ol_flags & PKT_TX_TCP_SEG) {
1691 if (m->nb_segs >= ETH_TX_MAX_BDS_PER_LSO_PACKET) {
1692 rte_errno = -EINVAL;
1695 /* TBD: confirm its ~9700B for both ? */
1696 if (m->tso_segsz > ETH_TX_MAX_NON_LSO_PKT_LEN) {
1697 rte_errno = -EINVAL;
1701 if (m->nb_segs >= ETH_TX_MAX_BDS_PER_NON_LSO_PACKET) {
1702 rte_errno = -EINVAL;
1706 if (ol_flags & QEDE_TX_OFFLOAD_NOTSUP_MASK) {
1707 rte_errno = -ENOTSUP;
1711 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1712 ret = rte_validate_tx_offload(m);
1720 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1721 if (unlikely(i != nb_pkts))
1722 PMD_TX_LOG(ERR, txq, "TX prepare failed for %u\n",
1728 #define MPLSINUDP_HDR_SIZE (12)
1730 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1732 qede_mpls_tunn_tx_sanity_check(struct rte_mbuf *mbuf,
1733 struct qede_tx_queue *txq)
1735 if (((mbuf->outer_l2_len + mbuf->outer_l3_len) / 2) > 0xff)
1736 PMD_TX_LOG(ERR, txq, "tunn_l4_hdr_start_offset overflow\n");
1737 if (((mbuf->outer_l2_len + mbuf->outer_l3_len +
1738 MPLSINUDP_HDR_SIZE) / 2) > 0xff)
1739 PMD_TX_LOG(ERR, txq, "tunn_hdr_size overflow\n");
1740 if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE) / 2) >
1741 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK)
1742 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
1743 if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2) >
1744 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
1745 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
1750 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1752 struct qede_tx_queue *txq = p_txq;
1753 struct qede_dev *qdev = txq->qdev;
1754 struct ecore_dev *edev = &qdev->edev;
1755 struct rte_mbuf *mbuf;
1756 struct rte_mbuf *m_seg = NULL;
1757 uint16_t nb_tx_pkts;
1761 uint16_t nb_pkt_sent = 0;
1765 __rte_unused bool tunn_flg;
1766 bool tunn_ipv6_ext_flg;
1767 struct eth_tx_1st_bd *bd1;
1768 struct eth_tx_2nd_bd *bd2;
1769 struct eth_tx_3rd_bd *bd3;
1770 uint64_t tx_ol_flags;
1774 uint8_t bd1_bd_flags_bf;
1783 uint8_t tunn_l4_hdr_start_offset;
1784 uint8_t tunn_hdr_size;
1785 uint8_t inner_l2_hdr_size;
1786 uint16_t inner_l4_hdr_offset;
1788 if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
1789 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
1790 nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
1791 qede_process_tx_compl(edev, txq);
1794 nb_tx_pkts = nb_pkts;
1795 bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1796 while (nb_tx_pkts--) {
1797 /* Init flags/values */
1807 bd1_bd_flags_bf = 0;
1812 mplsoudp_flg = false;
1813 tunn_ipv6_ext_flg = false;
1815 tunn_l4_hdr_start_offset = 0;
1820 /* Check minimum TX BDS availability against available BDs */
1821 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs))
1824 tx_ol_flags = mbuf->ol_flags;
1825 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
1827 /* TX prepare would have already checked supported tunnel Tx
1828 * offloads. Don't rely on pkt_type marked by Rx, instead use
1829 * tx_ol_flags to decide.
1831 if (((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
1832 PKT_TX_TUNNEL_VXLAN) ||
1833 ((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
1834 PKT_TX_TUNNEL_MPLSINUDP) ||
1835 ((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
1836 PKT_TX_TUNNEL_GENEVE)) {
1837 /* Check against max which is Tunnel IPv6 + ext */
1838 if (unlikely(txq->nb_tx_avail <
1839 ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT))
1842 /* First indicate its a tunnel pkt */
1843 bd1_bf |= ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
1844 ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1845 /* Legacy FW had flipped behavior in regard to this bit
1846 * i.e. it needed to set to prevent FW from touching
1847 * encapsulated packets when it didn't need to.
1849 if (unlikely(txq->is_legacy)) {
1851 ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1854 /* Outer IP checksum offload */
1855 if (tx_ol_flags & (PKT_TX_OUTER_IP_CKSUM |
1856 PKT_TX_OUTER_IPV4)) {
1858 ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
1859 ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
1863 * Currently, only inner checksum offload in MPLS-in-UDP
1864 * tunnel with one MPLS label is supported. Both outer
1865 * and inner layers lengths need to be provided in
1868 if ((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
1869 PKT_TX_TUNNEL_MPLSINUDP) {
1870 mplsoudp_flg = true;
1871 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1872 qede_mpls_tunn_tx_sanity_check(mbuf, txq);
1874 /* Outer L4 offset in two byte words */
1875 tunn_l4_hdr_start_offset =
1876 (mbuf->outer_l2_len + mbuf->outer_l3_len) / 2;
1877 /* Tunnel header size in two byte words */
1878 tunn_hdr_size = (mbuf->outer_l2_len +
1879 mbuf->outer_l3_len +
1880 MPLSINUDP_HDR_SIZE) / 2;
1881 /* Inner L2 header size in two byte words */
1882 inner_l2_hdr_size = (mbuf->l2_len -
1883 MPLSINUDP_HDR_SIZE) / 2;
1884 /* Inner L4 header offset from the beggining
1885 * of inner packet in two byte words
1887 inner_l4_hdr_offset = (mbuf->l2_len -
1888 MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2;
1890 /* Inner L2 size and address type */
1891 bd2_bf1 |= (inner_l2_hdr_size &
1892 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK) <<
1893 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT;
1894 bd2_bf1 |= (UNICAST_ADDRESS &
1895 ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK) <<
1896 ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT;
1897 /* Treated as IPv6+Ext */
1899 1 << ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT;
1901 /* Mark inner IPv6 if present */
1902 if (tx_ol_flags & PKT_TX_IPV6)
1904 1 << ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT;
1906 /* Inner L4 offsets */
1907 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
1908 (tx_ol_flags & (PKT_TX_UDP_CKSUM |
1909 PKT_TX_TCP_CKSUM))) {
1910 /* Determines if BD3 is needed */
1911 tunn_ipv6_ext_flg = true;
1912 if ((tx_ol_flags & PKT_TX_L4_MASK) ==
1915 1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
1918 /* TODO other pseudo checksum modes are
1922 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
1923 ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT;
1924 bd2_bf2 |= (inner_l4_hdr_offset &
1925 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK) <<
1926 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
1928 } /* End MPLSoUDP */
1929 } /* End Tunnel handling */
1931 if (tx_ol_flags & PKT_TX_TCP_SEG) {
1933 if (unlikely(txq->nb_tx_avail <
1934 ETH_TX_MIN_BDS_PER_LSO_PKT))
1936 /* For LSO, packet header and payload must reside on
1937 * buffers pointed by different BDs. Using BD1 for HDR
1938 * and BD2 onwards for data.
1940 hdr_size = mbuf->l2_len + mbuf->l3_len + mbuf->l4_len;
1941 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT;
1943 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1944 /* PKT_TX_TCP_SEG implies PKT_TX_TCP_CKSUM */
1946 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1947 mss = rte_cpu_to_le_16(mbuf->tso_segsz);
1948 /* Using one header BD */
1949 bd3_bf |= rte_cpu_to_le_16(1 <<
1950 ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
1952 if (unlikely(txq->nb_tx_avail <
1953 ETH_TX_MIN_BDS_PER_NON_LSO_PKT))
1956 (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
1957 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
1960 /* Descriptor based VLAN insertion */
1961 if (tx_ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1962 vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
1964 1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
1967 /* Offload the IP checksum in the hardware */
1968 if (tx_ol_flags & PKT_TX_IP_CKSUM) {
1970 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1971 /* There's no DPDK flag to request outer-L4 csum
1972 * offload. But in the case of tunnel if inner L3 or L4
1973 * csum offload is requested then we need to force
1974 * recalculation of L4 tunnel header csum also.
1978 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
1979 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
1983 /* L4 checksum offload (tcp or udp) */
1984 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
1985 (tx_ol_flags & (PKT_TX_UDP_CKSUM | PKT_TX_TCP_CKSUM))) {
1987 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1988 /* There's no DPDK flag to request outer-L4 csum
1989 * offload. But in the case of tunnel if inner L3 or L4
1990 * csum offload is requested then we need to force
1991 * recalculation of L4 tunnel header csum also.
1995 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
1996 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
2000 /* Fill the entry in the SW ring and the BDs in the FW ring */
2002 txq->sw_tx_ring[idx].mbuf = mbuf;
2005 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
2006 memset(bd1, 0, sizeof(struct eth_tx_1st_bd));
2009 /* Map MBUF linear data for DMA and set in the BD1 */
2010 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2012 bd1->data.bitfields = rte_cpu_to_le_16(bd1_bf);
2013 bd1->data.bd_flags.bitfields = bd1_bd_flags_bf;
2014 bd1->data.vlan = vlan;
2016 if (lso_flg || mplsoudp_flg) {
2017 bd2 = (struct eth_tx_2nd_bd *)ecore_chain_produce
2019 memset(bd2, 0, sizeof(struct eth_tx_2nd_bd));
2023 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2026 QEDE_BD_SET_ADDR_LEN(bd2, (hdr_size +
2027 rte_mbuf_data_iova(mbuf)),
2028 mbuf->data_len - hdr_size);
2029 bd2->data.bitfields1 = rte_cpu_to_le_16(bd2_bf1);
2031 bd2->data.bitfields2 =
2032 rte_cpu_to_le_16(bd2_bf2);
2034 bd2->data.tunn_ip_size =
2035 rte_cpu_to_le_16(mbuf->outer_l3_len);
2038 if (lso_flg || (mplsoudp_flg && tunn_ipv6_ext_flg)) {
2039 bd3 = (struct eth_tx_3rd_bd *)
2040 ecore_chain_produce(&txq->tx_pbl);
2041 memset(bd3, 0, sizeof(struct eth_tx_3rd_bd));
2043 bd3->data.bitfields = rte_cpu_to_le_16(bd3_bf);
2045 bd3->data.lso_mss = mss;
2047 bd3->data.tunn_l4_hdr_start_offset_w =
2048 tunn_l4_hdr_start_offset;
2049 bd3->data.tunn_hdr_size_w =
2055 /* Handle fragmented MBUF */
2057 /* Encode scatter gather buffer descriptors if required */
2058 nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3);
2059 bd1->data.nbds = nbds + nb_frags;
2060 txq->nb_tx_avail -= bd1->data.nbds;
2062 rte_prefetch0(txq->sw_tx_ring[TX_PROD(txq)].mbuf);
2064 rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2065 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2066 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);
2067 PMD_TX_LOG(INFO, txq, "lso=%d tunn=%d", lso_flg, tunn_flg);
2073 /* Write value of prod idx into bd_prod */
2074 txq->tx_db.data.bd_prod = bd_prod;
2076 rte_compiler_barrier();
2077 DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
2080 /* Check again for Tx completions */
2081 qede_process_tx_compl(edev, txq);
2083 PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d",
2084 nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());
2090 qede_rxtx_pkts_dummy(__rte_unused void *p_rxq,
2091 __rte_unused struct rte_mbuf **pkts,
2092 __rte_unused uint16_t nb_pkts)