2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 static bool gro_disable = 1; /* mod_param */
13 #define QEDE_FASTPATH_TX (1 << 0)
14 #define QEDE_FASTPATH_RX (1 << 1)
16 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
18 struct rte_mbuf *new_mb = NULL;
19 struct eth_rx_bd *rx_bd;
21 uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
23 new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
24 if (unlikely(!new_mb)) {
26 "Failed to allocate rx buffer "
27 "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
28 idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
29 rte_mempool_avail_count(rxq->mb_pool),
30 rte_mempool_in_use_count(rxq->mb_pool));
33 rxq->sw_rx_ring[idx].mbuf = new_mb;
34 rxq->sw_rx_ring[idx].page_offset = 0;
35 mapping = rte_mbuf_data_dma_addr_default(new_mb);
36 /* Advance PROD and get BD pointer */
37 rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
38 rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
39 rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
44 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
48 if (rxq->sw_rx_ring != NULL) {
49 for (i = 0; i < rxq->nb_rx_desc; i++) {
50 if (rxq->sw_rx_ring[i].mbuf != NULL) {
51 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
52 rxq->sw_rx_ring[i].mbuf = NULL;
58 void qede_rx_queue_release(void *rx_queue)
60 struct qede_rx_queue *rxq = rx_queue;
63 qede_rx_queue_release_mbufs(rxq);
64 rte_free(rxq->sw_rx_ring);
65 rxq->sw_rx_ring = NULL;
71 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
75 PMD_TX_LOG(DEBUG, txq, "releasing %u mbufs\n", txq->nb_tx_desc);
77 if (txq->sw_tx_ring) {
78 for (i = 0; i < txq->nb_tx_desc; i++) {
79 if (txq->sw_tx_ring[i].mbuf) {
80 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf);
81 txq->sw_tx_ring[i].mbuf = NULL;
88 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
89 uint16_t nb_desc, unsigned int socket_id,
90 const struct rte_eth_rxconf *rx_conf,
91 struct rte_mempool *mp)
93 struct qede_dev *qdev = dev->data->dev_private;
94 struct ecore_dev *edev = &qdev->edev;
95 struct rte_eth_dev_data *eth_data = dev->data;
96 struct qede_rx_queue *rxq;
97 uint16_t pkt_len = (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len;
103 PMD_INIT_FUNC_TRACE(edev);
105 /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
106 if (!rte_is_power_of_2(nb_desc)) {
107 DP_ERR(edev, "Ring size %u is not power of 2\n",
112 /* Free memory prior to re-allocation if needed... */
113 if (dev->data->rx_queues[queue_idx] != NULL) {
114 qede_rx_queue_release(dev->data->rx_queues[queue_idx]);
115 dev->data->rx_queues[queue_idx] = NULL;
118 /* First allocate the rx queue data structure */
119 rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
120 RTE_CACHE_LINE_SIZE, socket_id);
123 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
130 rxq->nb_rx_desc = nb_desc;
131 rxq->queue_id = queue_idx;
132 rxq->port_id = dev->data->port_id;
135 data_size = (uint16_t)rte_pktmbuf_data_room_size(mp) -
136 RTE_PKTMBUF_HEADROOM;
139 rxq->rx_buf_size = data_size;
141 DP_INFO(edev, "MTU = %u ; RX buffer = %u\n",
142 qdev->mtu, rxq->rx_buf_size);
144 if (pkt_len > ETHER_MAX_LEN) {
145 dev->data->dev_conf.rxmode.jumbo_frame = 1;
146 DP_NOTICE(edev, false, "jumbo frame enabled\n");
148 dev->data->dev_conf.rxmode.jumbo_frame = 0;
151 /* Allocate the parallel driver ring for Rx buffers */
152 size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
153 rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
154 RTE_CACHE_LINE_SIZE, socket_id);
155 if (!rxq->sw_rx_ring) {
156 DP_NOTICE(edev, false,
157 "Unable to alloc memory for sw_rx_ring on socket %u\n",
164 /* Allocate FW Rx ring */
165 rc = qdev->ops->common->chain_alloc(edev,
166 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
167 ECORE_CHAIN_MODE_NEXT_PTR,
168 ECORE_CHAIN_CNT_TYPE_U16,
170 sizeof(struct eth_rx_bd),
173 if (rc != ECORE_SUCCESS) {
174 DP_NOTICE(edev, false,
175 "Unable to alloc memory for rxbd ring on socket %u\n",
177 rte_free(rxq->sw_rx_ring);
178 rxq->sw_rx_ring = NULL;
184 /* Allocate FW completion ring */
185 rc = qdev->ops->common->chain_alloc(edev,
186 ECORE_CHAIN_USE_TO_CONSUME,
187 ECORE_CHAIN_MODE_PBL,
188 ECORE_CHAIN_CNT_TYPE_U16,
190 sizeof(union eth_rx_cqe),
193 if (rc != ECORE_SUCCESS) {
194 DP_NOTICE(edev, false,
195 "Unable to alloc memory for cqe ring on socket %u\n",
197 /* TBD: Freeing RX BD ring */
198 rte_free(rxq->sw_rx_ring);
199 rxq->sw_rx_ring = NULL;
204 /* Allocate buffers for the Rx ring */
205 for (i = 0; i < rxq->nb_rx_desc; i++) {
206 rc = qede_alloc_rx_buffer(rxq);
208 DP_NOTICE(edev, false,
209 "RX buffer allocation failed at idx=%d\n", i);
214 dev->data->rx_queues[queue_idx] = rxq;
216 DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
217 queue_idx, nb_desc, qdev->mtu, socket_id);
221 qede_rx_queue_release(rxq);
225 void qede_tx_queue_release(void *tx_queue)
227 struct qede_tx_queue *txq = tx_queue;
230 qede_tx_queue_release_mbufs(txq);
231 if (txq->sw_tx_ring) {
232 rte_free(txq->sw_tx_ring);
233 txq->sw_tx_ring = NULL;
241 qede_tx_queue_setup(struct rte_eth_dev *dev,
244 unsigned int socket_id,
245 const struct rte_eth_txconf *tx_conf)
247 struct qede_dev *qdev = dev->data->dev_private;
248 struct ecore_dev *edev = &qdev->edev;
249 struct qede_tx_queue *txq;
252 PMD_INIT_FUNC_TRACE(edev);
254 if (!rte_is_power_of_2(nb_desc)) {
255 DP_ERR(edev, "Ring size %u is not power of 2\n",
260 /* Free memory prior to re-allocation if needed... */
261 if (dev->data->tx_queues[queue_idx] != NULL) {
262 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
263 dev->data->tx_queues[queue_idx] = NULL;
266 txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
267 RTE_CACHE_LINE_SIZE, socket_id);
271 "Unable to allocate memory for txq on socket %u",
276 txq->nb_tx_desc = nb_desc;
278 txq->port_id = dev->data->port_id;
280 rc = qdev->ops->common->chain_alloc(edev,
281 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
282 ECORE_CHAIN_MODE_PBL,
283 ECORE_CHAIN_CNT_TYPE_U16,
285 sizeof(union eth_tx_bd_types),
287 if (rc != ECORE_SUCCESS) {
289 "Unable to allocate memory for txbd ring on socket %u",
291 qede_tx_queue_release(txq);
295 /* Allocate software ring */
296 txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
297 (sizeof(struct qede_tx_entry) *
299 RTE_CACHE_LINE_SIZE, socket_id);
301 if (!txq->sw_tx_ring) {
303 "Unable to allocate memory for txbd ring on socket %u",
305 qede_tx_queue_release(txq);
309 txq->queue_id = queue_idx;
311 txq->nb_tx_avail = txq->nb_tx_desc;
313 txq->tx_free_thresh =
314 tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
315 (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
317 dev->data->tx_queues[queue_idx] = txq;
320 "txq %u num_desc %u tx_free_thresh %u socket %u\n",
321 queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
326 /* This function inits fp content and resets the SB, RXQ and TXQ arrays */
327 static void qede_init_fp(struct qede_dev *qdev)
329 struct qede_fastpath *fp;
330 uint8_t i, rss_id, tc;
331 int fp_rx = qdev->fp_num_rx, rxq = 0, txq = 0;
333 memset((void *)qdev->fp_array, 0, (QEDE_QUEUE_CNT(qdev) *
334 sizeof(*qdev->fp_array)));
335 memset((void *)qdev->sb_array, 0, (QEDE_QUEUE_CNT(qdev) *
336 sizeof(*qdev->sb_array)));
338 fp = &qdev->fp_array[i];
340 fp->type = QEDE_FASTPATH_RX;
343 fp->type = QEDE_FASTPATH_TX;
347 fp->sb_info = &qdev->sb_array[i];
348 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d", "qdev", i);
351 qdev->gro_disable = gro_disable;
354 void qede_free_fp_arrays(struct qede_dev *qdev)
356 /* It asseumes qede_free_mem_load() is called before */
357 if (qdev->fp_array != NULL) {
358 rte_free(qdev->fp_array);
359 qdev->fp_array = NULL;
362 if (qdev->sb_array != NULL) {
363 rte_free(qdev->sb_array);
364 qdev->sb_array = NULL;
368 int qede_alloc_fp_array(struct qede_dev *qdev)
370 struct qede_fastpath *fp;
371 struct ecore_dev *edev = &qdev->edev;
374 qdev->fp_array = rte_calloc("fp", QEDE_QUEUE_CNT(qdev),
375 sizeof(*qdev->fp_array),
376 RTE_CACHE_LINE_SIZE);
378 if (!qdev->fp_array) {
379 DP_ERR(edev, "fp array allocation failed\n");
383 qdev->sb_array = rte_calloc("sb", QEDE_QUEUE_CNT(qdev),
384 sizeof(*qdev->sb_array),
385 RTE_CACHE_LINE_SIZE);
387 if (!qdev->sb_array) {
388 DP_ERR(edev, "sb array allocation failed\n");
389 rte_free(qdev->fp_array);
396 /* This function allocates fast-path status block memory */
398 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
401 struct ecore_dev *edev = &qdev->edev;
402 struct status_block *sb_virt;
406 sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys, sizeof(*sb_virt));
409 DP_ERR(edev, "Status block allocation failed\n");
413 rc = qdev->ops->common->sb_init(edev, sb_info,
414 sb_virt, sb_phys, sb_id,
415 QED_SB_TYPE_L2_QUEUE);
417 DP_ERR(edev, "Status block initialization failed\n");
418 /* TBD: No dma_free_coherent possible */
425 int qede_alloc_fp_resc(struct qede_dev *qdev)
427 struct qede_fastpath *fp;
431 qede_free_fp_arrays(qdev);
433 rc = qede_alloc_fp_array(qdev);
439 for (i = 0; i < QEDE_QUEUE_CNT(qdev); i++) {
440 fp = &qdev->fp_array[i];
441 if (qede_alloc_mem_sb(qdev, fp->sb_info, i)) {
442 qede_free_fp_arrays(qdev);
450 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
452 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
454 qede_free_mem_load(eth_dev);
455 qede_free_fp_arrays(qdev);
459 qede_update_rx_prod(struct qede_dev *edev, struct qede_rx_queue *rxq)
461 uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
462 uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
463 struct eth_rx_prod_data rx_prods = { 0 };
465 /* Update producers */
466 rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
467 rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
469 /* Make sure that the BD and SGE data is updated before updating the
470 * producers since FW might read the BD/SGE right after the producer
475 internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
476 (uint32_t *)&rx_prods);
478 /* mmiowb is needed to synchronize doorbell writes from more than one
479 * processor. It guarantees that the write arrives to the device before
480 * the napi lock is released and another qede_poll is called (possibly
481 * on another CPU). Without this barrier, the next doorbell can bypass
482 * this doorbell. This is applicable to IA64/Altix systems.
486 PMD_RX_LOG(DEBUG, rxq, "bd_prod %u cqe_prod %u\n", bd_prod, cqe_prod);
489 static inline uint32_t
490 qede_rxfh_indir_default(uint32_t index, uint32_t n_rx_rings)
492 return index % n_rx_rings;
495 static void qede_prandom_bytes(uint32_t *buff, size_t bytes)
499 srand((unsigned int)time(NULL));
501 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
506 qede_config_rss(struct rte_eth_dev *eth_dev,
507 struct qed_update_vport_rss_params *rss_params)
509 struct rte_eth_rss_conf rss_conf;
510 enum rte_eth_rx_mq_mode mode = eth_dev->data->dev_conf.rxmode.mq_mode;
511 struct qede_dev *qdev = eth_dev->data->dev_private;
512 struct ecore_dev *edev = &qdev->edev;
518 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
519 key = (uint32_t *)rss_conf.rss_key;
520 hf = rss_conf.rss_hf;
521 PMD_INIT_FUNC_TRACE(edev);
523 /* Check if RSS conditions are met.
524 * Note: Even though its meaningless to enable RSS with one queue, it
525 * could be used to produce RSS Hash, so skipping that check.
528 if (!(mode & ETH_MQ_RX_RSS)) {
529 DP_INFO(edev, "RSS flag is not set\n");
533 DP_INFO(edev, "RSS flag is set\n");
535 if (rss_conf.rss_hf == 0)
536 DP_NOTICE(edev, false, "RSS hash function = 0, disables RSS\n");
538 if (rss_conf.rss_key != NULL)
539 memcpy(qdev->rss_params.rss_key, rss_conf.rss_key,
540 rss_conf.rss_key_len);
542 memset(rss_params, 0, sizeof(*rss_params));
544 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
545 rss_params->rss_ind_table[i] = qede_rxfh_indir_default(i,
548 /* key and protocols */
549 if (rss_conf.rss_key == NULL)
550 qede_prandom_bytes(rss_params->rss_key,
551 sizeof(rss_params->rss_key));
553 memcpy(rss_params->rss_key, rss_conf.rss_key,
554 rss_conf.rss_key_len);
557 rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0;
558 rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0;
559 rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0;
560 rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0;
561 rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0;
562 rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0;
564 rss_params->rss_caps = rss_caps;
566 DP_INFO(edev, "RSS check passes\n");
571 static int qede_start_queues(struct rte_eth_dev *eth_dev, bool clear_stats)
573 struct qede_dev *qdev = eth_dev->data->dev_private;
574 struct ecore_dev *edev = &qdev->edev;
575 struct qed_update_vport_rss_params *rss_params = &qdev->rss_params;
576 struct qed_dev_info *qed_info = &qdev->dev_info.common;
577 struct qed_update_vport_params vport_update_params;
578 struct qede_tx_queue *txq;
579 struct qede_fastpath *fp;
580 dma_addr_t p_phys_table;
583 int vlan_removal_en = 1;
587 fp = &qdev->fp_array[i];
588 if (fp->type & QEDE_FASTPATH_RX) {
589 p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->
591 page_cnt = ecore_chain_get_page_cnt(&fp->rxq->
594 ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
596 rc = qdev->ops->q_rx_start(edev, i, fp->rxq->queue_id,
598 fp->sb_info->igu_sb_id,
600 fp->rxq->rx_buf_size,
601 fp->rxq->rx_bd_ring.p_phys_addr,
604 &fp->rxq->hw_rxq_prod_addr);
606 DP_ERR(edev, "Start rxq #%d failed %d\n",
607 fp->rxq->queue_id, rc);
611 fp->rxq->hw_cons_ptr =
612 &fp->sb_info->sb_virt->pi_array[RX_PI];
614 qede_update_rx_prod(qdev, fp->rxq);
617 if (!(fp->type & QEDE_FASTPATH_TX))
619 for (tc = 0; tc < qdev->num_tc; tc++) {
621 txq_index = tc * QEDE_RSS_CNT(qdev) + i;
623 p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
624 page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
625 rc = qdev->ops->q_tx_start(edev, i, txq->queue_id,
627 fp->sb_info->igu_sb_id,
629 p_phys_table, page_cnt,
630 &txq->doorbell_addr);
632 DP_ERR(edev, "Start txq %u failed %d\n",
638 &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
639 SET_FIELD(txq->tx_db.data.params,
640 ETH_DB_DATA_DEST, DB_DEST_XCM);
641 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
643 SET_FIELD(txq->tx_db.data.params,
644 ETH_DB_DATA_AGG_VAL_SEL,
645 DQ_XCM_ETH_TX_BD_PROD_CMD);
647 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
651 /* Prepare and send the vport enable */
652 memset(&vport_update_params, 0, sizeof(vport_update_params));
653 /* Update MTU via vport update */
654 vport_update_params.mtu = qdev->mtu;
655 vport_update_params.vport_id = 0;
656 vport_update_params.update_vport_active_flg = 1;
657 vport_update_params.vport_active_flg = 1;
660 if (qed_info->mf_mode == MF_NPAR && qed_info->tx_switching) {
661 /* TBD: Check SRIOV enabled for VF */
662 vport_update_params.update_tx_switching_flg = 1;
663 vport_update_params.tx_switching_flg = 1;
666 if (!qede_config_rss(eth_dev, rss_params)) {
667 vport_update_params.update_rss_flg = 1;
669 qdev->rss_enabled = 1;
670 DP_INFO(edev, "Updating RSS flag\n");
672 qdev->rss_enabled = 0;
673 DP_INFO(edev, "Not Updating RSS flag\n");
676 rte_memcpy(&vport_update_params.rss_params, rss_params,
677 sizeof(*rss_params));
679 rc = qdev->ops->vport_update(edev, &vport_update_params);
681 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
689 static bool qede_tunn_exist(uint16_t flag)
691 return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
692 PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
695 static inline uint8_t qede_check_tunn_csum(uint16_t flag)
698 uint16_t csum_flag = 0;
700 if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
701 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
702 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
703 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT;
705 if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
706 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag) {
707 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
708 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
709 tcsum = QEDE_TUNN_CSUM_UNNECESSARY;
712 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
713 PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT |
714 PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
715 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
717 if (csum_flag & flag)
718 return QEDE_CSUM_ERROR;
720 return QEDE_CSUM_UNNECESSARY | tcsum;
723 static inline uint8_t qede_tunn_exist(uint16_t flag)
728 static inline uint8_t qede_check_tunn_csum(uint16_t flag)
734 static inline uint8_t qede_check_notunn_csum(uint16_t flag)
737 uint16_t csum_flag = 0;
739 if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
740 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag) {
741 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
742 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
743 csum = QEDE_CSUM_UNNECESSARY;
746 csum_flag |= PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
747 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
749 if (csum_flag & flag)
750 return QEDE_CSUM_ERROR;
755 static inline uint8_t qede_check_csum(uint16_t flag)
757 if (likely(!qede_tunn_exist(flag)))
758 return qede_check_notunn_csum(flag);
760 return qede_check_tunn_csum(flag);
763 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
765 ecore_chain_consume(&rxq->rx_bd_ring);
770 qede_reuse_page(struct qede_dev *qdev,
771 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
773 struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
774 uint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
775 struct qede_rx_entry *curr_prod;
776 dma_addr_t new_mapping;
778 curr_prod = &rxq->sw_rx_ring[idx];
779 *curr_prod = *curr_cons;
781 new_mapping = rte_mbuf_data_dma_addr_default(curr_prod->mbuf) +
782 curr_prod->page_offset;
784 rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
785 rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
791 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
792 struct qede_dev *qdev, uint8_t count)
794 struct qede_rx_entry *curr_cons;
796 for (; count > 0; count--) {
797 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
798 qede_reuse_page(qdev, rxq, curr_cons);
799 qede_rx_bd_ring_consume(rxq);
803 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
806 /* TBD - L4 indications needed ? */
807 uint16_t protocol = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
808 PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) & flags);
810 /* protocol = 3 means LLC/SNAP over Ethernet */
811 if (unlikely(protocol == 0 || protocol == 3))
812 p_type = RTE_PTYPE_UNKNOWN;
813 else if (protocol == 1)
814 p_type = RTE_PTYPE_L3_IPV4;
815 else if (protocol == 2)
816 p_type = RTE_PTYPE_L3_IPV6;
818 return RTE_PTYPE_L2_ETHER | p_type;
822 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
824 struct qede_rx_queue *rxq = p_rxq;
825 struct qede_dev *qdev = rxq->qdev;
826 struct ecore_dev *edev = &qdev->edev;
827 struct qede_fastpath *fp = &qdev->fp_array[rxq->queue_id];
828 uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
830 union eth_rx_cqe *cqe;
831 struct eth_fast_path_rx_reg_cqe *fp_cqe;
832 register struct rte_mbuf *rx_mb = NULL;
833 enum eth_rx_cqe_type cqe_type;
835 uint16_t preload_idx;
838 enum rss_hash_type htype;
840 hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
841 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
845 if (hw_comp_cons == sw_comp_cons)
848 while (sw_comp_cons != hw_comp_cons) {
849 /* Get the CQE from the completion ring */
851 (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
852 cqe_type = cqe->fast_path_regular.type;
854 if (unlikely(cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH)) {
855 PMD_RX_LOG(DEBUG, rxq, "Got a slowath CQE\n");
857 qdev->ops->eth_cqe_completion(edev, fp->id,
858 (struct eth_slow_path_rx_cqe *)cqe);
862 /* Get the data from the SW ring */
863 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
864 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
865 assert(rx_mb != NULL);
868 fp_cqe = &cqe->fast_path_regular;
870 len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
871 pad = fp_cqe->placement_offset;
872 assert((len + pad) <= rx_mb->buf_len);
874 PMD_RX_LOG(DEBUG, rxq,
875 "CQE type = 0x%x, flags = 0x%x, vlan = 0x%x"
876 " len = %u, parsing_flags = %d\n",
877 cqe_type, fp_cqe->bitfields,
878 rte_le_to_cpu_16(fp_cqe->vlan_tag),
879 len, rte_le_to_cpu_16(fp_cqe->pars_flags.flags));
881 /* If this is an error packet then drop it */
883 rte_le_to_cpu_16(cqe->fast_path_regular.pars_flags.flags);
884 csum_flag = qede_check_csum(parse_flag);
885 if (unlikely(csum_flag == QEDE_CSUM_ERROR)) {
887 "CQE in CONS = %u has error, flags = 0x%x "
888 "dropping incoming packet\n",
889 sw_comp_cons, parse_flag);
891 qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
895 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
897 "New buffer allocation failed,"
898 "dropping incoming packet\n");
899 qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
900 rte_eth_devices[rxq->port_id].
901 data->rx_mbuf_alloc_failed++;
902 rxq->rx_alloc_errors++;
906 qede_rx_bd_ring_consume(rxq);
908 /* Prefetch next mbuf while processing current one. */
909 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
910 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
912 if (fp_cqe->bd_num != 1)
913 PMD_RX_LOG(DEBUG, rxq,
914 "Jumbo-over-BD packet not supported\n");
916 /* Update MBUF fields */
918 rx_mb->data_off = pad + RTE_PKTMBUF_HEADROOM;
920 rx_mb->data_len = len;
921 rx_mb->pkt_len = len;
922 rx_mb->port = rxq->port_id;
923 rx_mb->packet_type = qede_rx_cqe_to_pkt_type(parse_flag);
925 htype = (uint8_t)GET_FIELD(fp_cqe->bitfields,
926 ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
927 if (qdev->rss_enabled && htype) {
928 rx_mb->ol_flags |= PKT_RX_RSS_HASH;
929 rx_mb->hash.rss = rte_le_to_cpu_32(fp_cqe->rss_hash);
930 PMD_RX_LOG(DEBUG, rxq, "Hash result 0x%x\n",
934 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
936 if (CQE_HAS_VLAN(parse_flag)) {
937 rx_mb->vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
938 rx_mb->ol_flags |= PKT_RX_VLAN_PKT;
941 if (CQE_HAS_OUTER_VLAN(parse_flag)) {
942 /* FW does not provide indication of Outer VLAN tag,
943 * which is always stripped, so vlan_tci_outer is set
944 * to 0. Here vlan_tag represents inner VLAN tag.
946 rx_mb->vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
947 rx_mb->ol_flags |= PKT_RX_QINQ_PKT;
950 rx_pkts[rx_pkt] = rx_mb;
953 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
954 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
955 if (rx_pkt == nb_pkts) {
956 PMD_RX_LOG(DEBUG, rxq,
957 "Budget reached nb_pkts=%u received=%u\n",
963 qede_update_rx_prod(qdev, rxq);
965 PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d\n", rx_pkt, rte_lcore_id());
971 qede_free_tx_pkt(struct ecore_dev *edev, struct qede_tx_queue *txq)
973 uint16_t idx = TX_CONS(txq);
974 struct eth_tx_bd *tx_data_bd;
975 struct rte_mbuf *mbuf = txq->sw_tx_ring[idx].mbuf;
977 if (unlikely(!mbuf)) {
979 "null mbuf nb_tx_desc %u nb_tx_avail %u "
980 "sw_tx_cons %u sw_tx_prod %u\n",
981 txq->nb_tx_desc, txq->nb_tx_avail, idx,
987 rte_pktmbuf_free_seg(mbuf);
988 txq->sw_tx_ring[idx].mbuf = NULL;
989 ecore_chain_consume(&txq->tx_pbl);
995 static inline uint16_t
996 qede_process_tx_compl(struct ecore_dev *edev, struct qede_tx_queue *txq)
998 uint16_t tx_compl = 0;
1002 hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
1003 rte_compiler_barrier();
1005 while (hw_bd_cons != ecore_chain_get_cons_idx(&txq->tx_pbl)) {
1006 rc = qede_free_tx_pkt(edev, txq);
1008 DP_NOTICE(edev, false,
1009 "hw_bd_cons = %d, chain_cons=%d\n",
1011 ecore_chain_get_cons_idx(&txq->tx_pbl));
1014 txq->sw_tx_cons++; /* Making TXD available */
1018 PMD_TX_LOG(DEBUG, txq, "Tx compl %u sw_tx_cons %u avail %u\n",
1019 tx_compl, txq->sw_tx_cons, txq->nb_tx_avail);
1024 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1026 struct qede_tx_queue *txq = p_txq;
1027 struct qede_dev *qdev = txq->qdev;
1028 struct ecore_dev *edev = &qdev->edev;
1029 struct qede_fastpath *fp;
1030 struct eth_tx_1st_bd *first_bd;
1031 uint16_t nb_tx_pkts;
1032 uint16_t nb_pkt_sent = 0;
1037 fp = &qdev->fp_array[QEDE_RSS_COUNT(qdev) + txq->queue_id];
1039 if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
1040 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u\n",
1041 nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
1042 (void)qede_process_tx_compl(edev, txq);
1045 nb_tx_pkts = RTE_MIN(nb_pkts, (txq->nb_tx_avail / MAX_NUM_TX_BDS));
1046 if (unlikely(nb_tx_pkts == 0)) {
1047 PMD_TX_LOG(DEBUG, txq, "Out of BDs nb_pkts=%u avail=%u\n",
1048 nb_pkts, txq->nb_tx_avail);
1052 tx_count = nb_tx_pkts;
1053 while (nb_tx_pkts--) {
1054 /* Fill the entry in the SW ring and the BDs in the FW ring */
1056 struct rte_mbuf *mbuf = *tx_pkts++;
1057 txq->sw_tx_ring[idx].mbuf = mbuf;
1058 first_bd = (struct eth_tx_1st_bd *)
1059 ecore_chain_produce(&txq->tx_pbl);
1060 first_bd->data.bd_flags.bitfields =
1061 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
1062 /* Map MBUF linear data for DMA and set in the first BD */
1063 QEDE_BD_SET_ADDR_LEN(first_bd, rte_mbuf_data_dma_addr(mbuf),
1066 /* Descriptor based VLAN insertion */
1067 if (mbuf->ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1068 first_bd->data.vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
1069 first_bd->data.bd_flags.bitfields |=
1070 1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
1073 /* Offload the IP checksum in the hardware */
1074 if (mbuf->ol_flags & PKT_TX_IP_CKSUM) {
1075 first_bd->data.bd_flags.bitfields |=
1076 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1079 /* L4 checksum offload (tcp or udp) */
1080 if (mbuf->ol_flags & (PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
1081 first_bd->data.bd_flags.bitfields |=
1082 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1083 /* IPv6 + extn. -> later */
1085 first_bd->data.nbds = MAX_NUM_TX_BDS;
1087 rte_prefetch0(txq->sw_tx_ring[TX_PROD(txq)].mbuf);
1090 rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1094 /* Write value of prod idx into bd_prod */
1095 txq->tx_db.data.bd_prod = bd_prod;
1097 rte_compiler_barrier();
1098 DIRECT_REG_WR(edev, txq->doorbell_addr, txq->tx_db.raw);
1101 /* Check again for Tx completions */
1102 (void)qede_process_tx_compl(edev, txq);
1104 PMD_TX_LOG(DEBUG, txq, "to_send=%u can_send=%u sent=%u core=%d\n",
1105 nb_pkts, tx_count, nb_pkt_sent, rte_lcore_id());
1110 static void qede_init_fp_queue(struct rte_eth_dev *eth_dev)
1112 struct qede_dev *qdev = eth_dev->data->dev_private;
1113 struct qede_fastpath *fp;
1114 uint8_t i, rss_id, txq_index, tc;
1115 int rxq = 0, txq = 0;
1118 fp = &qdev->fp_array[i];
1119 if (fp->type & QEDE_FASTPATH_RX) {
1120 fp->rxq = eth_dev->data->rx_queues[i];
1121 fp->rxq->queue_id = rxq++;
1124 if (fp->type & QEDE_FASTPATH_TX) {
1125 for (tc = 0; tc < qdev->num_tc; tc++) {
1126 txq_index = tc * QEDE_TSS_CNT(qdev) + txq;
1128 eth_dev->data->tx_queues[txq_index];
1129 fp->txqs[tc]->queue_id = txq_index;
1136 int qede_dev_start(struct rte_eth_dev *eth_dev)
1138 struct qede_dev *qdev = eth_dev->data->dev_private;
1139 struct ecore_dev *edev = &qdev->edev;
1140 struct qed_link_output link_output;
1141 struct qede_fastpath *fp;
1144 DP_INFO(edev, "Device state is %d\n", qdev->state);
1146 if (qdev->state == QEDE_DEV_START) {
1147 DP_INFO(edev, "Port is already started\n");
1151 if (qdev->state == QEDE_DEV_CONFIG)
1152 qede_init_fp_queue(eth_dev);
1154 rc = qede_start_queues(eth_dev, true);
1156 DP_ERR(edev, "Failed to start queues\n");
1161 /* Bring-up the link */
1162 qede_dev_set_link_state(eth_dev, true);
1165 if (qede_reset_fp_rings(qdev))
1168 /* Start/resume traffic */
1169 qdev->ops->fastpath_start(edev);
1171 qdev->state = QEDE_DEV_START;
1173 DP_INFO(edev, "dev_state is QEDE_DEV_START\n");
1178 static int qede_drain_txq(struct qede_dev *qdev,
1179 struct qede_tx_queue *txq, bool allow_drain)
1181 struct ecore_dev *edev = &qdev->edev;
1184 while (txq->sw_tx_cons != txq->sw_tx_prod) {
1185 qede_process_tx_compl(edev, txq);
1188 DP_NOTICE(edev, false,
1189 "Tx queue[%u] is stuck,"
1190 "requesting MCP to drain\n",
1192 rc = qdev->ops->common->drain(edev);
1195 return qede_drain_txq(qdev, txq, false);
1198 DP_NOTICE(edev, false,
1199 "Timeout waiting for tx queue[%d]:"
1200 "PROD=%d, CONS=%d\n",
1201 txq->queue_id, txq->sw_tx_prod,
1207 rte_compiler_barrier();
1210 /* FW finished processing, wait for HW to transmit all tx packets */
1216 static int qede_stop_queues(struct qede_dev *qdev)
1218 struct qed_update_vport_params vport_update_params;
1219 struct ecore_dev *edev = &qdev->edev;
1222 /* Disable the vport */
1223 memset(&vport_update_params, 0, sizeof(vport_update_params));
1224 vport_update_params.vport_id = 0;
1225 vport_update_params.update_vport_active_flg = 1;
1226 vport_update_params.vport_active_flg = 0;
1227 vport_update_params.update_rss_flg = 0;
1229 DP_INFO(edev, "Deactivate vport\n");
1231 rc = qdev->ops->vport_update(edev, &vport_update_params);
1233 DP_ERR(edev, "Failed to update vport\n");
1237 DP_INFO(edev, "Flushing tx queues\n");
1239 /* Flush Tx queues. If needed, request drain from MCP */
1241 struct qede_fastpath *fp = &qdev->fp_array[i];
1243 if (fp->type & QEDE_FASTPATH_TX) {
1244 for (tc = 0; tc < qdev->num_tc; tc++) {
1245 struct qede_tx_queue *txq = fp->txqs[tc];
1247 rc = qede_drain_txq(qdev, txq, true);
1254 /* Stop all Queues in reverse order */
1255 for (i = QEDE_QUEUE_CNT(qdev) - 1; i >= 0; i--) {
1256 struct qed_stop_rxq_params rx_params;
1258 /* Stop the Tx Queue(s) */
1259 if (qdev->fp_array[i].type & QEDE_FASTPATH_TX) {
1260 for (tc = 0; tc < qdev->num_tc; tc++) {
1261 struct qed_stop_txq_params tx_params;
1264 tx_params.rss_id = i;
1265 val = qdev->fp_array[i].txqs[tc]->queue_id;
1266 tx_params.tx_queue_id = val;
1268 DP_INFO(edev, "Stopping tx queues\n");
1269 rc = qdev->ops->q_tx_stop(edev, &tx_params);
1271 DP_ERR(edev, "Failed to stop TXQ #%d\n",
1272 tx_params.tx_queue_id);
1278 /* Stop the Rx Queue */
1279 if (qdev->fp_array[i].type & QEDE_FASTPATH_RX) {
1280 memset(&rx_params, 0, sizeof(rx_params));
1281 rx_params.rss_id = i;
1282 rx_params.rx_queue_id = qdev->fp_array[i].rxq->queue_id;
1283 rx_params.eq_completion_only = 1;
1285 DP_INFO(edev, "Stopping rx queues\n");
1287 rc = qdev->ops->q_rx_stop(edev, &rx_params);
1289 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
1298 int qede_reset_fp_rings(struct qede_dev *qdev)
1300 struct qede_fastpath *fp;
1301 struct qede_tx_queue *txq;
1305 for_each_queue(id) {
1306 fp = &qdev->fp_array[id];
1308 if (fp->type & QEDE_FASTPATH_RX) {
1309 DP_INFO(&qdev->edev,
1310 "Reset FP chain for RSS %u\n", id);
1311 qede_rx_queue_release_mbufs(fp->rxq);
1312 ecore_chain_reset(&fp->rxq->rx_bd_ring);
1313 ecore_chain_reset(&fp->rxq->rx_comp_ring);
1314 fp->rxq->sw_rx_prod = 0;
1315 fp->rxq->sw_rx_cons = 0;
1316 *fp->rxq->hw_cons_ptr = 0;
1317 for (i = 0; i < fp->rxq->nb_rx_desc; i++) {
1318 if (qede_alloc_rx_buffer(fp->rxq)) {
1320 "RX buffer allocation failed\n");
1325 if (fp->type & QEDE_FASTPATH_TX) {
1326 for (tc = 0; tc < qdev->num_tc; tc++) {
1328 ecore_chain_reset(&txq->tx_pbl);
1329 txq->sw_tx_cons = 0;
1330 txq->sw_tx_prod = 0;
1331 *txq->hw_cons_ptr = 0;
1339 /* This function frees all memory of a single fp */
1340 static void qede_free_mem_fp(struct rte_eth_dev *eth_dev,
1341 struct qede_fastpath *fp)
1343 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1346 qede_rx_queue_release(fp->rxq);
1347 for (tc = 0; tc < qdev->num_tc; tc++) {
1348 qede_tx_queue_release(fp->txqs[tc]);
1349 eth_dev->data->tx_queues[tc] = NULL;
1353 void qede_free_mem_load(struct rte_eth_dev *eth_dev)
1355 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1356 struct qede_fastpath *fp;
1359 for_each_queue(rss_id) {
1360 fp = &qdev->fp_array[rss_id];
1361 qede_free_mem_fp(eth_dev, fp);
1362 eth_dev->data->rx_queues[rss_id] = NULL;
1366 void qede_dev_stop(struct rte_eth_dev *eth_dev)
1368 struct qede_dev *qdev = eth_dev->data->dev_private;
1369 struct ecore_dev *edev = &qdev->edev;
1371 DP_INFO(edev, "port %u\n", eth_dev->data->port_id);
1373 if (qdev->state != QEDE_DEV_START) {
1374 DP_INFO(edev, "Device not yet started\n");
1378 if (qede_stop_queues(qdev))
1379 DP_ERR(edev, "Didn't succeed to close queues\n");
1381 DP_INFO(edev, "Stopped queues\n");
1383 qdev->ops->fastpath_stop(edev);
1385 /* Bring the link down */
1386 qede_dev_set_link_state(eth_dev, false);
1388 qdev->state = QEDE_DEV_STOP;
1390 DP_INFO(edev, "dev_state is QEDE_DEV_STOP\n");