2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 static bool gro_disable = 1; /* mod_param */
13 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
15 struct rte_mbuf *new_mb = NULL;
16 struct eth_rx_bd *rx_bd;
18 uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
20 new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
21 if (unlikely(!new_mb)) {
23 "Failed to allocate rx buffer "
24 "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
25 idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
26 rte_mempool_avail_count(rxq->mb_pool),
27 rte_mempool_in_use_count(rxq->mb_pool));
30 rxq->sw_rx_ring[idx].mbuf = new_mb;
31 rxq->sw_rx_ring[idx].page_offset = 0;
32 mapping = rte_mbuf_data_dma_addr_default(new_mb);
33 /* Advance PROD and get BD pointer */
34 rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
35 rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
36 rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
41 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
45 if (rxq->sw_rx_ring != NULL) {
46 for (i = 0; i < rxq->nb_rx_desc; i++) {
47 if (rxq->sw_rx_ring[i].mbuf != NULL) {
48 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
49 rxq->sw_rx_ring[i].mbuf = NULL;
55 void qede_rx_queue_release(void *rx_queue)
57 struct qede_rx_queue *rxq = rx_queue;
60 qede_rx_queue_release_mbufs(rxq);
61 rte_free(rxq->sw_rx_ring);
62 rxq->sw_rx_ring = NULL;
68 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
72 PMD_TX_LOG(DEBUG, txq, "releasing %u mbufs", txq->nb_tx_desc);
74 if (txq->sw_tx_ring) {
75 for (i = 0; i < txq->nb_tx_desc; i++) {
76 if (txq->sw_tx_ring[i].mbuf) {
77 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf);
78 txq->sw_tx_ring[i].mbuf = NULL;
85 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
86 uint16_t nb_desc, unsigned int socket_id,
87 const struct rte_eth_rxconf *rx_conf,
88 struct rte_mempool *mp)
90 struct qede_dev *qdev = dev->data->dev_private;
91 struct ecore_dev *edev = &qdev->edev;
92 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
93 struct qede_rx_queue *rxq;
94 uint16_t max_rx_pkt_len;
100 PMD_INIT_FUNC_TRACE(edev);
102 /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
103 if (!rte_is_power_of_2(nb_desc)) {
104 DP_ERR(edev, "Ring size %u is not power of 2\n",
109 /* Free memory prior to re-allocation if needed... */
110 if (dev->data->rx_queues[queue_idx] != NULL) {
111 qede_rx_queue_release(dev->data->rx_queues[queue_idx]);
112 dev->data->rx_queues[queue_idx] = NULL;
115 /* First allocate the rx queue data structure */
116 rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
117 RTE_CACHE_LINE_SIZE, socket_id);
120 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
127 rxq->nb_rx_desc = nb_desc;
128 rxq->queue_id = queue_idx;
129 rxq->port_id = dev->data->port_id;
130 max_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len;
131 qdev->mtu = max_rx_pkt_len;
133 /* Fix up RX buffer size */
134 bufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
135 if ((rxmode->enable_scatter) ||
136 (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {
137 if (!dev->data->scattered_rx) {
138 DP_INFO(edev, "Forcing scatter-gather mode\n");
139 dev->data->scattered_rx = 1;
142 if (dev->data->scattered_rx)
143 rxq->rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
145 rxq->rx_buf_size = qdev->mtu + QEDE_ETH_OVERHEAD;
146 /* Align to cache-line size if needed */
147 rxq->rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rxq->rx_buf_size);
149 DP_INFO(edev, "mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\n",
150 qdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);
152 /* Allocate the parallel driver ring for Rx buffers */
153 size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
154 rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
155 RTE_CACHE_LINE_SIZE, socket_id);
156 if (!rxq->sw_rx_ring) {
157 DP_NOTICE(edev, false,
158 "Unable to alloc memory for sw_rx_ring on socket %u\n",
165 /* Allocate FW Rx ring */
166 rc = qdev->ops->common->chain_alloc(edev,
167 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
168 ECORE_CHAIN_MODE_NEXT_PTR,
169 ECORE_CHAIN_CNT_TYPE_U16,
171 sizeof(struct eth_rx_bd),
175 if (rc != ECORE_SUCCESS) {
176 DP_NOTICE(edev, false,
177 "Unable to alloc memory for rxbd ring on socket %u\n",
179 rte_free(rxq->sw_rx_ring);
180 rxq->sw_rx_ring = NULL;
186 /* Allocate FW completion ring */
187 rc = qdev->ops->common->chain_alloc(edev,
188 ECORE_CHAIN_USE_TO_CONSUME,
189 ECORE_CHAIN_MODE_PBL,
190 ECORE_CHAIN_CNT_TYPE_U16,
192 sizeof(union eth_rx_cqe),
196 if (rc != ECORE_SUCCESS) {
197 DP_NOTICE(edev, false,
198 "Unable to alloc memory for cqe ring on socket %u\n",
200 /* TBD: Freeing RX BD ring */
201 rte_free(rxq->sw_rx_ring);
202 rxq->sw_rx_ring = NULL;
207 /* Allocate buffers for the Rx ring */
208 for (i = 0; i < rxq->nb_rx_desc; i++) {
209 rc = qede_alloc_rx_buffer(rxq);
211 DP_NOTICE(edev, false,
212 "RX buffer allocation failed at idx=%d\n", i);
217 dev->data->rx_queues[queue_idx] = rxq;
219 DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
220 queue_idx, nb_desc, qdev->mtu, socket_id);
224 qede_rx_queue_release(rxq);
228 void qede_tx_queue_release(void *tx_queue)
230 struct qede_tx_queue *txq = tx_queue;
233 qede_tx_queue_release_mbufs(txq);
234 if (txq->sw_tx_ring) {
235 rte_free(txq->sw_tx_ring);
236 txq->sw_tx_ring = NULL;
244 qede_tx_queue_setup(struct rte_eth_dev *dev,
247 unsigned int socket_id,
248 const struct rte_eth_txconf *tx_conf)
250 struct qede_dev *qdev = dev->data->dev_private;
251 struct ecore_dev *edev = &qdev->edev;
252 struct qede_tx_queue *txq;
255 PMD_INIT_FUNC_TRACE(edev);
257 if (!rte_is_power_of_2(nb_desc)) {
258 DP_ERR(edev, "Ring size %u is not power of 2\n",
263 /* Free memory prior to re-allocation if needed... */
264 if (dev->data->tx_queues[queue_idx] != NULL) {
265 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
266 dev->data->tx_queues[queue_idx] = NULL;
269 txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
270 RTE_CACHE_LINE_SIZE, socket_id);
274 "Unable to allocate memory for txq on socket %u",
279 txq->nb_tx_desc = nb_desc;
281 txq->port_id = dev->data->port_id;
283 rc = qdev->ops->common->chain_alloc(edev,
284 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
285 ECORE_CHAIN_MODE_PBL,
286 ECORE_CHAIN_CNT_TYPE_U16,
288 sizeof(union eth_tx_bd_types),
291 if (rc != ECORE_SUCCESS) {
293 "Unable to allocate memory for txbd ring on socket %u",
295 qede_tx_queue_release(txq);
299 /* Allocate software ring */
300 txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
301 (sizeof(struct qede_tx_entry) *
303 RTE_CACHE_LINE_SIZE, socket_id);
305 if (!txq->sw_tx_ring) {
307 "Unable to allocate memory for txbd ring on socket %u",
309 qede_tx_queue_release(txq);
313 txq->queue_id = queue_idx;
315 txq->nb_tx_avail = txq->nb_tx_desc;
317 txq->tx_free_thresh =
318 tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
319 (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
321 dev->data->tx_queues[queue_idx] = txq;
324 "txq %u num_desc %u tx_free_thresh %u socket %u\n",
325 queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
330 /* This function inits fp content and resets the SB, RXQ and TXQ arrays */
331 static void qede_init_fp(struct qede_dev *qdev)
333 struct qede_fastpath *fp;
334 uint8_t i, rss_id, tc;
335 int fp_rx = qdev->fp_num_rx, rxq = 0, txq = 0;
337 memset((void *)qdev->fp_array, 0, (QEDE_QUEUE_CNT(qdev) *
338 sizeof(*qdev->fp_array)));
339 memset((void *)qdev->sb_array, 0, (QEDE_QUEUE_CNT(qdev) *
340 sizeof(*qdev->sb_array)));
342 fp = &qdev->fp_array[i];
344 fp->type = QEDE_FASTPATH_RX;
347 fp->type = QEDE_FASTPATH_TX;
351 fp->sb_info = &qdev->sb_array[i];
352 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d", "qdev", i);
355 qdev->gro_disable = gro_disable;
358 void qede_free_fp_arrays(struct qede_dev *qdev)
360 /* It asseumes qede_free_mem_load() is called before */
361 if (qdev->fp_array != NULL) {
362 rte_free(qdev->fp_array);
363 qdev->fp_array = NULL;
366 if (qdev->sb_array != NULL) {
367 rte_free(qdev->sb_array);
368 qdev->sb_array = NULL;
372 int qede_alloc_fp_array(struct qede_dev *qdev)
374 struct qede_fastpath *fp;
375 struct ecore_dev *edev = &qdev->edev;
378 qdev->fp_array = rte_calloc("fp", QEDE_QUEUE_CNT(qdev),
379 sizeof(*qdev->fp_array),
380 RTE_CACHE_LINE_SIZE);
382 if (!qdev->fp_array) {
383 DP_ERR(edev, "fp array allocation failed\n");
387 qdev->sb_array = rte_calloc("sb", QEDE_QUEUE_CNT(qdev),
388 sizeof(*qdev->sb_array),
389 RTE_CACHE_LINE_SIZE);
391 if (!qdev->sb_array) {
392 DP_ERR(edev, "sb array allocation failed\n");
393 rte_free(qdev->fp_array);
400 /* This function allocates fast-path status block memory */
402 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
405 struct ecore_dev *edev = &qdev->edev;
406 struct status_block *sb_virt;
410 sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys, sizeof(*sb_virt));
413 DP_ERR(edev, "Status block allocation failed\n");
417 rc = qdev->ops->common->sb_init(edev, sb_info,
418 sb_virt, sb_phys, sb_id,
419 QED_SB_TYPE_L2_QUEUE);
421 DP_ERR(edev, "Status block initialization failed\n");
422 /* TBD: No dma_free_coherent possible */
429 int qede_alloc_fp_resc(struct qede_dev *qdev)
431 struct ecore_dev *edev = &qdev->edev;
432 struct qede_fastpath *fp;
439 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
441 num_sbs = ecore_cxt_get_proto_cid_count
442 (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL);
445 DP_ERR(edev, "No status blocks available\n");
450 qede_free_fp_arrays(qdev);
452 rc = qede_alloc_fp_array(qdev);
458 for (i = 0; i < QEDE_QUEUE_CNT(qdev); i++) {
459 fp = &qdev->fp_array[i];
461 sb_idx = i % num_sbs;
464 if (qede_alloc_mem_sb(qdev, fp->sb_info, sb_idx)) {
465 qede_free_fp_arrays(qdev);
473 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
475 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
477 qede_free_mem_load(eth_dev);
478 qede_free_fp_arrays(qdev);
482 qede_update_rx_prod(struct qede_dev *edev, struct qede_rx_queue *rxq)
484 uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
485 uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
486 struct eth_rx_prod_data rx_prods = { 0 };
488 /* Update producers */
489 rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
490 rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
492 /* Make sure that the BD and SGE data is updated before updating the
493 * producers since FW might read the BD/SGE right after the producer
498 internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
499 (uint32_t *)&rx_prods);
501 /* mmiowb is needed to synchronize doorbell writes from more than one
502 * processor. It guarantees that the write arrives to the device before
503 * the napi lock is released and another qede_poll is called (possibly
504 * on another CPU). Without this barrier, the next doorbell can bypass
505 * this doorbell. This is applicable to IA64/Altix systems.
509 PMD_RX_LOG(DEBUG, rxq, "bd_prod %u cqe_prod %u", bd_prod, cqe_prod);
512 static int qede_start_queues(struct rte_eth_dev *eth_dev, bool clear_stats)
514 struct qede_dev *qdev = eth_dev->data->dev_private;
515 struct ecore_dev *edev = &qdev->edev;
516 struct ecore_queue_start_common_params q_params;
517 struct qed_dev_info *qed_info = &qdev->dev_info.common;
518 struct qed_update_vport_params vport_update_params;
519 struct qede_tx_queue *txq;
520 struct qede_fastpath *fp;
521 dma_addr_t p_phys_table;
524 int vlan_removal_en = 1;
528 fp = &qdev->fp_array[i];
529 if (fp->type & QEDE_FASTPATH_RX) {
530 struct ecore_rxq_start_ret_params ret_params;
532 p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->
534 page_cnt = ecore_chain_get_page_cnt(&fp->rxq->
537 memset(&ret_params, 0, sizeof(ret_params));
538 memset(&q_params, 0, sizeof(q_params));
539 q_params.queue_id = i;
540 q_params.vport_id = 0;
541 q_params.sb = fp->sb_info->igu_sb_id;
542 q_params.sb_idx = RX_PI;
544 ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
546 rc = qdev->ops->q_rx_start(edev, i, &q_params,
547 fp->rxq->rx_buf_size,
548 fp->rxq->rx_bd_ring.p_phys_addr,
553 DP_ERR(edev, "Start rxq #%d failed %d\n",
554 fp->rxq->queue_id, rc);
558 /* Use the return parameters */
559 fp->rxq->hw_rxq_prod_addr = ret_params.p_prod;
560 fp->rxq->handle = ret_params.p_handle;
562 fp->rxq->hw_cons_ptr =
563 &fp->sb_info->sb_virt->pi_array[RX_PI];
565 qede_update_rx_prod(qdev, fp->rxq);
568 if (!(fp->type & QEDE_FASTPATH_TX))
570 for (tc = 0; tc < qdev->num_tc; tc++) {
571 struct ecore_txq_start_ret_params ret_params;
574 txq_index = tc * QEDE_RSS_COUNT(qdev) + i;
576 p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
577 page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
579 memset(&q_params, 0, sizeof(q_params));
580 memset(&ret_params, 0, sizeof(ret_params));
581 q_params.queue_id = txq->queue_id;
582 q_params.vport_id = 0;
583 q_params.sb = fp->sb_info->igu_sb_id;
584 q_params.sb_idx = TX_PI(tc);
586 rc = qdev->ops->q_tx_start(edev, i, &q_params,
588 page_cnt, /* **pp_doorbell */
591 DP_ERR(edev, "Start txq %u failed %d\n",
596 txq->doorbell_addr = ret_params.p_doorbell;
597 txq->handle = ret_params.p_handle;
600 &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
601 SET_FIELD(txq->tx_db.data.params,
602 ETH_DB_DATA_DEST, DB_DEST_XCM);
603 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
605 SET_FIELD(txq->tx_db.data.params,
606 ETH_DB_DATA_AGG_VAL_SEL,
607 DQ_XCM_ETH_TX_BD_PROD_CMD);
609 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
613 /* Prepare and send the vport enable */
614 memset(&vport_update_params, 0, sizeof(vport_update_params));
615 /* Update MTU via vport update */
616 vport_update_params.mtu = qdev->mtu;
617 vport_update_params.vport_id = 0;
618 vport_update_params.update_vport_active_flg = 1;
619 vport_update_params.vport_active_flg = 1;
622 if (qed_info->mf_mode == MF_NPAR && qed_info->tx_switching) {
623 /* TBD: Check SRIOV enabled for VF */
624 vport_update_params.update_tx_switching_flg = 1;
625 vport_update_params.tx_switching_flg = 1;
628 rc = qdev->ops->vport_update(edev, &vport_update_params);
630 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
637 static bool qede_tunn_exist(uint16_t flag)
639 return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
640 PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
644 * qede_check_tunn_csum_l4:
646 * 1 : If L4 csum is enabled AND if the validation has failed.
649 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
651 if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
652 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
653 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
654 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
659 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
661 if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
662 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
663 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
664 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
669 static inline uint8_t
670 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
677 val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
678 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
681 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
682 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
683 ip = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
684 sizeof(struct ether_hdr));
685 pkt_csum = ip->hdr_checksum;
686 ip->hdr_checksum = 0;
687 calc_csum = rte_ipv4_cksum(ip);
688 ip->hdr_checksum = pkt_csum;
689 return (calc_csum != pkt_csum);
690 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
697 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
699 ecore_chain_consume(&rxq->rx_bd_ring);
704 qede_reuse_page(struct qede_dev *qdev,
705 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
707 struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
708 uint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
709 struct qede_rx_entry *curr_prod;
710 dma_addr_t new_mapping;
712 curr_prod = &rxq->sw_rx_ring[idx];
713 *curr_prod = *curr_cons;
715 new_mapping = rte_mbuf_data_dma_addr_default(curr_prod->mbuf) +
716 curr_prod->page_offset;
718 rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
719 rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
725 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
726 struct qede_dev *qdev, uint8_t count)
728 struct qede_rx_entry *curr_cons;
730 for (; count > 0; count--) {
731 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
732 qede_reuse_page(qdev, rxq, curr_cons);
733 qede_rx_bd_ring_consume(rxq);
737 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
742 static const uint32_t
743 ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
744 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4,
745 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6,
746 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
747 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
748 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
749 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
752 /* Bits (0..3) provides L3/L4 protocol type */
753 val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
754 PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
755 (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
756 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT)) & flags;
758 if (val < QEDE_PKT_TYPE_MAX)
759 return ptype_lkup_tbl[val] | RTE_PTYPE_L2_ETHER;
761 return RTE_PTYPE_UNKNOWN;
764 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
769 static const uint32_t
770 ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
771 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
772 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
773 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
774 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
775 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
776 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
777 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
778 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
779 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
780 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
781 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
782 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
783 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
784 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
785 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
786 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
787 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
788 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
789 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
790 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
791 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
792 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
793 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
794 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
795 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
796 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
797 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
798 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
799 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
800 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
801 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
802 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
803 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
804 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
805 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
806 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
807 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
808 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
809 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
810 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
813 /* Cover bits[4-0] to include tunn_type and next protocol */
814 val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
815 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
816 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
817 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
819 if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
820 return ptype_tunn_lkup_tbl[val];
822 return RTE_PTYPE_UNKNOWN;
826 qede_process_sg_pkts(void *p_rxq, struct rte_mbuf *rx_mb,
827 uint8_t num_segs, uint16_t pkt_len)
829 struct qede_rx_queue *rxq = p_rxq;
830 struct qede_dev *qdev = rxq->qdev;
831 struct ecore_dev *edev = &qdev->edev;
832 register struct rte_mbuf *seg1 = NULL;
833 register struct rte_mbuf *seg2 = NULL;
834 uint16_t sw_rx_index;
839 cur_size = pkt_len > rxq->rx_buf_size ? rxq->rx_buf_size :
841 if (unlikely(!cur_size)) {
842 PMD_RX_LOG(ERR, rxq, "Length is 0 while %u BDs"
843 " left for mapping jumbo", num_segs);
844 qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
847 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
848 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
849 qede_rx_bd_ring_consume(rxq);
851 seg2->data_len = cur_size;
862 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
864 struct qede_rx_queue *rxq = p_rxq;
865 struct qede_dev *qdev = rxq->qdev;
866 struct ecore_dev *edev = &qdev->edev;
867 struct qede_fastpath *fp = &qdev->fp_array[rxq->queue_id];
868 uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
870 union eth_rx_cqe *cqe;
871 struct eth_fast_path_rx_reg_cqe *fp_cqe;
872 register struct rte_mbuf *rx_mb = NULL;
873 register struct rte_mbuf *seg1 = NULL;
874 enum eth_rx_cqe_type cqe_type;
875 uint16_t pkt_len; /* Sum of all BD segments */
876 uint16_t len; /* Length of first BD */
877 uint8_t num_segs = 1;
879 uint16_t preload_idx;
882 enum rss_hash_type htype;
883 uint8_t tunn_parse_flag;
886 hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
887 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
891 if (hw_comp_cons == sw_comp_cons)
894 while (sw_comp_cons != hw_comp_cons) {
895 /* Get the CQE from the completion ring */
897 (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
898 cqe_type = cqe->fast_path_regular.type;
900 if (unlikely(cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH)) {
901 PMD_RX_LOG(DEBUG, rxq, "Got a slowath CQE");
903 qdev->ops->eth_cqe_completion(edev, fp->id,
904 (struct eth_slow_path_rx_cqe *)cqe);
908 /* Get the data from the SW ring */
909 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
910 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
911 assert(rx_mb != NULL);
914 fp_cqe = &cqe->fast_path_regular;
916 len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
917 pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
918 pad = fp_cqe->placement_offset;
919 assert((len + pad) <= rx_mb->buf_len);
921 PMD_RX_LOG(DEBUG, rxq,
922 "CQE type = 0x%x, flags = 0x%x, vlan = 0x%x"
923 " len = %u, parsing_flags = %d",
924 cqe_type, fp_cqe->bitfields,
925 rte_le_to_cpu_16(fp_cqe->vlan_tag),
926 len, rte_le_to_cpu_16(fp_cqe->pars_flags.flags));
928 /* If this is an error packet then drop it */
930 rte_le_to_cpu_16(cqe->fast_path_regular.pars_flags.flags);
934 if (qede_tunn_exist(parse_flag)) {
935 PMD_RX_LOG(DEBUG, rxq, "Rx tunneled packet");
936 if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
938 "L4 csum failed, flags = 0x%x",
941 rx_mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
944 fp_cqe->tunnel_pars_flags.flags;
946 qede_rx_cqe_to_tunn_pkt_type(
950 PMD_RX_LOG(DEBUG, rxq, "Rx non-tunneled packet");
951 if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
953 "L4 csum failed, flags = 0x%x",
956 rx_mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
957 } else if (unlikely(qede_check_notunn_csum_l3(rx_mb,
960 "IP csum failed, flags = 0x%x",
963 rx_mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
966 qede_rx_cqe_to_pkt_type(parse_flag);
970 PMD_RX_LOG(INFO, rxq, "packet_type 0x%x", rx_mb->packet_type);
972 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
974 "New buffer allocation failed,"
975 "dropping incoming packet");
976 qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
977 rte_eth_devices[rxq->port_id].
978 data->rx_mbuf_alloc_failed++;
979 rxq->rx_alloc_errors++;
982 qede_rx_bd_ring_consume(rxq);
983 if (fp_cqe->bd_num > 1) {
984 PMD_RX_LOG(DEBUG, rxq, "Jumbo-over-BD packet: %02x BDs"
985 " len on first: %04x Total Len: %04x",
986 fp_cqe->bd_num, len, pkt_len);
987 num_segs = fp_cqe->bd_num - 1;
989 if (qede_process_sg_pkts(p_rxq, seg1, num_segs,
992 for (j = 0; j < num_segs; j++) {
993 if (qede_alloc_rx_buffer(rxq)) {
995 "Buffer allocation failed");
996 rte_eth_devices[rxq->port_id].
997 data->rx_mbuf_alloc_failed++;
998 rxq->rx_alloc_errors++;
1004 rxq->rx_segs++; /* for the first segment */
1006 /* Prefetch next mbuf while processing current one. */
1007 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1008 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1010 /* Update rest of the MBUF fields */
1011 rx_mb->data_off = pad + RTE_PKTMBUF_HEADROOM;
1012 rx_mb->nb_segs = fp_cqe->bd_num;
1013 rx_mb->data_len = len;
1014 rx_mb->pkt_len = pkt_len;
1015 rx_mb->port = rxq->port_id;
1017 htype = (uint8_t)GET_FIELD(fp_cqe->bitfields,
1018 ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
1019 if (qdev->rss_enable && htype) {
1020 rx_mb->ol_flags |= PKT_RX_RSS_HASH;
1021 rx_mb->hash.rss = rte_le_to_cpu_32(fp_cqe->rss_hash);
1022 PMD_RX_LOG(DEBUG, rxq, "Hash result 0x%x",
1026 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
1028 if (CQE_HAS_VLAN(parse_flag)) {
1029 rx_mb->vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1030 rx_mb->ol_flags |= PKT_RX_VLAN_PKT;
1033 if (CQE_HAS_OUTER_VLAN(parse_flag)) {
1034 /* FW does not provide indication of Outer VLAN tag,
1035 * which is always stripped, so vlan_tci_outer is set
1036 * to 0. Here vlan_tag represents inner VLAN tag.
1038 rx_mb->vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1039 rx_mb->ol_flags |= PKT_RX_QINQ_PKT;
1040 rx_mb->vlan_tci_outer = 0;
1043 rx_pkts[rx_pkt] = rx_mb;
1046 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1047 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1048 if (rx_pkt == nb_pkts) {
1049 PMD_RX_LOG(DEBUG, rxq,
1050 "Budget reached nb_pkts=%u received=%u",
1056 qede_update_rx_prod(qdev, rxq);
1058 rxq->rcv_pkts += rx_pkt;
1060 PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
1066 qede_free_tx_pkt(struct ecore_dev *edev, struct qede_tx_queue *txq)
1068 uint16_t nb_segs, idx = TX_CONS(txq);
1069 struct eth_tx_bd *tx_data_bd;
1070 struct rte_mbuf *mbuf = txq->sw_tx_ring[idx].mbuf;
1072 if (unlikely(!mbuf)) {
1073 PMD_TX_LOG(ERR, txq, "null mbuf");
1074 PMD_TX_LOG(ERR, txq,
1075 "tx_desc %u tx_avail %u tx_cons %u tx_prod %u",
1076 txq->nb_tx_desc, txq->nb_tx_avail, idx,
1081 nb_segs = mbuf->nb_segs;
1083 /* It's like consuming rxbuf in recv() */
1084 ecore_chain_consume(&txq->tx_pbl);
1088 rte_pktmbuf_free(mbuf);
1089 txq->sw_tx_ring[idx].mbuf = NULL;
1094 static inline uint16_t
1095 qede_process_tx_compl(struct ecore_dev *edev, struct qede_tx_queue *txq)
1097 uint16_t tx_compl = 0;
1098 uint16_t hw_bd_cons;
1100 hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
1101 rte_compiler_barrier();
1103 while (hw_bd_cons != ecore_chain_get_cons_idx(&txq->tx_pbl)) {
1104 if (qede_free_tx_pkt(edev, txq)) {
1105 PMD_TX_LOG(ERR, txq,
1106 "hw_bd_cons = %u, chain_cons = %u",
1108 ecore_chain_get_cons_idx(&txq->tx_pbl));
1111 txq->sw_tx_cons++; /* Making TXD available */
1115 PMD_TX_LOG(DEBUG, txq, "Tx compl %u sw_tx_cons %u avail %u",
1116 tx_compl, txq->sw_tx_cons, txq->nb_tx_avail);
1120 /* Populate scatter gather buffer descriptor fields */
1121 static inline uint8_t
1122 qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg,
1123 struct eth_tx_1st_bd *bd1)
1125 struct qede_tx_queue *txq = p_txq;
1126 struct eth_tx_2nd_bd *bd2 = NULL;
1127 struct eth_tx_3rd_bd *bd3 = NULL;
1128 struct eth_tx_bd *tx_bd = NULL;
1130 uint8_t nb_segs = 1; /* min one segment per packet */
1132 /* Check for scattered buffers */
1135 bd2 = (struct eth_tx_2nd_bd *)
1136 ecore_chain_produce(&txq->tx_pbl);
1137 memset(bd2, 0, sizeof(*bd2));
1138 mapping = rte_mbuf_data_dma_addr(m_seg);
1139 QEDE_BD_SET_ADDR_LEN(bd2, mapping, m_seg->data_len);
1140 PMD_TX_LOG(DEBUG, txq, "BD2 len %04x",
1142 } else if (nb_segs == 2) {
1143 bd3 = (struct eth_tx_3rd_bd *)
1144 ecore_chain_produce(&txq->tx_pbl);
1145 memset(bd3, 0, sizeof(*bd3));
1146 mapping = rte_mbuf_data_dma_addr(m_seg);
1147 QEDE_BD_SET_ADDR_LEN(bd3, mapping, m_seg->data_len);
1148 PMD_TX_LOG(DEBUG, txq, "BD3 len %04x",
1151 tx_bd = (struct eth_tx_bd *)
1152 ecore_chain_produce(&txq->tx_pbl);
1153 memset(tx_bd, 0, sizeof(*tx_bd));
1154 mapping = rte_mbuf_data_dma_addr(m_seg);
1155 QEDE_BD_SET_ADDR_LEN(tx_bd, mapping, m_seg->data_len);
1156 PMD_TX_LOG(DEBUG, txq, "BD len %04x",
1160 m_seg = m_seg->next;
1163 /* Return total scattered buffers */
1168 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1170 struct qede_tx_queue *txq = p_txq;
1171 struct qede_dev *qdev = txq->qdev;
1172 struct ecore_dev *edev = &qdev->edev;
1173 struct qede_fastpath *fp;
1174 struct eth_tx_1st_bd *bd1;
1175 struct rte_mbuf *mbuf;
1176 struct rte_mbuf *m_seg = NULL;
1177 uint16_t nb_tx_pkts;
1182 uint16_t nb_pkt_sent = 0;
1184 fp = &qdev->fp_array[QEDE_RSS_COUNT(qdev) + txq->queue_id];
1186 if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
1187 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
1188 nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
1189 (void)qede_process_tx_compl(edev, txq);
1192 nb_tx_pkts = RTE_MIN(nb_pkts, (txq->nb_tx_avail /
1193 ETH_TX_MAX_BDS_PER_NON_LSO_PACKET));
1194 if (unlikely(nb_tx_pkts == 0)) {
1195 PMD_TX_LOG(DEBUG, txq, "Out of BDs nb_pkts=%u avail=%u",
1196 nb_pkts, txq->nb_tx_avail);
1200 tx_count = nb_tx_pkts;
1201 while (nb_tx_pkts--) {
1202 /* Fill the entry in the SW ring and the BDs in the FW ring */
1205 txq->sw_tx_ring[idx].mbuf = mbuf;
1206 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
1207 bd1->data.bd_flags.bitfields =
1208 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
1209 /* FW 8.10.x specific change */
1210 bd1->data.bitfields =
1211 (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
1212 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
1213 /* Map MBUF linear data for DMA and set in the first BD */
1214 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_dma_addr(mbuf),
1216 PMD_TX_LOG(INFO, txq, "BD1 len %04x", mbuf->data_len);
1218 if (RTE_ETH_IS_TUNNEL_PKT(mbuf->packet_type)) {
1219 PMD_TX_LOG(INFO, txq, "Tx tunnel packet");
1220 /* First indicate its a tunnel pkt */
1221 bd1->data.bd_flags.bitfields |=
1222 ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
1223 ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1225 /* Legacy FW had flipped behavior in regard to this bit
1226 * i.e. it needed to set to prevent FW from touching
1227 * encapsulated packets when it didn't need to.
1229 if (unlikely(txq->is_legacy))
1230 bd1->data.bitfields ^=
1231 1 << ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1233 /* Outer IP checksum offload */
1234 if (mbuf->ol_flags & PKT_TX_OUTER_IP_CKSUM) {
1235 PMD_TX_LOG(INFO, txq, "OuterIP csum offload");
1236 bd1->data.bd_flags.bitfields |=
1237 ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
1238 ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
1241 /* Outer UDP checksum offload */
1242 bd1->data.bd_flags.bitfields |=
1243 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
1244 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
1247 /* Descriptor based VLAN insertion */
1248 if (mbuf->ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1249 PMD_TX_LOG(INFO, txq, "Insert VLAN 0x%x",
1251 bd1->data.vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
1252 bd1->data.bd_flags.bitfields |=
1253 1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
1256 /* Offload the IP checksum in the hardware */
1257 if (mbuf->ol_flags & PKT_TX_IP_CKSUM) {
1258 PMD_TX_LOG(INFO, txq, "IP csum offload");
1259 bd1->data.bd_flags.bitfields |=
1260 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1263 /* L4 checksum offload (tcp or udp) */
1264 if (mbuf->ol_flags & (PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
1265 PMD_TX_LOG(INFO, txq, "L4 csum offload");
1266 bd1->data.bd_flags.bitfields |=
1267 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1268 /* IPv6 + extn. -> later */
1271 /* Handle fragmented MBUF */
1273 /* Encode scatter gather buffer descriptors if required */
1274 nb_frags = qede_encode_sg_bd(txq, m_seg, bd1);
1275 bd1->data.nbds = nb_frags;
1276 txq->nb_tx_avail -= nb_frags;
1278 rte_prefetch0(txq->sw_tx_ring[TX_PROD(txq)].mbuf);
1280 rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1283 PMD_TX_LOG(INFO, txq, "nbds = %d pkt_len = %04x",
1284 bd1->data.nbds, mbuf->pkt_len);
1287 /* Write value of prod idx into bd_prod */
1288 txq->tx_db.data.bd_prod = bd_prod;
1290 rte_compiler_barrier();
1291 DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
1294 /* Check again for Tx completions */
1295 (void)qede_process_tx_compl(edev, txq);
1297 PMD_TX_LOG(DEBUG, txq, "to_send=%u can_send=%u sent=%u core=%d",
1298 nb_pkts, tx_count, nb_pkt_sent, rte_lcore_id());
1303 static void qede_init_fp_queue(struct rte_eth_dev *eth_dev)
1305 struct qede_dev *qdev = eth_dev->data->dev_private;
1306 struct qede_fastpath *fp;
1307 uint8_t i, rss_id, txq_index, tc;
1308 int rxq = 0, txq = 0;
1311 fp = &qdev->fp_array[i];
1312 if (fp->type & QEDE_FASTPATH_RX) {
1313 fp->rxq = eth_dev->data->rx_queues[i];
1314 fp->rxq->queue_id = rxq++;
1317 if (fp->type & QEDE_FASTPATH_TX) {
1318 for (tc = 0; tc < qdev->num_tc; tc++) {
1319 txq_index = tc * QEDE_TSS_COUNT(qdev) + txq;
1321 eth_dev->data->tx_queues[txq_index];
1322 fp->txqs[tc]->queue_id = txq_index;
1323 if (qdev->dev_info.is_legacy)
1324 fp->txqs[tc]->is_legacy = true;
1331 int qede_dev_start(struct rte_eth_dev *eth_dev)
1333 struct qede_dev *qdev = eth_dev->data->dev_private;
1334 struct ecore_dev *edev = &qdev->edev;
1335 struct qed_link_output link_output;
1336 struct qede_fastpath *fp;
1339 DP_INFO(edev, "Device state is %d\n", qdev->state);
1341 if (qdev->state == QEDE_DEV_START) {
1342 DP_INFO(edev, "Port is already started\n");
1346 if (qdev->state == QEDE_DEV_CONFIG)
1347 qede_init_fp_queue(eth_dev);
1349 rc = qede_start_queues(eth_dev, true);
1351 DP_ERR(edev, "Failed to start queues\n");
1356 /* Bring-up the link */
1357 qede_dev_set_link_state(eth_dev, true);
1360 if (qede_reset_fp_rings(qdev))
1363 /* Start/resume traffic */
1364 qdev->ops->fastpath_start(edev);
1366 qdev->state = QEDE_DEV_START;
1368 DP_INFO(edev, "dev_state is QEDE_DEV_START\n");
1373 static int qede_drain_txq(struct qede_dev *qdev,
1374 struct qede_tx_queue *txq, bool allow_drain)
1376 struct ecore_dev *edev = &qdev->edev;
1379 while (txq->sw_tx_cons != txq->sw_tx_prod) {
1380 qede_process_tx_compl(edev, txq);
1383 DP_NOTICE(edev, false,
1384 "Tx queue[%u] is stuck,"
1385 "requesting MCP to drain\n",
1387 rc = qdev->ops->common->drain(edev);
1390 return qede_drain_txq(qdev, txq, false);
1393 DP_NOTICE(edev, false,
1394 "Timeout waiting for tx queue[%d]:"
1395 "PROD=%d, CONS=%d\n",
1396 txq->queue_id, txq->sw_tx_prod,
1402 rte_compiler_barrier();
1405 /* FW finished processing, wait for HW to transmit all tx packets */
1411 static int qede_stop_queues(struct qede_dev *qdev)
1413 struct qed_update_vport_params vport_update_params;
1414 struct ecore_dev *edev = &qdev->edev;
1415 struct qede_fastpath *fp;
1418 /* Disable the vport */
1419 memset(&vport_update_params, 0, sizeof(vport_update_params));
1420 vport_update_params.vport_id = 0;
1421 vport_update_params.update_vport_active_flg = 1;
1422 vport_update_params.vport_active_flg = 0;
1423 vport_update_params.update_rss_flg = 0;
1425 DP_INFO(edev, "Deactivate vport\n");
1427 rc = qdev->ops->vport_update(edev, &vport_update_params);
1429 DP_ERR(edev, "Failed to update vport\n");
1433 DP_INFO(edev, "Flushing tx queues\n");
1435 /* Flush Tx queues. If needed, request drain from MCP */
1437 fp = &qdev->fp_array[i];
1439 if (fp->type & QEDE_FASTPATH_TX) {
1440 for (tc = 0; tc < qdev->num_tc; tc++) {
1441 struct qede_tx_queue *txq = fp->txqs[tc];
1443 rc = qede_drain_txq(qdev, txq, true);
1450 /* Stop all Queues in reverse order */
1451 for (i = QEDE_QUEUE_CNT(qdev) - 1; i >= 0; i--) {
1452 fp = &qdev->fp_array[i];
1454 /* Stop the Tx Queue(s) */
1455 if (qdev->fp_array[i].type & QEDE_FASTPATH_TX) {
1456 for (tc = 0; tc < qdev->num_tc; tc++) {
1457 struct qede_tx_queue *txq = fp->txqs[tc];
1458 DP_INFO(edev, "Stopping tx queues\n");
1459 rc = qdev->ops->q_tx_stop(edev, i, txq->handle);
1461 DP_ERR(edev, "Failed to stop TXQ #%d\n",
1468 /* Stop the Rx Queue */
1469 if (qdev->fp_array[i].type & QEDE_FASTPATH_RX) {
1470 DP_INFO(edev, "Stopping rx queues\n");
1471 rc = qdev->ops->q_rx_stop(edev, i, fp->rxq->handle);
1473 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
1482 int qede_reset_fp_rings(struct qede_dev *qdev)
1484 struct qede_fastpath *fp;
1485 struct qede_tx_queue *txq;
1489 for_each_queue(id) {
1490 fp = &qdev->fp_array[id];
1492 if (fp->type & QEDE_FASTPATH_RX) {
1493 DP_INFO(&qdev->edev,
1494 "Reset FP chain for RSS %u\n", id);
1495 qede_rx_queue_release_mbufs(fp->rxq);
1496 ecore_chain_reset(&fp->rxq->rx_bd_ring);
1497 ecore_chain_reset(&fp->rxq->rx_comp_ring);
1498 fp->rxq->sw_rx_prod = 0;
1499 fp->rxq->sw_rx_cons = 0;
1500 *fp->rxq->hw_cons_ptr = 0;
1501 for (i = 0; i < fp->rxq->nb_rx_desc; i++) {
1502 if (qede_alloc_rx_buffer(fp->rxq)) {
1504 "RX buffer allocation failed\n");
1509 if (fp->type & QEDE_FASTPATH_TX) {
1510 for (tc = 0; tc < qdev->num_tc; tc++) {
1512 qede_tx_queue_release_mbufs(txq);
1513 ecore_chain_reset(&txq->tx_pbl);
1514 txq->sw_tx_cons = 0;
1515 txq->sw_tx_prod = 0;
1516 *txq->hw_cons_ptr = 0;
1524 /* This function frees all memory of a single fp */
1525 void qede_free_mem_load(struct rte_eth_dev *eth_dev)
1527 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1528 struct qede_fastpath *fp;
1533 for_each_queue(id) {
1534 fp = &qdev->fp_array[id];
1535 if (fp->type & QEDE_FASTPATH_RX) {
1538 qede_rx_queue_release(fp->rxq);
1539 eth_dev->data->rx_queues[id] = NULL;
1541 for (tc = 0; tc < qdev->num_tc; tc++) {
1544 txq_idx = fp->txqs[tc]->queue_id;
1545 qede_tx_queue_release(fp->txqs[tc]);
1546 eth_dev->data->tx_queues[txq_idx] = NULL;
1552 void qede_dev_stop(struct rte_eth_dev *eth_dev)
1554 struct qede_dev *qdev = eth_dev->data->dev_private;
1555 struct ecore_dev *edev = &qdev->edev;
1557 DP_INFO(edev, "port %u\n", eth_dev->data->port_id);
1559 if (qdev->state != QEDE_DEV_START) {
1560 DP_INFO(edev, "Device not yet started\n");
1564 if (qede_stop_queues(qdev))
1565 DP_ERR(edev, "Didn't succeed to close queues\n");
1567 DP_INFO(edev, "Stopped queues\n");
1569 qdev->ops->fastpath_stop(edev);
1571 /* Bring the link down */
1572 qede_dev_set_link_state(eth_dev, false);
1574 qdev->state = QEDE_DEV_STOP;
1576 DP_INFO(edev, "dev_state is QEDE_DEV_STOP\n");