2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
10 #include "qede_rxtx.h"
12 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
14 struct rte_mbuf *new_mb = NULL;
15 struct eth_rx_bd *rx_bd;
17 uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
19 new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
20 if (unlikely(!new_mb)) {
22 "Failed to allocate rx buffer "
23 "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
24 idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
25 rte_mempool_avail_count(rxq->mb_pool),
26 rte_mempool_in_use_count(rxq->mb_pool));
29 rxq->sw_rx_ring[idx].mbuf = new_mb;
30 rxq->sw_rx_ring[idx].page_offset = 0;
31 mapping = rte_mbuf_data_dma_addr_default(new_mb);
32 /* Advance PROD and get BD pointer */
33 rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
34 rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
35 rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
40 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
44 if (rxq->sw_rx_ring != NULL) {
45 for (i = 0; i < rxq->nb_rx_desc; i++) {
46 if (rxq->sw_rx_ring[i].mbuf != NULL) {
47 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
48 rxq->sw_rx_ring[i].mbuf = NULL;
54 void qede_rx_queue_release(void *rx_queue)
56 struct qede_rx_queue *rxq = rx_queue;
59 qede_rx_queue_release_mbufs(rxq);
60 rte_free(rxq->sw_rx_ring);
61 rxq->sw_rx_ring = NULL;
67 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
71 PMD_TX_LOG(DEBUG, txq, "releasing %u mbufs", txq->nb_tx_desc);
73 if (txq->sw_tx_ring) {
74 for (i = 0; i < txq->nb_tx_desc; i++) {
75 if (txq->sw_tx_ring[i].mbuf) {
76 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf);
77 txq->sw_tx_ring[i].mbuf = NULL;
84 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
85 uint16_t nb_desc, unsigned int socket_id,
86 const struct rte_eth_rxconf *rx_conf,
87 struct rte_mempool *mp)
89 struct qede_dev *qdev = dev->data->dev_private;
90 struct ecore_dev *edev = &qdev->edev;
91 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
92 struct qede_rx_queue *rxq;
93 uint16_t max_rx_pkt_len;
99 PMD_INIT_FUNC_TRACE(edev);
101 /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
102 if (!rte_is_power_of_2(nb_desc)) {
103 DP_ERR(edev, "Ring size %u is not power of 2\n",
108 /* Free memory prior to re-allocation if needed... */
109 if (dev->data->rx_queues[queue_idx] != NULL) {
110 qede_rx_queue_release(dev->data->rx_queues[queue_idx]);
111 dev->data->rx_queues[queue_idx] = NULL;
114 /* First allocate the rx queue data structure */
115 rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
116 RTE_CACHE_LINE_SIZE, socket_id);
119 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
126 rxq->nb_rx_desc = nb_desc;
127 rxq->queue_id = queue_idx;
128 rxq->port_id = dev->data->port_id;
129 max_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len;
130 qdev->mtu = max_rx_pkt_len;
132 /* Fix up RX buffer size */
133 bufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
134 if ((rxmode->enable_scatter) ||
135 (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {
136 if (!dev->data->scattered_rx) {
137 DP_INFO(edev, "Forcing scatter-gather mode\n");
138 dev->data->scattered_rx = 1;
141 if (dev->data->scattered_rx)
142 rxq->rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
144 rxq->rx_buf_size = qdev->mtu + QEDE_ETH_OVERHEAD;
145 /* Align to cache-line size if needed */
146 rxq->rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rxq->rx_buf_size);
148 DP_INFO(edev, "mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\n",
149 qdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);
151 /* Allocate the parallel driver ring for Rx buffers */
152 size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
153 rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
154 RTE_CACHE_LINE_SIZE, socket_id);
155 if (!rxq->sw_rx_ring) {
156 DP_NOTICE(edev, false,
157 "Unable to alloc memory for sw_rx_ring on socket %u\n",
164 /* Allocate FW Rx ring */
165 rc = qdev->ops->common->chain_alloc(edev,
166 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
167 ECORE_CHAIN_MODE_NEXT_PTR,
168 ECORE_CHAIN_CNT_TYPE_U16,
170 sizeof(struct eth_rx_bd),
174 if (rc != ECORE_SUCCESS) {
175 DP_NOTICE(edev, false,
176 "Unable to alloc memory for rxbd ring on socket %u\n",
178 rte_free(rxq->sw_rx_ring);
179 rxq->sw_rx_ring = NULL;
185 /* Allocate FW completion ring */
186 rc = qdev->ops->common->chain_alloc(edev,
187 ECORE_CHAIN_USE_TO_CONSUME,
188 ECORE_CHAIN_MODE_PBL,
189 ECORE_CHAIN_CNT_TYPE_U16,
191 sizeof(union eth_rx_cqe),
195 if (rc != ECORE_SUCCESS) {
196 DP_NOTICE(edev, false,
197 "Unable to alloc memory for cqe ring on socket %u\n",
199 /* TBD: Freeing RX BD ring */
200 rte_free(rxq->sw_rx_ring);
201 rxq->sw_rx_ring = NULL;
206 /* Allocate buffers for the Rx ring */
207 for (i = 0; i < rxq->nb_rx_desc; i++) {
208 rc = qede_alloc_rx_buffer(rxq);
210 DP_NOTICE(edev, false,
211 "RX buffer allocation failed at idx=%d\n", i);
216 dev->data->rx_queues[queue_idx] = rxq;
218 DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
219 queue_idx, nb_desc, qdev->mtu, socket_id);
223 qede_rx_queue_release(rxq);
227 void qede_tx_queue_release(void *tx_queue)
229 struct qede_tx_queue *txq = tx_queue;
232 qede_tx_queue_release_mbufs(txq);
233 if (txq->sw_tx_ring) {
234 rte_free(txq->sw_tx_ring);
235 txq->sw_tx_ring = NULL;
243 qede_tx_queue_setup(struct rte_eth_dev *dev,
246 unsigned int socket_id,
247 const struct rte_eth_txconf *tx_conf)
249 struct qede_dev *qdev = dev->data->dev_private;
250 struct ecore_dev *edev = &qdev->edev;
251 struct qede_tx_queue *txq;
254 PMD_INIT_FUNC_TRACE(edev);
256 if (!rte_is_power_of_2(nb_desc)) {
257 DP_ERR(edev, "Ring size %u is not power of 2\n",
262 /* Free memory prior to re-allocation if needed... */
263 if (dev->data->tx_queues[queue_idx] != NULL) {
264 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
265 dev->data->tx_queues[queue_idx] = NULL;
268 txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
269 RTE_CACHE_LINE_SIZE, socket_id);
273 "Unable to allocate memory for txq on socket %u",
278 txq->nb_tx_desc = nb_desc;
280 txq->port_id = dev->data->port_id;
282 rc = qdev->ops->common->chain_alloc(edev,
283 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
284 ECORE_CHAIN_MODE_PBL,
285 ECORE_CHAIN_CNT_TYPE_U16,
287 sizeof(union eth_tx_bd_types),
290 if (rc != ECORE_SUCCESS) {
292 "Unable to allocate memory for txbd ring on socket %u",
294 qede_tx_queue_release(txq);
298 /* Allocate software ring */
299 txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
300 (sizeof(struct qede_tx_entry) *
302 RTE_CACHE_LINE_SIZE, socket_id);
304 if (!txq->sw_tx_ring) {
306 "Unable to allocate memory for txbd ring on socket %u",
308 qede_tx_queue_release(txq);
312 txq->queue_id = queue_idx;
314 txq->nb_tx_avail = txq->nb_tx_desc;
316 txq->tx_free_thresh =
317 tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
318 (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
320 dev->data->tx_queues[queue_idx] = txq;
323 "txq %u num_desc %u tx_free_thresh %u socket %u\n",
324 queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
329 /* This function inits fp content and resets the SB, RXQ and TXQ arrays */
330 static void qede_init_fp(struct qede_dev *qdev)
332 struct qede_fastpath *fp;
333 uint8_t i, rss_id, tc;
334 int fp_rx = qdev->fp_num_rx, rxq = 0, txq = 0;
336 memset((void *)qdev->fp_array, 0, (QEDE_QUEUE_CNT(qdev) *
337 sizeof(*qdev->fp_array)));
338 memset((void *)qdev->sb_array, 0, (QEDE_QUEUE_CNT(qdev) *
339 sizeof(*qdev->sb_array)));
341 fp = &qdev->fp_array[i];
343 fp->type = QEDE_FASTPATH_RX;
346 fp->type = QEDE_FASTPATH_TX;
350 fp->sb_info = &qdev->sb_array[i];
351 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d", "qdev", i);
356 void qede_free_fp_arrays(struct qede_dev *qdev)
358 /* It asseumes qede_free_mem_load() is called before */
359 if (qdev->fp_array != NULL) {
360 rte_free(qdev->fp_array);
361 qdev->fp_array = NULL;
364 if (qdev->sb_array != NULL) {
365 rte_free(qdev->sb_array);
366 qdev->sb_array = NULL;
370 int qede_alloc_fp_array(struct qede_dev *qdev)
372 struct qede_fastpath *fp;
373 struct ecore_dev *edev = &qdev->edev;
376 qdev->fp_array = rte_calloc("fp", QEDE_QUEUE_CNT(qdev),
377 sizeof(*qdev->fp_array),
378 RTE_CACHE_LINE_SIZE);
380 if (!qdev->fp_array) {
381 DP_ERR(edev, "fp array allocation failed\n");
385 qdev->sb_array = rte_calloc("sb", QEDE_QUEUE_CNT(qdev),
386 sizeof(*qdev->sb_array),
387 RTE_CACHE_LINE_SIZE);
389 if (!qdev->sb_array) {
390 DP_ERR(edev, "sb array allocation failed\n");
391 rte_free(qdev->fp_array);
398 /* This function allocates fast-path status block memory */
400 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
403 struct ecore_dev *edev = &qdev->edev;
404 struct status_block *sb_virt;
408 sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys, sizeof(*sb_virt));
411 DP_ERR(edev, "Status block allocation failed\n");
415 rc = qdev->ops->common->sb_init(edev, sb_info,
416 sb_virt, sb_phys, sb_id,
417 QED_SB_TYPE_L2_QUEUE);
419 DP_ERR(edev, "Status block initialization failed\n");
420 /* TBD: No dma_free_coherent possible */
427 int qede_alloc_fp_resc(struct qede_dev *qdev)
429 struct ecore_dev *edev = &qdev->edev;
430 struct qede_fastpath *fp;
437 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
439 num_sbs = ecore_cxt_get_proto_cid_count
440 (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL);
443 DP_ERR(edev, "No status blocks available\n");
448 qede_free_fp_arrays(qdev);
450 rc = qede_alloc_fp_array(qdev);
456 for (i = 0; i < QEDE_QUEUE_CNT(qdev); i++) {
457 fp = &qdev->fp_array[i];
459 sb_idx = i % num_sbs;
462 if (qede_alloc_mem_sb(qdev, fp->sb_info, sb_idx)) {
463 qede_free_fp_arrays(qdev);
471 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
473 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
475 qede_free_mem_load(eth_dev);
476 qede_free_fp_arrays(qdev);
480 qede_update_rx_prod(struct qede_dev *edev, struct qede_rx_queue *rxq)
482 uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
483 uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
484 struct eth_rx_prod_data rx_prods = { 0 };
486 /* Update producers */
487 rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
488 rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
490 /* Make sure that the BD and SGE data is updated before updating the
491 * producers since FW might read the BD/SGE right after the producer
496 internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
497 (uint32_t *)&rx_prods);
499 /* mmiowb is needed to synchronize doorbell writes from more than one
500 * processor. It guarantees that the write arrives to the device before
501 * the napi lock is released and another qede_poll is called (possibly
502 * on another CPU). Without this barrier, the next doorbell can bypass
503 * this doorbell. This is applicable to IA64/Altix systems.
507 PMD_RX_LOG(DEBUG, rxq, "bd_prod %u cqe_prod %u", bd_prod, cqe_prod);
511 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
512 uint16_t mtu, bool enable)
514 /* Enable LRO in split mode */
515 sge_tpa_params->tpa_ipv4_en_flg = enable;
516 sge_tpa_params->tpa_ipv6_en_flg = enable;
517 sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
518 sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
519 /* set if tpa enable changes */
520 sge_tpa_params->update_tpa_en_flg = 1;
521 /* set if tpa parameters should be handled */
522 sge_tpa_params->update_tpa_param_flg = enable;
524 sge_tpa_params->max_buffers_per_cqe = 20;
525 sge_tpa_params->tpa_pkt_split_flg = 1;
526 sge_tpa_params->tpa_hdr_data_split_flg = 0;
527 sge_tpa_params->tpa_gro_consistent_flg = 0;
528 sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
529 sge_tpa_params->tpa_max_size = 0x7FFF;
530 sge_tpa_params->tpa_min_size_to_start = mtu / 2;
531 sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
534 static int qede_start_queues(struct rte_eth_dev *eth_dev, bool clear_stats)
536 struct qede_dev *qdev = eth_dev->data->dev_private;
537 struct ecore_dev *edev = &qdev->edev;
538 struct ecore_queue_start_common_params q_params;
539 struct qed_dev_info *qed_info = &qdev->dev_info.common;
540 struct qed_update_vport_params vport_update_params;
541 struct ecore_sge_tpa_params tpa_params;
542 struct qede_tx_queue *txq;
543 struct qede_fastpath *fp;
544 dma_addr_t p_phys_table;
547 int vlan_removal_en = 1;
551 fp = &qdev->fp_array[i];
552 if (fp->type & QEDE_FASTPATH_RX) {
553 struct ecore_rxq_start_ret_params ret_params;
556 ecore_chain_get_pbl_phys(&fp->rxq->rx_comp_ring);
558 ecore_chain_get_page_cnt(&fp->rxq->rx_comp_ring);
560 memset(&ret_params, 0, sizeof(ret_params));
561 memset(&q_params, 0, sizeof(q_params));
562 q_params.queue_id = i;
563 q_params.vport_id = 0;
564 q_params.sb = fp->sb_info->igu_sb_id;
565 q_params.sb_idx = RX_PI;
567 ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
569 rc = qdev->ops->q_rx_start(edev, i, &q_params,
570 fp->rxq->rx_buf_size,
571 fp->rxq->rx_bd_ring.p_phys_addr,
576 DP_ERR(edev, "Start rxq #%d failed %d\n",
577 fp->rxq->queue_id, rc);
581 /* Use the return parameters */
582 fp->rxq->hw_rxq_prod_addr = ret_params.p_prod;
583 fp->rxq->handle = ret_params.p_handle;
585 fp->rxq->hw_cons_ptr =
586 &fp->sb_info->sb_virt->pi_array[RX_PI];
588 qede_update_rx_prod(qdev, fp->rxq);
591 if (!(fp->type & QEDE_FASTPATH_TX))
593 for (tc = 0; tc < qdev->num_tc; tc++) {
594 struct ecore_txq_start_ret_params ret_params;
597 txq_index = tc * QEDE_RSS_COUNT(qdev) + i;
599 p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
600 page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
602 memset(&q_params, 0, sizeof(q_params));
603 memset(&ret_params, 0, sizeof(ret_params));
604 q_params.queue_id = txq->queue_id;
605 q_params.vport_id = 0;
606 q_params.sb = fp->sb_info->igu_sb_id;
607 q_params.sb_idx = TX_PI(tc);
609 rc = qdev->ops->q_tx_start(edev, i, &q_params,
611 page_cnt, /* **pp_doorbell */
614 DP_ERR(edev, "Start txq %u failed %d\n",
619 txq->doorbell_addr = ret_params.p_doorbell;
620 txq->handle = ret_params.p_handle;
623 &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
624 SET_FIELD(txq->tx_db.data.params,
625 ETH_DB_DATA_DEST, DB_DEST_XCM);
626 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
628 SET_FIELD(txq->tx_db.data.params,
629 ETH_DB_DATA_AGG_VAL_SEL,
630 DQ_XCM_ETH_TX_BD_PROD_CMD);
632 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
636 /* Prepare and send the vport enable */
637 memset(&vport_update_params, 0, sizeof(vport_update_params));
638 /* Update MTU via vport update */
639 vport_update_params.mtu = qdev->mtu;
640 vport_update_params.vport_id = 0;
641 vport_update_params.update_vport_active_flg = 1;
642 vport_update_params.vport_active_flg = 1;
645 if (qed_info->mf_mode == MF_NPAR && qed_info->tx_switching) {
646 /* TBD: Check SRIOV enabled for VF */
647 vport_update_params.update_tx_switching_flg = 1;
648 vport_update_params.tx_switching_flg = 1;
652 if (qdev->enable_lro) {
653 DP_INFO(edev, "Enabling LRO\n");
654 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
655 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, true);
656 vport_update_params.sge_tpa_params = &tpa_params;
659 rc = qdev->ops->vport_update(edev, &vport_update_params);
661 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
668 static bool qede_tunn_exist(uint16_t flag)
670 return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
671 PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
675 * qede_check_tunn_csum_l4:
677 * 1 : If L4 csum is enabled AND if the validation has failed.
680 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
682 if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
683 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
684 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
685 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
690 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
692 if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
693 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
694 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
695 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
700 static inline uint8_t
701 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
708 val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
709 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
712 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
713 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
714 ip = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
715 sizeof(struct ether_hdr));
716 pkt_csum = ip->hdr_checksum;
717 ip->hdr_checksum = 0;
718 calc_csum = rte_ipv4_cksum(ip);
719 ip->hdr_checksum = pkt_csum;
720 return (calc_csum != pkt_csum);
721 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
728 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
730 ecore_chain_consume(&rxq->rx_bd_ring);
735 qede_reuse_page(struct qede_dev *qdev,
736 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
738 struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
739 uint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
740 struct qede_rx_entry *curr_prod;
741 dma_addr_t new_mapping;
743 curr_prod = &rxq->sw_rx_ring[idx];
744 *curr_prod = *curr_cons;
746 new_mapping = rte_mbuf_data_dma_addr_default(curr_prod->mbuf) +
747 curr_prod->page_offset;
749 rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
750 rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
756 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
757 struct qede_dev *qdev, uint8_t count)
759 struct qede_rx_entry *curr_cons;
761 for (; count > 0; count--) {
762 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
763 qede_reuse_page(qdev, rxq, curr_cons);
764 qede_rx_bd_ring_consume(rxq);
768 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
773 static const uint32_t
774 ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
775 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4,
776 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6,
777 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
778 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
779 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
780 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
783 /* Bits (0..3) provides L3/L4 protocol type */
784 val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
785 PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
786 (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
787 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT)) & flags;
789 if (val < QEDE_PKT_TYPE_MAX)
790 return ptype_lkup_tbl[val] | RTE_PTYPE_L2_ETHER;
792 return RTE_PTYPE_UNKNOWN;
796 qede_rx_process_tpa_cont_cqe(struct qede_dev *qdev,
797 struct qede_rx_queue *rxq,
798 struct eth_fast_path_rx_tpa_cont_cqe *cqe)
800 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
801 struct qede_agg_info *tpa_info;
802 struct rte_mbuf *temp_frag; /* Pointer to mbuf chain head */
803 struct rte_mbuf *curr_frag;
804 uint8_t list_count = 0;
808 PMD_RX_LOG(INFO, rxq, "TPA cont[%02x] - len_list [%04x %04x]\n",
809 cqe->tpa_agg_index, rte_le_to_cpu_16(cqe->len_list[0]),
810 rte_le_to_cpu_16(cqe->len_list[1]));
812 tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
813 temp_frag = tpa_info->mbuf;
816 for (i = 0; cqe->len_list[i]; i++) {
817 cons_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
818 curr_frag = rxq->sw_rx_ring[cons_idx].mbuf;
819 qede_rx_bd_ring_consume(rxq);
820 curr_frag->data_len = rte_le_to_cpu_16(cqe->len_list[i]);
821 temp_frag->next = curr_frag;
822 temp_frag = curr_frag;
826 /* Allocate RX mbuf on the RX BD ring for those many consumed */
827 for (i = 0 ; i < list_count ; i++) {
828 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
829 DP_ERR(edev, "Failed to allocate mbuf for LRO cont\n");
830 tpa_info->state = QEDE_AGG_STATE_ERROR;
836 qede_rx_process_tpa_end_cqe(struct qede_dev *qdev,
837 struct qede_rx_queue *rxq,
838 struct eth_fast_path_rx_tpa_end_cqe *cqe)
840 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
841 struct qede_agg_info *tpa_info;
842 struct rte_mbuf *temp_frag; /* Pointer to mbuf chain head */
843 struct rte_mbuf *curr_frag;
844 struct rte_mbuf *rx_mb;
845 uint8_t list_count = 0;
849 PMD_RX_LOG(INFO, rxq, "TPA End[%02x] - len_list [%04x %04x]\n",
850 cqe->tpa_agg_index, rte_le_to_cpu_16(cqe->len_list[0]),
851 rte_le_to_cpu_16(cqe->len_list[1]));
853 tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
854 temp_frag = tpa_info->mbuf;
857 for (i = 0; cqe->len_list[i]; i++) {
858 cons_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
859 curr_frag = rxq->sw_rx_ring[cons_idx].mbuf;
860 qede_rx_bd_ring_consume(rxq);
861 curr_frag->data_len = rte_le_to_cpu_16(cqe->len_list[i]);
862 temp_frag->next = curr_frag;
863 temp_frag = curr_frag;
867 /* Allocate RX mbuf on the RX BD ring for those many consumed */
868 for (i = 0 ; i < list_count ; i++) {
869 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
870 DP_ERR(edev, "Failed to allocate mbuf for lro end\n");
871 tpa_info->state = QEDE_AGG_STATE_ERROR;
875 /* Update total length and frags based on end TPA */
876 rx_mb = rxq->tpa_info[cqe->tpa_agg_index].mbuf;
877 /* TBD: Add sanity checks here */
878 rx_mb->nb_segs = cqe->num_of_bds;
879 rx_mb->pkt_len = cqe->total_packet_len;
880 tpa_info->state = QEDE_AGG_STATE_NONE;
883 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
888 static const uint32_t
889 ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
890 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
891 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
892 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
893 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
894 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
895 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
896 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
897 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
898 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
899 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
900 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
901 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
902 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
903 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
904 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
905 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
906 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
907 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
908 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
909 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
910 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
911 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
912 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
913 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
914 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
915 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
916 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
917 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
918 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
919 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
920 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
921 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
922 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
923 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
924 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
925 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
926 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
927 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
928 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
929 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
932 /* Cover bits[4-0] to include tunn_type and next protocol */
933 val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
934 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
935 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
936 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
938 if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
939 return ptype_tunn_lkup_tbl[val];
941 return RTE_PTYPE_UNKNOWN;
945 qede_process_sg_pkts(void *p_rxq, struct rte_mbuf *rx_mb,
946 uint8_t num_segs, uint16_t pkt_len)
948 struct qede_rx_queue *rxq = p_rxq;
949 struct qede_dev *qdev = rxq->qdev;
950 struct ecore_dev *edev = &qdev->edev;
951 register struct rte_mbuf *seg1 = NULL;
952 register struct rte_mbuf *seg2 = NULL;
953 uint16_t sw_rx_index;
958 cur_size = pkt_len > rxq->rx_buf_size ? rxq->rx_buf_size :
960 if (unlikely(!cur_size)) {
961 PMD_RX_LOG(ERR, rxq, "Length is 0 while %u BDs"
962 " left for mapping jumbo", num_segs);
963 qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
966 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
967 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
968 qede_rx_bd_ring_consume(rxq);
970 seg2->data_len = cur_size;
981 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
983 struct qede_rx_queue *rxq = p_rxq;
984 struct qede_dev *qdev = rxq->qdev;
985 struct ecore_dev *edev = &qdev->edev;
986 struct qede_fastpath *fp = &qdev->fp_array[rxq->queue_id];
987 uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
989 union eth_rx_cqe *cqe;
990 struct eth_fast_path_rx_reg_cqe *fp_cqe;
991 register struct rte_mbuf *rx_mb = NULL;
992 register struct rte_mbuf *seg1 = NULL;
993 enum eth_rx_cqe_type cqe_type;
994 uint16_t pkt_len; /* Sum of all BD segments */
995 uint16_t len; /* Length of first BD */
996 uint8_t num_segs = 1;
997 uint16_t preload_idx;
1000 enum rss_hash_type htype;
1001 uint8_t tunn_parse_flag;
1003 struct eth_fast_path_rx_tpa_start_cqe *cqe_start_tpa;
1005 uint32_t packet_type;
1008 uint8_t bitfield_val;
1009 uint8_t offset, tpa_agg_idx, flags;
1010 struct qede_agg_info *tpa_info;
1012 hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
1013 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1017 if (hw_comp_cons == sw_comp_cons)
1020 while (sw_comp_cons != hw_comp_cons) {
1022 packet_type = RTE_PTYPE_UNKNOWN;
1024 tpa_start_flg = false;
1026 /* Get the CQE from the completion ring */
1028 (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
1029 cqe_type = cqe->fast_path_regular.type;
1030 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type);
1033 case ETH_RX_CQE_TYPE_REGULAR:
1034 fp_cqe = &cqe->fast_path_regular;
1036 case ETH_RX_CQE_TYPE_TPA_START:
1037 cqe_start_tpa = &cqe->fast_path_tpa_start;
1038 tpa_info = &rxq->tpa_info[cqe_start_tpa->tpa_agg_index];
1039 tpa_start_flg = true;
1040 PMD_RX_LOG(INFO, rxq,
1041 "TPA start[%u] - len %04x [header %02x]"
1042 " [bd_list[0] %04x], [seg_len %04x]\n",
1043 cqe_start_tpa->tpa_agg_index,
1044 rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd),
1045 cqe_start_tpa->header_len,
1046 rte_le_to_cpu_16(cqe_start_tpa->ext_bd_len_list[0]),
1047 rte_le_to_cpu_16(cqe_start_tpa->seg_len));
1050 case ETH_RX_CQE_TYPE_TPA_CONT:
1051 qede_rx_process_tpa_cont_cqe(qdev, rxq,
1052 &cqe->fast_path_tpa_cont);
1054 case ETH_RX_CQE_TYPE_TPA_END:
1055 qede_rx_process_tpa_end_cqe(qdev, rxq,
1056 &cqe->fast_path_tpa_end);
1057 tpa_agg_idx = cqe->fast_path_tpa_end.tpa_agg_index;
1058 rx_mb = rxq->tpa_info[tpa_agg_idx].mbuf;
1059 PMD_RX_LOG(INFO, rxq, "TPA end reason %d\n",
1060 cqe->fast_path_tpa_end.end_reason);
1062 case ETH_RX_CQE_TYPE_SLOW_PATH:
1063 PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n");
1064 qdev->ops->eth_cqe_completion(edev, fp->id,
1065 (struct eth_slow_path_rx_cqe *)cqe);
1071 /* Get the data from the SW ring */
1072 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1073 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
1074 assert(rx_mb != NULL);
1076 /* Handle regular CQE or TPA start CQE */
1077 if (!tpa_start_flg) {
1078 parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);
1079 bitfield_val = fp_cqe->bitfields;
1080 offset = fp_cqe->placement_offset;
1081 len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
1082 pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1085 rte_le_to_cpu_16(cqe_start_tpa->pars_flags.flags);
1086 bitfield_val = cqe_start_tpa->bitfields;
1087 offset = cqe_start_tpa->placement_offset;
1088 /* seg_len = len_on_first_bd */
1089 len = rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd);
1090 tpa_info->start_cqe_bd_len = len +
1091 cqe_start_tpa->header_len;
1092 tpa_info->mbuf = rx_mb;
1094 if (qede_tunn_exist(parse_flag)) {
1095 PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n");
1096 if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1097 PMD_RX_LOG(ERR, rxq,
1098 "L4 csum failed, flags = 0x%x\n",
1100 rxq->rx_hw_errors++;
1101 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1103 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1106 cqe_start_tpa->tunnel_pars_flags.flags;
1108 flags = fp_cqe->tunnel_pars_flags.flags;
1109 tunn_parse_flag = flags;
1111 qede_rx_cqe_to_tunn_pkt_type(tunn_parse_flag);
1114 PMD_RX_LOG(INFO, rxq, "Rx non-tunneled packet\n");
1115 if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1116 PMD_RX_LOG(ERR, rxq,
1117 "L4 csum failed, flags = 0x%x\n",
1119 rxq->rx_hw_errors++;
1120 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1122 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1124 if (unlikely(qede_check_notunn_csum_l3(rx_mb,
1126 PMD_RX_LOG(ERR, rxq,
1127 "IP csum failed, flags = 0x%x\n",
1129 rxq->rx_hw_errors++;
1130 ol_flags |= PKT_RX_IP_CKSUM_BAD;
1132 ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1134 qede_rx_cqe_to_pkt_type(parse_flag);
1138 if (CQE_HAS_VLAN(parse_flag)) {
1139 vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1140 ol_flags |= PKT_RX_VLAN_PKT;
1143 if (CQE_HAS_OUTER_VLAN(parse_flag)) {
1144 vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1145 ol_flags |= PKT_RX_QINQ_PKT;
1146 rx_mb->vlan_tci_outer = 0;
1150 htype = (uint8_t)GET_FIELD(bitfield_val,
1151 ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
1152 if (qdev->rss_enable && htype) {
1153 ol_flags |= PKT_RX_RSS_HASH;
1154 rx_mb->hash.rss = rte_le_to_cpu_32(fp_cqe->rss_hash);
1155 PMD_RX_LOG(INFO, rxq, "Hash result 0x%x\n",
1159 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1160 PMD_RX_LOG(ERR, rxq,
1161 "New buffer allocation failed,"
1162 "dropping incoming packet\n");
1163 qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
1164 rte_eth_devices[rxq->port_id].
1165 data->rx_mbuf_alloc_failed++;
1166 rxq->rx_alloc_errors++;
1169 qede_rx_bd_ring_consume(rxq);
1171 if (!tpa_start_flg && fp_cqe->bd_num > 1) {
1172 PMD_RX_LOG(DEBUG, rxq, "Jumbo-over-BD packet: %02x BDs"
1173 " len on first: %04x Total Len: %04x",
1174 fp_cqe->bd_num, len, pkt_len);
1175 num_segs = fp_cqe->bd_num - 1;
1177 if (qede_process_sg_pkts(p_rxq, seg1, num_segs,
1180 for (j = 0; j < num_segs; j++) {
1181 if (qede_alloc_rx_buffer(rxq)) {
1182 PMD_RX_LOG(ERR, rxq,
1183 "Buffer allocation failed");
1184 rte_eth_devices[rxq->port_id].
1185 data->rx_mbuf_alloc_failed++;
1186 rxq->rx_alloc_errors++;
1192 rxq->rx_segs++; /* for the first segment */
1194 /* Prefetch next mbuf while processing current one. */
1195 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1196 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1198 /* Update rest of the MBUF fields */
1199 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1200 rx_mb->port = rxq->port_id;
1201 rx_mb->ol_flags = ol_flags;
1202 rx_mb->data_len = len;
1203 rx_mb->vlan_tci = vlan_tci;
1204 rx_mb->packet_type = packet_type;
1205 PMD_RX_LOG(INFO, rxq, "pkt_type %04x len %04x flags %04lx\n",
1206 packet_type, len, (unsigned long)ol_flags);
1207 if (!tpa_start_flg) {
1208 rx_mb->nb_segs = fp_cqe->bd_num;
1209 rx_mb->pkt_len = pkt_len;
1211 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
1213 if (!tpa_start_flg) {
1214 rx_pkts[rx_pkt] = rx_mb;
1218 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1219 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1220 if (rx_pkt == nb_pkts) {
1221 PMD_RX_LOG(DEBUG, rxq,
1222 "Budget reached nb_pkts=%u received=%u",
1228 qede_update_rx_prod(qdev, rxq);
1230 rxq->rcv_pkts += rx_pkt;
1232 PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
1238 qede_free_tx_pkt(struct qede_tx_queue *txq)
1240 struct rte_mbuf *mbuf;
1246 mbuf = txq->sw_tx_ring[idx].mbuf;
1248 nb_segs = mbuf->nb_segs;
1249 PMD_TX_LOG(DEBUG, txq, "nb_segs to free %u\n", nb_segs);
1251 /* It's like consuming rxbuf in recv() */
1252 ecore_chain_consume(&txq->tx_pbl);
1256 rte_pktmbuf_free(mbuf);
1257 txq->sw_tx_ring[idx].mbuf = NULL;
1259 PMD_TX_LOG(DEBUG, txq, "Freed tx packet\n");
1261 ecore_chain_consume(&txq->tx_pbl);
1267 qede_process_tx_compl(struct ecore_dev *edev, struct qede_tx_queue *txq)
1269 uint16_t hw_bd_cons;
1270 uint16_t sw_tx_cons;
1272 rte_compiler_barrier();
1273 hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
1274 sw_tx_cons = ecore_chain_get_cons_idx(&txq->tx_pbl);
1275 PMD_TX_LOG(DEBUG, txq, "Tx Completions = %u\n",
1276 abs(hw_bd_cons - sw_tx_cons));
1277 while (hw_bd_cons != ecore_chain_get_cons_idx(&txq->tx_pbl))
1278 qede_free_tx_pkt(txq);
1281 /* Populate scatter gather buffer descriptor fields */
1282 static inline uint8_t
1283 qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg,
1284 struct eth_tx_2nd_bd **bd2, struct eth_tx_3rd_bd **bd3)
1286 struct qede_tx_queue *txq = p_txq;
1287 struct eth_tx_bd *tx_bd = NULL;
1289 uint8_t nb_segs = 0;
1291 /* Check for scattered buffers */
1295 *bd2 = (struct eth_tx_2nd_bd *)
1296 ecore_chain_produce(&txq->tx_pbl);
1297 memset(*bd2, 0, sizeof(struct eth_tx_2nd_bd));
1300 mapping = rte_mbuf_data_dma_addr(m_seg);
1301 QEDE_BD_SET_ADDR_LEN(*bd2, mapping, m_seg->data_len);
1302 PMD_TX_LOG(DEBUG, txq, "BD2 len %04x", m_seg->data_len);
1303 } else if (nb_segs == 1) {
1305 *bd3 = (struct eth_tx_3rd_bd *)
1306 ecore_chain_produce(&txq->tx_pbl);
1307 memset(*bd3, 0, sizeof(struct eth_tx_3rd_bd));
1310 mapping = rte_mbuf_data_dma_addr(m_seg);
1311 QEDE_BD_SET_ADDR_LEN(*bd3, mapping, m_seg->data_len);
1312 PMD_TX_LOG(DEBUG, txq, "BD3 len %04x", m_seg->data_len);
1314 tx_bd = (struct eth_tx_bd *)
1315 ecore_chain_produce(&txq->tx_pbl);
1316 memset(tx_bd, 0, sizeof(*tx_bd));
1318 mapping = rte_mbuf_data_dma_addr(m_seg);
1319 QEDE_BD_SET_ADDR_LEN(tx_bd, mapping, m_seg->data_len);
1320 PMD_TX_LOG(DEBUG, txq, "BD len %04x", m_seg->data_len);
1322 m_seg = m_seg->next;
1325 /* Return total scattered buffers */
1329 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1331 print_tx_bd_info(struct qede_tx_queue *txq,
1332 struct eth_tx_1st_bd *bd1,
1333 struct eth_tx_2nd_bd *bd2,
1334 struct eth_tx_3rd_bd *bd3,
1335 uint64_t tx_ol_flags)
1337 char ol_buf[256] = { 0 }; /* for verbose prints */
1340 PMD_TX_LOG(INFO, txq,
1341 "BD1: nbytes=%u nbds=%u bd_flags=04%x bf=%04x",
1342 rte_cpu_to_le_16(bd1->nbytes), bd1->data.nbds,
1343 bd1->data.bd_flags.bitfields,
1344 rte_cpu_to_le_16(bd1->data.bitfields));
1346 PMD_TX_LOG(INFO, txq,
1347 "BD2: nbytes=%u bf=%04x\n",
1348 rte_cpu_to_le_16(bd2->nbytes), bd2->data.bitfields1);
1350 PMD_TX_LOG(INFO, txq,
1351 "BD3: nbytes=%u bf=%04x mss=%u\n",
1352 rte_cpu_to_le_16(bd3->nbytes),
1353 rte_cpu_to_le_16(bd3->data.bitfields),
1354 rte_cpu_to_le_16(bd3->data.lso_mss));
1356 rte_get_tx_ol_flag_list(tx_ol_flags, ol_buf, sizeof(ol_buf));
1357 PMD_TX_LOG(INFO, txq, "TX offloads = %s\n", ol_buf);
1361 /* TX prepare to check packets meets TX conditions */
1363 qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
1366 struct qede_tx_queue *txq = p_txq;
1372 for (i = 0; i < nb_pkts; i++) {
1374 ol_flags = m->ol_flags;
1375 if (ol_flags & PKT_TX_TCP_SEG) {
1376 if (m->nb_segs >= ETH_TX_MAX_BDS_PER_LSO_PACKET) {
1377 rte_errno = -EINVAL;
1380 /* TBD: confirm its ~9700B for both ? */
1381 if (m->tso_segsz > ETH_TX_MAX_NON_LSO_PKT_LEN) {
1382 rte_errno = -EINVAL;
1386 if (m->nb_segs >= ETH_TX_MAX_BDS_PER_NON_LSO_PACKET) {
1387 rte_errno = -EINVAL;
1391 if (ol_flags & QEDE_TX_OFFLOAD_NOTSUP_MASK) {
1392 rte_errno = -ENOTSUP;
1396 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1397 ret = rte_validate_tx_offload(m);
1403 /* TBD: pseudo csum calcuation required iff
1404 * ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE not set?
1406 ret = rte_net_intel_cksum_prepare(m);
1413 if (unlikely(i != nb_pkts))
1414 PMD_TX_LOG(ERR, txq, "TX prepare failed for %u\n",
1420 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1422 struct qede_tx_queue *txq = p_txq;
1423 struct qede_dev *qdev = txq->qdev;
1424 struct ecore_dev *edev = &qdev->edev;
1425 struct rte_mbuf *mbuf;
1426 struct rte_mbuf *m_seg = NULL;
1427 uint16_t nb_tx_pkts;
1431 uint16_t nb_pkt_sent = 0;
1436 struct eth_tx_1st_bd *bd1;
1437 struct eth_tx_2nd_bd *bd2;
1438 struct eth_tx_3rd_bd *bd3;
1439 uint64_t tx_ol_flags;
1442 if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
1443 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
1444 nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
1445 qede_process_tx_compl(edev, txq);
1448 nb_tx_pkts = nb_pkts;
1449 bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1450 while (nb_tx_pkts--) {
1451 /* Init flags/values */
1452 ipv6_ext_flg = false;
1464 /* Check minimum TX BDS availability against available BDs */
1465 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs))
1468 tx_ol_flags = mbuf->ol_flags;
1470 #define RTE_ETH_IS_IPV6_HDR_EXT(ptype) ((ptype) & RTE_PTYPE_L3_IPV6_EXT)
1471 if (RTE_ETH_IS_IPV6_HDR_EXT(mbuf->packet_type))
1472 ipv6_ext_flg = true;
1474 if (RTE_ETH_IS_TUNNEL_PKT(mbuf->packet_type))
1477 if (tx_ol_flags & PKT_TX_TCP_SEG)
1481 if (unlikely(txq->nb_tx_avail <
1482 ETH_TX_MIN_BDS_PER_LSO_PKT))
1485 if (unlikely(txq->nb_tx_avail <
1486 ETH_TX_MIN_BDS_PER_NON_LSO_PKT))
1490 if (tunn_flg && ipv6_ext_flg) {
1491 if (unlikely(txq->nb_tx_avail <
1492 ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT))
1496 if (unlikely(txq->nb_tx_avail <
1497 ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT))
1501 /* Fill the entry in the SW ring and the BDs in the FW ring */
1504 txq->sw_tx_ring[idx].mbuf = mbuf;
1507 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
1508 memset(bd1, 0, sizeof(struct eth_tx_1st_bd));
1511 bd1->data.bd_flags.bitfields |=
1512 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
1513 /* FW 8.10.x specific change */
1515 bd1->data.bitfields |=
1516 (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
1517 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
1518 /* Map MBUF linear data for DMA and set in the BD1 */
1519 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_dma_addr(mbuf),
1522 /* For LSO, packet header and payload must reside on
1523 * buffers pointed by different BDs. Using BD1 for HDR
1524 * and BD2 onwards for data.
1526 hdr_size = mbuf->l2_len + mbuf->l3_len + mbuf->l4_len;
1527 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_dma_addr(mbuf),
1532 /* First indicate its a tunnel pkt */
1533 bd1->data.bd_flags.bitfields |=
1534 ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
1535 ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1537 /* Legacy FW had flipped behavior in regard to this bit
1538 * i.e. it needed to set to prevent FW from touching
1539 * encapsulated packets when it didn't need to.
1541 if (unlikely(txq->is_legacy))
1542 bd1->data.bitfields ^=
1543 1 << ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1545 /* Outer IP checksum offload */
1546 if (tx_ol_flags & PKT_TX_OUTER_IP_CKSUM) {
1547 bd1->data.bd_flags.bitfields |=
1548 ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
1549 ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
1552 /* Outer UDP checksum offload */
1553 bd1->data.bd_flags.bitfields |=
1554 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
1555 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
1558 /* Descriptor based VLAN insertion */
1559 if (tx_ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1560 bd1->data.vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
1561 bd1->data.bd_flags.bitfields |=
1562 1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
1566 bd1->data.bd_flags.bitfields |=
1567 1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT;
1569 /* Offload the IP checksum in the hardware */
1570 if ((lso_flg) || (tx_ol_flags & PKT_TX_IP_CKSUM))
1571 bd1->data.bd_flags.bitfields |=
1572 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1574 /* L4 checksum offload (tcp or udp) */
1575 if ((lso_flg) || (tx_ol_flags & (PKT_TX_TCP_CKSUM |
1577 /* PKT_TX_TCP_SEG implies PKT_TX_TCP_CKSUM */
1578 bd1->data.bd_flags.bitfields |=
1579 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1582 if (lso_flg || ipv6_ext_flg) {
1583 bd2 = (struct eth_tx_2nd_bd *)ecore_chain_produce
1585 memset(bd2, 0, sizeof(struct eth_tx_2nd_bd));
1587 QEDE_BD_SET_ADDR_LEN(bd2,
1589 rte_mbuf_data_dma_addr(mbuf)),
1590 mbuf->data_len - hdr_size);
1591 /* TBD: check pseudo csum iff tx_prepare not called? */
1593 bd2->data.bitfields1 |=
1594 ETH_L4_PSEUDO_CSUM_ZERO_LENGTH <<
1595 ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT;
1600 if (lso_flg || ipv6_ext_flg) {
1601 bd3 = (struct eth_tx_3rd_bd *)ecore_chain_produce
1603 memset(bd3, 0, sizeof(struct eth_tx_3rd_bd));
1607 rte_cpu_to_le_16(mbuf->tso_segsz);
1608 /* Using one header BD */
1609 bd3->data.bitfields |=
1610 rte_cpu_to_le_16(1 <<
1611 ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
1615 /* Handle fragmented MBUF */
1617 /* Encode scatter gather buffer descriptors if required */
1618 nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3);
1619 bd1->data.nbds = nbds + nb_frags;
1620 txq->nb_tx_avail -= bd1->data.nbds;
1622 rte_prefetch0(txq->sw_tx_ring[TX_PROD(txq)].mbuf);
1624 rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1625 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1626 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);
1627 PMD_TX_LOG(INFO, txq, "lso=%d tunn=%d ipv6_ext=%d\n",
1628 lso_flg, tunn_flg, ipv6_ext_flg);
1634 /* Write value of prod idx into bd_prod */
1635 txq->tx_db.data.bd_prod = bd_prod;
1637 rte_compiler_barrier();
1638 DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
1641 /* Check again for Tx completions */
1642 qede_process_tx_compl(edev, txq);
1644 PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d",
1645 nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());
1650 static void qede_init_fp_queue(struct rte_eth_dev *eth_dev)
1652 struct qede_dev *qdev = eth_dev->data->dev_private;
1653 struct qede_fastpath *fp;
1654 uint8_t i, rss_id, txq_index, tc;
1655 int rxq = 0, txq = 0;
1658 fp = &qdev->fp_array[i];
1659 if (fp->type & QEDE_FASTPATH_RX) {
1660 fp->rxq = eth_dev->data->rx_queues[i];
1661 fp->rxq->queue_id = rxq++;
1664 if (fp->type & QEDE_FASTPATH_TX) {
1665 for (tc = 0; tc < qdev->num_tc; tc++) {
1666 txq_index = tc * QEDE_TSS_COUNT(qdev) + txq;
1668 eth_dev->data->tx_queues[txq_index];
1669 fp->txqs[tc]->queue_id = txq_index;
1670 if (qdev->dev_info.is_legacy)
1671 fp->txqs[tc]->is_legacy = true;
1678 int qede_dev_start(struct rte_eth_dev *eth_dev)
1680 struct qede_dev *qdev = eth_dev->data->dev_private;
1681 struct ecore_dev *edev = &qdev->edev;
1682 struct qed_link_output link_output;
1683 struct qede_fastpath *fp;
1686 DP_INFO(edev, "Device state is %d\n", qdev->state);
1688 if (qdev->state == QEDE_DEV_START) {
1689 DP_INFO(edev, "Port is already started\n");
1693 if (qdev->state == QEDE_DEV_CONFIG)
1694 qede_init_fp_queue(eth_dev);
1696 rc = qede_start_queues(eth_dev, true);
1698 DP_ERR(edev, "Failed to start queues\n");
1703 /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1704 * enabling RSS. Hence RSS configuration is deferred upto this point.
1705 * Also, we would like to retain similar behavior in PF case, so we
1706 * don't do PF/VF specific check here.
1708 if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1709 if (qede_config_rss(eth_dev))
1712 /* Bring-up the link */
1713 qede_dev_set_link_state(eth_dev, true);
1716 if (qede_reset_fp_rings(qdev))
1719 /* Start/resume traffic */
1720 qdev->ops->fastpath_start(edev);
1722 qdev->state = QEDE_DEV_START;
1724 DP_INFO(edev, "dev_state is QEDE_DEV_START\n");
1729 static int qede_drain_txq(struct qede_dev *qdev,
1730 struct qede_tx_queue *txq, bool allow_drain)
1732 struct ecore_dev *edev = &qdev->edev;
1735 while (txq->sw_tx_cons != txq->sw_tx_prod) {
1736 qede_process_tx_compl(edev, txq);
1739 DP_ERR(edev, "Tx queue[%u] is stuck,"
1740 "requesting MCP to drain\n",
1742 rc = qdev->ops->common->drain(edev);
1745 return qede_drain_txq(qdev, txq, false);
1747 DP_ERR(edev, "Timeout waiting for tx queue[%d]:"
1748 "PROD=%d, CONS=%d\n",
1749 txq->queue_id, txq->sw_tx_prod,
1755 rte_compiler_barrier();
1758 /* FW finished processing, wait for HW to transmit all tx packets */
1764 static int qede_stop_queues(struct qede_dev *qdev)
1766 struct qed_update_vport_params vport_update_params;
1767 struct ecore_dev *edev = &qdev->edev;
1768 struct ecore_sge_tpa_params tpa_params;
1769 struct qede_fastpath *fp;
1772 /* Disable the vport */
1773 memset(&vport_update_params, 0, sizeof(vport_update_params));
1774 vport_update_params.vport_id = 0;
1775 vport_update_params.update_vport_active_flg = 1;
1776 vport_update_params.vport_active_flg = 0;
1777 vport_update_params.update_rss_flg = 0;
1779 if (qdev->enable_lro) {
1780 DP_INFO(edev, "Disabling LRO\n");
1781 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
1782 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, false);
1783 vport_update_params.sge_tpa_params = &tpa_params;
1786 DP_INFO(edev, "Deactivate vport\n");
1787 rc = qdev->ops->vport_update(edev, &vport_update_params);
1789 DP_ERR(edev, "Failed to update vport\n");
1793 DP_INFO(edev, "Flushing tx queues\n");
1795 /* Flush Tx queues. If needed, request drain from MCP */
1797 fp = &qdev->fp_array[i];
1799 if (fp->type & QEDE_FASTPATH_TX) {
1800 for (tc = 0; tc < qdev->num_tc; tc++) {
1801 struct qede_tx_queue *txq = fp->txqs[tc];
1803 rc = qede_drain_txq(qdev, txq, true);
1810 /* Stop all Queues in reverse order */
1811 for (i = QEDE_QUEUE_CNT(qdev) - 1; i >= 0; i--) {
1812 fp = &qdev->fp_array[i];
1814 /* Stop the Tx Queue(s) */
1815 if (qdev->fp_array[i].type & QEDE_FASTPATH_TX) {
1816 for (tc = 0; tc < qdev->num_tc; tc++) {
1817 struct qede_tx_queue *txq = fp->txqs[tc];
1818 DP_INFO(edev, "Stopping tx queues\n");
1819 rc = qdev->ops->q_tx_stop(edev, i, txq->handle);
1821 DP_ERR(edev, "Failed to stop TXQ #%d\n",
1828 /* Stop the Rx Queue */
1829 if (qdev->fp_array[i].type & QEDE_FASTPATH_RX) {
1830 DP_INFO(edev, "Stopping rx queues\n");
1831 rc = qdev->ops->q_rx_stop(edev, i, fp->rxq->handle);
1833 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
1842 int qede_reset_fp_rings(struct qede_dev *qdev)
1844 struct qede_fastpath *fp;
1845 struct qede_tx_queue *txq;
1849 for_each_queue(id) {
1850 fp = &qdev->fp_array[id];
1852 if (fp->type & QEDE_FASTPATH_RX) {
1853 DP_INFO(&qdev->edev,
1854 "Reset FP chain for RSS %u\n", id);
1855 qede_rx_queue_release_mbufs(fp->rxq);
1856 ecore_chain_reset(&fp->rxq->rx_bd_ring);
1857 ecore_chain_reset(&fp->rxq->rx_comp_ring);
1858 fp->rxq->sw_rx_prod = 0;
1859 fp->rxq->sw_rx_cons = 0;
1860 *fp->rxq->hw_cons_ptr = 0;
1861 for (i = 0; i < fp->rxq->nb_rx_desc; i++) {
1862 if (qede_alloc_rx_buffer(fp->rxq)) {
1864 "RX buffer allocation failed\n");
1869 if (fp->type & QEDE_FASTPATH_TX) {
1870 for (tc = 0; tc < qdev->num_tc; tc++) {
1872 qede_tx_queue_release_mbufs(txq);
1873 ecore_chain_reset(&txq->tx_pbl);
1874 txq->sw_tx_cons = 0;
1875 txq->sw_tx_prod = 0;
1876 *txq->hw_cons_ptr = 0;
1884 /* This function frees all memory of a single fp */
1885 void qede_free_mem_load(struct rte_eth_dev *eth_dev)
1887 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1888 struct qede_fastpath *fp;
1893 for_each_queue(id) {
1894 fp = &qdev->fp_array[id];
1895 if (fp->type & QEDE_FASTPATH_RX) {
1898 qede_rx_queue_release(fp->rxq);
1899 eth_dev->data->rx_queues[id] = NULL;
1901 for (tc = 0; tc < qdev->num_tc; tc++) {
1904 txq_idx = fp->txqs[tc]->queue_id;
1905 qede_tx_queue_release(fp->txqs[tc]);
1906 eth_dev->data->tx_queues[txq_idx] = NULL;
1912 void qede_dev_stop(struct rte_eth_dev *eth_dev)
1914 struct qede_dev *qdev = eth_dev->data->dev_private;
1915 struct ecore_dev *edev = &qdev->edev;
1917 DP_INFO(edev, "port %u\n", eth_dev->data->port_id);
1919 if (qdev->state != QEDE_DEV_START) {
1920 DP_INFO(edev, "Device not yet started\n");
1924 if (qede_stop_queues(qdev))
1925 DP_ERR(edev, "Didn't succeed to close queues\n");
1927 DP_INFO(edev, "Stopped queues\n");
1929 qdev->ops->fastpath_stop(edev);
1931 /* Bring the link down */
1932 qede_dev_set_link_state(eth_dev, false);
1934 qdev->state = QEDE_DEV_STOP;
1936 DP_INFO(edev, "dev_state is QEDE_DEV_STOP\n");
1940 qede_rxtx_pkts_dummy(__rte_unused void *p_rxq,
1941 __rte_unused struct rte_mbuf **pkts,
1942 __rte_unused uint16_t nb_pkts)