drivers/net/qede/qede_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include <rte_net.h>
   8 #include "qede_rxtx.h"
   9
  10 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
  11 {
  12         struct rte_mbuf *new_mb = NULL;
  13         struct eth_rx_bd *rx_bd;
  14         dma_addr_t mapping;
  15         uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
  16
  17         new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
  18         if (unlikely(!new_mb)) {
  19                 PMD_RX_LOG(ERR, rxq,
  20                            "Failed to allocate rx buffer "
  21                            "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
  22                            idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
  23                            rte_mempool_avail_count(rxq->mb_pool),
  24                            rte_mempool_in_use_count(rxq->mb_pool));
  25                 return -ENOMEM;
  26         }
  27         rxq->sw_rx_ring[idx].mbuf = new_mb;
  28         rxq->sw_rx_ring[idx].page_offset = 0;
  29         mapping = rte_mbuf_data_iova_default(new_mb);
  30         /* Advance PROD and get BD pointer */
  31         rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
  32         rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
  33         rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
  34         rxq->sw_rx_prod++;
  35         return 0;
  36 }
  37
  38 #define QEDE_MAX_BULK_ALLOC_COUNT 512
  39
  40 static inline int qede_alloc_rx_bulk_mbufs(struct qede_rx_queue *rxq, int count)
  41 {
  42         void *obj_p[QEDE_MAX_BULK_ALLOC_COUNT] __rte_cache_aligned;
  43         struct rte_mbuf *mbuf = NULL;
  44         struct eth_rx_bd *rx_bd;
  45         dma_addr_t mapping;
  46         int i, ret = 0;
  47         uint16_t idx;
  48
  49         if (count > QEDE_MAX_BULK_ALLOC_COUNT)
  50                 count = QEDE_MAX_BULK_ALLOC_COUNT;
  51
  52         ret = rte_mempool_get_bulk(rxq->mb_pool, obj_p, count);
  53         if (unlikely(ret)) {
  54                 PMD_RX_LOG(ERR, rxq,
  55                            "Failed to allocate %d rx buffers "
  56                             "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
  57                             count,
  58                             rxq->sw_rx_prod & NUM_RX_BDS(rxq),
  59                             rxq->sw_rx_cons & NUM_RX_BDS(rxq),
  60                             rte_mempool_avail_count(rxq->mb_pool),
  61                             rte_mempool_in_use_count(rxq->mb_pool));
  62                 return -ENOMEM;
  63         }
  64
  65         for (i = 0; i < count; i++) {
  66                 mbuf = obj_p[i];
  67                 if (likely(i < count - 1))
  68                         rte_prefetch0(obj_p[i + 1]);
  69
  70                 idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
  71                 rxq->sw_rx_ring[idx].mbuf = mbuf;
  72                 rxq->sw_rx_ring[idx].page_offset = 0;
  73                 mapping = rte_mbuf_data_iova_default(mbuf);
  74                 rx_bd = (struct eth_rx_bd *)
  75                         ecore_chain_produce(&rxq->rx_bd_ring);
  76                 rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
  77                 rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
  78                 rxq->sw_rx_prod++;
  79         }
  80
  81         return 0;
  82 }
  83
  84 /* Criterias for calculating Rx buffer size -
  85  * 1) rx_buf_size should not exceed the size of mbuf
  86  * 2) In scattered_rx mode - minimum rx_buf_size should be
  87  *    (MTU + Maximum L2 Header Size + 2) / ETH_RX_MAX_BUFF_PER_PKT
  88  * 3) In regular mode - minimum rx_buf_size should be
  89  *    (MTU + Maximum L2 Header Size + 2)
  90  *    In above cases +2 corrosponds to 2 bytes padding in front of L2
  91  *    header.
  92  * 4) rx_buf_size should be cacheline-size aligned. So considering
  93  *    criteria 1, we need to adjust the size to floor instead of ceil,
  94  *    so that we don't exceed mbuf size while ceiling rx_buf_size.
  95  */
  96 int
  97 qede_calc_rx_buf_size(struct rte_eth_dev *dev, uint16_t mbufsz,
  98                       uint16_t max_frame_size)
  99 {
 100         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
 101         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 102         int rx_buf_size;
 103
 104         if (dev->data->scattered_rx) {
 105                 /* per HW limitation, only ETH_RX_MAX_BUFF_PER_PKT number of
 106                  * bufferes can be used for single packet. So need to make sure
 107                  * mbuf size is sufficient enough for this.
 108                  */
 109                 if ((mbufsz * ETH_RX_MAX_BUFF_PER_PKT) <
 110                      (max_frame_size + QEDE_ETH_OVERHEAD)) {
 111                         DP_ERR(edev, "mbuf %d size is not enough to hold max fragments (%d) for max rx packet length (%d)\n",
 112                                mbufsz, ETH_RX_MAX_BUFF_PER_PKT, max_frame_size);
 113                         return -EINVAL;
 114                 }
 115
 116                 rx_buf_size = RTE_MAX(mbufsz,
 117                                       (max_frame_size + QEDE_ETH_OVERHEAD) /
 118                                        ETH_RX_MAX_BUFF_PER_PKT);
 119         } else {
 120                 rx_buf_size = max_frame_size + QEDE_ETH_OVERHEAD;
 121         }
 122
 123         /* Align to cache-line size if needed */
 124         return QEDE_FLOOR_TO_CACHE_LINE_SIZE(rx_buf_size);
 125 }
 126
 127 static struct qede_rx_queue *
 128 qede_alloc_rx_queue_mem(struct rte_eth_dev *dev,
 129                         uint16_t queue_idx,
 130                         uint16_t nb_desc,
 131                         unsigned int socket_id,
 132                         struct rte_mempool *mp,
 133                         uint16_t bufsz)
 134 {
 135         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
 136         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 137         struct qede_rx_queue *rxq;
 138         size_t size;
 139         int rc;
 140
 141         /* First allocate the rx queue data structure */
 142         rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
 143                                  RTE_CACHE_LINE_SIZE, socket_id);
 144
 145         if (!rxq) {
 146                 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
 147                           socket_id);
 148                 return NULL;
 149         }
 150
 151         rxq->qdev = qdev;
 152         rxq->mb_pool = mp;
 153         rxq->nb_rx_desc = nb_desc;
 154         rxq->queue_id = queue_idx;
 155         rxq->port_id = dev->data->port_id;
 156
 157
 158         rxq->rx_buf_size = bufsz;
 159
 160         DP_INFO(edev, "mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\n",
 161                 qdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);
 162
 163         /* Allocate the parallel driver ring for Rx buffers */
 164         size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
 165         rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
 166                                              RTE_CACHE_LINE_SIZE, socket_id);
 167         if (!rxq->sw_rx_ring) {
 168                 DP_ERR(edev, "Memory allocation fails for sw_rx_ring on"
 169                        " socket %u\n", socket_id);
 170                 rte_free(rxq);
 171                 return NULL;
 172         }
 173
 174         /* Allocate FW Rx ring  */
 175         rc = qdev->ops->common->chain_alloc(edev,
 176                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 177                                             ECORE_CHAIN_MODE_NEXT_PTR,
 178                                             ECORE_CHAIN_CNT_TYPE_U16,
 179                                             rxq->nb_rx_desc,
 180                                             sizeof(struct eth_rx_bd),
 181                                             &rxq->rx_bd_ring,
 182                                             NULL);
 183
 184         if (rc != ECORE_SUCCESS) {
 185                 DP_ERR(edev, "Memory allocation fails for RX BD ring"
 186                        " on socket %u\n", socket_id);
 187                 rte_free(rxq->sw_rx_ring);
 188                 rte_free(rxq);
 189                 return NULL;
 190         }
 191
 192         /* Allocate FW completion ring */
 193         rc = qdev->ops->common->chain_alloc(edev,
 194                                             ECORE_CHAIN_USE_TO_CONSUME,
 195                                             ECORE_CHAIN_MODE_PBL,
 196                                             ECORE_CHAIN_CNT_TYPE_U16,
 197                                             rxq->nb_rx_desc,
 198                                             sizeof(union eth_rx_cqe),
 199                                             &rxq->rx_comp_ring,
 200                                             NULL);
 201
 202         if (rc != ECORE_SUCCESS) {
 203                 DP_ERR(edev, "Memory allocation fails for RX CQE ring"
 204                        " on socket %u\n", socket_id);
 205                 qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);
 206                 rte_free(rxq->sw_rx_ring);
 207                 rte_free(rxq);
 208                 return NULL;
 209         }
 210
 211         return rxq;
 212 }
 213
 214 int
 215 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qid,
 216                     uint16_t nb_desc, unsigned int socket_id,
 217                     __rte_unused const struct rte_eth_rxconf *rx_conf,
 218                     struct rte_mempool *mp)
 219 {
 220         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
 221         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 222         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
 223         struct qede_rx_queue *rxq;
 224         uint16_t max_rx_pkt_len;
 225         uint16_t bufsz;
 226         int rc;
 227
 228         PMD_INIT_FUNC_TRACE(edev);
 229
 230         /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
 231         if (!rte_is_power_of_2(nb_desc)) {
 232                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 233                           nb_desc);
 234                 return -EINVAL;
 235         }
 236
 237         /* Free memory prior to re-allocation if needed... */
 238         if (dev->data->rx_queues[qid] != NULL) {
 239                 qede_rx_queue_release(dev->data->rx_queues[qid]);
 240                 dev->data->rx_queues[qid] = NULL;
 241         }
 242
 243         max_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len;
 244
 245         /* Fix up RX buffer size */
 246         bufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 247         /* cache align the mbuf size to simplfy rx_buf_size calculation */
 248         bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
 249         if ((rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) ||
 250             (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {
 251                 if (!dev->data->scattered_rx) {
 252                         DP_INFO(edev, "Forcing scatter-gather mode\n");
 253                         dev->data->scattered_rx = 1;
 254                 }
 255         }
 256
 257         rc = qede_calc_rx_buf_size(dev, bufsz, max_rx_pkt_len);
 258         if (rc < 0)
 259                 return rc;
 260
 261         bufsz = rc;
 262
 263         if (ECORE_IS_CMT(edev)) {
 264                 rxq = qede_alloc_rx_queue_mem(dev, qid * 2, nb_desc,
 265                                               socket_id, mp, bufsz);
 266                 if (!rxq)
 267                         return -ENOMEM;
 268
 269                 qdev->fp_array[qid * 2].rxq = rxq;
 270                 rxq = qede_alloc_rx_queue_mem(dev, qid * 2 + 1, nb_desc,
 271                                               socket_id, mp, bufsz);
 272                 if (!rxq)
 273                         return -ENOMEM;
 274
 275                 qdev->fp_array[qid * 2 + 1].rxq = rxq;
 276                 /* provide per engine fp struct as rx queue */
 277                 dev->data->rx_queues[qid] = &qdev->fp_array_cmt[qid];
 278         } else {
 279                 rxq = qede_alloc_rx_queue_mem(dev, qid, nb_desc,
 280                                               socket_id, mp, bufsz);
 281                 if (!rxq)
 282                         return -ENOMEM;
 283
 284                 dev->data->rx_queues[qid] = rxq;
 285                 qdev->fp_array[qid].rxq = rxq;
 286         }
 287
 288         DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
 289                   qid, nb_desc, rxq->rx_buf_size, socket_id);
 290
 291         return 0;
 292 }
 293
 294 static void
 295 qede_rx_queue_reset(__rte_unused struct qede_dev *qdev,
 296                     struct qede_rx_queue *rxq)
 297 {
 298         DP_INFO(&qdev->edev, "Reset RX queue %u\n", rxq->queue_id);
 299         ecore_chain_reset(&rxq->rx_bd_ring);
 300         ecore_chain_reset(&rxq->rx_comp_ring);
 301         rxq->sw_rx_prod = 0;
 302         rxq->sw_rx_cons = 0;
 303         *rxq->hw_cons_ptr = 0;
 304 }
 305
 306 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
 307 {
 308         uint16_t i;
 309
 310         if (rxq->sw_rx_ring) {
 311                 for (i = 0; i < rxq->nb_rx_desc; i++) {
 312                         if (rxq->sw_rx_ring[i].mbuf) {
 313                                 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
 314                                 rxq->sw_rx_ring[i].mbuf = NULL;
 315                         }
 316                 }
 317         }
 318 }
 319
 320 static void _qede_rx_queue_release(struct qede_dev *qdev,
 321                                    struct ecore_dev *edev,
 322                                    struct qede_rx_queue *rxq)
 323 {
 324         qede_rx_queue_release_mbufs(rxq);
 325         qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);
 326         qdev->ops->common->chain_free(edev, &rxq->rx_comp_ring);
 327         rte_free(rxq->sw_rx_ring);
 328         rte_free(rxq);
 329 }
 330
 331 void qede_rx_queue_release(void *rx_queue)
 332 {
 333         struct qede_rx_queue *rxq = rx_queue;
 334         struct qede_fastpath_cmt *fp_cmt;
 335         struct qede_dev *qdev;
 336         struct ecore_dev *edev;
 337
 338         if (rxq) {
 339                 qdev = rxq->qdev;
 340                 edev = QEDE_INIT_EDEV(qdev);
 341                 PMD_INIT_FUNC_TRACE(edev);
 342                 if (ECORE_IS_CMT(edev)) {
 343                         fp_cmt = rx_queue;
 344                         _qede_rx_queue_release(qdev, edev, fp_cmt->fp0->rxq);
 345                         _qede_rx_queue_release(qdev, edev, fp_cmt->fp1->rxq);
 346                 } else {
 347                         _qede_rx_queue_release(qdev, edev, rxq);
 348                 }
 349         }
 350 }
 351
 352 /* Stops a given RX queue in the HW */
 353 static int qede_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 354 {
 355         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 356         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 357         struct ecore_hwfn *p_hwfn;
 358         struct qede_rx_queue *rxq;
 359         int hwfn_index;
 360         int rc;
 361
 362         if (rx_queue_id < qdev->num_rx_queues) {
 363                 rxq = qdev->fp_array[rx_queue_id].rxq;
 364                 hwfn_index = rx_queue_id % edev->num_hwfns;
 365                 p_hwfn = &edev->hwfns[hwfn_index];
 366                 rc = ecore_eth_rx_queue_stop(p_hwfn, rxq->handle,
 367                                 true, false);
 368                 if (rc != ECORE_SUCCESS) {
 369                         DP_ERR(edev, "RX queue %u stop fails\n", rx_queue_id);
 370                         return -1;
 371                 }
 372                 qede_rx_queue_release_mbufs(rxq);
 373                 qede_rx_queue_reset(qdev, rxq);
 374                 eth_dev->data->rx_queue_state[rx_queue_id] =
 375                         RTE_ETH_QUEUE_STATE_STOPPED;
 376                 DP_INFO(edev, "RX queue %u stopped\n", rx_queue_id);
 377         } else {
 378                 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
 379                 rc = -EINVAL;
 380         }
 381
 382         return rc;
 383 }
 384
 385 static struct qede_tx_queue *
 386 qede_alloc_tx_queue_mem(struct rte_eth_dev *dev,
 387                         uint16_t queue_idx,
 388                         uint16_t nb_desc,
 389                         unsigned int socket_id,
 390                         const struct rte_eth_txconf *tx_conf)
 391 {
 392         struct qede_dev *qdev = dev->data->dev_private;
 393         struct ecore_dev *edev = &qdev->edev;
 394         struct qede_tx_queue *txq;
 395         int rc;
 396         size_t sw_tx_ring_size;
 397
 398         txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
 399                                  RTE_CACHE_LINE_SIZE, socket_id);
 400
 401         if (txq == NULL) {
 402                 DP_ERR(edev,
 403                        "Unable to allocate memory for txq on socket %u",
 404                        socket_id);
 405                 return NULL;
 406         }
 407
 408         txq->nb_tx_desc = nb_desc;
 409         txq->qdev = qdev;
 410         txq->port_id = dev->data->port_id;
 411
 412         rc = qdev->ops->common->chain_alloc(edev,
 413                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 414                                             ECORE_CHAIN_MODE_PBL,
 415                                             ECORE_CHAIN_CNT_TYPE_U16,
 416                                             txq->nb_tx_desc,
 417                                             sizeof(union eth_tx_bd_types),
 418                                             &txq->tx_pbl,
 419                                             NULL);
 420         if (rc != ECORE_SUCCESS) {
 421                 DP_ERR(edev,
 422                        "Unable to allocate memory for txbd ring on socket %u",
 423                        socket_id);
 424                 qede_tx_queue_release(txq);
 425                 return NULL;
 426         }
 427
 428         /* Allocate software ring */
 429         sw_tx_ring_size = sizeof(txq->sw_tx_ring) * txq->nb_tx_desc;
 430         txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
 431                                              sw_tx_ring_size,
 432                                              RTE_CACHE_LINE_SIZE, socket_id);
 433
 434         if (!txq->sw_tx_ring) {
 435                 DP_ERR(edev,
 436                        "Unable to allocate memory for txbd ring on socket %u",
 437                        socket_id);
 438                 qdev->ops->common->chain_free(edev, &txq->tx_pbl);
 439                 qede_tx_queue_release(txq);
 440                 return NULL;
 441         }
 442
 443         txq->queue_id = queue_idx;
 444
 445         txq->nb_tx_avail = txq->nb_tx_desc;
 446
 447         txq->tx_free_thresh =
 448             tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
 449             (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
 450
 451         DP_INFO(edev,
 452                   "txq %u num_desc %u tx_free_thresh %u socket %u\n",
 453                   queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
 454         return txq;
 455 }
 456
 457 int
 458 qede_tx_queue_setup(struct rte_eth_dev *dev,
 459                     uint16_t queue_idx,
 460                     uint16_t nb_desc,
 461                     unsigned int socket_id,
 462                     const struct rte_eth_txconf *tx_conf)
 463 {
 464         struct qede_dev *qdev = dev->data->dev_private;
 465         struct ecore_dev *edev = &qdev->edev;
 466         struct qede_tx_queue *txq;
 467
 468         PMD_INIT_FUNC_TRACE(edev);
 469
 470         if (!rte_is_power_of_2(nb_desc)) {
 471                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 472                        nb_desc);
 473                 return -EINVAL;
 474         }
 475
 476         /* Free memory prior to re-allocation if needed... */
 477         if (dev->data->tx_queues[queue_idx] != NULL) {
 478                 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
 479                 dev->data->tx_queues[queue_idx] = NULL;
 480         }
 481
 482         if (ECORE_IS_CMT(edev)) {
 483                 txq = qede_alloc_tx_queue_mem(dev, queue_idx * 2, nb_desc,
 484                                               socket_id, tx_conf);
 485                 if (!txq)
 486                         return -ENOMEM;
 487
 488                 qdev->fp_array[queue_idx * 2].txq = txq;
 489                 txq = qede_alloc_tx_queue_mem(dev, (queue_idx * 2) + 1, nb_desc,
 490                                               socket_id, tx_conf);
 491                 if (!txq)
 492                         return -ENOMEM;
 493
 494                 qdev->fp_array[(queue_idx * 2) + 1].txq = txq;
 495                 dev->data->tx_queues[queue_idx] =
 496                                         &qdev->fp_array_cmt[queue_idx];
 497         } else {
 498                 txq = qede_alloc_tx_queue_mem(dev, queue_idx, nb_desc,
 499                                               socket_id, tx_conf);
 500                 if (!txq)
 501                         return -ENOMEM;
 502
 503                 dev->data->tx_queues[queue_idx] = txq;
 504                 qdev->fp_array[queue_idx].txq = txq;
 505         }
 506
 507         return 0;
 508 }
 509
 510 static void
 511 qede_tx_queue_reset(__rte_unused struct qede_dev *qdev,
 512                     struct qede_tx_queue *txq)
 513 {
 514         DP_INFO(&qdev->edev, "Reset TX queue %u\n", txq->queue_id);
 515         ecore_chain_reset(&txq->tx_pbl);
 516         txq->sw_tx_cons = 0;
 517         txq->sw_tx_prod = 0;
 518         *txq->hw_cons_ptr = 0;
 519 }
 520
 521 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
 522 {
 523         uint16_t i;
 524
 525         if (txq->sw_tx_ring) {
 526                 for (i = 0; i < txq->nb_tx_desc; i++) {
 527                         if (txq->sw_tx_ring[i]) {
 528                                 rte_pktmbuf_free(txq->sw_tx_ring[i]);
 529                                 txq->sw_tx_ring[i] = NULL;
 530                         }
 531                 }
 532         }
 533 }
 534
 535 static void _qede_tx_queue_release(struct qede_dev *qdev,
 536                                    struct ecore_dev *edev,
 537                                    struct qede_tx_queue *txq)
 538 {
 539         qede_tx_queue_release_mbufs(txq);
 540         qdev->ops->common->chain_free(edev, &txq->tx_pbl);
 541         rte_free(txq->sw_tx_ring);
 542         rte_free(txq);
 543 }
 544
 545 void qede_tx_queue_release(void *tx_queue)
 546 {
 547         struct qede_tx_queue *txq = tx_queue;
 548         struct qede_fastpath_cmt *fp_cmt;
 549         struct qede_dev *qdev;
 550         struct ecore_dev *edev;
 551
 552         if (txq) {
 553                 qdev = txq->qdev;
 554                 edev = QEDE_INIT_EDEV(qdev);
 555                 PMD_INIT_FUNC_TRACE(edev);
 556
 557                 if (ECORE_IS_CMT(edev)) {
 558                         fp_cmt = tx_queue;
 559                         _qede_tx_queue_release(qdev, edev, fp_cmt->fp0->txq);
 560                         _qede_tx_queue_release(qdev, edev, fp_cmt->fp1->txq);
 561                 } else {
 562                         _qede_tx_queue_release(qdev, edev, txq);
 563                 }
 564         }
 565 }
 566
 567 /* This function allocates fast-path status block memory */
 568 static int
 569 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
 570                   uint16_t sb_id)
 571 {
 572         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 573         struct status_block *sb_virt;
 574         dma_addr_t sb_phys;
 575         int rc;
 576
 577         sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys,
 578                                           sizeof(struct status_block));
 579         if (!sb_virt) {
 580                 DP_ERR(edev, "Status block allocation failed\n");
 581                 return -ENOMEM;
 582         }
 583         rc = qdev->ops->common->sb_init(edev, sb_info, sb_virt,
 584                                         sb_phys, sb_id);
 585         if (rc) {
 586                 DP_ERR(edev, "Status block initialization failed\n");
 587                 OSAL_DMA_FREE_COHERENT(edev, sb_virt, sb_phys,
 588                                        sizeof(struct status_block));
 589                 return rc;
 590         }
 591
 592         return 0;
 593 }
 594
 595 int qede_alloc_fp_resc(struct qede_dev *qdev)
 596 {
 597         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 598         struct qede_fastpath *fp;
 599         uint32_t num_sbs;
 600         uint16_t sb_idx;
 601         int i;
 602
 603         PMD_INIT_FUNC_TRACE(edev);
 604
 605         if (IS_VF(edev))
 606                 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
 607         else
 608                 num_sbs = ecore_cxt_get_proto_cid_count
 609                           (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL);
 610
 611         if (num_sbs == 0) {
 612                 DP_ERR(edev, "No status blocks available\n");
 613                 return -EINVAL;
 614         }
 615
 616         qdev->fp_array = rte_calloc("fp", QEDE_RXTX_MAX(qdev),
 617                                 sizeof(*qdev->fp_array), RTE_CACHE_LINE_SIZE);
 618
 619         if (!qdev->fp_array) {
 620                 DP_ERR(edev, "fp array allocation failed\n");
 621                 return -ENOMEM;
 622         }
 623
 624         memset((void *)qdev->fp_array, 0, QEDE_RXTX_MAX(qdev) *
 625                         sizeof(*qdev->fp_array));
 626
 627         if (ECORE_IS_CMT(edev)) {
 628                 qdev->fp_array_cmt = rte_calloc("fp_cmt",
 629                                                 QEDE_RXTX_MAX(qdev) / 2,
 630                                                 sizeof(*qdev->fp_array_cmt),
 631                                                 RTE_CACHE_LINE_SIZE);
 632
 633                 if (!qdev->fp_array_cmt) {
 634                         DP_ERR(edev, "fp array for CMT allocation failed\n");
 635                         return -ENOMEM;
 636                 }
 637
 638                 memset((void *)qdev->fp_array_cmt, 0,
 639                        (QEDE_RXTX_MAX(qdev) / 2) * sizeof(*qdev->fp_array_cmt));
 640
 641                 /* Establish the mapping of fp_array with fp_array_cmt */
 642                 for (i = 0; i < QEDE_RXTX_MAX(qdev) / 2; i++) {
 643                         qdev->fp_array_cmt[i].qdev = qdev;
 644                         qdev->fp_array_cmt[i].fp0 = &qdev->fp_array[i * 2];
 645                         qdev->fp_array_cmt[i].fp1 = &qdev->fp_array[i * 2 + 1];
 646                 }
 647         }
 648
 649         for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
 650                 fp = &qdev->fp_array[sb_idx];
 651                 fp->sb_info = rte_calloc("sb", 1, sizeof(struct ecore_sb_info),
 652                                 RTE_CACHE_LINE_SIZE);
 653                 if (!fp->sb_info) {
 654                         DP_ERR(edev, "FP sb_info allocation fails\n");
 655                         return -1;
 656                 }
 657                 if (qede_alloc_mem_sb(qdev, fp->sb_info, sb_idx)) {
 658                         DP_ERR(edev, "FP status block allocation fails\n");
 659                         return -1;
 660                 }
 661                 DP_INFO(edev, "sb_info idx 0x%x initialized\n",
 662                                 fp->sb_info->igu_sb_id);
 663         }
 664
 665         return 0;
 666 }
 667
 668 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
 669 {
 670         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 671         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 672         struct qede_fastpath *fp;
 673         uint16_t sb_idx;
 674         uint8_t i;
 675
 676         PMD_INIT_FUNC_TRACE(edev);
 677
 678         for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
 679                 fp = &qdev->fp_array[sb_idx];
 680                 if (fp->sb_info) {
 681                         DP_INFO(edev, "Free sb_info index 0x%x\n",
 682                                         fp->sb_info->igu_sb_id);
 683                         OSAL_DMA_FREE_COHERENT(edev, fp->sb_info->sb_virt,
 684                                 fp->sb_info->sb_phys,
 685                                 sizeof(struct status_block));
 686                         rte_free(fp->sb_info);
 687                         fp->sb_info = NULL;
 688                 }
 689         }
 690
 691         /* Free packet buffers and ring memories */
 692         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 693                 if (eth_dev->data->rx_queues[i]) {
 694                         qede_rx_queue_release(eth_dev->data->rx_queues[i]);
 695                         eth_dev->data->rx_queues[i] = NULL;
 696                 }
 697         }
 698
 699         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
 700                 if (eth_dev->data->tx_queues[i]) {
 701                         qede_tx_queue_release(eth_dev->data->tx_queues[i]);
 702                         eth_dev->data->tx_queues[i] = NULL;
 703                 }
 704         }
 705
 706         if (qdev->fp_array)
 707                 rte_free(qdev->fp_array);
 708         qdev->fp_array = NULL;
 709
 710         if (qdev->fp_array_cmt)
 711                 rte_free(qdev->fp_array_cmt);
 712         qdev->fp_array_cmt = NULL;
 713 }
 714
 715 static inline void
 716 qede_update_rx_prod(__rte_unused struct qede_dev *edev,
 717                     struct qede_rx_queue *rxq)
 718 {
 719         uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
 720         uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
 721         struct eth_rx_prod_data rx_prods = { 0 };
 722
 723         /* Update producers */
 724         rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
 725         rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
 726
 727         /* Make sure that the BD and SGE data is updated before updating the
 728          * producers since FW might read the BD/SGE right after the producer
 729          * is updated.
 730          */
 731         rte_wmb();
 732
 733         internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
 734                         (uint32_t *)&rx_prods);
 735
 736         /* mmiowb is needed to synchronize doorbell writes from more than one
 737          * processor. It guarantees that the write arrives to the device before
 738          * the napi lock is released and another qede_poll is called (possibly
 739          * on another CPU). Without this barrier, the next doorbell can bypass
 740          * this doorbell. This is applicable to IA64/Altix systems.
 741          */
 742         rte_wmb();
 743
 744         PMD_RX_LOG(DEBUG, rxq, "bd_prod %u  cqe_prod %u", bd_prod, cqe_prod);
 745 }
 746
 747 /* Starts a given RX queue in HW */
 748 static int
 749 qede_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 750 {
 751         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 752         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 753         struct ecore_queue_start_common_params params;
 754         struct ecore_rxq_start_ret_params ret_params;
 755         struct qede_rx_queue *rxq;
 756         struct qede_fastpath *fp;
 757         struct ecore_hwfn *p_hwfn;
 758         dma_addr_t p_phys_table;
 759         uint16_t page_cnt;
 760         uint16_t j;
 761         int hwfn_index;
 762         int rc;
 763
 764         if (rx_queue_id < qdev->num_rx_queues) {
 765                 fp = &qdev->fp_array[rx_queue_id];
 766                 rxq = fp->rxq;
 767                 /* Allocate buffers for the Rx ring */
 768                 for (j = 0; j < rxq->nb_rx_desc; j++) {
 769                         rc = qede_alloc_rx_buffer(rxq);
 770                         if (rc) {
 771                                 DP_ERR(edev, "RX buffer allocation failed"
 772                                                 " for rxq = %u\n", rx_queue_id);
 773                                 return -ENOMEM;
 774                         }
 775                 }
 776                 /* disable interrupts */
 777                 ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
 778                 /* Prepare ramrod */
 779                 memset(&params, 0, sizeof(params));
 780                 params.queue_id = rx_queue_id / edev->num_hwfns;
 781                 params.vport_id = 0;
 782                 params.stats_id = params.vport_id;
 783                 params.p_sb = fp->sb_info;
 784                 DP_INFO(edev, "rxq %u igu_sb_id 0x%x\n",
 785                                 fp->rxq->queue_id, fp->sb_info->igu_sb_id);
 786                 params.sb_idx = RX_PI;
 787                 hwfn_index = rx_queue_id % edev->num_hwfns;
 788                 p_hwfn = &edev->hwfns[hwfn_index];
 789                 p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->rx_comp_ring);
 790                 page_cnt = ecore_chain_get_page_cnt(&fp->rxq->rx_comp_ring);
 791                 memset(&ret_params, 0, sizeof(ret_params));
 792                 rc = ecore_eth_rx_queue_start(p_hwfn,
 793                                 p_hwfn->hw_info.opaque_fid,
 794                                 &params, fp->rxq->rx_buf_size,
 795                                 fp->rxq->rx_bd_ring.p_phys_addr,
 796                                 p_phys_table, page_cnt,
 797                                 &ret_params);
 798                 if (rc) {
 799                         DP_ERR(edev, "RX queue %u could not be started, rc = %d\n",
 800                                         rx_queue_id, rc);
 801                         return -1;
 802                 }
 803                 /* Update with the returned parameters */
 804                 fp->rxq->hw_rxq_prod_addr = ret_params.p_prod;
 805                 fp->rxq->handle = ret_params.p_handle;
 806
 807                 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_pi_array[RX_PI];
 808                 qede_update_rx_prod(qdev, fp->rxq);
 809                 eth_dev->data->rx_queue_state[rx_queue_id] =
 810                         RTE_ETH_QUEUE_STATE_STARTED;
 811                 DP_INFO(edev, "RX queue %u started\n", rx_queue_id);
 812         } else {
 813                 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
 814                 rc = -EINVAL;
 815         }
 816
 817         return rc;
 818 }
 819
 820 static int
 821 qede_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 822 {
 823         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 824         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 825         struct ecore_queue_start_common_params params;
 826         struct ecore_txq_start_ret_params ret_params;
 827         struct ecore_hwfn *p_hwfn;
 828         dma_addr_t p_phys_table;
 829         struct qede_tx_queue *txq;
 830         struct qede_fastpath *fp;
 831         uint16_t page_cnt;
 832         int hwfn_index;
 833         int rc;
 834
 835         if (tx_queue_id < qdev->num_tx_queues) {
 836                 fp = &qdev->fp_array[tx_queue_id];
 837                 txq = fp->txq;
 838                 memset(&params, 0, sizeof(params));
 839                 params.queue_id = tx_queue_id / edev->num_hwfns;
 840                 params.vport_id = 0;
 841                 params.stats_id = params.vport_id;
 842                 params.p_sb = fp->sb_info;
 843                 DP_INFO(edev, "txq %u igu_sb_id 0x%x\n",
 844                                 fp->txq->queue_id, fp->sb_info->igu_sb_id);
 845                 params.sb_idx = TX_PI(0); /* tc = 0 */
 846                 p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
 847                 page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
 848                 hwfn_index = tx_queue_id % edev->num_hwfns;
 849                 p_hwfn = &edev->hwfns[hwfn_index];
 850                 if (qdev->dev_info.is_legacy)
 851                         fp->txq->is_legacy = true;
 852                 rc = ecore_eth_tx_queue_start(p_hwfn,
 853                                 p_hwfn->hw_info.opaque_fid,
 854                                 &params, 0 /* tc */,
 855                                 p_phys_table, page_cnt,
 856                                 &ret_params);
 857                 if (rc != ECORE_SUCCESS) {
 858                         DP_ERR(edev, "TX queue %u couldn't be started, rc=%d\n",
 859                                         tx_queue_id, rc);
 860                         return -1;
 861                 }
 862                 txq->doorbell_addr = ret_params.p_doorbell;
 863                 txq->handle = ret_params.p_handle;
 864
 865                 txq->hw_cons_ptr = &fp->sb_info->sb_pi_array[TX_PI(0)];
 866                 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_DEST,
 867                                 DB_DEST_XCM);
 868                 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
 869                                 DB_AGG_CMD_SET);
 870                 SET_FIELD(txq->tx_db.data.params,
 871                                 ETH_DB_DATA_AGG_VAL_SEL,
 872                                 DQ_XCM_ETH_TX_BD_PROD_CMD);
 873                 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
 874                 eth_dev->data->tx_queue_state[tx_queue_id] =
 875                         RTE_ETH_QUEUE_STATE_STARTED;
 876                 DP_INFO(edev, "TX queue %u started\n", tx_queue_id);
 877         } else {
 878                 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
 879                 rc = -EINVAL;
 880         }
 881
 882         return rc;
 883 }
 884
 885 static inline void
 886 qede_process_tx_compl(__rte_unused struct ecore_dev *edev,
 887                       struct qede_tx_queue *txq)
 888 {
 889         uint16_t hw_bd_cons;
 890         uint16_t sw_tx_cons;
 891         uint16_t remaining;
 892         uint16_t mask;
 893         struct rte_mbuf *mbuf;
 894         uint16_t nb_segs;
 895         uint16_t idx;
 896
 897         rte_compiler_barrier();
 898         sw_tx_cons = ecore_chain_get_cons_idx(&txq->tx_pbl);
 899         hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
 900 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
 901         PMD_TX_LOG(DEBUG, txq, "Tx Completions = %u\n",
 902                    abs(hw_bd_cons - sw_tx_cons));
 903 #endif
 904
 905         mask = NUM_TX_BDS(txq);
 906         idx = txq->sw_tx_cons & mask;
 907
 908         remaining = hw_bd_cons - sw_tx_cons;
 909         txq->nb_tx_avail += remaining;
 910
 911         while (remaining) {
 912                 mbuf = txq->sw_tx_ring[idx];
 913                 RTE_ASSERT(mbuf);
 914                 nb_segs = mbuf->nb_segs;
 915                 remaining -= nb_segs;
 916
 917                 PMD_TX_LOG(DEBUG, txq, "nb_segs to free %u\n", nb_segs);
 918
 919                 while (nb_segs) {
 920                         ecore_chain_consume(&txq->tx_pbl);
 921                         nb_segs--;
 922                 }
 923
 924                 rte_pktmbuf_free(mbuf);
 925                 idx = (idx + 1) & mask;
 926                 PMD_TX_LOG(DEBUG, txq, "Freed tx packet\n");
 927         }
 928         txq->sw_tx_cons = idx;
 929 }
 930
 931 static int qede_drain_txq(struct qede_dev *qdev,
 932                           struct qede_tx_queue *txq, bool allow_drain)
 933 {
 934         struct ecore_dev *edev = &qdev->edev;
 935         int rc, cnt = 1000;
 936
 937         while (txq->sw_tx_cons != txq->sw_tx_prod) {
 938                 qede_process_tx_compl(edev, txq);
 939                 if (!cnt) {
 940                         if (allow_drain) {
 941                                 DP_ERR(edev, "Tx queue[%u] is stuck,"
 942                                           "requesting MCP to drain\n",
 943                                           txq->queue_id);
 944                                 rc = qdev->ops->common->drain(edev);
 945                                 if (rc)
 946                                         return rc;
 947                                 return qede_drain_txq(qdev, txq, false);
 948                         }
 949                         DP_ERR(edev, "Timeout waiting for tx queue[%d]:"
 950                                   "PROD=%d, CONS=%d\n",
 951                                   txq->queue_id, txq->sw_tx_prod,
 952                                   txq->sw_tx_cons);
 953                         return -1;
 954                 }
 955                 cnt--;
 956                 DELAY(1000);
 957                 rte_compiler_barrier();
 958         }
 959
 960         /* FW finished processing, wait for HW to transmit all tx packets */
 961         DELAY(2000);
 962
 963         return 0;
 964 }
 965
 966 /* Stops a given TX queue in the HW */
 967 static int qede_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 968 {
 969         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 970         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 971         struct ecore_hwfn *p_hwfn;
 972         struct qede_tx_queue *txq;
 973         int hwfn_index;
 974         int rc;
 975
 976         if (tx_queue_id < qdev->num_tx_queues) {
 977                 txq = qdev->fp_array[tx_queue_id].txq;
 978                 /* Drain txq */
 979                 if (qede_drain_txq(qdev, txq, true))
 980                         return -1; /* For the lack of retcodes */
 981                 /* Stop txq */
 982                 hwfn_index = tx_queue_id % edev->num_hwfns;
 983                 p_hwfn = &edev->hwfns[hwfn_index];
 984                 rc = ecore_eth_tx_queue_stop(p_hwfn, txq->handle);
 985                 if (rc != ECORE_SUCCESS) {
 986                         DP_ERR(edev, "TX queue %u stop fails\n", tx_queue_id);
 987                         return -1;
 988                 }
 989                 qede_tx_queue_release_mbufs(txq);
 990                 qede_tx_queue_reset(qdev, txq);
 991                 eth_dev->data->tx_queue_state[tx_queue_id] =
 992                         RTE_ETH_QUEUE_STATE_STOPPED;
 993                 DP_INFO(edev, "TX queue %u stopped\n", tx_queue_id);
 994         } else {
 995                 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
 996                 rc = -EINVAL;
 997         }
 998
 999         return rc;
1000 }
1001
1002 int qede_start_queues(struct rte_eth_dev *eth_dev)
1003 {
1004         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1005         uint8_t id;
1006         int rc = -1;
1007
1008         for (id = 0; id < qdev->num_rx_queues; id++) {
1009                 rc = qede_rx_queue_start(eth_dev, id);
1010                 if (rc != ECORE_SUCCESS)
1011                         return -1;
1012         }
1013
1014         for (id = 0; id < qdev->num_tx_queues; id++) {
1015                 rc = qede_tx_queue_start(eth_dev, id);
1016                 if (rc != ECORE_SUCCESS)
1017                         return -1;
1018         }
1019
1020         return rc;
1021 }
1022
1023 void qede_stop_queues(struct rte_eth_dev *eth_dev)
1024 {
1025         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1026         uint8_t id;
1027
1028         /* Stopping RX/TX queues */
1029         for (id = 0; id < qdev->num_tx_queues; id++)
1030                 qede_tx_queue_stop(eth_dev, id);
1031
1032         for (id = 0; id < qdev->num_rx_queues; id++)
1033                 qede_rx_queue_stop(eth_dev, id);
1034 }
1035
1036 static inline bool qede_tunn_exist(uint16_t flag)
1037 {
1038         return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
1039                     PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
1040 }
1041
1042 static inline uint8_t qede_check_tunn_csum_l3(uint16_t flag)
1043 {
1044         return !!((PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
1045                 PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT) & flag);
1046 }
1047
1048 /*
1049  * qede_check_tunn_csum_l4:
1050  * Returns:
1051  * 1 : If L4 csum is enabled AND if the validation has failed.
1052  * 0 : Otherwise
1053  */
1054 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
1055 {
1056         if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
1057              PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
1058                 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
1059                         PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
1060
1061         return 0;
1062 }
1063
1064 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
1065 {
1066         if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1067              PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
1068                 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1069                            PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
1070
1071         return 0;
1072 }
1073
1074 /* Returns outer L2, L3 and L4 packet_type for tunneled packets */
1075 static inline uint32_t qede_rx_cqe_to_pkt_type_outer(struct rte_mbuf *m)
1076 {
1077         uint32_t packet_type = RTE_PTYPE_UNKNOWN;
1078         struct rte_ether_hdr *eth_hdr;
1079         struct rte_ipv4_hdr *ipv4_hdr;
1080         struct rte_ipv6_hdr *ipv6_hdr;
1081         struct rte_vlan_hdr *vlan_hdr;
1082         uint16_t ethertype;
1083         bool vlan_tagged = 0;
1084         uint16_t len;
1085
1086         eth_hdr = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
1087         len = sizeof(struct rte_ether_hdr);
1088         ethertype = rte_cpu_to_be_16(eth_hdr->ether_type);
1089
1090          /* Note: Valid only if VLAN stripping is disabled */
1091         if (ethertype == RTE_ETHER_TYPE_VLAN) {
1092                 vlan_tagged = 1;
1093                 vlan_hdr = (struct rte_vlan_hdr *)(eth_hdr + 1);
1094                 len += sizeof(struct rte_vlan_hdr);
1095                 ethertype = rte_cpu_to_be_16(vlan_hdr->eth_proto);
1096         }
1097
1098         if (ethertype == RTE_ETHER_TYPE_IPV4) {
1099                 packet_type |= RTE_PTYPE_L3_IPV4;
1100                 ipv4_hdr = rte_pktmbuf_mtod_offset(m,
1101                                         struct rte_ipv4_hdr *, len);
1102                 if (ipv4_hdr->next_proto_id == IPPROTO_TCP)
1103                         packet_type |= RTE_PTYPE_L4_TCP;
1104                 else if (ipv4_hdr->next_proto_id == IPPROTO_UDP)
1105                         packet_type |= RTE_PTYPE_L4_UDP;
1106         } else if (ethertype == RTE_ETHER_TYPE_IPV6) {
1107                 packet_type |= RTE_PTYPE_L3_IPV6;
1108                 ipv6_hdr = rte_pktmbuf_mtod_offset(m,
1109                                                 struct rte_ipv6_hdr *, len);
1110                 if (ipv6_hdr->proto == IPPROTO_TCP)
1111                         packet_type |= RTE_PTYPE_L4_TCP;
1112                 else if (ipv6_hdr->proto == IPPROTO_UDP)
1113                         packet_type |= RTE_PTYPE_L4_UDP;
1114         }
1115
1116         if (vlan_tagged)
1117                 packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
1118         else
1119                 packet_type |= RTE_PTYPE_L2_ETHER;
1120
1121         return packet_type;
1122 }
1123
1124 static inline uint32_t qede_rx_cqe_to_pkt_type_inner(uint16_t flags)
1125 {
1126         uint16_t val;
1127
1128         /* Lookup table */
1129         static const uint32_t
1130         ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
1131                 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_INNER_L3_IPV4          |
1132                                        RTE_PTYPE_INNER_L2_ETHER,
1133                 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_INNER_L3_IPV6          |
1134                                        RTE_PTYPE_INNER_L2_ETHER,
1135                 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_INNER_L3_IPV4      |
1136                                            RTE_PTYPE_INNER_L4_TCP       |
1137                                            RTE_PTYPE_INNER_L2_ETHER,
1138                 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_INNER_L3_IPV6      |
1139                                            RTE_PTYPE_INNER_L4_TCP       |
1140                                            RTE_PTYPE_INNER_L2_ETHER,
1141                 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_INNER_L3_IPV4      |
1142                                            RTE_PTYPE_INNER_L4_UDP       |
1143                                            RTE_PTYPE_INNER_L2_ETHER,
1144                 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_INNER_L3_IPV6      |
1145                                            RTE_PTYPE_INNER_L4_UDP       |
1146                                            RTE_PTYPE_INNER_L2_ETHER,
1147                 /* Frags with no VLAN */
1148                 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_INNER_L3_IPV4     |
1149                                             RTE_PTYPE_INNER_L4_FRAG     |
1150                                             RTE_PTYPE_INNER_L2_ETHER,
1151                 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_INNER_L3_IPV6     |
1152                                             RTE_PTYPE_INNER_L4_FRAG     |
1153                                             RTE_PTYPE_INNER_L2_ETHER,
1154                 /* VLANs */
1155                 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_INNER_L3_IPV4     |
1156                                             RTE_PTYPE_INNER_L2_ETHER_VLAN,
1157                 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_INNER_L3_IPV6     |
1158                                             RTE_PTYPE_INNER_L2_ETHER_VLAN,
1159                 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
1160                                                 RTE_PTYPE_INNER_L4_TCP  |
1161                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1162                 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
1163                                                 RTE_PTYPE_INNER_L4_TCP  |
1164                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1165                 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
1166                                                 RTE_PTYPE_INNER_L4_UDP  |
1167                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1168                 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
1169                                                 RTE_PTYPE_INNER_L4_UDP  |
1170                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1171                 /* Frags with VLAN */
1172                 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV4 |
1173                                                  RTE_PTYPE_INNER_L4_FRAG |
1174                                                  RTE_PTYPE_INNER_L2_ETHER_VLAN,
1175                 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV6 |
1176                                                  RTE_PTYPE_INNER_L4_FRAG |
1177                                                  RTE_PTYPE_INNER_L2_ETHER_VLAN,
1178         };
1179
1180         /* Bits (0..3) provides L3/L4 protocol type */
1181         /* Bits (4,5) provides frag and VLAN info */
1182         val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
1183                PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
1184                (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
1185                 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) |
1186                (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1187                 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) |
1188                 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK <<
1189                  PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags;
1190
1191         if (val < QEDE_PKT_TYPE_MAX)
1192                 return ptype_lkup_tbl[val];
1193
1194         return RTE_PTYPE_UNKNOWN;
1195 }
1196
1197 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
1198 {
1199         uint16_t val;
1200
1201         /* Lookup table */
1202         static const uint32_t
1203         ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
1204                 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L2_ETHER,
1205                 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L2_ETHER,
1206                 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4    |
1207                                            RTE_PTYPE_L4_TCP     |
1208                                            RTE_PTYPE_L2_ETHER,
1209                 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6    |
1210                                            RTE_PTYPE_L4_TCP     |
1211                                            RTE_PTYPE_L2_ETHER,
1212                 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4    |
1213                                            RTE_PTYPE_L4_UDP     |
1214                                            RTE_PTYPE_L2_ETHER,
1215                 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6    |
1216                                            RTE_PTYPE_L4_UDP     |
1217                                            RTE_PTYPE_L2_ETHER,
1218                 /* Frags with no VLAN */
1219                 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_L3_IPV4   |
1220                                             RTE_PTYPE_L4_FRAG   |
1221                                             RTE_PTYPE_L2_ETHER,
1222                 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_L3_IPV6   |
1223                                             RTE_PTYPE_L4_FRAG   |
1224                                             RTE_PTYPE_L2_ETHER,
1225                 /* VLANs */
1226                 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_L3_IPV4           |
1227                                             RTE_PTYPE_L2_ETHER_VLAN,
1228                 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_L3_IPV6           |
1229                                             RTE_PTYPE_L2_ETHER_VLAN,
1230                 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_L3_IPV4       |
1231                                                 RTE_PTYPE_L4_TCP        |
1232                                                 RTE_PTYPE_L2_ETHER_VLAN,
1233                 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_L3_IPV6       |
1234                                                 RTE_PTYPE_L4_TCP        |
1235                                                 RTE_PTYPE_L2_ETHER_VLAN,
1236                 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_L3_IPV4       |
1237                                                 RTE_PTYPE_L4_UDP        |
1238                                                 RTE_PTYPE_L2_ETHER_VLAN,
1239                 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_L3_IPV6       |
1240                                                 RTE_PTYPE_L4_UDP        |
1241                                                 RTE_PTYPE_L2_ETHER_VLAN,
1242                 /* Frags with VLAN */
1243                 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_L3_IPV4      |
1244                                                  RTE_PTYPE_L4_FRAG      |
1245                                                  RTE_PTYPE_L2_ETHER_VLAN,
1246                 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_L3_IPV6      |
1247                                                  RTE_PTYPE_L4_FRAG      |
1248                                                  RTE_PTYPE_L2_ETHER_VLAN,
1249         };
1250
1251         /* Bits (0..3) provides L3/L4 protocol type */
1252         /* Bits (4,5) provides frag and VLAN info */
1253         val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
1254                PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
1255                (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
1256                 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) |
1257                (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1258                 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) |
1259                 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK <<
1260                  PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags;
1261
1262         if (val < QEDE_PKT_TYPE_MAX)
1263                 return ptype_lkup_tbl[val];
1264
1265         return RTE_PTYPE_UNKNOWN;
1266 }
1267
1268 static inline uint8_t
1269 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
1270 {
1271         struct rte_ipv4_hdr *ip;
1272         uint16_t pkt_csum;
1273         uint16_t calc_csum;
1274         uint16_t val;
1275
1276         val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1277                 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
1278
1279         if (unlikely(val)) {
1280                 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
1281                 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
1282                         ip = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
1283                                            sizeof(struct rte_ether_hdr));
1284                         pkt_csum = ip->hdr_checksum;
1285                         ip->hdr_checksum = 0;
1286                         calc_csum = rte_ipv4_cksum(ip);
1287                         ip->hdr_checksum = pkt_csum;
1288                         return (calc_csum != pkt_csum);
1289                 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
1290                         return 1;
1291                 }
1292         }
1293         return 0;
1294 }
1295
1296 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
1297 {
1298         ecore_chain_consume(&rxq->rx_bd_ring);
1299         rxq->sw_rx_cons++;
1300 }
1301
1302 static inline void
1303 qede_reuse_page(__rte_unused struct qede_dev *qdev,
1304                 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
1305 {
1306         struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
1307         uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
1308         struct qede_rx_entry *curr_prod;
1309         dma_addr_t new_mapping;
1310
1311         curr_prod = &rxq->sw_rx_ring[idx];
1312         *curr_prod = *curr_cons;
1313
1314         new_mapping = rte_mbuf_data_iova_default(curr_prod->mbuf) +
1315                       curr_prod->page_offset;
1316
1317         rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
1318         rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
1319
1320         rxq->sw_rx_prod++;
1321 }
1322
1323 static inline void
1324 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
1325                         struct qede_dev *qdev, uint8_t count)
1326 {
1327         struct qede_rx_entry *curr_cons;
1328
1329         for (; count > 0; count--) {
1330                 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
1331                 qede_reuse_page(qdev, rxq, curr_cons);
1332                 qede_rx_bd_ring_consume(rxq);
1333         }
1334 }
1335
1336 static inline void
1337 qede_rx_process_tpa_cmn_cont_end_cqe(__rte_unused struct qede_dev *qdev,
1338                                      struct qede_rx_queue *rxq,
1339                                      uint8_t agg_index, uint16_t len)
1340 {
1341         struct qede_agg_info *tpa_info;
1342         struct rte_mbuf *curr_frag; /* Pointer to currently filled TPA seg */
1343         uint16_t cons_idx;
1344
1345         /* Under certain conditions it is possible that FW may not consume
1346          * additional or new BD. So decision to consume the BD must be made
1347          * based on len_list[0].
1348          */
1349         if (rte_le_to_cpu_16(len)) {
1350                 tpa_info = &rxq->tpa_info[agg_index];
1351                 cons_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1352                 curr_frag = rxq->sw_rx_ring[cons_idx].mbuf;
1353                 assert(curr_frag);
1354                 curr_frag->nb_segs = 1;
1355                 curr_frag->pkt_len = rte_le_to_cpu_16(len);
1356                 curr_frag->data_len = curr_frag->pkt_len;
1357                 tpa_info->tpa_tail->next = curr_frag;
1358                 tpa_info->tpa_tail = curr_frag;
1359                 qede_rx_bd_ring_consume(rxq);
1360                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1361                         PMD_RX_LOG(ERR, rxq, "mbuf allocation fails\n");
1362                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1363                         rxq->rx_alloc_errors++;
1364                 }
1365         }
1366 }
1367
1368 static inline void
1369 qede_rx_process_tpa_cont_cqe(struct qede_dev *qdev,
1370                              struct qede_rx_queue *rxq,
1371                              struct eth_fast_path_rx_tpa_cont_cqe *cqe)
1372 {
1373         PMD_RX_LOG(INFO, rxq, "TPA cont[%d] - len [%d]\n",
1374                    cqe->tpa_agg_index, rte_le_to_cpu_16(cqe->len_list[0]));
1375         /* only len_list[0] will have value */
1376         qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
1377                                              cqe->len_list[0]);
1378 }
1379
1380 static inline void
1381 qede_rx_process_tpa_end_cqe(struct qede_dev *qdev,
1382                             struct qede_rx_queue *rxq,
1383                             struct eth_fast_path_rx_tpa_end_cqe *cqe)
1384 {
1385         struct rte_mbuf *rx_mb; /* Pointer to head of the chained agg */
1386
1387         qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
1388                                              cqe->len_list[0]);
1389         /* Update total length and frags based on end TPA */
1390         rx_mb = rxq->tpa_info[cqe->tpa_agg_index].tpa_head;
1391         /* TODO:  Add Sanity Checks */
1392         rx_mb->nb_segs = cqe->num_of_bds;
1393         rx_mb->pkt_len = cqe->total_packet_len;
1394
1395         PMD_RX_LOG(INFO, rxq, "TPA End[%d] reason %d cqe_len %d nb_segs %d"
1396                    " pkt_len %d\n", cqe->tpa_agg_index, cqe->end_reason,
1397                    rte_le_to_cpu_16(cqe->len_list[0]), rx_mb->nb_segs,
1398                    rx_mb->pkt_len);
1399 }
1400
1401 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
1402 {
1403         uint32_t val;
1404
1405         /* Lookup table */
1406         static const uint32_t
1407         ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
1408                 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
1409                 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
1410                 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
1411                 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
1412                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
1413                                 RTE_PTYPE_TUNNEL_GENEVE,
1414                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
1415                                 RTE_PTYPE_TUNNEL_GRE,
1416                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
1417                                 RTE_PTYPE_TUNNEL_VXLAN,
1418                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
1419                                 RTE_PTYPE_TUNNEL_GENEVE,
1420                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
1421                                 RTE_PTYPE_TUNNEL_GRE,
1422                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
1423                                 RTE_PTYPE_TUNNEL_VXLAN,
1424                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
1425                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1426                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
1427                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1428                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
1429                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1430                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
1431                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1432                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
1433                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1434                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
1435                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1436                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
1437                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1438                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
1439                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1440                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
1441                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1442                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
1443                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1444                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
1445                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1446                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
1447                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1448         };
1449
1450         /* Cover bits[4-0] to include tunn_type and next protocol */
1451         val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
1452                 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
1453                 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
1454                 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
1455
1456         if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
1457                 return ptype_tunn_lkup_tbl[val];
1458         else
1459                 return RTE_PTYPE_UNKNOWN;
1460 }
1461
1462 static inline int
1463 qede_process_sg_pkts(void *p_rxq,  struct rte_mbuf *rx_mb,
1464                      uint8_t num_segs, uint16_t pkt_len)
1465 {
1466         struct qede_rx_queue *rxq = p_rxq;
1467         struct qede_dev *qdev = rxq->qdev;
1468         register struct rte_mbuf *seg1 = NULL;
1469         register struct rte_mbuf *seg2 = NULL;
1470         uint16_t sw_rx_index;
1471         uint16_t cur_size;
1472
1473         seg1 = rx_mb;
1474         while (num_segs) {
1475                 cur_size = pkt_len > rxq->rx_buf_size ? rxq->rx_buf_size :
1476                                                         pkt_len;
1477                 if (unlikely(!cur_size)) {
1478                         PMD_RX_LOG(ERR, rxq, "Length is 0 while %u BDs"
1479                                    " left for mapping jumbo\n", num_segs);
1480                         qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
1481                         return -EINVAL;
1482                 }
1483                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1484                 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
1485                 qede_rx_bd_ring_consume(rxq);
1486                 pkt_len -= cur_size;
1487                 seg2->data_len = cur_size;
1488                 seg1->next = seg2;
1489                 seg1 = seg1->next;
1490                 num_segs--;
1491                 rxq->rx_segs++;
1492         }
1493
1494         return 0;
1495 }
1496
1497 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1498 static inline void
1499 print_rx_bd_info(struct rte_mbuf *m, struct qede_rx_queue *rxq,
1500                  uint8_t bitfield)
1501 {
1502         PMD_RX_LOG(INFO, rxq,
1503                 "len 0x%04x bf 0x%04x hash_val 0x%x"
1504                 " ol_flags 0x%04lx l2=%s l3=%s l4=%s tunn=%s"
1505                 " inner_l2=%s inner_l3=%s inner_l4=%s\n",
1506                 m->data_len, bitfield, m->hash.rss,
1507                 (unsigned long)m->ol_flags,
1508                 rte_get_ptype_l2_name(m->packet_type),
1509                 rte_get_ptype_l3_name(m->packet_type),
1510                 rte_get_ptype_l4_name(m->packet_type),
1511                 rte_get_ptype_tunnel_name(m->packet_type),
1512                 rte_get_ptype_inner_l2_name(m->packet_type),
1513                 rte_get_ptype_inner_l3_name(m->packet_type),
1514                 rte_get_ptype_inner_l4_name(m->packet_type));
1515 }
1516 #endif
1517
1518 uint16_t
1519 qede_recv_pkts_regular(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1520 {
1521         struct eth_fast_path_rx_reg_cqe *fp_cqe = NULL;
1522         register struct rte_mbuf *rx_mb = NULL;
1523         struct qede_rx_queue *rxq = p_rxq;
1524         struct qede_dev *qdev = rxq->qdev;
1525         struct ecore_dev *edev = &qdev->edev;
1526         union eth_rx_cqe *cqe;
1527         uint64_t ol_flags;
1528         enum eth_rx_cqe_type cqe_type;
1529         int rss_enable = qdev->rss_enable;
1530         int rx_alloc_count = 0;
1531         uint32_t packet_type;
1532         uint32_t rss_hash;
1533         uint16_t vlan_tci, port_id;
1534         uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index, num_rx_bds;
1535         uint16_t rx_pkt = 0;
1536         uint16_t pkt_len = 0;
1537         uint16_t len; /* Length of first BD */
1538         uint16_t preload_idx;
1539         uint16_t parse_flag;
1540 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1541         uint8_t bitfield_val;
1542 #endif
1543         uint8_t offset, flags, bd_num;
1544
1545
1546         /* Allocate buffers that we used in previous loop */
1547         if (rxq->rx_alloc_count) {
1548                 if (unlikely(qede_alloc_rx_bulk_mbufs(rxq,
1549                              rxq->rx_alloc_count))) {
1550                         struct rte_eth_dev *dev;
1551
1552                         PMD_RX_LOG(ERR, rxq,
1553                                    "New buffer allocation failed,"
1554                                    "dropping incoming packetn");
1555                         dev = &rte_eth_devices[rxq->port_id];
1556                         dev->data->rx_mbuf_alloc_failed +=
1557                                                         rxq->rx_alloc_count;
1558                         rxq->rx_alloc_errors += rxq->rx_alloc_count;
1559                         return 0;
1560                 }
1561                 qede_update_rx_prod(qdev, rxq);
1562                 rxq->rx_alloc_count = 0;
1563         }
1564
1565         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
1566         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1567
1568         rte_rmb();
1569
1570         if (hw_comp_cons == sw_comp_cons)
1571                 return 0;
1572
1573         num_rx_bds =  NUM_RX_BDS(rxq);
1574         port_id = rxq->port_id;
1575
1576         while (sw_comp_cons != hw_comp_cons) {
1577                 ol_flags = 0;
1578                 packet_type = RTE_PTYPE_UNKNOWN;
1579                 vlan_tci = 0;
1580                 rss_hash = 0;
1581
1582                 /* Get the CQE from the completion ring */
1583                 cqe =
1584                     (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
1585                 cqe_type = cqe->fast_path_regular.type;
1586                 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type);
1587
1588                 if (likely(cqe_type == ETH_RX_CQE_TYPE_REGULAR)) {
1589                         fp_cqe = &cqe->fast_path_regular;
1590                 } else {
1591                         if (cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH) {
1592                                 PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n");
1593                                 ecore_eth_cqe_completion
1594                                         (&edev->hwfns[rxq->queue_id %
1595                                                       edev->num_hwfns],
1596                                          (struct eth_slow_path_rx_cqe *)cqe);
1597                         }
1598                         goto next_cqe;
1599                 }
1600
1601                 /* Get the data from the SW ring */
1602                 sw_rx_index = rxq->sw_rx_cons & num_rx_bds;
1603                 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
1604                 assert(rx_mb != NULL);
1605
1606                 parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);
1607                 offset = fp_cqe->placement_offset;
1608                 len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
1609                 pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1610                 vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1611                 rss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash);
1612                 bd_num = fp_cqe->bd_num;
1613 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1614                 bitfield_val = fp_cqe->bitfields;
1615 #endif
1616
1617                 if (unlikely(qede_tunn_exist(parse_flag))) {
1618                         PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n");
1619                         if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1620                                 PMD_RX_LOG(ERR, rxq,
1621                                             "L4 csum failed, flags = 0x%x\n",
1622                                             parse_flag);
1623                                 rxq->rx_hw_errors++;
1624                                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1625                         } else {
1626                                 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1627                         }
1628
1629                         if (unlikely(qede_check_tunn_csum_l3(parse_flag))) {
1630                                 PMD_RX_LOG(ERR, rxq,
1631                                         "Outer L3 csum failed, flags = 0x%x\n",
1632                                         parse_flag);
1633                                 rxq->rx_hw_errors++;
1634                                 ol_flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
1635                         } else {
1636                                 ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1637                         }
1638
1639                         flags = fp_cqe->tunnel_pars_flags.flags;
1640
1641                         /* Tunnel_type */
1642                         packet_type =
1643                                 qede_rx_cqe_to_tunn_pkt_type(flags);
1644
1645                         /* Inner header */
1646                         packet_type |=
1647                               qede_rx_cqe_to_pkt_type_inner(parse_flag);
1648
1649                         /* Outer L3/L4 types is not available in CQE */
1650                         packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1651
1652                         /* Outer L3/L4 types is not available in CQE.
1653                          * Need to add offset to parse correctly,
1654                          */
1655                         rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1656                         packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1657                 } else {
1658                         packet_type |= qede_rx_cqe_to_pkt_type(parse_flag);
1659                 }
1660
1661                 /* Common handling for non-tunnel packets and for inner
1662                  * headers in the case of tunnel.
1663                  */
1664                 if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1665                         PMD_RX_LOG(ERR, rxq,
1666                                     "L4 csum failed, flags = 0x%x\n",
1667                                     parse_flag);
1668                         rxq->rx_hw_errors++;
1669                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
1670                 } else {
1671                         ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1672                 }
1673                 if (unlikely(qede_check_notunn_csum_l3(rx_mb, parse_flag))) {
1674                         PMD_RX_LOG(ERR, rxq, "IP csum failed, flags = 0x%x\n",
1675                                    parse_flag);
1676                         rxq->rx_hw_errors++;
1677                         ol_flags |= PKT_RX_IP_CKSUM_BAD;
1678                 } else {
1679                         ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1680                 }
1681
1682                 if (unlikely(CQE_HAS_VLAN(parse_flag) ||
1683                              CQE_HAS_OUTER_VLAN(parse_flag))) {
1684                         /* Note: FW doesn't indicate Q-in-Q packet */
1685                         ol_flags |= PKT_RX_VLAN;
1686                         if (qdev->vlan_strip_flg) {
1687                                 ol_flags |= PKT_RX_VLAN_STRIPPED;
1688                                 rx_mb->vlan_tci = vlan_tci;
1689                         }
1690                 }
1691
1692                 if (rss_enable) {
1693                         ol_flags |= PKT_RX_RSS_HASH;
1694                         rx_mb->hash.rss = rss_hash;
1695                 }
1696
1697                 rx_alloc_count++;
1698                 qede_rx_bd_ring_consume(rxq);
1699
1700                 /* Prefetch next mbuf while processing current one. */
1701                 preload_idx = rxq->sw_rx_cons & num_rx_bds;
1702                 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1703
1704                 /* Update rest of the MBUF fields */
1705                 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1706                 rx_mb->port = port_id;
1707                 rx_mb->ol_flags = ol_flags;
1708                 rx_mb->data_len = len;
1709                 rx_mb->packet_type = packet_type;
1710 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1711                 print_rx_bd_info(rx_mb, rxq, bitfield_val);
1712 #endif
1713                 rx_mb->nb_segs = bd_num;
1714                 rx_mb->pkt_len = pkt_len;
1715
1716                 rx_pkts[rx_pkt] = rx_mb;
1717                 rx_pkt++;
1718
1719 next_cqe:
1720                 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1721                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1722                 if (rx_pkt == nb_pkts) {
1723                         PMD_RX_LOG(DEBUG, rxq,
1724                                    "Budget reached nb_pkts=%u received=%u",
1725                                    rx_pkt, nb_pkts);
1726                         break;
1727                 }
1728         }
1729
1730         /* Request number of bufferes to be allocated in next loop */
1731         rxq->rx_alloc_count = rx_alloc_count;
1732
1733         rxq->rcv_pkts += rx_pkt;
1734         rxq->rx_segs += rx_pkt;
1735         PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
1736
1737         return rx_pkt;
1738 }
1739
1740 uint16_t
1741 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1742 {
1743         struct qede_rx_queue *rxq = p_rxq;
1744         struct qede_dev *qdev = rxq->qdev;
1745         struct ecore_dev *edev = &qdev->edev;
1746         uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
1747         uint16_t rx_pkt = 0;
1748         union eth_rx_cqe *cqe;
1749         struct eth_fast_path_rx_reg_cqe *fp_cqe = NULL;
1750         register struct rte_mbuf *rx_mb = NULL;
1751         register struct rte_mbuf *seg1 = NULL;
1752         enum eth_rx_cqe_type cqe_type;
1753         uint16_t pkt_len = 0; /* Sum of all BD segments */
1754         uint16_t len; /* Length of first BD */
1755         uint8_t num_segs = 1;
1756         uint16_t preload_idx;
1757         uint16_t parse_flag;
1758 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1759         uint8_t bitfield_val;
1760 #endif
1761         uint8_t tunn_parse_flag;
1762         struct eth_fast_path_rx_tpa_start_cqe *cqe_start_tpa;
1763         uint64_t ol_flags;
1764         uint32_t packet_type;
1765         uint16_t vlan_tci;
1766         bool tpa_start_flg;
1767         uint8_t offset, tpa_agg_idx, flags;
1768         struct qede_agg_info *tpa_info = NULL;
1769         uint32_t rss_hash;
1770         int rx_alloc_count = 0;
1771
1772
1773         /* Allocate buffers that we used in previous loop */
1774         if (rxq->rx_alloc_count) {
1775                 if (unlikely(qede_alloc_rx_bulk_mbufs(rxq,
1776                              rxq->rx_alloc_count))) {
1777                         struct rte_eth_dev *dev;
1778
1779                         PMD_RX_LOG(ERR, rxq,
1780                                    "New buffer allocation failed,"
1781                                    "dropping incoming packetn");
1782                         dev = &rte_eth_devices[rxq->port_id];
1783                         dev->data->rx_mbuf_alloc_failed +=
1784                                                         rxq->rx_alloc_count;
1785                         rxq->rx_alloc_errors += rxq->rx_alloc_count;
1786                         return 0;
1787                 }
1788                 qede_update_rx_prod(qdev, rxq);
1789                 rxq->rx_alloc_count = 0;
1790         }
1791
1792         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
1793         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1794
1795         rte_rmb();
1796
1797         if (hw_comp_cons == sw_comp_cons)
1798                 return 0;
1799
1800         while (sw_comp_cons != hw_comp_cons) {
1801                 ol_flags = 0;
1802                 packet_type = RTE_PTYPE_UNKNOWN;
1803                 vlan_tci = 0;
1804                 tpa_start_flg = false;
1805                 rss_hash = 0;
1806
1807                 /* Get the CQE from the completion ring */
1808                 cqe =
1809                     (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
1810                 cqe_type = cqe->fast_path_regular.type;
1811                 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type);
1812
1813                 switch (cqe_type) {
1814                 case ETH_RX_CQE_TYPE_REGULAR:
1815                         fp_cqe = &cqe->fast_path_regular;
1816                 break;
1817                 case ETH_RX_CQE_TYPE_TPA_START:
1818                         cqe_start_tpa = &cqe->fast_path_tpa_start;
1819                         tpa_info = &rxq->tpa_info[cqe_start_tpa->tpa_agg_index];
1820                         tpa_start_flg = true;
1821                         /* Mark it as LRO packet */
1822                         ol_flags |= PKT_RX_LRO;
1823                         /* In split mode,  seg_len is same as len_on_first_bd
1824                          * and bw_ext_bd_len_list will be empty since there are
1825                          * no additional buffers
1826                          */
1827                         PMD_RX_LOG(INFO, rxq,
1828                          "TPA start[%d] - len_on_first_bd %d header %d"
1829                          " [bd_list[0] %d], [seg_len %d]\n",
1830                          cqe_start_tpa->tpa_agg_index,
1831                          rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd),
1832                          cqe_start_tpa->header_len,
1833                          rte_le_to_cpu_16(cqe_start_tpa->bw_ext_bd_len_list[0]),
1834                          rte_le_to_cpu_16(cqe_start_tpa->seg_len));
1835
1836                 break;
1837                 case ETH_RX_CQE_TYPE_TPA_CONT:
1838                         qede_rx_process_tpa_cont_cqe(qdev, rxq,
1839                                                      &cqe->fast_path_tpa_cont);
1840                         goto next_cqe;
1841                 case ETH_RX_CQE_TYPE_TPA_END:
1842                         qede_rx_process_tpa_end_cqe(qdev, rxq,
1843                                                     &cqe->fast_path_tpa_end);
1844                         tpa_agg_idx = cqe->fast_path_tpa_end.tpa_agg_index;
1845                         tpa_info = &rxq->tpa_info[tpa_agg_idx];
1846                         rx_mb = rxq->tpa_info[tpa_agg_idx].tpa_head;
1847                         goto tpa_end;
1848                 case ETH_RX_CQE_TYPE_SLOW_PATH:
1849                         PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n");
1850                         ecore_eth_cqe_completion(
1851                                 &edev->hwfns[rxq->queue_id % edev->num_hwfns],
1852                                 (struct eth_slow_path_rx_cqe *)cqe);
1853                         /* fall-thru */
1854                 default:
1855                         goto next_cqe;
1856                 }
1857
1858                 /* Get the data from the SW ring */
1859                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1860                 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
1861                 assert(rx_mb != NULL);
1862
1863                 /* Handle regular CQE or TPA start CQE */
1864                 if (!tpa_start_flg) {
1865                         parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);
1866                         offset = fp_cqe->placement_offset;
1867                         len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
1868                         pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1869                         vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1870                         rss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash);
1871 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1872                         bitfield_val = fp_cqe->bitfields;
1873 #endif
1874                 } else {
1875                         parse_flag =
1876                             rte_le_to_cpu_16(cqe_start_tpa->pars_flags.flags);
1877                         offset = cqe_start_tpa->placement_offset;
1878                         /* seg_len = len_on_first_bd */
1879                         len = rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd);
1880                         vlan_tci = rte_le_to_cpu_16(cqe_start_tpa->vlan_tag);
1881 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1882                         bitfield_val = cqe_start_tpa->bitfields;
1883 #endif
1884                         rss_hash = rte_le_to_cpu_32(cqe_start_tpa->rss_hash);
1885                 }
1886                 if (qede_tunn_exist(parse_flag)) {
1887                         PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n");
1888                         if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1889                                 PMD_RX_LOG(ERR, rxq,
1890                                             "L4 csum failed, flags = 0x%x\n",
1891                                             parse_flag);
1892                                 rxq->rx_hw_errors++;
1893                                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1894                         } else {
1895                                 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1896                         }
1897
1898                         if (unlikely(qede_check_tunn_csum_l3(parse_flag))) {
1899                                 PMD_RX_LOG(ERR, rxq,
1900                                         "Outer L3 csum failed, flags = 0x%x\n",
1901                                         parse_flag);
1902                                   rxq->rx_hw_errors++;
1903                                   ol_flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
1904                         } else {
1905                                   ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1906                         }
1907
1908                         if (tpa_start_flg)
1909                                 flags = cqe_start_tpa->tunnel_pars_flags.flags;
1910                         else
1911                                 flags = fp_cqe->tunnel_pars_flags.flags;
1912                         tunn_parse_flag = flags;
1913
1914                         /* Tunnel_type */
1915                         packet_type =
1916                                 qede_rx_cqe_to_tunn_pkt_type(tunn_parse_flag);
1917
1918                         /* Inner header */
1919                         packet_type |=
1920                               qede_rx_cqe_to_pkt_type_inner(parse_flag);
1921
1922                         /* Outer L3/L4 types is not available in CQE */
1923                         packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1924
1925                         /* Outer L3/L4 types is not available in CQE.
1926                          * Need to add offset to parse correctly,
1927                          */
1928                         rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1929                         packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1930                 } else {
1931                         packet_type |= qede_rx_cqe_to_pkt_type(parse_flag);
1932                 }
1933
1934                 /* Common handling for non-tunnel packets and for inner
1935                  * headers in the case of tunnel.
1936                  */
1937                 if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1938                         PMD_RX_LOG(ERR, rxq,
1939                                     "L4 csum failed, flags = 0x%x\n",
1940                                     parse_flag);
1941                         rxq->rx_hw_errors++;
1942                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
1943                 } else {
1944                         ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1945                 }
1946                 if (unlikely(qede_check_notunn_csum_l3(rx_mb, parse_flag))) {
1947                         PMD_RX_LOG(ERR, rxq, "IP csum failed, flags = 0x%x\n",
1948                                    parse_flag);
1949                         rxq->rx_hw_errors++;
1950                         ol_flags |= PKT_RX_IP_CKSUM_BAD;
1951                 } else {
1952                         ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1953                 }
1954
1955                 if (CQE_HAS_VLAN(parse_flag) ||
1956                     CQE_HAS_OUTER_VLAN(parse_flag)) {
1957                         /* Note: FW doesn't indicate Q-in-Q packet */
1958                         ol_flags |= PKT_RX_VLAN;
1959                         if (qdev->vlan_strip_flg) {
1960                                 ol_flags |= PKT_RX_VLAN_STRIPPED;
1961                                 rx_mb->vlan_tci = vlan_tci;
1962                         }
1963                 }
1964
1965                 /* RSS Hash */
1966                 if (qdev->rss_enable) {
1967                         ol_flags |= PKT_RX_RSS_HASH;
1968                         rx_mb->hash.rss = rss_hash;
1969                 }
1970
1971                 rx_alloc_count++;
1972                 qede_rx_bd_ring_consume(rxq);
1973
1974                 if (!tpa_start_flg && fp_cqe->bd_num > 1) {
1975                         PMD_RX_LOG(DEBUG, rxq, "Jumbo-over-BD packet: %02x BDs"
1976                                    " len on first: %04x Total Len: %04x",
1977                                    fp_cqe->bd_num, len, pkt_len);
1978                         num_segs = fp_cqe->bd_num - 1;
1979                         seg1 = rx_mb;
1980                         if (qede_process_sg_pkts(p_rxq, seg1, num_segs,
1981                                                  pkt_len - len))
1982                                 goto next_cqe;
1983
1984                         rx_alloc_count += num_segs;
1985                         rxq->rx_segs += num_segs;
1986                 }
1987                 rxq->rx_segs++; /* for the first segment */
1988
1989                 /* Prefetch next mbuf while processing current one. */
1990                 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1991                 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1992
1993                 /* Update rest of the MBUF fields */
1994                 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1995                 rx_mb->port = rxq->port_id;
1996                 rx_mb->ol_flags = ol_flags;
1997                 rx_mb->data_len = len;
1998                 rx_mb->packet_type = packet_type;
1999 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
2000                 print_rx_bd_info(rx_mb, rxq, bitfield_val);
2001 #endif
2002                 if (!tpa_start_flg) {
2003                         rx_mb->nb_segs = fp_cqe->bd_num;
2004                         rx_mb->pkt_len = pkt_len;
2005                 } else {
2006                         /* store ref to the updated mbuf */
2007                         tpa_info->tpa_head = rx_mb;
2008                         tpa_info->tpa_tail = tpa_info->tpa_head;
2009                 }
2010                 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
2011 tpa_end:
2012                 if (!tpa_start_flg) {
2013                         rx_pkts[rx_pkt] = rx_mb;
2014                         rx_pkt++;
2015                 }
2016 next_cqe:
2017                 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
2018                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
2019                 if (rx_pkt == nb_pkts) {
2020                         PMD_RX_LOG(DEBUG, rxq,
2021                                    "Budget reached nb_pkts=%u received=%u",
2022                                    rx_pkt, nb_pkts);
2023                         break;
2024                 }
2025         }
2026
2027         /* Request number of bufferes to be allocated in next loop */
2028         rxq->rx_alloc_count = rx_alloc_count;
2029
2030         rxq->rcv_pkts += rx_pkt;
2031
2032         PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
2033
2034         return rx_pkt;
2035 }
2036
2037 uint16_t
2038 qede_recv_pkts_cmt(void *p_fp_cmt, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2039 {
2040         struct qede_fastpath_cmt *fp_cmt = p_fp_cmt;
2041         uint16_t eng0_pkts, eng1_pkts;
2042
2043         eng0_pkts = nb_pkts / 2;
2044
2045         eng0_pkts = qede_recv_pkts(fp_cmt->fp0->rxq, rx_pkts, eng0_pkts);
2046
2047         eng1_pkts = nb_pkts - eng0_pkts;
2048
2049         eng1_pkts = qede_recv_pkts(fp_cmt->fp1->rxq, rx_pkts + eng0_pkts,
2050                                    eng1_pkts);
2051
2052         return eng0_pkts + eng1_pkts;
2053 }
2054
2055 /* Populate scatter gather buffer descriptor fields */
2056 static inline uint16_t
2057 qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg,
2058                   struct eth_tx_2nd_bd **bd2, struct eth_tx_3rd_bd **bd3,
2059                   uint16_t start_seg)
2060 {
2061         struct qede_tx_queue *txq = p_txq;
2062         struct eth_tx_bd *tx_bd = NULL;
2063         dma_addr_t mapping;
2064         uint16_t nb_segs = 0;
2065
2066         /* Check for scattered buffers */
2067         while (m_seg) {
2068                 if (start_seg == 0) {
2069                         if (!*bd2) {
2070                                 *bd2 = (struct eth_tx_2nd_bd *)
2071                                         ecore_chain_produce(&txq->tx_pbl);
2072                                 memset(*bd2, 0, sizeof(struct eth_tx_2nd_bd));
2073                                 nb_segs++;
2074                         }
2075                         mapping = rte_mbuf_data_iova(m_seg);
2076                         QEDE_BD_SET_ADDR_LEN(*bd2, mapping, m_seg->data_len);
2077                         PMD_TX_LOG(DEBUG, txq, "BD2 len %04x", m_seg->data_len);
2078                 } else if (start_seg == 1) {
2079                         if (!*bd3) {
2080                                 *bd3 = (struct eth_tx_3rd_bd *)
2081                                         ecore_chain_produce(&txq->tx_pbl);
2082                                 memset(*bd3, 0, sizeof(struct eth_tx_3rd_bd));
2083                                 nb_segs++;
2084                         }
2085                         mapping = rte_mbuf_data_iova(m_seg);
2086                         QEDE_BD_SET_ADDR_LEN(*bd3, mapping, m_seg->data_len);
2087                         PMD_TX_LOG(DEBUG, txq, "BD3 len %04x", m_seg->data_len);
2088                 } else {
2089                         tx_bd = (struct eth_tx_bd *)
2090                                 ecore_chain_produce(&txq->tx_pbl);
2091                         memset(tx_bd, 0, sizeof(*tx_bd));
2092                         nb_segs++;
2093                         mapping = rte_mbuf_data_iova(m_seg);
2094                         QEDE_BD_SET_ADDR_LEN(tx_bd, mapping, m_seg->data_len);
2095                         PMD_TX_LOG(DEBUG, txq, "BD len %04x", m_seg->data_len);
2096                 }
2097                 start_seg++;
2098                 m_seg = m_seg->next;
2099         }
2100
2101         /* Return total scattered buffers */
2102         return nb_segs;
2103 }
2104
2105 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2106 static inline void
2107 print_tx_bd_info(struct qede_tx_queue *txq,
2108                  struct eth_tx_1st_bd *bd1,
2109                  struct eth_tx_2nd_bd *bd2,
2110                  struct eth_tx_3rd_bd *bd3,
2111                  uint64_t tx_ol_flags)
2112 {
2113         char ol_buf[256] = { 0 }; /* for verbose prints */
2114
2115         if (bd1)
2116                 PMD_TX_LOG(INFO, txq,
2117                    "BD1: nbytes=0x%04x nbds=0x%04x bd_flags=0x%04x bf=0x%04x",
2118                    rte_cpu_to_le_16(bd1->nbytes), bd1->data.nbds,
2119                    bd1->data.bd_flags.bitfields,
2120                    rte_cpu_to_le_16(bd1->data.bitfields));
2121         if (bd2)
2122                 PMD_TX_LOG(INFO, txq,
2123                    "BD2: nbytes=0x%04x bf1=0x%04x bf2=0x%04x tunn_ip=0x%04x\n",
2124                    rte_cpu_to_le_16(bd2->nbytes), bd2->data.bitfields1,
2125                    bd2->data.bitfields2, bd2->data.tunn_ip_size);
2126         if (bd3)
2127                 PMD_TX_LOG(INFO, txq,
2128                    "BD3: nbytes=0x%04x bf=0x%04x MSS=0x%04x "
2129                    "tunn_l4_hdr_start_offset_w=0x%04x tunn_hdr_size=0x%04x\n",
2130                    rte_cpu_to_le_16(bd3->nbytes),
2131                    rte_cpu_to_le_16(bd3->data.bitfields),
2132                    rte_cpu_to_le_16(bd3->data.lso_mss),
2133                    bd3->data.tunn_l4_hdr_start_offset_w,
2134                    bd3->data.tunn_hdr_size_w);
2135
2136         rte_get_tx_ol_flag_list(tx_ol_flags, ol_buf, sizeof(ol_buf));
2137         PMD_TX_LOG(INFO, txq, "TX offloads = %s\n", ol_buf);
2138 }
2139 #endif
2140
2141 /* TX prepare to check packets meets TX conditions */
2142 uint16_t
2143 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2144 qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
2145                     uint16_t nb_pkts)
2146 {
2147         struct qede_tx_queue *txq = p_txq;
2148 #else
2149 qede_xmit_prep_pkts(__rte_unused void *p_txq, struct rte_mbuf **tx_pkts,
2150                     uint16_t nb_pkts)
2151 {
2152 #endif
2153         uint64_t ol_flags;
2154         struct rte_mbuf *m;
2155         uint16_t i;
2156 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2157         int ret;
2158 #endif
2159
2160         for (i = 0; i < nb_pkts; i++) {
2161                 m = tx_pkts[i];
2162                 ol_flags = m->ol_flags;
2163                 if (ol_flags & PKT_TX_TCP_SEG) {
2164                         if (m->nb_segs >= ETH_TX_MAX_BDS_PER_LSO_PACKET) {
2165                                 rte_errno = EINVAL;
2166                                 break;
2167                         }
2168                         /* TBD: confirm its ~9700B for both ? */
2169                         if (m->tso_segsz > ETH_TX_MAX_NON_LSO_PKT_LEN) {
2170                                 rte_errno = EINVAL;
2171                                 break;
2172                         }
2173                 } else {
2174                         if (m->nb_segs >= ETH_TX_MAX_BDS_PER_NON_LSO_PACKET) {
2175                                 rte_errno = EINVAL;
2176                                 break;
2177                         }
2178                 }
2179                 if (ol_flags & QEDE_TX_OFFLOAD_NOTSUP_MASK) {
2180                         /* We support only limited tunnel protocols */
2181                         if (ol_flags & PKT_TX_TUNNEL_MASK) {
2182                                 uint64_t temp;
2183
2184                                 temp = ol_flags & PKT_TX_TUNNEL_MASK;
2185                                 if (temp == PKT_TX_TUNNEL_VXLAN ||
2186                                     temp == PKT_TX_TUNNEL_GENEVE ||
2187                                     temp == PKT_TX_TUNNEL_MPLSINUDP ||
2188                                     temp == PKT_TX_TUNNEL_GRE)
2189                                         continue;
2190                         }
2191
2192                         rte_errno = ENOTSUP;
2193                         break;
2194                 }
2195
2196 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2197                 ret = rte_validate_tx_offload(m);
2198                 if (ret != 0) {
2199                         rte_errno = -ret;
2200                         break;
2201                 }
2202 #endif
2203         }
2204
2205 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2206         if (unlikely(i != nb_pkts))
2207                 PMD_TX_LOG(ERR, txq, "TX prepare failed for %u\n",
2208                            nb_pkts - i);
2209 #endif
2210         return i;
2211 }
2212
2213 #define MPLSINUDP_HDR_SIZE                      (12)
2214
2215 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2216 static inline void
2217 qede_mpls_tunn_tx_sanity_check(struct rte_mbuf *mbuf,
2218                                struct qede_tx_queue *txq)
2219 {
2220         if (((mbuf->outer_l2_len + mbuf->outer_l3_len) / 2) > 0xff)
2221                 PMD_TX_LOG(ERR, txq, "tunn_l4_hdr_start_offset overflow\n");
2222         if (((mbuf->outer_l2_len + mbuf->outer_l3_len +
2223                 MPLSINUDP_HDR_SIZE) / 2) > 0xff)
2224                 PMD_TX_LOG(ERR, txq, "tunn_hdr_size overflow\n");
2225         if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE) / 2) >
2226                 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK)
2227                 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
2228         if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2) >
2229                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
2230                 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
2231 }
2232 #endif
2233
2234 uint16_t
2235 qede_xmit_pkts_regular(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2236 {
2237         struct qede_tx_queue *txq = p_txq;
2238         struct qede_dev *qdev = txq->qdev;
2239         struct ecore_dev *edev = &qdev->edev;
2240         struct eth_tx_1st_bd *bd1;
2241         struct eth_tx_2nd_bd *bd2;
2242         struct eth_tx_3rd_bd *bd3;
2243         struct rte_mbuf *m_seg = NULL;
2244         struct rte_mbuf *mbuf;
2245         struct rte_mbuf **sw_tx_ring;
2246         uint16_t nb_tx_pkts;
2247         uint16_t bd_prod;
2248         uint16_t idx;
2249         uint16_t nb_frags = 0;
2250         uint16_t nb_pkt_sent = 0;
2251         uint8_t nbds;
2252         uint64_t tx_ol_flags;
2253         /* BD1 */
2254         uint16_t bd1_bf;
2255         uint8_t bd1_bd_flags_bf;
2256
2257         if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
2258                 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
2259                            nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
2260                 qede_process_tx_compl(edev, txq);
2261         }
2262
2263         nb_tx_pkts  = nb_pkts;
2264         bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2265         sw_tx_ring = txq->sw_tx_ring;
2266
2267         while (nb_tx_pkts--) {
2268                 /* Init flags/values */
2269                 nbds = 0;
2270                 bd1 = NULL;
2271                 bd2 = NULL;
2272                 bd3 = NULL;
2273                 bd1_bf = 0;
2274                 bd1_bd_flags_bf = 0;
2275                 nb_frags = 0;
2276
2277                 mbuf = *tx_pkts++;
2278                 assert(mbuf);
2279
2280
2281                 /* Check minimum TX BDS availability against available BDs */
2282                 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs))
2283                         break;
2284
2285                 tx_ol_flags = mbuf->ol_flags;
2286                 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
2287
2288                 if (unlikely(txq->nb_tx_avail <
2289                                 ETH_TX_MIN_BDS_PER_NON_LSO_PKT))
2290                         break;
2291                 bd1_bf |=
2292                        (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
2293                         << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
2294
2295                 /* Offload the IP checksum in the hardware */
2296                 if (tx_ol_flags & PKT_TX_IP_CKSUM)
2297                         bd1_bd_flags_bf |=
2298                                 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
2299
2300                 /* L4 checksum offload (tcp or udp) */
2301                 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
2302                     (tx_ol_flags & (PKT_TX_UDP_CKSUM | PKT_TX_TCP_CKSUM)))
2303                         bd1_bd_flags_bf |=
2304                                 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
2305
2306                 /* Fill the entry in the SW ring and the BDs in the FW ring */
2307                 idx = TX_PROD(txq);
2308                 sw_tx_ring[idx] = mbuf;
2309
2310                 /* BD1 */
2311                 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
2312                 memset(bd1, 0, sizeof(struct eth_tx_1st_bd));
2313                 nbds++;
2314
2315                 /* Map MBUF linear data for DMA and set in the BD1 */
2316                 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2317                                      mbuf->data_len);
2318                 bd1->data.bitfields = rte_cpu_to_le_16(bd1_bf);
2319                 bd1->data.bd_flags.bitfields = bd1_bd_flags_bf;
2320
2321                 /* Handle fragmented MBUF */
2322                 if (unlikely(mbuf->nb_segs > 1)) {
2323                         m_seg = mbuf->next;
2324
2325                         /* Encode scatter gather buffer descriptors */
2326                         nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3,
2327                                                      nbds - 1);
2328                 }
2329
2330                 bd1->data.nbds = nbds + nb_frags;
2331
2332                 txq->nb_tx_avail -= bd1->data.nbds;
2333                 txq->sw_tx_prod++;
2334                 bd_prod =
2335                     rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2336 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2337                 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);
2338 #endif
2339                 nb_pkt_sent++;
2340                 txq->xmit_pkts++;
2341         }
2342
2343         /* Write value of prod idx into bd_prod */
2344         txq->tx_db.data.bd_prod = bd_prod;
2345         rte_wmb();
2346         rte_compiler_barrier();
2347         DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
2348         rte_wmb();
2349
2350         /* Check again for Tx completions */
2351         qede_process_tx_compl(edev, txq);
2352
2353         PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d",
2354                    nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());
2355
2356         return nb_pkt_sent;
2357 }
2358
2359 uint16_t
2360 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2361 {
2362         struct qede_tx_queue *txq = p_txq;
2363         struct qede_dev *qdev = txq->qdev;
2364         struct ecore_dev *edev = &qdev->edev;
2365         struct rte_mbuf *mbuf;
2366         struct rte_mbuf *m_seg = NULL;
2367         uint16_t nb_tx_pkts;
2368         uint16_t bd_prod;
2369         uint16_t idx;
2370         uint16_t nb_frags;
2371         uint16_t nb_pkt_sent = 0;
2372         uint8_t nbds;
2373         bool lso_flg;
2374         bool mplsoudp_flg;
2375         __rte_unused bool tunn_flg;
2376         bool tunn_ipv6_ext_flg;
2377         struct eth_tx_1st_bd *bd1;
2378         struct eth_tx_2nd_bd *bd2;
2379         struct eth_tx_3rd_bd *bd3;
2380         uint64_t tx_ol_flags;
2381         uint16_t hdr_size;
2382         /* BD1 */
2383         uint16_t bd1_bf;
2384         uint8_t bd1_bd_flags_bf;
2385         uint16_t vlan;
2386         /* BD2 */
2387         uint16_t bd2_bf1;
2388         uint16_t bd2_bf2;
2389         /* BD3 */
2390         uint16_t mss;
2391         uint16_t bd3_bf;
2392
2393         uint8_t tunn_l4_hdr_start_offset;
2394         uint8_t tunn_hdr_size;
2395         uint8_t inner_l2_hdr_size;
2396         uint16_t inner_l4_hdr_offset;
2397
2398         if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
2399                 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
2400                            nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
2401                 qede_process_tx_compl(edev, txq);
2402         }
2403
2404         nb_tx_pkts  = nb_pkts;
2405         bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2406         while (nb_tx_pkts--) {
2407                 /* Init flags/values */
2408                 tunn_flg = false;
2409                 lso_flg = false;
2410                 nbds = 0;
2411                 vlan = 0;
2412                 bd1 = NULL;
2413                 bd2 = NULL;
2414                 bd3 = NULL;
2415                 hdr_size = 0;
2416                 bd1_bf = 0;
2417                 bd1_bd_flags_bf = 0;
2418                 bd2_bf1 = 0;
2419                 bd2_bf2 = 0;
2420                 mss = 0;
2421                 bd3_bf = 0;
2422                 mplsoudp_flg = false;
2423                 tunn_ipv6_ext_flg = false;
2424                 tunn_hdr_size = 0;
2425                 tunn_l4_hdr_start_offset = 0;
2426
2427                 mbuf = *tx_pkts++;
2428                 assert(mbuf);
2429
2430                 /* Check minimum TX BDS availability against available BDs */
2431                 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs))
2432                         break;
2433
2434                 tx_ol_flags = mbuf->ol_flags;
2435                 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
2436
2437                 /* TX prepare would have already checked supported tunnel Tx
2438                  * offloads. Don't rely on pkt_type marked by Rx, instead use
2439                  * tx_ol_flags to decide.
2440                  */
2441                 tunn_flg = !!(tx_ol_flags & PKT_TX_TUNNEL_MASK);
2442
2443                 if (tunn_flg) {
2444                         /* Check against max which is Tunnel IPv6 + ext */
2445                         if (unlikely(txq->nb_tx_avail <
2446                                 ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT))
2447                                         break;
2448
2449                         /* First indicate its a tunnel pkt */
2450                         bd1_bf |= ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
2451                                   ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
2452                         /* Legacy FW had flipped behavior in regard to this bit
2453                          * i.e. it needed to set to prevent FW from touching
2454                          * encapsulated packets when it didn't need to.
2455                          */
2456                         if (unlikely(txq->is_legacy)) {
2457                                 bd1_bf ^= 1 <<
2458                                         ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
2459                         }
2460
2461                         /* Outer IP checksum offload */
2462                         if (tx_ol_flags & (PKT_TX_OUTER_IP_CKSUM |
2463                                            PKT_TX_OUTER_IPV4)) {
2464                                 bd1_bd_flags_bf |=
2465                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
2466                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
2467                         }
2468
2469                         /**
2470                          * Currently, only inner checksum offload in MPLS-in-UDP
2471                          * tunnel with one MPLS label is supported. Both outer
2472                          * and inner layers  lengths need to be provided in
2473                          * mbuf.
2474                          */
2475                         if ((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
2476                                                 PKT_TX_TUNNEL_MPLSINUDP) {
2477                                 mplsoudp_flg = true;
2478 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2479                                 qede_mpls_tunn_tx_sanity_check(mbuf, txq);
2480 #endif
2481                                 /* Outer L4 offset in two byte words */
2482                                 tunn_l4_hdr_start_offset =
2483                                   (mbuf->outer_l2_len + mbuf->outer_l3_len) / 2;
2484                                 /* Tunnel header size in two byte words */
2485                                 tunn_hdr_size = (mbuf->outer_l2_len +
2486                                                 mbuf->outer_l3_len +
2487                                                 MPLSINUDP_HDR_SIZE) / 2;
2488                                 /* Inner L2 header size in two byte words */
2489                                 inner_l2_hdr_size = (mbuf->l2_len -
2490                                                 MPLSINUDP_HDR_SIZE) / 2;
2491                                 /* Inner L4 header offset from the beggining
2492                                  * of inner packet in two byte words
2493                                  */
2494                                 inner_l4_hdr_offset = (mbuf->l2_len -
2495                                         MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2;
2496
2497                                 /* Inner L2 size and address type */
2498                                 bd2_bf1 |= (inner_l2_hdr_size &
2499                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK) <<
2500                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT;
2501                                 bd2_bf1 |= (UNICAST_ADDRESS &
2502                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK) <<
2503                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT;
2504                                 /* Treated as IPv6+Ext */
2505                                 bd2_bf1 |=
2506                                     1 << ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT;
2507
2508                                 /* Mark inner IPv6 if present */
2509                                 if (tx_ol_flags & PKT_TX_IPV6)
2510                                         bd2_bf1 |=
2511                                                 1 << ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT;
2512
2513                                 /* Inner L4 offsets */
2514                                 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
2515                                      (tx_ol_flags & (PKT_TX_UDP_CKSUM |
2516                                                         PKT_TX_TCP_CKSUM))) {
2517                                         /* Determines if BD3 is needed */
2518                                         tunn_ipv6_ext_flg = true;
2519                                         if ((tx_ol_flags & PKT_TX_L4_MASK) ==
2520                                                         PKT_TX_UDP_CKSUM) {
2521                                                 bd2_bf1 |=
2522                                                         1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
2523                                         }
2524
2525                                         /* TODO other pseudo checksum modes are
2526                                          * not supported
2527                                          */
2528                                         bd2_bf1 |=
2529                                         ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
2530                                         ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT;
2531                                         bd2_bf2 |= (inner_l4_hdr_offset &
2532                                                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK) <<
2533                                                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
2534                                 }
2535                         } /* End MPLSoUDP */
2536                 } /* End Tunnel handling */
2537
2538                 if (tx_ol_flags & PKT_TX_TCP_SEG) {
2539                         lso_flg = true;
2540                         if (unlikely(txq->nb_tx_avail <
2541                                                 ETH_TX_MIN_BDS_PER_LSO_PKT))
2542                                 break;
2543                         /* For LSO, packet header and payload must reside on
2544                          * buffers pointed by different BDs. Using BD1 for HDR
2545                          * and BD2 onwards for data.
2546                          */
2547                         hdr_size = mbuf->l2_len + mbuf->l3_len + mbuf->l4_len;
2548                         if (tunn_flg)
2549                                 hdr_size += mbuf->outer_l2_len +
2550                                             mbuf->outer_l3_len;
2551
2552                         bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT;
2553                         bd1_bd_flags_bf |=
2554                                         1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
2555                         /* PKT_TX_TCP_SEG implies PKT_TX_TCP_CKSUM */
2556                         bd1_bd_flags_bf |=
2557                                         1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
2558                         mss = rte_cpu_to_le_16(mbuf->tso_segsz);
2559                         /* Using one header BD */
2560                         bd3_bf |= rte_cpu_to_le_16(1 <<
2561                                         ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
2562                 } else {
2563                         if (unlikely(txq->nb_tx_avail <
2564                                         ETH_TX_MIN_BDS_PER_NON_LSO_PKT))
2565                                 break;
2566                         bd1_bf |=
2567                                (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
2568                                 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
2569                 }
2570
2571                 /* Descriptor based VLAN insertion */
2572                 if (tx_ol_flags & PKT_TX_VLAN_PKT) {
2573                         vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
2574                         bd1_bd_flags_bf |=
2575                             1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
2576                 }
2577
2578                 /* Offload the IP checksum in the hardware */
2579                 if (tx_ol_flags & PKT_TX_IP_CKSUM) {
2580                         bd1_bd_flags_bf |=
2581                                 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
2582                         /* There's no DPDK flag to request outer-L4 csum
2583                          * offload. But in the case of tunnel if inner L3 or L4
2584                          * csum offload is requested then we need to force
2585                          * recalculation of L4 tunnel header csum also.
2586                          */
2587                         if (tunn_flg && ((tx_ol_flags & PKT_TX_TUNNEL_MASK) !=
2588                                                         PKT_TX_TUNNEL_GRE)) {
2589                                 bd1_bd_flags_bf |=
2590                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
2591                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
2592                         }
2593                 }
2594
2595                 /* L4 checksum offload (tcp or udp) */
2596                 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
2597                     (tx_ol_flags & (PKT_TX_UDP_CKSUM | PKT_TX_TCP_CKSUM))) {
2598                         bd1_bd_flags_bf |=
2599                                 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
2600                         /* There's no DPDK flag to request outer-L4 csum
2601                          * offload. But in the case of tunnel if inner L3 or L4
2602                          * csum offload is requested then we need to force
2603                          * recalculation of L4 tunnel header csum also.
2604                          */
2605                         if (tunn_flg) {
2606                                 bd1_bd_flags_bf |=
2607                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
2608                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
2609                         }
2610                 }
2611
2612                 /* Fill the entry in the SW ring and the BDs in the FW ring */
2613                 idx = TX_PROD(txq);
2614                 txq->sw_tx_ring[idx] = mbuf;
2615
2616                 /* BD1 */
2617                 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
2618                 memset(bd1, 0, sizeof(struct eth_tx_1st_bd));
2619                 nbds++;
2620
2621                 /* Map MBUF linear data for DMA and set in the BD1 */
2622                 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2623                                      mbuf->data_len);
2624                 bd1->data.bitfields = rte_cpu_to_le_16(bd1_bf);
2625                 bd1->data.bd_flags.bitfields = bd1_bd_flags_bf;
2626                 bd1->data.vlan = vlan;
2627
2628                 if (lso_flg || mplsoudp_flg) {
2629                         bd2 = (struct eth_tx_2nd_bd *)ecore_chain_produce
2630                                                         (&txq->tx_pbl);
2631                         memset(bd2, 0, sizeof(struct eth_tx_2nd_bd));
2632                         nbds++;
2633
2634                         /* BD1 */
2635                         QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2636                                              hdr_size);
2637                         /* BD2 */
2638                         QEDE_BD_SET_ADDR_LEN(bd2, (hdr_size +
2639                                              rte_mbuf_data_iova(mbuf)),
2640                                              mbuf->data_len - hdr_size);
2641                         bd2->data.bitfields1 = rte_cpu_to_le_16(bd2_bf1);
2642                         if (mplsoudp_flg) {
2643                                 bd2->data.bitfields2 =
2644                                         rte_cpu_to_le_16(bd2_bf2);
2645                                 /* Outer L3 size */
2646                                 bd2->data.tunn_ip_size =
2647                                         rte_cpu_to_le_16(mbuf->outer_l3_len);
2648                         }
2649                         /* BD3 */
2650                         if (lso_flg || (mplsoudp_flg && tunn_ipv6_ext_flg)) {
2651                                 bd3 = (struct eth_tx_3rd_bd *)
2652                                         ecore_chain_produce(&txq->tx_pbl);
2653                                 memset(bd3, 0, sizeof(struct eth_tx_3rd_bd));
2654                                 nbds++;
2655                                 bd3->data.bitfields = rte_cpu_to_le_16(bd3_bf);
2656                                 if (lso_flg)
2657                                         bd3->data.lso_mss = mss;
2658                                 if (mplsoudp_flg) {
2659                                         bd3->data.tunn_l4_hdr_start_offset_w =
2660                                                 tunn_l4_hdr_start_offset;
2661                                         bd3->data.tunn_hdr_size_w =
2662                                                 tunn_hdr_size;
2663                                 }
2664                         }
2665                 }
2666
2667                 /* Handle fragmented MBUF */
2668                 m_seg = mbuf->next;
2669
2670                 /* Encode scatter gather buffer descriptors if required */
2671                 nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3, nbds - 1);
2672                 bd1->data.nbds = nbds + nb_frags;
2673
2674                 txq->nb_tx_avail -= bd1->data.nbds;
2675                 txq->sw_tx_prod++;
2676                 bd_prod =
2677                     rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2678 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2679                 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);
2680 #endif
2681                 nb_pkt_sent++;
2682                 txq->xmit_pkts++;
2683         }
2684
2685         /* Write value of prod idx into bd_prod */
2686         txq->tx_db.data.bd_prod = bd_prod;
2687         rte_wmb();
2688         rte_compiler_barrier();
2689         DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
2690         rte_wmb();
2691
2692         /* Check again for Tx completions */
2693         qede_process_tx_compl(edev, txq);
2694
2695         PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d",
2696                    nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());
2697
2698         return nb_pkt_sent;
2699 }
2700
2701 uint16_t
2702 qede_xmit_pkts_cmt(void *p_fp_cmt, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2703 {
2704         struct qede_fastpath_cmt *fp_cmt = p_fp_cmt;
2705         uint16_t eng0_pkts, eng1_pkts;
2706
2707         eng0_pkts = nb_pkts / 2;
2708
2709         eng0_pkts = qede_xmit_pkts(fp_cmt->fp0->txq, tx_pkts, eng0_pkts);
2710
2711         eng1_pkts = nb_pkts - eng0_pkts;
2712
2713         eng1_pkts = qede_xmit_pkts(fp_cmt->fp1->txq, tx_pkts + eng0_pkts,
2714                                    eng1_pkts);
2715
2716         return eng0_pkts + eng1_pkts;
2717 }
2718
2719 uint16_t
2720 qede_rxtx_pkts_dummy(__rte_unused void *p_rxq,
2721                      __rte_unused struct rte_mbuf **pkts,
2722                      __rte_unused uint16_t nb_pkts)
2723 {
2724         return 0;
2725 }
2726
2727
2728 /* this function does a fake walk through over completion queue
2729  * to calculate number of BDs used by HW.
2730  * At the end, it restores the state of completion queue.
2731  */
2732 static uint16_t
2733 qede_parse_fp_cqe(struct qede_rx_queue *rxq)
2734 {
2735         uint16_t hw_comp_cons, sw_comp_cons, bd_count = 0;
2736         union eth_rx_cqe *cqe, *orig_cqe = NULL;
2737
2738         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
2739         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
2740
2741         if (hw_comp_cons == sw_comp_cons)
2742                 return 0;
2743
2744         /* Get the CQE from the completion ring */
2745         cqe = (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
2746         orig_cqe = cqe;
2747
2748         while (sw_comp_cons != hw_comp_cons) {
2749                 switch (cqe->fast_path_regular.type) {
2750                 case ETH_RX_CQE_TYPE_REGULAR:
2751                         bd_count += cqe->fast_path_regular.bd_num;
2752                         break;
2753                 case ETH_RX_CQE_TYPE_TPA_END:
2754                         bd_count += cqe->fast_path_tpa_end.num_of_bds;
2755                         break;
2756                 default:
2757                         break;
2758                 }
2759
2760                 cqe =
2761                 (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
2762                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
2763         }
2764
2765         /* revert comp_ring to original state */
2766         ecore_chain_set_cons(&rxq->rx_comp_ring, sw_comp_cons, orig_cqe);
2767
2768         return bd_count;
2769 }
2770
2771 int
2772 qede_rx_descriptor_status(void *p_rxq, uint16_t offset)
2773 {
2774         uint16_t hw_bd_cons, sw_bd_cons, sw_bd_prod;
2775         uint16_t produced, consumed;
2776         struct qede_rx_queue *rxq = p_rxq;
2777
2778         if (offset > rxq->nb_rx_desc)
2779                 return -EINVAL;
2780
2781         sw_bd_cons = ecore_chain_get_cons_idx(&rxq->rx_bd_ring);
2782         sw_bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
2783
2784         /* find BDs used by HW from completion queue elements */
2785         hw_bd_cons = sw_bd_cons + qede_parse_fp_cqe(rxq);
2786
2787         if (hw_bd_cons < sw_bd_cons)
2788                 /* wraparound case */
2789                 consumed = (0xffff - sw_bd_cons) + hw_bd_cons;
2790         else
2791                 consumed = hw_bd_cons - sw_bd_cons;
2792
2793         if (offset <= consumed)
2794                 return RTE_ETH_RX_DESC_DONE;
2795
2796         if (sw_bd_prod < sw_bd_cons)
2797                 /* wraparound case */
2798                 produced = (0xffff - sw_bd_cons) + sw_bd_prod;
2799         else
2800                 produced = sw_bd_prod - sw_bd_cons;
2801
2802         if (offset <= produced)
2803                 return RTE_ETH_RX_DESC_AVAIL;
2804
2805         return RTE_ETH_RX_DESC_UNAVAIL;
2806 }