drivers/net/qede/qede_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include <rte_net.h>
   8 #include "qede_rxtx.h"
   9
  10 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
  11 {
  12         struct rte_mbuf *new_mb = NULL;
  13         struct eth_rx_bd *rx_bd;
  14         dma_addr_t mapping;
  15         uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
  16
  17         new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
  18         if (unlikely(!new_mb)) {
  19                 PMD_RX_LOG(ERR, rxq,
  20                            "Failed to allocate rx buffer "
  21                            "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
  22                            idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
  23                            rte_mempool_avail_count(rxq->mb_pool),
  24                            rte_mempool_in_use_count(rxq->mb_pool));
  25                 return -ENOMEM;
  26         }
  27         rxq->sw_rx_ring[idx].mbuf = new_mb;
  28         rxq->sw_rx_ring[idx].page_offset = 0;
  29         mapping = rte_mbuf_data_iova_default(new_mb);
  30         /* Advance PROD and get BD pointer */
  31         rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
  32         rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
  33         rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
  34         rxq->sw_rx_prod++;
  35         return 0;
  36 }
  37
  38 #define QEDE_MAX_BULK_ALLOC_COUNT 512
  39
  40 static inline int qede_alloc_rx_bulk_mbufs(struct qede_rx_queue *rxq, int count)
  41 {
  42         void *obj_p[QEDE_MAX_BULK_ALLOC_COUNT] __rte_cache_aligned;
  43         struct rte_mbuf *mbuf = NULL;
  44         struct eth_rx_bd *rx_bd;
  45         dma_addr_t mapping;
  46         int i, ret = 0;
  47         uint16_t idx;
  48
  49         if (count > QEDE_MAX_BULK_ALLOC_COUNT)
  50                 count = QEDE_MAX_BULK_ALLOC_COUNT;
  51
  52         ret = rte_mempool_get_bulk(rxq->mb_pool, obj_p, count);
  53         if (unlikely(ret)) {
  54                 PMD_RX_LOG(ERR, rxq,
  55                            "Failed to allocate %d rx buffers "
  56                             "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
  57                             count,
  58                             rxq->sw_rx_prod & NUM_RX_BDS(rxq),
  59                             rxq->sw_rx_cons & NUM_RX_BDS(rxq),
  60                             rte_mempool_avail_count(rxq->mb_pool),
  61                             rte_mempool_in_use_count(rxq->mb_pool));
  62                 return -ENOMEM;
  63         }
  64
  65         for (i = 0; i < count; i++) {
  66                 mbuf = obj_p[i];
  67                 if (likely(i < count - 1))
  68                         rte_prefetch0(obj_p[i + 1]);
  69
  70                 idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
  71                 rxq->sw_rx_ring[idx].mbuf = mbuf;
  72                 rxq->sw_rx_ring[idx].page_offset = 0;
  73                 mapping = rte_mbuf_data_iova_default(mbuf);
  74                 rx_bd = (struct eth_rx_bd *)
  75                         ecore_chain_produce(&rxq->rx_bd_ring);
  76                 rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
  77                 rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
  78                 rxq->sw_rx_prod++;
  79         }
  80
  81         return 0;
  82 }
  83
  84 /* Criterias for calculating Rx buffer size -
  85  * 1) rx_buf_size should not exceed the size of mbuf
  86  * 2) In scattered_rx mode - minimum rx_buf_size should be
  87  *    (MTU + Maximum L2 Header Size + 2) / ETH_RX_MAX_BUFF_PER_PKT
  88  * 3) In regular mode - minimum rx_buf_size should be
  89  *    (MTU + Maximum L2 Header Size + 2)
  90  *    In above cases +2 corrosponds to 2 bytes padding in front of L2
  91  *    header.
  92  * 4) rx_buf_size should be cacheline-size aligned. So considering
  93  *    criteria 1, we need to adjust the size to floor instead of ceil,
  94  *    so that we don't exceed mbuf size while ceiling rx_buf_size.
  95  */
  96 int
  97 qede_calc_rx_buf_size(struct rte_eth_dev *dev, uint16_t mbufsz,
  98                       uint16_t max_frame_size)
  99 {
 100         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
 101         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 102         int rx_buf_size;
 103
 104         if (dev->data->scattered_rx) {
 105                 /* per HW limitation, only ETH_RX_MAX_BUFF_PER_PKT number of
 106                  * bufferes can be used for single packet. So need to make sure
 107                  * mbuf size is sufficient enough for this.
 108                  */
 109                 if ((mbufsz * ETH_RX_MAX_BUFF_PER_PKT) <
 110                      (max_frame_size + QEDE_ETH_OVERHEAD)) {
 111                         DP_ERR(edev, "mbuf %d size is not enough to hold max fragments (%d) for max rx packet length (%d)\n",
 112                                mbufsz, ETH_RX_MAX_BUFF_PER_PKT, max_frame_size);
 113                         return -EINVAL;
 114                 }
 115
 116                 rx_buf_size = RTE_MAX(mbufsz,
 117                                       (max_frame_size + QEDE_ETH_OVERHEAD) /
 118                                        ETH_RX_MAX_BUFF_PER_PKT);
 119         } else {
 120                 rx_buf_size = max_frame_size + QEDE_ETH_OVERHEAD;
 121         }
 122
 123         /* Align to cache-line size if needed */
 124         return QEDE_FLOOR_TO_CACHE_LINE_SIZE(rx_buf_size);
 125 }
 126
 127 static struct qede_rx_queue *
 128 qede_alloc_rx_queue_mem(struct rte_eth_dev *dev,
 129                         uint16_t queue_idx,
 130                         uint16_t nb_desc,
 131                         unsigned int socket_id,
 132                         struct rte_mempool *mp,
 133                         uint16_t bufsz)
 134 {
 135         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
 136         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 137         struct qede_rx_queue *rxq;
 138         size_t size;
 139         int rc;
 140
 141         /* First allocate the rx queue data structure */
 142         rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
 143                                  RTE_CACHE_LINE_SIZE, socket_id);
 144
 145         if (!rxq) {
 146                 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
 147                           socket_id);
 148                 return NULL;
 149         }
 150
 151         rxq->qdev = qdev;
 152         rxq->mb_pool = mp;
 153         rxq->nb_rx_desc = nb_desc;
 154         rxq->queue_id = queue_idx;
 155         rxq->port_id = dev->data->port_id;
 156
 157
 158         rxq->rx_buf_size = bufsz;
 159
 160         DP_INFO(edev, "mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\n",
 161                 qdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);
 162
 163         /* Allocate the parallel driver ring for Rx buffers */
 164         size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
 165         rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
 166                                              RTE_CACHE_LINE_SIZE, socket_id);
 167         if (!rxq->sw_rx_ring) {
 168                 DP_ERR(edev, "Memory allocation fails for sw_rx_ring on"
 169                        " socket %u\n", socket_id);
 170                 rte_free(rxq);
 171                 return NULL;
 172         }
 173
 174         /* Allocate FW Rx ring  */
 175         rc = qdev->ops->common->chain_alloc(edev,
 176                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 177                                             ECORE_CHAIN_MODE_NEXT_PTR,
 178                                             ECORE_CHAIN_CNT_TYPE_U16,
 179                                             rxq->nb_rx_desc,
 180                                             sizeof(struct eth_rx_bd),
 181                                             &rxq->rx_bd_ring,
 182                                             NULL);
 183
 184         if (rc != ECORE_SUCCESS) {
 185                 DP_ERR(edev, "Memory allocation fails for RX BD ring"
 186                        " on socket %u\n", socket_id);
 187                 rte_free(rxq->sw_rx_ring);
 188                 rte_free(rxq);
 189                 return NULL;
 190         }
 191
 192         /* Allocate FW completion ring */
 193         rc = qdev->ops->common->chain_alloc(edev,
 194                                             ECORE_CHAIN_USE_TO_CONSUME,
 195                                             ECORE_CHAIN_MODE_PBL,
 196                                             ECORE_CHAIN_CNT_TYPE_U16,
 197                                             rxq->nb_rx_desc,
 198                                             sizeof(union eth_rx_cqe),
 199                                             &rxq->rx_comp_ring,
 200                                             NULL);
 201
 202         if (rc != ECORE_SUCCESS) {
 203                 DP_ERR(edev, "Memory allocation fails for RX CQE ring"
 204                        " on socket %u\n", socket_id);
 205                 qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);
 206                 rte_free(rxq->sw_rx_ring);
 207                 rte_free(rxq);
 208                 return NULL;
 209         }
 210
 211         return rxq;
 212 }
 213
 214 int
 215 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qid,
 216                     uint16_t nb_desc, unsigned int socket_id,
 217                     __rte_unused const struct rte_eth_rxconf *rx_conf,
 218                     struct rte_mempool *mp)
 219 {
 220         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
 221         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 222         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
 223         struct qede_rx_queue *rxq;
 224         uint16_t max_rx_pkt_len;
 225         uint16_t bufsz;
 226         int rc;
 227
 228         PMD_INIT_FUNC_TRACE(edev);
 229
 230         /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
 231         if (!rte_is_power_of_2(nb_desc)) {
 232                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 233                           nb_desc);
 234                 return -EINVAL;
 235         }
 236
 237         /* Free memory prior to re-allocation if needed... */
 238         if (dev->data->rx_queues[qid] != NULL) {
 239                 qede_rx_queue_release(dev->data->rx_queues[qid]);
 240                 dev->data->rx_queues[qid] = NULL;
 241         }
 242
 243         max_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len;
 244
 245         /* Fix up RX buffer size */
 246         bufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 247         /* cache align the mbuf size to simplfy rx_buf_size calculation */
 248         bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
 249         if ((rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) ||
 250             (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {
 251                 if (!dev->data->scattered_rx) {
 252                         DP_INFO(edev, "Forcing scatter-gather mode\n");
 253                         dev->data->scattered_rx = 1;
 254                 }
 255         }
 256
 257         rc = qede_calc_rx_buf_size(dev, bufsz, max_rx_pkt_len);
 258         if (rc < 0)
 259                 return rc;
 260
 261         bufsz = rc;
 262
 263         if (ECORE_IS_CMT(edev)) {
 264                 rxq = qede_alloc_rx_queue_mem(dev, qid * 2, nb_desc,
 265                                               socket_id, mp, bufsz);
 266                 if (!rxq)
 267                         return -ENOMEM;
 268
 269                 qdev->fp_array[qid * 2].rxq = rxq;
 270                 rxq = qede_alloc_rx_queue_mem(dev, qid * 2 + 1, nb_desc,
 271                                               socket_id, mp, bufsz);
 272                 if (!rxq)
 273                         return -ENOMEM;
 274
 275                 qdev->fp_array[qid * 2 + 1].rxq = rxq;
 276                 /* provide per engine fp struct as rx queue */
 277                 dev->data->rx_queues[qid] = &qdev->fp_array_cmt[qid];
 278         } else {
 279                 rxq = qede_alloc_rx_queue_mem(dev, qid, nb_desc,
 280                                               socket_id, mp, bufsz);
 281                 if (!rxq)
 282                         return -ENOMEM;
 283
 284                 dev->data->rx_queues[qid] = rxq;
 285                 qdev->fp_array[qid].rxq = rxq;
 286         }
 287
 288         DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
 289                   qid, nb_desc, rxq->rx_buf_size, socket_id);
 290
 291         return 0;
 292 }
 293
 294 static void
 295 qede_rx_queue_reset(__rte_unused struct qede_dev *qdev,
 296                     struct qede_rx_queue *rxq)
 297 {
 298         DP_INFO(&qdev->edev, "Reset RX queue %u\n", rxq->queue_id);
 299         ecore_chain_reset(&rxq->rx_bd_ring);
 300         ecore_chain_reset(&rxq->rx_comp_ring);
 301         rxq->sw_rx_prod = 0;
 302         rxq->sw_rx_cons = 0;
 303         *rxq->hw_cons_ptr = 0;
 304 }
 305
 306 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
 307 {
 308         uint16_t i;
 309
 310         if (rxq->sw_rx_ring) {
 311                 for (i = 0; i < rxq->nb_rx_desc; i++) {
 312                         if (rxq->sw_rx_ring[i].mbuf) {
 313                                 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
 314                                 rxq->sw_rx_ring[i].mbuf = NULL;
 315                         }
 316                 }
 317         }
 318 }
 319
 320 static void _qede_rx_queue_release(struct qede_dev *qdev,
 321                                    struct ecore_dev *edev,
 322                                    struct qede_rx_queue *rxq)
 323 {
 324         qede_rx_queue_release_mbufs(rxq);
 325         qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);
 326         qdev->ops->common->chain_free(edev, &rxq->rx_comp_ring);
 327         rte_free(rxq->sw_rx_ring);
 328         rte_free(rxq);
 329 }
 330
 331 void qede_rx_queue_release(void *rx_queue)
 332 {
 333         struct qede_rx_queue *rxq = rx_queue;
 334         struct qede_fastpath_cmt *fp_cmt;
 335         struct qede_dev *qdev;
 336         struct ecore_dev *edev;
 337
 338         if (rxq) {
 339                 qdev = rxq->qdev;
 340                 edev = QEDE_INIT_EDEV(qdev);
 341                 PMD_INIT_FUNC_TRACE(edev);
 342                 if (ECORE_IS_CMT(edev)) {
 343                         fp_cmt = rx_queue;
 344                         _qede_rx_queue_release(qdev, edev, fp_cmt->fp0->rxq);
 345                         _qede_rx_queue_release(qdev, edev, fp_cmt->fp1->rxq);
 346                 } else {
 347                         _qede_rx_queue_release(qdev, edev, rxq);
 348                 }
 349         }
 350 }
 351
 352 /* Stops a given RX queue in the HW */
 353 static int qede_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 354 {
 355         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 356         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 357         struct ecore_hwfn *p_hwfn;
 358         struct qede_rx_queue *rxq;
 359         int hwfn_index;
 360         int rc;
 361
 362         if (rx_queue_id < qdev->num_rx_queues) {
 363                 rxq = qdev->fp_array[rx_queue_id].rxq;
 364                 hwfn_index = rx_queue_id % edev->num_hwfns;
 365                 p_hwfn = &edev->hwfns[hwfn_index];
 366                 rc = ecore_eth_rx_queue_stop(p_hwfn, rxq->handle,
 367                                 true, false);
 368                 if (rc != ECORE_SUCCESS) {
 369                         DP_ERR(edev, "RX queue %u stop fails\n", rx_queue_id);
 370                         return -1;
 371                 }
 372                 qede_rx_queue_release_mbufs(rxq);
 373                 qede_rx_queue_reset(qdev, rxq);
 374                 eth_dev->data->rx_queue_state[rx_queue_id] =
 375                         RTE_ETH_QUEUE_STATE_STOPPED;
 376                 DP_INFO(edev, "RX queue %u stopped\n", rx_queue_id);
 377         } else {
 378                 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
 379                 rc = -EINVAL;
 380         }
 381
 382         return rc;
 383 }
 384
 385 static struct qede_tx_queue *
 386 qede_alloc_tx_queue_mem(struct rte_eth_dev *dev,
 387                         uint16_t queue_idx,
 388                         uint16_t nb_desc,
 389                         unsigned int socket_id,
 390                         const struct rte_eth_txconf *tx_conf)
 391 {
 392         struct qede_dev *qdev = dev->data->dev_private;
 393         struct ecore_dev *edev = &qdev->edev;
 394         struct qede_tx_queue *txq;
 395         int rc;
 396         size_t sw_tx_ring_size;
 397
 398         txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
 399                                  RTE_CACHE_LINE_SIZE, socket_id);
 400
 401         if (txq == NULL) {
 402                 DP_ERR(edev,
 403                        "Unable to allocate memory for txq on socket %u",
 404                        socket_id);
 405                 return NULL;
 406         }
 407
 408         txq->nb_tx_desc = nb_desc;
 409         txq->qdev = qdev;
 410         txq->port_id = dev->data->port_id;
 411
 412         rc = qdev->ops->common->chain_alloc(edev,
 413                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 414                                             ECORE_CHAIN_MODE_PBL,
 415                                             ECORE_CHAIN_CNT_TYPE_U16,
 416                                             txq->nb_tx_desc,
 417                                             sizeof(union eth_tx_bd_types),
 418                                             &txq->tx_pbl,
 419                                             NULL);
 420         if (rc != ECORE_SUCCESS) {
 421                 DP_ERR(edev,
 422                        "Unable to allocate memory for txbd ring on socket %u",
 423                        socket_id);
 424                 qede_tx_queue_release(txq);
 425                 return NULL;
 426         }
 427
 428         /* Allocate software ring */
 429         sw_tx_ring_size = sizeof(txq->sw_tx_ring) * txq->nb_tx_desc;
 430         txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
 431                                              sw_tx_ring_size,
 432                                              RTE_CACHE_LINE_SIZE, socket_id);
 433
 434         if (!txq->sw_tx_ring) {
 435                 DP_ERR(edev,
 436                        "Unable to allocate memory for txbd ring on socket %u",
 437                        socket_id);
 438                 qdev->ops->common->chain_free(edev, &txq->tx_pbl);
 439                 qede_tx_queue_release(txq);
 440                 return NULL;
 441         }
 442
 443         txq->queue_id = queue_idx;
 444
 445         txq->nb_tx_avail = txq->nb_tx_desc;
 446
 447         txq->tx_free_thresh =
 448             tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
 449             (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
 450
 451         DP_INFO(edev,
 452                   "txq %u num_desc %u tx_free_thresh %u socket %u\n",
 453                   queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
 454         return txq;
 455 }
 456
 457 int
 458 qede_tx_queue_setup(struct rte_eth_dev *dev,
 459                     uint16_t queue_idx,
 460                     uint16_t nb_desc,
 461                     unsigned int socket_id,
 462                     const struct rte_eth_txconf *tx_conf)
 463 {
 464         struct qede_dev *qdev = dev->data->dev_private;
 465         struct ecore_dev *edev = &qdev->edev;
 466         struct qede_tx_queue *txq;
 467
 468         PMD_INIT_FUNC_TRACE(edev);
 469
 470         if (!rte_is_power_of_2(nb_desc)) {
 471                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 472                        nb_desc);
 473                 return -EINVAL;
 474         }
 475
 476         /* Free memory prior to re-allocation if needed... */
 477         if (dev->data->tx_queues[queue_idx] != NULL) {
 478                 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
 479                 dev->data->tx_queues[queue_idx] = NULL;
 480         }
 481
 482         if (ECORE_IS_CMT(edev)) {
 483                 txq = qede_alloc_tx_queue_mem(dev, queue_idx * 2, nb_desc,
 484                                               socket_id, tx_conf);
 485                 if (!txq)
 486                         return -ENOMEM;
 487
 488                 qdev->fp_array[queue_idx * 2].txq = txq;
 489                 txq = qede_alloc_tx_queue_mem(dev, (queue_idx * 2) + 1, nb_desc,
 490                                               socket_id, tx_conf);
 491                 if (!txq)
 492                         return -ENOMEM;
 493
 494                 qdev->fp_array[(queue_idx * 2) + 1].txq = txq;
 495                 dev->data->tx_queues[queue_idx] =
 496                                         &qdev->fp_array_cmt[queue_idx];
 497         } else {
 498                 txq = qede_alloc_tx_queue_mem(dev, queue_idx, nb_desc,
 499                                               socket_id, tx_conf);
 500                 if (!txq)
 501                         return -ENOMEM;
 502
 503                 dev->data->tx_queues[queue_idx] = txq;
 504                 qdev->fp_array[queue_idx].txq = txq;
 505         }
 506
 507         return 0;
 508 }
 509
 510 static void
 511 qede_tx_queue_reset(__rte_unused struct qede_dev *qdev,
 512                     struct qede_tx_queue *txq)
 513 {
 514         DP_INFO(&qdev->edev, "Reset TX queue %u\n", txq->queue_id);
 515         ecore_chain_reset(&txq->tx_pbl);
 516         txq->sw_tx_cons = 0;
 517         txq->sw_tx_prod = 0;
 518         *txq->hw_cons_ptr = 0;
 519 }
 520
 521 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
 522 {
 523         uint16_t i;
 524
 525         if (txq->sw_tx_ring) {
 526                 for (i = 0; i < txq->nb_tx_desc; i++) {
 527                         if (txq->sw_tx_ring[i]) {
 528                                 rte_pktmbuf_free(txq->sw_tx_ring[i]);
 529                                 txq->sw_tx_ring[i] = NULL;
 530                         }
 531                 }
 532         }
 533 }
 534
 535 static void _qede_tx_queue_release(struct qede_dev *qdev,
 536                                    struct ecore_dev *edev,
 537                                    struct qede_tx_queue *txq)
 538 {
 539         qede_tx_queue_release_mbufs(txq);
 540         qdev->ops->common->chain_free(edev, &txq->tx_pbl);
 541         rte_free(txq->sw_tx_ring);
 542         rte_free(txq);
 543 }
 544
 545 void qede_tx_queue_release(void *tx_queue)
 546 {
 547         struct qede_tx_queue *txq = tx_queue;
 548         struct qede_fastpath_cmt *fp_cmt;
 549         struct qede_dev *qdev;
 550         struct ecore_dev *edev;
 551
 552         if (txq) {
 553                 qdev = txq->qdev;
 554                 edev = QEDE_INIT_EDEV(qdev);
 555                 PMD_INIT_FUNC_TRACE(edev);
 556
 557                 if (ECORE_IS_CMT(edev)) {
 558                         fp_cmt = tx_queue;
 559                         _qede_tx_queue_release(qdev, edev, fp_cmt->fp0->txq);
 560                         _qede_tx_queue_release(qdev, edev, fp_cmt->fp1->txq);
 561                 } else {
 562                         _qede_tx_queue_release(qdev, edev, txq);
 563                 }
 564         }
 565 }
 566
 567 /* This function allocates fast-path status block memory */
 568 static int
 569 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
 570                   uint16_t sb_id)
 571 {
 572         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 573         struct status_block *sb_virt;
 574         dma_addr_t sb_phys;
 575         int rc;
 576
 577         sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys,
 578                                           sizeof(struct status_block));
 579         if (!sb_virt) {
 580                 DP_ERR(edev, "Status block allocation failed\n");
 581                 return -ENOMEM;
 582         }
 583         rc = qdev->ops->common->sb_init(edev, sb_info, sb_virt,
 584                                         sb_phys, sb_id);
 585         if (rc) {
 586                 DP_ERR(edev, "Status block initialization failed\n");
 587                 OSAL_DMA_FREE_COHERENT(edev, sb_virt, sb_phys,
 588                                        sizeof(struct status_block));
 589                 return rc;
 590         }
 591
 592         return 0;
 593 }
 594
 595 int qede_alloc_fp_resc(struct qede_dev *qdev)
 596 {
 597         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 598         struct qede_fastpath *fp;
 599         uint32_t num_sbs;
 600         uint16_t sb_idx;
 601         int i;
 602
 603         PMD_INIT_FUNC_TRACE(edev);
 604
 605         if (IS_VF(edev))
 606                 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
 607         else
 608                 num_sbs = ecore_cxt_get_proto_cid_count
 609                           (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL);
 610
 611         if (num_sbs == 0) {
 612                 DP_ERR(edev, "No status blocks available\n");
 613                 return -EINVAL;
 614         }
 615
 616         qdev->fp_array = rte_calloc("fp", QEDE_RXTX_MAX(qdev),
 617                                 sizeof(*qdev->fp_array), RTE_CACHE_LINE_SIZE);
 618
 619         if (!qdev->fp_array) {
 620                 DP_ERR(edev, "fp array allocation failed\n");
 621                 return -ENOMEM;
 622         }
 623
 624         memset((void *)qdev->fp_array, 0, QEDE_RXTX_MAX(qdev) *
 625                         sizeof(*qdev->fp_array));
 626
 627         if (ECORE_IS_CMT(edev)) {
 628                 qdev->fp_array_cmt = rte_calloc("fp_cmt",
 629                                                 QEDE_RXTX_MAX(qdev) / 2,
 630                                                 sizeof(*qdev->fp_array_cmt),
 631                                                 RTE_CACHE_LINE_SIZE);
 632
 633                 if (!qdev->fp_array_cmt) {
 634                         DP_ERR(edev, "fp array for CMT allocation failed\n");
 635                         return -ENOMEM;
 636                 }
 637
 638                 memset((void *)qdev->fp_array_cmt, 0,
 639                        (QEDE_RXTX_MAX(qdev) / 2) * sizeof(*qdev->fp_array_cmt));
 640
 641                 /* Establish the mapping of fp_array with fp_array_cmt */
 642                 for (i = 0; i < QEDE_RXTX_MAX(qdev) / 2; i++) {
 643                         qdev->fp_array_cmt[i].qdev = qdev;
 644                         qdev->fp_array_cmt[i].fp0 = &qdev->fp_array[i * 2];
 645                         qdev->fp_array_cmt[i].fp1 = &qdev->fp_array[i * 2 + 1];
 646                 }
 647         }
 648
 649         for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
 650                 fp = &qdev->fp_array[sb_idx];
 651                 fp->sb_info = rte_calloc("sb", 1, sizeof(struct ecore_sb_info),
 652                                 RTE_CACHE_LINE_SIZE);
 653                 if (!fp->sb_info) {
 654                         DP_ERR(edev, "FP sb_info allocation fails\n");
 655                         return -1;
 656                 }
 657                 if (qede_alloc_mem_sb(qdev, fp->sb_info, sb_idx)) {
 658                         DP_ERR(edev, "FP status block allocation fails\n");
 659                         return -1;
 660                 }
 661                 DP_INFO(edev, "sb_info idx 0x%x initialized\n",
 662                                 fp->sb_info->igu_sb_id);
 663         }
 664
 665         return 0;
 666 }
 667
 668 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
 669 {
 670         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 671         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 672         struct qede_fastpath *fp;
 673         uint16_t sb_idx;
 674         uint8_t i;
 675
 676         PMD_INIT_FUNC_TRACE(edev);
 677
 678         for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
 679                 fp = &qdev->fp_array[sb_idx];
 680                 if (fp->sb_info) {
 681                         DP_INFO(edev, "Free sb_info index 0x%x\n",
 682                                         fp->sb_info->igu_sb_id);
 683                         OSAL_DMA_FREE_COHERENT(edev, fp->sb_info->sb_virt,
 684                                 fp->sb_info->sb_phys,
 685                                 sizeof(struct status_block));
 686                         rte_free(fp->sb_info);
 687                         fp->sb_info = NULL;
 688                 }
 689         }
 690
 691         /* Free packet buffers and ring memories */
 692         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 693                 if (eth_dev->data->rx_queues[i]) {
 694                         qede_rx_queue_release(eth_dev->data->rx_queues[i]);
 695                         eth_dev->data->rx_queues[i] = NULL;
 696                 }
 697         }
 698
 699         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
 700                 if (eth_dev->data->tx_queues[i]) {
 701                         qede_tx_queue_release(eth_dev->data->tx_queues[i]);
 702                         eth_dev->data->tx_queues[i] = NULL;
 703                 }
 704         }
 705
 706         if (qdev->fp_array)
 707                 rte_free(qdev->fp_array);
 708         qdev->fp_array = NULL;
 709
 710         if (qdev->fp_array_cmt)
 711                 rte_free(qdev->fp_array_cmt);
 712         qdev->fp_array_cmt = NULL;
 713 }
 714
 715 static inline void
 716 qede_update_rx_prod(__rte_unused struct qede_dev *edev,
 717                     struct qede_rx_queue *rxq)
 718 {
 719         uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
 720         uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
 721         struct eth_rx_prod_data rx_prods = { 0 };
 722
 723         /* Update producers */
 724         rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
 725         rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
 726
 727         /* Make sure that the BD and SGE data is updated before updating the
 728          * producers since FW might read the BD/SGE right after the producer
 729          * is updated.
 730          */
 731         rte_wmb();
 732
 733         internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
 734                         (uint32_t *)&rx_prods);
 735
 736         /* mmiowb is needed to synchronize doorbell writes from more than one
 737          * processor. It guarantees that the write arrives to the device before
 738          * the napi lock is released and another qede_poll is called (possibly
 739          * on another CPU). Without this barrier, the next doorbell can bypass
 740          * this doorbell. This is applicable to IA64/Altix systems.
 741          */
 742         rte_wmb();
 743
 744         PMD_RX_LOG(DEBUG, rxq, "bd_prod %u  cqe_prod %u", bd_prod, cqe_prod);
 745 }
 746
 747 /* Starts a given RX queue in HW */
 748 static int
 749 qede_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 750 {
 751         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 752         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 753         struct ecore_queue_start_common_params params;
 754         struct ecore_rxq_start_ret_params ret_params;
 755         struct qede_rx_queue *rxq;
 756         struct qede_fastpath *fp;
 757         struct ecore_hwfn *p_hwfn;
 758         dma_addr_t p_phys_table;
 759         uint16_t page_cnt;
 760         uint16_t j;
 761         int hwfn_index;
 762         int rc;
 763
 764         if (rx_queue_id < qdev->num_rx_queues) {
 765                 fp = &qdev->fp_array[rx_queue_id];
 766                 rxq = fp->rxq;
 767                 /* Allocate buffers for the Rx ring */
 768                 for (j = 0; j < rxq->nb_rx_desc; j++) {
 769                         rc = qede_alloc_rx_buffer(rxq);
 770                         if (rc) {
 771                                 DP_ERR(edev, "RX buffer allocation failed"
 772                                                 " for rxq = %u\n", rx_queue_id);
 773                                 return -ENOMEM;
 774                         }
 775                 }
 776                 /* disable interrupts */
 777                 ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
 778                 /* Prepare ramrod */
 779                 memset(&params, 0, sizeof(params));
 780                 params.queue_id = rx_queue_id / edev->num_hwfns;
 781                 params.vport_id = 0;
 782                 params.stats_id = params.vport_id;
 783                 params.p_sb = fp->sb_info;
 784                 DP_INFO(edev, "rxq %u igu_sb_id 0x%x\n",
 785                                 fp->rxq->queue_id, fp->sb_info->igu_sb_id);
 786                 params.sb_idx = RX_PI;
 787                 hwfn_index = rx_queue_id % edev->num_hwfns;
 788                 p_hwfn = &edev->hwfns[hwfn_index];
 789                 p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->rx_comp_ring);
 790                 page_cnt = ecore_chain_get_page_cnt(&fp->rxq->rx_comp_ring);
 791                 memset(&ret_params, 0, sizeof(ret_params));
 792                 rc = ecore_eth_rx_queue_start(p_hwfn,
 793                                 p_hwfn->hw_info.opaque_fid,
 794                                 &params, fp->rxq->rx_buf_size,
 795                                 fp->rxq->rx_bd_ring.p_phys_addr,
 796                                 p_phys_table, page_cnt,
 797                                 &ret_params);
 798                 if (rc) {
 799                         DP_ERR(edev, "RX queue %u could not be started, rc = %d\n",
 800                                         rx_queue_id, rc);
 801                         return -1;
 802                 }
 803                 /* Update with the returned parameters */
 804                 fp->rxq->hw_rxq_prod_addr = ret_params.p_prod;
 805                 fp->rxq->handle = ret_params.p_handle;
 806
 807                 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_pi_array[RX_PI];
 808                 qede_update_rx_prod(qdev, fp->rxq);
 809                 eth_dev->data->rx_queue_state[rx_queue_id] =
 810                         RTE_ETH_QUEUE_STATE_STARTED;
 811                 DP_INFO(edev, "RX queue %u started\n", rx_queue_id);
 812         } else {
 813                 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
 814                 rc = -EINVAL;
 815         }
 816
 817         return rc;
 818 }
 819
 820 static int
 821 qede_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 822 {
 823         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 824         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 825         struct ecore_queue_start_common_params params;
 826         struct ecore_txq_start_ret_params ret_params;
 827         struct ecore_hwfn *p_hwfn;
 828         dma_addr_t p_phys_table;
 829         struct qede_tx_queue *txq;
 830         struct qede_fastpath *fp;
 831         uint16_t page_cnt;
 832         int hwfn_index;
 833         int rc;
 834
 835         if (tx_queue_id < qdev->num_tx_queues) {
 836                 fp = &qdev->fp_array[tx_queue_id];
 837                 txq = fp->txq;
 838                 memset(&params, 0, sizeof(params));
 839                 params.queue_id = tx_queue_id / edev->num_hwfns;
 840                 params.vport_id = 0;
 841                 params.stats_id = params.vport_id;
 842                 params.p_sb = fp->sb_info;
 843                 DP_INFO(edev, "txq %u igu_sb_id 0x%x\n",
 844                                 fp->txq->queue_id, fp->sb_info->igu_sb_id);
 845                 params.sb_idx = TX_PI(0); /* tc = 0 */
 846                 p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
 847                 page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
 848                 hwfn_index = tx_queue_id % edev->num_hwfns;
 849                 p_hwfn = &edev->hwfns[hwfn_index];
 850                 if (qdev->dev_info.is_legacy)
 851                         fp->txq->is_legacy = true;
 852                 rc = ecore_eth_tx_queue_start(p_hwfn,
 853                                 p_hwfn->hw_info.opaque_fid,
 854                                 &params, 0 /* tc */,
 855                                 p_phys_table, page_cnt,
 856                                 &ret_params);
 857                 if (rc != ECORE_SUCCESS) {
 858                         DP_ERR(edev, "TX queue %u couldn't be started, rc=%d\n",
 859                                         tx_queue_id, rc);
 860                         return -1;
 861                 }
 862                 txq->doorbell_addr = ret_params.p_doorbell;
 863                 txq->handle = ret_params.p_handle;
 864
 865                 txq->hw_cons_ptr = &fp->sb_info->sb_pi_array[TX_PI(0)];
 866                 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_DEST,
 867                                 DB_DEST_XCM);
 868                 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
 869                                 DB_AGG_CMD_SET);
 870                 SET_FIELD(txq->tx_db.data.params,
 871                                 ETH_DB_DATA_AGG_VAL_SEL,
 872                                 DQ_XCM_ETH_TX_BD_PROD_CMD);
 873                 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
 874                 eth_dev->data->tx_queue_state[tx_queue_id] =
 875                         RTE_ETH_QUEUE_STATE_STARTED;
 876                 DP_INFO(edev, "TX queue %u started\n", tx_queue_id);
 877         } else {
 878                 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
 879                 rc = -EINVAL;
 880         }
 881
 882         return rc;
 883 }
 884
 885 static inline void
 886 qede_process_tx_compl(__rte_unused struct ecore_dev *edev,
 887                       struct qede_tx_queue *txq)
 888 {
 889         uint16_t hw_bd_cons;
 890         uint16_t sw_tx_cons;
 891         uint16_t remaining;
 892         uint16_t mask;
 893         struct rte_mbuf *mbuf;
 894         uint16_t nb_segs;
 895         uint16_t idx;
 896         uint16_t first_idx;
 897
 898         rte_compiler_barrier();
 899         rte_prefetch0(txq->hw_cons_ptr);
 900         sw_tx_cons = ecore_chain_get_cons_idx(&txq->tx_pbl);
 901         hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
 902 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
 903         PMD_TX_LOG(DEBUG, txq, "Tx Completions = %u\n",
 904                    abs(hw_bd_cons - sw_tx_cons));
 905 #endif
 906
 907         mask = NUM_TX_BDS(txq);
 908         idx = txq->sw_tx_cons & mask;
 909
 910         remaining = hw_bd_cons - sw_tx_cons;
 911         txq->nb_tx_avail += remaining;
 912         first_idx = idx;
 913
 914         while (remaining) {
 915                 mbuf = txq->sw_tx_ring[idx];
 916                 RTE_ASSERT(mbuf);
 917                 nb_segs = mbuf->nb_segs;
 918                 remaining -= nb_segs;
 919
 920                 PMD_TX_LOG(DEBUG, txq, "nb_segs to free %u\n", nb_segs);
 921
 922                 while (nb_segs) {
 923                         ecore_chain_consume(&txq->tx_pbl);
 924                         nb_segs--;
 925                 }
 926
 927                 idx = (idx + 1) & mask;
 928                 PMD_TX_LOG(DEBUG, txq, "Freed tx packet\n");
 929         }
 930         txq->sw_tx_cons = idx;
 931
 932         if (first_idx > idx) {
 933                 rte_pktmbuf_free_bulk(&txq->sw_tx_ring[first_idx],
 934                                                           mask - first_idx + 1);
 935                 rte_pktmbuf_free_bulk(&txq->sw_tx_ring[0], idx);
 936         } else {
 937                 rte_pktmbuf_free_bulk(&txq->sw_tx_ring[first_idx],
 938                                                           idx - first_idx);
 939         }
 940 }
 941
 942 static int qede_drain_txq(struct qede_dev *qdev,
 943                           struct qede_tx_queue *txq, bool allow_drain)
 944 {
 945         struct ecore_dev *edev = &qdev->edev;
 946         int rc, cnt = 1000;
 947
 948         while (txq->sw_tx_cons != txq->sw_tx_prod) {
 949                 qede_process_tx_compl(edev, txq);
 950                 if (!cnt) {
 951                         if (allow_drain) {
 952                                 DP_ERR(edev, "Tx queue[%u] is stuck,"
 953                                           "requesting MCP to drain\n",
 954                                           txq->queue_id);
 955                                 rc = qdev->ops->common->drain(edev);
 956                                 if (rc)
 957                                         return rc;
 958                                 return qede_drain_txq(qdev, txq, false);
 959                         }
 960                         DP_ERR(edev, "Timeout waiting for tx queue[%d]:"
 961                                   "PROD=%d, CONS=%d\n",
 962                                   txq->queue_id, txq->sw_tx_prod,
 963                                   txq->sw_tx_cons);
 964                         return -1;
 965                 }
 966                 cnt--;
 967                 DELAY(1000);
 968                 rte_compiler_barrier();
 969         }
 970
 971         /* FW finished processing, wait for HW to transmit all tx packets */
 972         DELAY(2000);
 973
 974         return 0;
 975 }
 976
 977 /* Stops a given TX queue in the HW */
 978 static int qede_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 979 {
 980         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 981         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 982         struct ecore_hwfn *p_hwfn;
 983         struct qede_tx_queue *txq;
 984         int hwfn_index;
 985         int rc;
 986
 987         if (tx_queue_id < qdev->num_tx_queues) {
 988                 txq = qdev->fp_array[tx_queue_id].txq;
 989                 /* Drain txq */
 990                 if (qede_drain_txq(qdev, txq, true))
 991                         return -1; /* For the lack of retcodes */
 992                 /* Stop txq */
 993                 hwfn_index = tx_queue_id % edev->num_hwfns;
 994                 p_hwfn = &edev->hwfns[hwfn_index];
 995                 rc = ecore_eth_tx_queue_stop(p_hwfn, txq->handle);
 996                 if (rc != ECORE_SUCCESS) {
 997                         DP_ERR(edev, "TX queue %u stop fails\n", tx_queue_id);
 998                         return -1;
 999                 }
1000                 qede_tx_queue_release_mbufs(txq);
1001                 qede_tx_queue_reset(qdev, txq);
1002                 eth_dev->data->tx_queue_state[tx_queue_id] =
1003                         RTE_ETH_QUEUE_STATE_STOPPED;
1004                 DP_INFO(edev, "TX queue %u stopped\n", tx_queue_id);
1005         } else {
1006                 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
1007                 rc = -EINVAL;
1008         }
1009
1010         return rc;
1011 }
1012
1013 int qede_start_queues(struct rte_eth_dev *eth_dev)
1014 {
1015         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1016         uint8_t id;
1017         int rc = -1;
1018
1019         for (id = 0; id < qdev->num_rx_queues; id++) {
1020                 rc = qede_rx_queue_start(eth_dev, id);
1021                 if (rc != ECORE_SUCCESS)
1022                         return -1;
1023         }
1024
1025         for (id = 0; id < qdev->num_tx_queues; id++) {
1026                 rc = qede_tx_queue_start(eth_dev, id);
1027                 if (rc != ECORE_SUCCESS)
1028                         return -1;
1029         }
1030
1031         return rc;
1032 }
1033
1034 void qede_stop_queues(struct rte_eth_dev *eth_dev)
1035 {
1036         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1037         uint8_t id;
1038
1039         /* Stopping RX/TX queues */
1040         for (id = 0; id < qdev->num_tx_queues; id++)
1041                 qede_tx_queue_stop(eth_dev, id);
1042
1043         for (id = 0; id < qdev->num_rx_queues; id++)
1044                 qede_rx_queue_stop(eth_dev, id);
1045 }
1046
1047 static inline bool qede_tunn_exist(uint16_t flag)
1048 {
1049         return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
1050                     PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
1051 }
1052
1053 static inline uint8_t qede_check_tunn_csum_l3(uint16_t flag)
1054 {
1055         return !!((PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
1056                 PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT) & flag);
1057 }
1058
1059 /*
1060  * qede_check_tunn_csum_l4:
1061  * Returns:
1062  * 1 : If L4 csum is enabled AND if the validation has failed.
1063  * 0 : Otherwise
1064  */
1065 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
1066 {
1067         if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
1068              PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
1069                 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
1070                         PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
1071
1072         return 0;
1073 }
1074
1075 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
1076 {
1077         if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1078              PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
1079                 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1080                            PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
1081
1082         return 0;
1083 }
1084
1085 /* Returns outer L2, L3 and L4 packet_type for tunneled packets */
1086 static inline uint32_t qede_rx_cqe_to_pkt_type_outer(struct rte_mbuf *m)
1087 {
1088         uint32_t packet_type = RTE_PTYPE_UNKNOWN;
1089         struct rte_ether_hdr *eth_hdr;
1090         struct rte_ipv4_hdr *ipv4_hdr;
1091         struct rte_ipv6_hdr *ipv6_hdr;
1092         struct rte_vlan_hdr *vlan_hdr;
1093         uint16_t ethertype;
1094         bool vlan_tagged = 0;
1095         uint16_t len;
1096
1097         eth_hdr = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
1098         len = sizeof(struct rte_ether_hdr);
1099         ethertype = rte_cpu_to_be_16(eth_hdr->ether_type);
1100
1101          /* Note: Valid only if VLAN stripping is disabled */
1102         if (ethertype == RTE_ETHER_TYPE_VLAN) {
1103                 vlan_tagged = 1;
1104                 vlan_hdr = (struct rte_vlan_hdr *)(eth_hdr + 1);
1105                 len += sizeof(struct rte_vlan_hdr);
1106                 ethertype = rte_cpu_to_be_16(vlan_hdr->eth_proto);
1107         }
1108
1109         if (ethertype == RTE_ETHER_TYPE_IPV4) {
1110                 packet_type |= RTE_PTYPE_L3_IPV4;
1111                 ipv4_hdr = rte_pktmbuf_mtod_offset(m,
1112                                         struct rte_ipv4_hdr *, len);
1113                 if (ipv4_hdr->next_proto_id == IPPROTO_TCP)
1114                         packet_type |= RTE_PTYPE_L4_TCP;
1115                 else if (ipv4_hdr->next_proto_id == IPPROTO_UDP)
1116                         packet_type |= RTE_PTYPE_L4_UDP;
1117         } else if (ethertype == RTE_ETHER_TYPE_IPV6) {
1118                 packet_type |= RTE_PTYPE_L3_IPV6;
1119                 ipv6_hdr = rte_pktmbuf_mtod_offset(m,
1120                                                 struct rte_ipv6_hdr *, len);
1121                 if (ipv6_hdr->proto == IPPROTO_TCP)
1122                         packet_type |= RTE_PTYPE_L4_TCP;
1123                 else if (ipv6_hdr->proto == IPPROTO_UDP)
1124                         packet_type |= RTE_PTYPE_L4_UDP;
1125         }
1126
1127         if (vlan_tagged)
1128                 packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
1129         else
1130                 packet_type |= RTE_PTYPE_L2_ETHER;
1131
1132         return packet_type;
1133 }
1134
1135 static inline uint32_t qede_rx_cqe_to_pkt_type_inner(uint16_t flags)
1136 {
1137         uint16_t val;
1138
1139         /* Lookup table */
1140         static const uint32_t
1141         ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
1142                 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_INNER_L3_IPV4          |
1143                                        RTE_PTYPE_INNER_L2_ETHER,
1144                 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_INNER_L3_IPV6          |
1145                                        RTE_PTYPE_INNER_L2_ETHER,
1146                 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_INNER_L3_IPV4      |
1147                                            RTE_PTYPE_INNER_L4_TCP       |
1148                                            RTE_PTYPE_INNER_L2_ETHER,
1149                 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_INNER_L3_IPV6      |
1150                                            RTE_PTYPE_INNER_L4_TCP       |
1151                                            RTE_PTYPE_INNER_L2_ETHER,
1152                 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_INNER_L3_IPV4      |
1153                                            RTE_PTYPE_INNER_L4_UDP       |
1154                                            RTE_PTYPE_INNER_L2_ETHER,
1155                 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_INNER_L3_IPV6      |
1156                                            RTE_PTYPE_INNER_L4_UDP       |
1157                                            RTE_PTYPE_INNER_L2_ETHER,
1158                 /* Frags with no VLAN */
1159                 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_INNER_L3_IPV4     |
1160                                             RTE_PTYPE_INNER_L4_FRAG     |
1161                                             RTE_PTYPE_INNER_L2_ETHER,
1162                 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_INNER_L3_IPV6     |
1163                                             RTE_PTYPE_INNER_L4_FRAG     |
1164                                             RTE_PTYPE_INNER_L2_ETHER,
1165                 /* VLANs */
1166                 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_INNER_L3_IPV4     |
1167                                             RTE_PTYPE_INNER_L2_ETHER_VLAN,
1168                 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_INNER_L3_IPV6     |
1169                                             RTE_PTYPE_INNER_L2_ETHER_VLAN,
1170                 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
1171                                                 RTE_PTYPE_INNER_L4_TCP  |
1172                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1173                 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
1174                                                 RTE_PTYPE_INNER_L4_TCP  |
1175                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1176                 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
1177                                                 RTE_PTYPE_INNER_L4_UDP  |
1178                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1179                 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
1180                                                 RTE_PTYPE_INNER_L4_UDP  |
1181                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1182                 /* Frags with VLAN */
1183                 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV4 |
1184                                                  RTE_PTYPE_INNER_L4_FRAG |
1185                                                  RTE_PTYPE_INNER_L2_ETHER_VLAN,
1186                 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV6 |
1187                                                  RTE_PTYPE_INNER_L4_FRAG |
1188                                                  RTE_PTYPE_INNER_L2_ETHER_VLAN,
1189         };
1190
1191         /* Bits (0..3) provides L3/L4 protocol type */
1192         /* Bits (4,5) provides frag and VLAN info */
1193         val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
1194                PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
1195                (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
1196                 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) |
1197                (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1198                 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) |
1199                 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK <<
1200                  PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags;
1201
1202         if (val < QEDE_PKT_TYPE_MAX)
1203                 return ptype_lkup_tbl[val];
1204
1205         return RTE_PTYPE_UNKNOWN;
1206 }
1207
1208 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
1209 {
1210         uint16_t val;
1211
1212         /* Lookup table */
1213         static const uint32_t
1214         ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
1215                 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L2_ETHER,
1216                 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L2_ETHER,
1217                 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4    |
1218                                            RTE_PTYPE_L4_TCP     |
1219                                            RTE_PTYPE_L2_ETHER,
1220                 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6    |
1221                                            RTE_PTYPE_L4_TCP     |
1222                                            RTE_PTYPE_L2_ETHER,
1223                 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4    |
1224                                            RTE_PTYPE_L4_UDP     |
1225                                            RTE_PTYPE_L2_ETHER,
1226                 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6    |
1227                                            RTE_PTYPE_L4_UDP     |
1228                                            RTE_PTYPE_L2_ETHER,
1229                 /* Frags with no VLAN */
1230                 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_L3_IPV4   |
1231                                             RTE_PTYPE_L4_FRAG   |
1232                                             RTE_PTYPE_L2_ETHER,
1233                 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_L3_IPV6   |
1234                                             RTE_PTYPE_L4_FRAG   |
1235                                             RTE_PTYPE_L2_ETHER,
1236                 /* VLANs */
1237                 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_L3_IPV4           |
1238                                             RTE_PTYPE_L2_ETHER_VLAN,
1239                 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_L3_IPV6           |
1240                                             RTE_PTYPE_L2_ETHER_VLAN,
1241                 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_L3_IPV4       |
1242                                                 RTE_PTYPE_L4_TCP        |
1243                                                 RTE_PTYPE_L2_ETHER_VLAN,
1244                 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_L3_IPV6       |
1245                                                 RTE_PTYPE_L4_TCP        |
1246                                                 RTE_PTYPE_L2_ETHER_VLAN,
1247                 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_L3_IPV4       |
1248                                                 RTE_PTYPE_L4_UDP        |
1249                                                 RTE_PTYPE_L2_ETHER_VLAN,
1250                 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_L3_IPV6       |
1251                                                 RTE_PTYPE_L4_UDP        |
1252                                                 RTE_PTYPE_L2_ETHER_VLAN,
1253                 /* Frags with VLAN */
1254                 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_L3_IPV4      |
1255                                                  RTE_PTYPE_L4_FRAG      |
1256                                                  RTE_PTYPE_L2_ETHER_VLAN,
1257                 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_L3_IPV6      |
1258                                                  RTE_PTYPE_L4_FRAG      |
1259                                                  RTE_PTYPE_L2_ETHER_VLAN,
1260         };
1261
1262         /* Bits (0..3) provides L3/L4 protocol type */
1263         /* Bits (4,5) provides frag and VLAN info */
1264         val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
1265                PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
1266                (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
1267                 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) |
1268                (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1269                 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) |
1270                 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK <<
1271                  PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags;
1272
1273         if (val < QEDE_PKT_TYPE_MAX)
1274                 return ptype_lkup_tbl[val];
1275
1276         return RTE_PTYPE_UNKNOWN;
1277 }
1278
1279 static inline uint8_t
1280 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
1281 {
1282         struct rte_ipv4_hdr *ip;
1283         uint16_t pkt_csum;
1284         uint16_t calc_csum;
1285         uint16_t val;
1286
1287         val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1288                 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
1289
1290         if (unlikely(val)) {
1291                 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
1292                 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
1293                         ip = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
1294                                            sizeof(struct rte_ether_hdr));
1295                         pkt_csum = ip->hdr_checksum;
1296                         ip->hdr_checksum = 0;
1297                         calc_csum = rte_ipv4_cksum(ip);
1298                         ip->hdr_checksum = pkt_csum;
1299                         return (calc_csum != pkt_csum);
1300                 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
1301                         return 1;
1302                 }
1303         }
1304         return 0;
1305 }
1306
1307 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
1308 {
1309         ecore_chain_consume(&rxq->rx_bd_ring);
1310         rxq->sw_rx_cons++;
1311 }
1312
1313 static inline void
1314 qede_reuse_page(__rte_unused struct qede_dev *qdev,
1315                 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
1316 {
1317         struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
1318         uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
1319         struct qede_rx_entry *curr_prod;
1320         dma_addr_t new_mapping;
1321
1322         curr_prod = &rxq->sw_rx_ring[idx];
1323         *curr_prod = *curr_cons;
1324
1325         new_mapping = rte_mbuf_data_iova_default(curr_prod->mbuf) +
1326                       curr_prod->page_offset;
1327
1328         rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
1329         rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
1330
1331         rxq->sw_rx_prod++;
1332 }
1333
1334 static inline void
1335 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
1336                         struct qede_dev *qdev, uint8_t count)
1337 {
1338         struct qede_rx_entry *curr_cons;
1339
1340         for (; count > 0; count--) {
1341                 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
1342                 qede_reuse_page(qdev, rxq, curr_cons);
1343                 qede_rx_bd_ring_consume(rxq);
1344         }
1345 }
1346
1347 static inline void
1348 qede_rx_process_tpa_cmn_cont_end_cqe(__rte_unused struct qede_dev *qdev,
1349                                      struct qede_rx_queue *rxq,
1350                                      uint8_t agg_index, uint16_t len)
1351 {
1352         struct qede_agg_info *tpa_info;
1353         struct rte_mbuf *curr_frag; /* Pointer to currently filled TPA seg */
1354         uint16_t cons_idx;
1355
1356         /* Under certain conditions it is possible that FW may not consume
1357          * additional or new BD. So decision to consume the BD must be made
1358          * based on len_list[0].
1359          */
1360         if (rte_le_to_cpu_16(len)) {
1361                 tpa_info = &rxq->tpa_info[agg_index];
1362                 cons_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1363                 curr_frag = rxq->sw_rx_ring[cons_idx].mbuf;
1364                 assert(curr_frag);
1365                 curr_frag->nb_segs = 1;
1366                 curr_frag->pkt_len = rte_le_to_cpu_16(len);
1367                 curr_frag->data_len = curr_frag->pkt_len;
1368                 tpa_info->tpa_tail->next = curr_frag;
1369                 tpa_info->tpa_tail = curr_frag;
1370                 qede_rx_bd_ring_consume(rxq);
1371                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1372                         PMD_RX_LOG(ERR, rxq, "mbuf allocation fails\n");
1373                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1374                         rxq->rx_alloc_errors++;
1375                 }
1376         }
1377 }
1378
1379 static inline void
1380 qede_rx_process_tpa_cont_cqe(struct qede_dev *qdev,
1381                              struct qede_rx_queue *rxq,
1382                              struct eth_fast_path_rx_tpa_cont_cqe *cqe)
1383 {
1384         PMD_RX_LOG(INFO, rxq, "TPA cont[%d] - len [%d]\n",
1385                    cqe->tpa_agg_index, rte_le_to_cpu_16(cqe->len_list[0]));
1386         /* only len_list[0] will have value */
1387         qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
1388                                              cqe->len_list[0]);
1389 }
1390
1391 static inline void
1392 qede_rx_process_tpa_end_cqe(struct qede_dev *qdev,
1393                             struct qede_rx_queue *rxq,
1394                             struct eth_fast_path_rx_tpa_end_cqe *cqe)
1395 {
1396         struct rte_mbuf *rx_mb; /* Pointer to head of the chained agg */
1397
1398         qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
1399                                              cqe->len_list[0]);
1400         /* Update total length and frags based on end TPA */
1401         rx_mb = rxq->tpa_info[cqe->tpa_agg_index].tpa_head;
1402         /* TODO:  Add Sanity Checks */
1403         rx_mb->nb_segs = cqe->num_of_bds;
1404         rx_mb->pkt_len = cqe->total_packet_len;
1405
1406         PMD_RX_LOG(INFO, rxq, "TPA End[%d] reason %d cqe_len %d nb_segs %d"
1407                    " pkt_len %d\n", cqe->tpa_agg_index, cqe->end_reason,
1408                    rte_le_to_cpu_16(cqe->len_list[0]), rx_mb->nb_segs,
1409                    rx_mb->pkt_len);
1410 }
1411
1412 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
1413 {
1414         uint32_t val;
1415
1416         /* Lookup table */
1417         static const uint32_t
1418         ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
1419                 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
1420                 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
1421                 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
1422                 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
1423                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
1424                                 RTE_PTYPE_TUNNEL_GENEVE,
1425                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
1426                                 RTE_PTYPE_TUNNEL_GRE,
1427                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
1428                                 RTE_PTYPE_TUNNEL_VXLAN,
1429                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
1430                                 RTE_PTYPE_TUNNEL_GENEVE,
1431                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
1432                                 RTE_PTYPE_TUNNEL_GRE,
1433                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
1434                                 RTE_PTYPE_TUNNEL_VXLAN,
1435                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
1436                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1437                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
1438                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1439                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
1440                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1441                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
1442                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1443                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
1444                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1445                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
1446                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1447                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
1448                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1449                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
1450                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1451                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
1452                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1453                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
1454                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1455                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
1456                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1457                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
1458                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1459         };
1460
1461         /* Cover bits[4-0] to include tunn_type and next protocol */
1462         val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
1463                 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
1464                 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
1465                 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
1466
1467         if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
1468                 return ptype_tunn_lkup_tbl[val];
1469         else
1470                 return RTE_PTYPE_UNKNOWN;
1471 }
1472
1473 static inline int
1474 qede_process_sg_pkts(void *p_rxq,  struct rte_mbuf *rx_mb,
1475                      uint8_t num_segs, uint16_t pkt_len)
1476 {
1477         struct qede_rx_queue *rxq = p_rxq;
1478         struct qede_dev *qdev = rxq->qdev;
1479         register struct rte_mbuf *seg1 = NULL;
1480         register struct rte_mbuf *seg2 = NULL;
1481         uint16_t sw_rx_index;
1482         uint16_t cur_size;
1483
1484         seg1 = rx_mb;
1485         while (num_segs) {
1486                 cur_size = pkt_len > rxq->rx_buf_size ? rxq->rx_buf_size :
1487                                                         pkt_len;
1488                 if (unlikely(!cur_size)) {
1489                         PMD_RX_LOG(ERR, rxq, "Length is 0 while %u BDs"
1490                                    " left for mapping jumbo\n", num_segs);
1491                         qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
1492                         return -EINVAL;
1493                 }
1494                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1495                 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
1496                 qede_rx_bd_ring_consume(rxq);
1497                 pkt_len -= cur_size;
1498                 seg2->data_len = cur_size;
1499                 seg1->next = seg2;
1500                 seg1 = seg1->next;
1501                 num_segs--;
1502                 rxq->rx_segs++;
1503         }
1504
1505         return 0;
1506 }
1507
1508 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1509 static inline void
1510 print_rx_bd_info(struct rte_mbuf *m, struct qede_rx_queue *rxq,
1511                  uint8_t bitfield)
1512 {
1513         PMD_RX_LOG(INFO, rxq,
1514                 "len 0x%04x bf 0x%04x hash_val 0x%x"
1515                 " ol_flags 0x%04lx l2=%s l3=%s l4=%s tunn=%s"
1516                 " inner_l2=%s inner_l3=%s inner_l4=%s\n",
1517                 m->data_len, bitfield, m->hash.rss,
1518                 (unsigned long)m->ol_flags,
1519                 rte_get_ptype_l2_name(m->packet_type),
1520                 rte_get_ptype_l3_name(m->packet_type),
1521                 rte_get_ptype_l4_name(m->packet_type),
1522                 rte_get_ptype_tunnel_name(m->packet_type),
1523                 rte_get_ptype_inner_l2_name(m->packet_type),
1524                 rte_get_ptype_inner_l3_name(m->packet_type),
1525                 rte_get_ptype_inner_l4_name(m->packet_type));
1526 }
1527 #endif
1528
1529 uint16_t
1530 qede_recv_pkts_regular(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1531 {
1532         struct eth_fast_path_rx_reg_cqe *fp_cqe = NULL;
1533         register struct rte_mbuf *rx_mb = NULL;
1534         struct qede_rx_queue *rxq = p_rxq;
1535         struct qede_dev *qdev = rxq->qdev;
1536         struct ecore_dev *edev = &qdev->edev;
1537         union eth_rx_cqe *cqe;
1538         uint64_t ol_flags;
1539         enum eth_rx_cqe_type cqe_type;
1540         int rss_enable = qdev->rss_enable;
1541         int rx_alloc_count = 0;
1542         uint32_t packet_type;
1543         uint32_t rss_hash;
1544         uint16_t vlan_tci, port_id;
1545         uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index, num_rx_bds;
1546         uint16_t rx_pkt = 0;
1547         uint16_t pkt_len = 0;
1548         uint16_t len; /* Length of first BD */
1549         uint16_t preload_idx;
1550         uint16_t parse_flag;
1551 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1552         uint8_t bitfield_val;
1553 #endif
1554         uint8_t offset, flags, bd_num;
1555
1556
1557         /* Allocate buffers that we used in previous loop */
1558         if (rxq->rx_alloc_count) {
1559                 if (unlikely(qede_alloc_rx_bulk_mbufs(rxq,
1560                              rxq->rx_alloc_count))) {
1561                         struct rte_eth_dev *dev;
1562
1563                         PMD_RX_LOG(ERR, rxq,
1564                                    "New buffer allocation failed,"
1565                                    "dropping incoming packetn");
1566                         dev = &rte_eth_devices[rxq->port_id];
1567                         dev->data->rx_mbuf_alloc_failed +=
1568                                                         rxq->rx_alloc_count;
1569                         rxq->rx_alloc_errors += rxq->rx_alloc_count;
1570                         return 0;
1571                 }
1572                 qede_update_rx_prod(qdev, rxq);
1573                 rxq->rx_alloc_count = 0;
1574         }
1575
1576         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
1577         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1578
1579         rte_rmb();
1580
1581         if (hw_comp_cons == sw_comp_cons)
1582                 return 0;
1583
1584         num_rx_bds =  NUM_RX_BDS(rxq);
1585         port_id = rxq->port_id;
1586
1587         while (sw_comp_cons != hw_comp_cons) {
1588                 ol_flags = 0;
1589                 packet_type = RTE_PTYPE_UNKNOWN;
1590                 vlan_tci = 0;
1591                 rss_hash = 0;
1592
1593                 /* Get the CQE from the completion ring */
1594                 cqe =
1595                     (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
1596                 cqe_type = cqe->fast_path_regular.type;
1597                 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type);
1598
1599                 if (likely(cqe_type == ETH_RX_CQE_TYPE_REGULAR)) {
1600                         fp_cqe = &cqe->fast_path_regular;
1601                 } else {
1602                         if (cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH) {
1603                                 PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n");
1604                                 ecore_eth_cqe_completion
1605                                         (&edev->hwfns[rxq->queue_id %
1606                                                       edev->num_hwfns],
1607                                          (struct eth_slow_path_rx_cqe *)cqe);
1608                         }
1609                         goto next_cqe;
1610                 }
1611
1612                 /* Get the data from the SW ring */
1613                 sw_rx_index = rxq->sw_rx_cons & num_rx_bds;
1614                 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
1615                 assert(rx_mb != NULL);
1616
1617                 parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);
1618                 offset = fp_cqe->placement_offset;
1619                 len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
1620                 pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1621                 vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1622                 rss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash);
1623                 bd_num = fp_cqe->bd_num;
1624 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1625                 bitfield_val = fp_cqe->bitfields;
1626 #endif
1627
1628                 if (unlikely(qede_tunn_exist(parse_flag))) {
1629                         PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n");
1630                         if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1631                                 PMD_RX_LOG(ERR, rxq,
1632                                             "L4 csum failed, flags = 0x%x\n",
1633                                             parse_flag);
1634                                 rxq->rx_hw_errors++;
1635                                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1636                         } else {
1637                                 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1638                         }
1639
1640                         if (unlikely(qede_check_tunn_csum_l3(parse_flag))) {
1641                                 PMD_RX_LOG(ERR, rxq,
1642                                         "Outer L3 csum failed, flags = 0x%x\n",
1643                                         parse_flag);
1644                                 rxq->rx_hw_errors++;
1645                                 ol_flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
1646                         } else {
1647                                 ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1648                         }
1649
1650                         flags = fp_cqe->tunnel_pars_flags.flags;
1651
1652                         /* Tunnel_type */
1653                         packet_type =
1654                                 qede_rx_cqe_to_tunn_pkt_type(flags);
1655
1656                         /* Inner header */
1657                         packet_type |=
1658                               qede_rx_cqe_to_pkt_type_inner(parse_flag);
1659
1660                         /* Outer L3/L4 types is not available in CQE */
1661                         packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1662
1663                         /* Outer L3/L4 types is not available in CQE.
1664                          * Need to add offset to parse correctly,
1665                          */
1666                         rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1667                         packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1668                 } else {
1669                         packet_type |= qede_rx_cqe_to_pkt_type(parse_flag);
1670                 }
1671
1672                 /* Common handling for non-tunnel packets and for inner
1673                  * headers in the case of tunnel.
1674                  */
1675                 if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1676                         PMD_RX_LOG(ERR, rxq,
1677                                     "L4 csum failed, flags = 0x%x\n",
1678                                     parse_flag);
1679                         rxq->rx_hw_errors++;
1680                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
1681                 } else {
1682                         ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1683                 }
1684                 if (unlikely(qede_check_notunn_csum_l3(rx_mb, parse_flag))) {
1685                         PMD_RX_LOG(ERR, rxq, "IP csum failed, flags = 0x%x\n",
1686                                    parse_flag);
1687                         rxq->rx_hw_errors++;
1688                         ol_flags |= PKT_RX_IP_CKSUM_BAD;
1689                 } else {
1690                         ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1691                 }
1692
1693                 if (unlikely(CQE_HAS_VLAN(parse_flag) ||
1694                              CQE_HAS_OUTER_VLAN(parse_flag))) {
1695                         /* Note: FW doesn't indicate Q-in-Q packet */
1696                         ol_flags |= PKT_RX_VLAN;
1697                         if (qdev->vlan_strip_flg) {
1698                                 ol_flags |= PKT_RX_VLAN_STRIPPED;
1699                                 rx_mb->vlan_tci = vlan_tci;
1700                         }
1701                 }
1702
1703                 if (rss_enable) {
1704                         ol_flags |= PKT_RX_RSS_HASH;
1705                         rx_mb->hash.rss = rss_hash;
1706                 }
1707
1708                 rx_alloc_count++;
1709                 qede_rx_bd_ring_consume(rxq);
1710
1711                 /* Prefetch next mbuf while processing current one. */
1712                 preload_idx = rxq->sw_rx_cons & num_rx_bds;
1713                 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1714
1715                 /* Update rest of the MBUF fields */
1716                 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1717                 rx_mb->port = port_id;
1718                 rx_mb->ol_flags = ol_flags;
1719                 rx_mb->data_len = len;
1720                 rx_mb->packet_type = packet_type;
1721 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1722                 print_rx_bd_info(rx_mb, rxq, bitfield_val);
1723 #endif
1724                 rx_mb->nb_segs = bd_num;
1725                 rx_mb->pkt_len = pkt_len;
1726
1727                 rx_pkts[rx_pkt] = rx_mb;
1728                 rx_pkt++;
1729
1730 next_cqe:
1731                 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1732                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1733                 if (rx_pkt == nb_pkts) {
1734                         PMD_RX_LOG(DEBUG, rxq,
1735                                    "Budget reached nb_pkts=%u received=%u",
1736                                    rx_pkt, nb_pkts);
1737                         break;
1738                 }
1739         }
1740
1741         /* Request number of bufferes to be allocated in next loop */
1742         rxq->rx_alloc_count = rx_alloc_count;
1743
1744         rxq->rcv_pkts += rx_pkt;
1745         rxq->rx_segs += rx_pkt;
1746         PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
1747
1748         return rx_pkt;
1749 }
1750
1751 uint16_t
1752 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1753 {
1754         struct qede_rx_queue *rxq = p_rxq;
1755         struct qede_dev *qdev = rxq->qdev;
1756         struct ecore_dev *edev = &qdev->edev;
1757         uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
1758         uint16_t rx_pkt = 0;
1759         union eth_rx_cqe *cqe;
1760         struct eth_fast_path_rx_reg_cqe *fp_cqe = NULL;
1761         register struct rte_mbuf *rx_mb = NULL;
1762         register struct rte_mbuf *seg1 = NULL;
1763         enum eth_rx_cqe_type cqe_type;
1764         uint16_t pkt_len = 0; /* Sum of all BD segments */
1765         uint16_t len; /* Length of first BD */
1766         uint8_t num_segs = 1;
1767         uint16_t preload_idx;
1768         uint16_t parse_flag;
1769 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1770         uint8_t bitfield_val;
1771 #endif
1772         uint8_t tunn_parse_flag;
1773         struct eth_fast_path_rx_tpa_start_cqe *cqe_start_tpa;
1774         uint64_t ol_flags;
1775         uint32_t packet_type;
1776         uint16_t vlan_tci;
1777         bool tpa_start_flg;
1778         uint8_t offset, tpa_agg_idx, flags;
1779         struct qede_agg_info *tpa_info = NULL;
1780         uint32_t rss_hash;
1781         int rx_alloc_count = 0;
1782
1783
1784         /* Allocate buffers that we used in previous loop */
1785         if (rxq->rx_alloc_count) {
1786                 if (unlikely(qede_alloc_rx_bulk_mbufs(rxq,
1787                              rxq->rx_alloc_count))) {
1788                         struct rte_eth_dev *dev;
1789
1790                         PMD_RX_LOG(ERR, rxq,
1791                                    "New buffer allocation failed,"
1792                                    "dropping incoming packetn");
1793                         dev = &rte_eth_devices[rxq->port_id];
1794                         dev->data->rx_mbuf_alloc_failed +=
1795                                                         rxq->rx_alloc_count;
1796                         rxq->rx_alloc_errors += rxq->rx_alloc_count;
1797                         return 0;
1798                 }
1799                 qede_update_rx_prod(qdev, rxq);
1800                 rxq->rx_alloc_count = 0;
1801         }
1802
1803         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
1804         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1805
1806         rte_rmb();
1807
1808         if (hw_comp_cons == sw_comp_cons)
1809                 return 0;
1810
1811         while (sw_comp_cons != hw_comp_cons) {
1812                 ol_flags = 0;
1813                 packet_type = RTE_PTYPE_UNKNOWN;
1814                 vlan_tci = 0;
1815                 tpa_start_flg = false;
1816                 rss_hash = 0;
1817
1818                 /* Get the CQE from the completion ring */
1819                 cqe =
1820                     (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
1821                 cqe_type = cqe->fast_path_regular.type;
1822                 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type);
1823
1824                 switch (cqe_type) {
1825                 case ETH_RX_CQE_TYPE_REGULAR:
1826                         fp_cqe = &cqe->fast_path_regular;
1827                 break;
1828                 case ETH_RX_CQE_TYPE_TPA_START:
1829                         cqe_start_tpa = &cqe->fast_path_tpa_start;
1830                         tpa_info = &rxq->tpa_info[cqe_start_tpa->tpa_agg_index];
1831                         tpa_start_flg = true;
1832                         /* Mark it as LRO packet */
1833                         ol_flags |= PKT_RX_LRO;
1834                         /* In split mode,  seg_len is same as len_on_first_bd
1835                          * and bw_ext_bd_len_list will be empty since there are
1836                          * no additional buffers
1837                          */
1838                         PMD_RX_LOG(INFO, rxq,
1839                          "TPA start[%d] - len_on_first_bd %d header %d"
1840                          " [bd_list[0] %d], [seg_len %d]\n",
1841                          cqe_start_tpa->tpa_agg_index,
1842                          rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd),
1843                          cqe_start_tpa->header_len,
1844                          rte_le_to_cpu_16(cqe_start_tpa->bw_ext_bd_len_list[0]),
1845                          rte_le_to_cpu_16(cqe_start_tpa->seg_len));
1846
1847                 break;
1848                 case ETH_RX_CQE_TYPE_TPA_CONT:
1849                         qede_rx_process_tpa_cont_cqe(qdev, rxq,
1850                                                      &cqe->fast_path_tpa_cont);
1851                         goto next_cqe;
1852                 case ETH_RX_CQE_TYPE_TPA_END:
1853                         qede_rx_process_tpa_end_cqe(qdev, rxq,
1854                                                     &cqe->fast_path_tpa_end);
1855                         tpa_agg_idx = cqe->fast_path_tpa_end.tpa_agg_index;
1856                         tpa_info = &rxq->tpa_info[tpa_agg_idx];
1857                         rx_mb = rxq->tpa_info[tpa_agg_idx].tpa_head;
1858                         goto tpa_end;
1859                 case ETH_RX_CQE_TYPE_SLOW_PATH:
1860                         PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n");
1861                         ecore_eth_cqe_completion(
1862                                 &edev->hwfns[rxq->queue_id % edev->num_hwfns],
1863                                 (struct eth_slow_path_rx_cqe *)cqe);
1864                         /* fall-thru */
1865                 default:
1866                         goto next_cqe;
1867                 }
1868
1869                 /* Get the data from the SW ring */
1870                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1871                 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
1872                 assert(rx_mb != NULL);
1873
1874                 /* Handle regular CQE or TPA start CQE */
1875                 if (!tpa_start_flg) {
1876                         parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);
1877                         offset = fp_cqe->placement_offset;
1878                         len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
1879                         pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1880                         vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1881                         rss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash);
1882 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1883                         bitfield_val = fp_cqe->bitfields;
1884 #endif
1885                 } else {
1886                         parse_flag =
1887                             rte_le_to_cpu_16(cqe_start_tpa->pars_flags.flags);
1888                         offset = cqe_start_tpa->placement_offset;
1889                         /* seg_len = len_on_first_bd */
1890                         len = rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd);
1891                         vlan_tci = rte_le_to_cpu_16(cqe_start_tpa->vlan_tag);
1892 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1893                         bitfield_val = cqe_start_tpa->bitfields;
1894 #endif
1895                         rss_hash = rte_le_to_cpu_32(cqe_start_tpa->rss_hash);
1896                 }
1897                 if (qede_tunn_exist(parse_flag)) {
1898                         PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n");
1899                         if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1900                                 PMD_RX_LOG(ERR, rxq,
1901                                             "L4 csum failed, flags = 0x%x\n",
1902                                             parse_flag);
1903                                 rxq->rx_hw_errors++;
1904                                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1905                         } else {
1906                                 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1907                         }
1908
1909                         if (unlikely(qede_check_tunn_csum_l3(parse_flag))) {
1910                                 PMD_RX_LOG(ERR, rxq,
1911                                         "Outer L3 csum failed, flags = 0x%x\n",
1912                                         parse_flag);
1913                                   rxq->rx_hw_errors++;
1914                                   ol_flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
1915                         } else {
1916                                   ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1917                         }
1918
1919                         if (tpa_start_flg)
1920                                 flags = cqe_start_tpa->tunnel_pars_flags.flags;
1921                         else
1922                                 flags = fp_cqe->tunnel_pars_flags.flags;
1923                         tunn_parse_flag = flags;
1924
1925                         /* Tunnel_type */
1926                         packet_type =
1927                                 qede_rx_cqe_to_tunn_pkt_type(tunn_parse_flag);
1928
1929                         /* Inner header */
1930                         packet_type |=
1931                               qede_rx_cqe_to_pkt_type_inner(parse_flag);
1932
1933                         /* Outer L3/L4 types is not available in CQE */
1934                         packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1935
1936                         /* Outer L3/L4 types is not available in CQE.
1937                          * Need to add offset to parse correctly,
1938                          */
1939                         rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1940                         packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1941                 } else {
1942                         packet_type |= qede_rx_cqe_to_pkt_type(parse_flag);
1943                 }
1944
1945                 /* Common handling for non-tunnel packets and for inner
1946                  * headers in the case of tunnel.
1947                  */
1948                 if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1949                         PMD_RX_LOG(ERR, rxq,
1950                                     "L4 csum failed, flags = 0x%x\n",
1951                                     parse_flag);
1952                         rxq->rx_hw_errors++;
1953                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
1954                 } else {
1955                         ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1956                 }
1957                 if (unlikely(qede_check_notunn_csum_l3(rx_mb, parse_flag))) {
1958                         PMD_RX_LOG(ERR, rxq, "IP csum failed, flags = 0x%x\n",
1959                                    parse_flag);
1960                         rxq->rx_hw_errors++;
1961                         ol_flags |= PKT_RX_IP_CKSUM_BAD;
1962                 } else {
1963                         ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1964                 }
1965
1966                 if (CQE_HAS_VLAN(parse_flag) ||
1967                     CQE_HAS_OUTER_VLAN(parse_flag)) {
1968                         /* Note: FW doesn't indicate Q-in-Q packet */
1969                         ol_flags |= PKT_RX_VLAN;
1970                         if (qdev->vlan_strip_flg) {
1971                                 ol_flags |= PKT_RX_VLAN_STRIPPED;
1972                                 rx_mb->vlan_tci = vlan_tci;
1973                         }
1974                 }
1975
1976                 /* RSS Hash */
1977                 if (qdev->rss_enable) {
1978                         ol_flags |= PKT_RX_RSS_HASH;
1979                         rx_mb->hash.rss = rss_hash;
1980                 }
1981
1982                 rx_alloc_count++;
1983                 qede_rx_bd_ring_consume(rxq);
1984
1985                 if (!tpa_start_flg && fp_cqe->bd_num > 1) {
1986                         PMD_RX_LOG(DEBUG, rxq, "Jumbo-over-BD packet: %02x BDs"
1987                                    " len on first: %04x Total Len: %04x",
1988                                    fp_cqe->bd_num, len, pkt_len);
1989                         num_segs = fp_cqe->bd_num - 1;
1990                         seg1 = rx_mb;
1991                         if (qede_process_sg_pkts(p_rxq, seg1, num_segs,
1992                                                  pkt_len - len))
1993                                 goto next_cqe;
1994
1995                         rx_alloc_count += num_segs;
1996                         rxq->rx_segs += num_segs;
1997                 }
1998                 rxq->rx_segs++; /* for the first segment */
1999
2000                 /* Prefetch next mbuf while processing current one. */
2001                 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
2002                 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
2003
2004                 /* Update rest of the MBUF fields */
2005                 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
2006                 rx_mb->port = rxq->port_id;
2007                 rx_mb->ol_flags = ol_flags;
2008                 rx_mb->data_len = len;
2009                 rx_mb->packet_type = packet_type;
2010 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
2011                 print_rx_bd_info(rx_mb, rxq, bitfield_val);
2012 #endif
2013                 if (!tpa_start_flg) {
2014                         rx_mb->nb_segs = fp_cqe->bd_num;
2015                         rx_mb->pkt_len = pkt_len;
2016                 } else {
2017                         /* store ref to the updated mbuf */
2018                         tpa_info->tpa_head = rx_mb;
2019                         tpa_info->tpa_tail = tpa_info->tpa_head;
2020                 }
2021                 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
2022 tpa_end:
2023                 if (!tpa_start_flg) {
2024                         rx_pkts[rx_pkt] = rx_mb;
2025                         rx_pkt++;
2026                 }
2027 next_cqe:
2028                 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
2029                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
2030                 if (rx_pkt == nb_pkts) {
2031                         PMD_RX_LOG(DEBUG, rxq,
2032                                    "Budget reached nb_pkts=%u received=%u",
2033                                    rx_pkt, nb_pkts);
2034                         break;
2035                 }
2036         }
2037
2038         /* Request number of bufferes to be allocated in next loop */
2039         rxq->rx_alloc_count = rx_alloc_count;
2040
2041         rxq->rcv_pkts += rx_pkt;
2042
2043         PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
2044
2045         return rx_pkt;
2046 }
2047
2048 uint16_t
2049 qede_recv_pkts_cmt(void *p_fp_cmt, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2050 {
2051         struct qede_fastpath_cmt *fp_cmt = p_fp_cmt;
2052         uint16_t eng0_pkts, eng1_pkts;
2053
2054         eng0_pkts = nb_pkts / 2;
2055
2056         eng0_pkts = qede_recv_pkts(fp_cmt->fp0->rxq, rx_pkts, eng0_pkts);
2057
2058         eng1_pkts = nb_pkts - eng0_pkts;
2059
2060         eng1_pkts = qede_recv_pkts(fp_cmt->fp1->rxq, rx_pkts + eng0_pkts,
2061                                    eng1_pkts);
2062
2063         return eng0_pkts + eng1_pkts;
2064 }
2065
2066 /* Populate scatter gather buffer descriptor fields */
2067 static inline uint16_t
2068 qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg,
2069                   struct eth_tx_2nd_bd **bd2, struct eth_tx_3rd_bd **bd3,
2070                   uint16_t start_seg)
2071 {
2072         struct qede_tx_queue *txq = p_txq;
2073         struct eth_tx_bd *tx_bd = NULL;
2074         dma_addr_t mapping;
2075         uint16_t nb_segs = 0;
2076
2077         /* Check for scattered buffers */
2078         while (m_seg) {
2079                 if (start_seg == 0) {
2080                         if (!*bd2) {
2081                                 *bd2 = (struct eth_tx_2nd_bd *)
2082                                         ecore_chain_produce(&txq->tx_pbl);
2083                                 memset(*bd2, 0, sizeof(struct eth_tx_2nd_bd));
2084                                 nb_segs++;
2085                         }
2086                         mapping = rte_mbuf_data_iova(m_seg);
2087                         QEDE_BD_SET_ADDR_LEN(*bd2, mapping, m_seg->data_len);
2088                         PMD_TX_LOG(DEBUG, txq, "BD2 len %04x", m_seg->data_len);
2089                 } else if (start_seg == 1) {
2090                         if (!*bd3) {
2091                                 *bd3 = (struct eth_tx_3rd_bd *)
2092                                         ecore_chain_produce(&txq->tx_pbl);
2093                                 memset(*bd3, 0, sizeof(struct eth_tx_3rd_bd));
2094                                 nb_segs++;
2095                         }
2096                         mapping = rte_mbuf_data_iova(m_seg);
2097                         QEDE_BD_SET_ADDR_LEN(*bd3, mapping, m_seg->data_len);
2098                         PMD_TX_LOG(DEBUG, txq, "BD3 len %04x", m_seg->data_len);
2099                 } else {
2100                         tx_bd = (struct eth_tx_bd *)
2101                                 ecore_chain_produce(&txq->tx_pbl);
2102                         memset(tx_bd, 0, sizeof(*tx_bd));
2103                         nb_segs++;
2104                         mapping = rte_mbuf_data_iova(m_seg);
2105                         QEDE_BD_SET_ADDR_LEN(tx_bd, mapping, m_seg->data_len);
2106                         PMD_TX_LOG(DEBUG, txq, "BD len %04x", m_seg->data_len);
2107                 }
2108                 start_seg++;
2109                 m_seg = m_seg->next;
2110         }
2111
2112         /* Return total scattered buffers */
2113         return nb_segs;
2114 }
2115
2116 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2117 static inline void
2118 print_tx_bd_info(struct qede_tx_queue *txq,
2119                  struct eth_tx_1st_bd *bd1,
2120                  struct eth_tx_2nd_bd *bd2,
2121                  struct eth_tx_3rd_bd *bd3,
2122                  uint64_t tx_ol_flags)
2123 {
2124         char ol_buf[256] = { 0 }; /* for verbose prints */
2125
2126         if (bd1)
2127                 PMD_TX_LOG(INFO, txq,
2128                    "BD1: nbytes=0x%04x nbds=0x%04x bd_flags=0x%04x bf=0x%04x",
2129                    rte_cpu_to_le_16(bd1->nbytes), bd1->data.nbds,
2130                    bd1->data.bd_flags.bitfields,
2131                    rte_cpu_to_le_16(bd1->data.bitfields));
2132         if (bd2)
2133                 PMD_TX_LOG(INFO, txq,
2134                    "BD2: nbytes=0x%04x bf1=0x%04x bf2=0x%04x tunn_ip=0x%04x\n",
2135                    rte_cpu_to_le_16(bd2->nbytes), bd2->data.bitfields1,
2136                    bd2->data.bitfields2, bd2->data.tunn_ip_size);
2137         if (bd3)
2138                 PMD_TX_LOG(INFO, txq,
2139                    "BD3: nbytes=0x%04x bf=0x%04x MSS=0x%04x "
2140                    "tunn_l4_hdr_start_offset_w=0x%04x tunn_hdr_size=0x%04x\n",
2141                    rte_cpu_to_le_16(bd3->nbytes),
2142                    rte_cpu_to_le_16(bd3->data.bitfields),
2143                    rte_cpu_to_le_16(bd3->data.lso_mss),
2144                    bd3->data.tunn_l4_hdr_start_offset_w,
2145                    bd3->data.tunn_hdr_size_w);
2146
2147         rte_get_tx_ol_flag_list(tx_ol_flags, ol_buf, sizeof(ol_buf));
2148         PMD_TX_LOG(INFO, txq, "TX offloads = %s\n", ol_buf);
2149 }
2150 #endif
2151
2152 /* TX prepare to check packets meets TX conditions */
2153 uint16_t
2154 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2155 qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
2156                     uint16_t nb_pkts)
2157 {
2158         struct qede_tx_queue *txq = p_txq;
2159 #else
2160 qede_xmit_prep_pkts(__rte_unused void *p_txq, struct rte_mbuf **tx_pkts,
2161                     uint16_t nb_pkts)
2162 {
2163 #endif
2164         uint64_t ol_flags;
2165         struct rte_mbuf *m;
2166         uint16_t i;
2167 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2168         int ret;
2169 #endif
2170
2171         for (i = 0; i < nb_pkts; i++) {
2172                 m = tx_pkts[i];
2173                 ol_flags = m->ol_flags;
2174                 if (ol_flags & PKT_TX_TCP_SEG) {
2175                         if (m->nb_segs >= ETH_TX_MAX_BDS_PER_LSO_PACKET) {
2176                                 rte_errno = EINVAL;
2177                                 break;
2178                         }
2179                         /* TBD: confirm its ~9700B for both ? */
2180                         if (m->tso_segsz > ETH_TX_MAX_NON_LSO_PKT_LEN) {
2181                                 rte_errno = EINVAL;
2182                                 break;
2183                         }
2184                 } else {
2185                         if (m->nb_segs >= ETH_TX_MAX_BDS_PER_NON_LSO_PACKET) {
2186                                 rte_errno = EINVAL;
2187                                 break;
2188                         }
2189                 }
2190                 if (ol_flags & QEDE_TX_OFFLOAD_NOTSUP_MASK) {
2191                         /* We support only limited tunnel protocols */
2192                         if (ol_flags & PKT_TX_TUNNEL_MASK) {
2193                                 uint64_t temp;
2194
2195                                 temp = ol_flags & PKT_TX_TUNNEL_MASK;
2196                                 if (temp == PKT_TX_TUNNEL_VXLAN ||
2197                                     temp == PKT_TX_TUNNEL_GENEVE ||
2198                                     temp == PKT_TX_TUNNEL_MPLSINUDP ||
2199                                     temp == PKT_TX_TUNNEL_GRE)
2200                                         continue;
2201                         }
2202
2203                         rte_errno = ENOTSUP;
2204                         break;
2205                 }
2206
2207 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2208                 ret = rte_validate_tx_offload(m);
2209                 if (ret != 0) {
2210                         rte_errno = -ret;
2211                         break;
2212                 }
2213 #endif
2214         }
2215
2216 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2217         if (unlikely(i != nb_pkts))
2218                 PMD_TX_LOG(ERR, txq, "TX prepare failed for %u\n",
2219                            nb_pkts - i);
2220 #endif
2221         return i;
2222 }
2223
2224 #define MPLSINUDP_HDR_SIZE                      (12)
2225
2226 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2227 static inline void
2228 qede_mpls_tunn_tx_sanity_check(struct rte_mbuf *mbuf,
2229                                struct qede_tx_queue *txq)
2230 {
2231         if (((mbuf->outer_l2_len + mbuf->outer_l3_len) / 2) > 0xff)
2232                 PMD_TX_LOG(ERR, txq, "tunn_l4_hdr_start_offset overflow\n");
2233         if (((mbuf->outer_l2_len + mbuf->outer_l3_len +
2234                 MPLSINUDP_HDR_SIZE) / 2) > 0xff)
2235                 PMD_TX_LOG(ERR, txq, "tunn_hdr_size overflow\n");
2236         if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE) / 2) >
2237                 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK)
2238                 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
2239         if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2) >
2240                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
2241                 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
2242 }
2243 #endif
2244
2245 uint16_t
2246 qede_xmit_pkts_regular(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2247 {
2248         struct qede_tx_queue *txq = p_txq;
2249         struct qede_dev *qdev = txq->qdev;
2250         struct ecore_dev *edev = &qdev->edev;
2251         struct eth_tx_1st_bd *bd1;
2252         struct eth_tx_2nd_bd *bd2;
2253         struct eth_tx_3rd_bd *bd3;
2254         struct rte_mbuf *m_seg = NULL;
2255         struct rte_mbuf *mbuf;
2256         struct rte_mbuf **sw_tx_ring;
2257         uint16_t nb_tx_pkts;
2258         uint16_t bd_prod;
2259         uint16_t idx;
2260         uint16_t nb_frags = 0;
2261         uint16_t nb_pkt_sent = 0;
2262         uint8_t nbds;
2263         uint64_t tx_ol_flags;
2264         /* BD1 */
2265         uint16_t bd1_bf;
2266         uint8_t bd1_bd_flags_bf;
2267
2268         if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
2269                 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
2270                            nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
2271                 qede_process_tx_compl(edev, txq);
2272         }
2273
2274         nb_tx_pkts  = nb_pkts;
2275         bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2276         sw_tx_ring = txq->sw_tx_ring;
2277
2278         while (nb_tx_pkts--) {
2279                 /* Init flags/values */
2280                 nbds = 0;
2281                 bd1 = NULL;
2282                 bd2 = NULL;
2283                 bd3 = NULL;
2284                 bd1_bf = 0;
2285                 bd1_bd_flags_bf = 0;
2286                 nb_frags = 0;
2287
2288                 mbuf = *tx_pkts++;
2289                 assert(mbuf);
2290
2291
2292                 /* Check minimum TX BDS availability against available BDs */
2293                 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs))
2294                         break;
2295
2296                 tx_ol_flags = mbuf->ol_flags;
2297                 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
2298
2299                 if (unlikely(txq->nb_tx_avail <
2300                                 ETH_TX_MIN_BDS_PER_NON_LSO_PKT))
2301                         break;
2302                 bd1_bf |=
2303                        (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
2304                         << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
2305
2306                 /* Offload the IP checksum in the hardware */
2307                 if (tx_ol_flags & PKT_TX_IP_CKSUM)
2308                         bd1_bd_flags_bf |=
2309                                 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
2310
2311                 /* L4 checksum offload (tcp or udp) */
2312                 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
2313                     (tx_ol_flags & (PKT_TX_UDP_CKSUM | PKT_TX_TCP_CKSUM)))
2314                         bd1_bd_flags_bf |=
2315                                 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
2316
2317                 /* Fill the entry in the SW ring and the BDs in the FW ring */
2318                 idx = TX_PROD(txq);
2319                 sw_tx_ring[idx] = mbuf;
2320
2321                 /* BD1 */
2322                 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
2323                 memset(bd1, 0, sizeof(struct eth_tx_1st_bd));
2324                 nbds++;
2325
2326                 /* Map MBUF linear data for DMA and set in the BD1 */
2327                 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2328                                      mbuf->data_len);
2329                 bd1->data.bitfields = rte_cpu_to_le_16(bd1_bf);
2330                 bd1->data.bd_flags.bitfields = bd1_bd_flags_bf;
2331
2332                 /* Handle fragmented MBUF */
2333                 if (unlikely(mbuf->nb_segs > 1)) {
2334                         m_seg = mbuf->next;
2335
2336                         /* Encode scatter gather buffer descriptors */
2337                         nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3,
2338                                                      nbds - 1);
2339                 }
2340
2341                 bd1->data.nbds = nbds + nb_frags;
2342
2343                 txq->nb_tx_avail -= bd1->data.nbds;
2344                 txq->sw_tx_prod++;
2345                 bd_prod =
2346                     rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2347 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2348                 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);
2349 #endif
2350                 nb_pkt_sent++;
2351                 txq->xmit_pkts++;
2352         }
2353
2354         /* Write value of prod idx into bd_prod */
2355         txq->tx_db.data.bd_prod = bd_prod;
2356         rte_wmb();
2357         rte_compiler_barrier();
2358         DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
2359         rte_wmb();
2360
2361         /* Check again for Tx completions */
2362         qede_process_tx_compl(edev, txq);
2363
2364         PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d",
2365                    nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());
2366
2367         return nb_pkt_sent;
2368 }
2369
2370 uint16_t
2371 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2372 {
2373         struct qede_tx_queue *txq = p_txq;
2374         struct qede_dev *qdev = txq->qdev;
2375         struct ecore_dev *edev = &qdev->edev;
2376         struct rte_mbuf *mbuf;
2377         struct rte_mbuf *m_seg = NULL;
2378         uint16_t nb_tx_pkts;
2379         uint16_t bd_prod;
2380         uint16_t idx;
2381         uint16_t nb_frags;
2382         uint16_t nb_pkt_sent = 0;
2383         uint8_t nbds;
2384         bool lso_flg;
2385         bool mplsoudp_flg;
2386         __rte_unused bool tunn_flg;
2387         bool tunn_ipv6_ext_flg;
2388         struct eth_tx_1st_bd *bd1;
2389         struct eth_tx_2nd_bd *bd2;
2390         struct eth_tx_3rd_bd *bd3;
2391         uint64_t tx_ol_flags;
2392         uint16_t hdr_size;
2393         /* BD1 */
2394         uint16_t bd1_bf;
2395         uint8_t bd1_bd_flags_bf;
2396         uint16_t vlan;
2397         /* BD2 */
2398         uint16_t bd2_bf1;
2399         uint16_t bd2_bf2;
2400         /* BD3 */
2401         uint16_t mss;
2402         uint16_t bd3_bf;
2403
2404         uint8_t tunn_l4_hdr_start_offset;
2405         uint8_t tunn_hdr_size;
2406         uint8_t inner_l2_hdr_size;
2407         uint16_t inner_l4_hdr_offset;
2408
2409         if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
2410                 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
2411                            nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
2412                 qede_process_tx_compl(edev, txq);
2413         }
2414
2415         nb_tx_pkts  = nb_pkts;
2416         bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2417         while (nb_tx_pkts--) {
2418                 /* Init flags/values */
2419                 tunn_flg = false;
2420                 lso_flg = false;
2421                 nbds = 0;
2422                 vlan = 0;
2423                 bd1 = NULL;
2424                 bd2 = NULL;
2425                 bd3 = NULL;
2426                 hdr_size = 0;
2427                 bd1_bf = 0;
2428                 bd1_bd_flags_bf = 0;
2429                 bd2_bf1 = 0;
2430                 bd2_bf2 = 0;
2431                 mss = 0;
2432                 bd3_bf = 0;
2433                 mplsoudp_flg = false;
2434                 tunn_ipv6_ext_flg = false;
2435                 tunn_hdr_size = 0;
2436                 tunn_l4_hdr_start_offset = 0;
2437
2438                 mbuf = *tx_pkts++;
2439                 assert(mbuf);
2440
2441                 /* Check minimum TX BDS availability against available BDs */
2442                 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs))
2443                         break;
2444
2445                 tx_ol_flags = mbuf->ol_flags;
2446                 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
2447
2448                 /* TX prepare would have already checked supported tunnel Tx
2449                  * offloads. Don't rely on pkt_type marked by Rx, instead use
2450                  * tx_ol_flags to decide.
2451                  */
2452                 tunn_flg = !!(tx_ol_flags & PKT_TX_TUNNEL_MASK);
2453
2454                 if (tunn_flg) {
2455                         /* Check against max which is Tunnel IPv6 + ext */
2456                         if (unlikely(txq->nb_tx_avail <
2457                                 ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT))
2458                                         break;
2459
2460                         /* First indicate its a tunnel pkt */
2461                         bd1_bf |= ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
2462                                   ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
2463                         /* Legacy FW had flipped behavior in regard to this bit
2464                          * i.e. it needed to set to prevent FW from touching
2465                          * encapsulated packets when it didn't need to.
2466                          */
2467                         if (unlikely(txq->is_legacy)) {
2468                                 bd1_bf ^= 1 <<
2469                                         ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
2470                         }
2471
2472                         /* Outer IP checksum offload */
2473                         if (tx_ol_flags & (PKT_TX_OUTER_IP_CKSUM |
2474                                            PKT_TX_OUTER_IPV4)) {
2475                                 bd1_bd_flags_bf |=
2476                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
2477                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
2478                         }
2479
2480                         /**
2481                          * Currently, only inner checksum offload in MPLS-in-UDP
2482                          * tunnel with one MPLS label is supported. Both outer
2483                          * and inner layers  lengths need to be provided in
2484                          * mbuf.
2485                          */
2486                         if ((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
2487                                                 PKT_TX_TUNNEL_MPLSINUDP) {
2488                                 mplsoudp_flg = true;
2489 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2490                                 qede_mpls_tunn_tx_sanity_check(mbuf, txq);
2491 #endif
2492                                 /* Outer L4 offset in two byte words */
2493                                 tunn_l4_hdr_start_offset =
2494                                   (mbuf->outer_l2_len + mbuf->outer_l3_len) / 2;
2495                                 /* Tunnel header size in two byte words */
2496                                 tunn_hdr_size = (mbuf->outer_l2_len +
2497                                                 mbuf->outer_l3_len +
2498                                                 MPLSINUDP_HDR_SIZE) / 2;
2499                                 /* Inner L2 header size in two byte words */
2500                                 inner_l2_hdr_size = (mbuf->l2_len -
2501                                                 MPLSINUDP_HDR_SIZE) / 2;
2502                                 /* Inner L4 header offset from the beggining
2503                                  * of inner packet in two byte words
2504                                  */
2505                                 inner_l4_hdr_offset = (mbuf->l2_len -
2506                                         MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2;
2507
2508                                 /* Inner L2 size and address type */
2509                                 bd2_bf1 |= (inner_l2_hdr_size &
2510                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK) <<
2511                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT;
2512                                 bd2_bf1 |= (UNICAST_ADDRESS &
2513                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK) <<
2514                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT;
2515                                 /* Treated as IPv6+Ext */
2516                                 bd2_bf1 |=
2517                                     1 << ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT;
2518
2519                                 /* Mark inner IPv6 if present */
2520                                 if (tx_ol_flags & PKT_TX_IPV6)
2521                                         bd2_bf1 |=
2522                                                 1 << ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT;
2523
2524                                 /* Inner L4 offsets */
2525                                 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
2526                                      (tx_ol_flags & (PKT_TX_UDP_CKSUM |
2527                                                         PKT_TX_TCP_CKSUM))) {
2528                                         /* Determines if BD3 is needed */
2529                                         tunn_ipv6_ext_flg = true;
2530                                         if ((tx_ol_flags & PKT_TX_L4_MASK) ==
2531                                                         PKT_TX_UDP_CKSUM) {
2532                                                 bd2_bf1 |=
2533                                                         1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
2534                                         }
2535
2536                                         /* TODO other pseudo checksum modes are
2537                                          * not supported
2538                                          */
2539                                         bd2_bf1 |=
2540                                         ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
2541                                         ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT;
2542                                         bd2_bf2 |= (inner_l4_hdr_offset &
2543                                                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK) <<
2544                                                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
2545                                 }
2546                         } /* End MPLSoUDP */
2547                 } /* End Tunnel handling */
2548
2549                 if (tx_ol_flags & PKT_TX_TCP_SEG) {
2550                         lso_flg = true;
2551                         if (unlikely(txq->nb_tx_avail <
2552                                                 ETH_TX_MIN_BDS_PER_LSO_PKT))
2553                                 break;
2554                         /* For LSO, packet header and payload must reside on
2555                          * buffers pointed by different BDs. Using BD1 for HDR
2556                          * and BD2 onwards for data.
2557                          */
2558                         hdr_size = mbuf->l2_len + mbuf->l3_len + mbuf->l4_len;
2559                         if (tunn_flg)
2560                                 hdr_size += mbuf->outer_l2_len +
2561                                             mbuf->outer_l3_len;
2562
2563                         bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT;
2564                         bd1_bd_flags_bf |=
2565                                         1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
2566                         /* PKT_TX_TCP_SEG implies PKT_TX_TCP_CKSUM */
2567                         bd1_bd_flags_bf |=
2568                                         1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
2569                         mss = rte_cpu_to_le_16(mbuf->tso_segsz);
2570                         /* Using one header BD */
2571                         bd3_bf |= rte_cpu_to_le_16(1 <<
2572                                         ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
2573                 } else {
2574                         if (unlikely(txq->nb_tx_avail <
2575                                         ETH_TX_MIN_BDS_PER_NON_LSO_PKT))
2576                                 break;
2577                         bd1_bf |=
2578                                (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
2579                                 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
2580                 }
2581
2582                 /* Descriptor based VLAN insertion */
2583                 if (tx_ol_flags & PKT_TX_VLAN_PKT) {
2584                         vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
2585                         bd1_bd_flags_bf |=
2586                             1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
2587                 }
2588
2589                 /* Offload the IP checksum in the hardware */
2590                 if (tx_ol_flags & PKT_TX_IP_CKSUM) {
2591                         bd1_bd_flags_bf |=
2592                                 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
2593                         /* There's no DPDK flag to request outer-L4 csum
2594                          * offload. But in the case of tunnel if inner L3 or L4
2595                          * csum offload is requested then we need to force
2596                          * recalculation of L4 tunnel header csum also.
2597                          */
2598                         if (tunn_flg && ((tx_ol_flags & PKT_TX_TUNNEL_MASK) !=
2599                                                         PKT_TX_TUNNEL_GRE)) {
2600                                 bd1_bd_flags_bf |=
2601                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
2602                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
2603                         }
2604                 }
2605
2606                 /* L4 checksum offload (tcp or udp) */
2607                 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
2608                     (tx_ol_flags & (PKT_TX_UDP_CKSUM | PKT_TX_TCP_CKSUM))) {
2609                         bd1_bd_flags_bf |=
2610                                 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
2611                         /* There's no DPDK flag to request outer-L4 csum
2612                          * offload. But in the case of tunnel if inner L3 or L4
2613                          * csum offload is requested then we need to force
2614                          * recalculation of L4 tunnel header csum also.
2615                          */
2616                         if (tunn_flg) {
2617                                 bd1_bd_flags_bf |=
2618                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
2619                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
2620                         }
2621                 }
2622
2623                 /* Fill the entry in the SW ring and the BDs in the FW ring */
2624                 idx = TX_PROD(txq);
2625                 txq->sw_tx_ring[idx] = mbuf;
2626
2627                 /* BD1 */
2628                 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
2629                 memset(bd1, 0, sizeof(struct eth_tx_1st_bd));
2630                 nbds++;
2631
2632                 /* Map MBUF linear data for DMA and set in the BD1 */
2633                 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2634                                      mbuf->data_len);
2635                 bd1->data.bitfields = rte_cpu_to_le_16(bd1_bf);
2636                 bd1->data.bd_flags.bitfields = bd1_bd_flags_bf;
2637                 bd1->data.vlan = vlan;
2638
2639                 if (lso_flg || mplsoudp_flg) {
2640                         bd2 = (struct eth_tx_2nd_bd *)ecore_chain_produce
2641                                                         (&txq->tx_pbl);
2642                         memset(bd2, 0, sizeof(struct eth_tx_2nd_bd));
2643                         nbds++;
2644
2645                         /* BD1 */
2646                         QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2647                                              hdr_size);
2648                         /* BD2 */
2649                         QEDE_BD_SET_ADDR_LEN(bd2, (hdr_size +
2650                                              rte_mbuf_data_iova(mbuf)),
2651                                              mbuf->data_len - hdr_size);
2652                         bd2->data.bitfields1 = rte_cpu_to_le_16(bd2_bf1);
2653                         if (mplsoudp_flg) {
2654                                 bd2->data.bitfields2 =
2655                                         rte_cpu_to_le_16(bd2_bf2);
2656                                 /* Outer L3 size */
2657                                 bd2->data.tunn_ip_size =
2658                                         rte_cpu_to_le_16(mbuf->outer_l3_len);
2659                         }
2660                         /* BD3 */
2661                         if (lso_flg || (mplsoudp_flg && tunn_ipv6_ext_flg)) {
2662                                 bd3 = (struct eth_tx_3rd_bd *)
2663                                         ecore_chain_produce(&txq->tx_pbl);
2664                                 memset(bd3, 0, sizeof(struct eth_tx_3rd_bd));
2665                                 nbds++;
2666                                 bd3->data.bitfields = rte_cpu_to_le_16(bd3_bf);
2667                                 if (lso_flg)
2668                                         bd3->data.lso_mss = mss;
2669                                 if (mplsoudp_flg) {
2670                                         bd3->data.tunn_l4_hdr_start_offset_w =
2671                                                 tunn_l4_hdr_start_offset;
2672                                         bd3->data.tunn_hdr_size_w =
2673                                                 tunn_hdr_size;
2674                                 }
2675                         }
2676                 }
2677
2678                 /* Handle fragmented MBUF */
2679                 m_seg = mbuf->next;
2680
2681                 /* Encode scatter gather buffer descriptors if required */
2682                 nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3, nbds - 1);
2683                 bd1->data.nbds = nbds + nb_frags;
2684
2685                 txq->nb_tx_avail -= bd1->data.nbds;
2686                 txq->sw_tx_prod++;
2687                 bd_prod =
2688                     rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2689 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2690                 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);
2691 #endif
2692                 nb_pkt_sent++;
2693                 txq->xmit_pkts++;
2694         }
2695
2696         /* Write value of prod idx into bd_prod */
2697         txq->tx_db.data.bd_prod = bd_prod;
2698         rte_wmb();
2699         rte_compiler_barrier();
2700         DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
2701         rte_wmb();
2702
2703         /* Check again for Tx completions */
2704         qede_process_tx_compl(edev, txq);
2705
2706         PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d",
2707                    nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());
2708
2709         return nb_pkt_sent;
2710 }
2711
2712 uint16_t
2713 qede_xmit_pkts_cmt(void *p_fp_cmt, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2714 {
2715         struct qede_fastpath_cmt *fp_cmt = p_fp_cmt;
2716         uint16_t eng0_pkts, eng1_pkts;
2717
2718         eng0_pkts = nb_pkts / 2;
2719
2720         eng0_pkts = qede_xmit_pkts(fp_cmt->fp0->txq, tx_pkts, eng0_pkts);
2721
2722         eng1_pkts = nb_pkts - eng0_pkts;
2723
2724         eng1_pkts = qede_xmit_pkts(fp_cmt->fp1->txq, tx_pkts + eng0_pkts,
2725                                    eng1_pkts);
2726
2727         return eng0_pkts + eng1_pkts;
2728 }
2729
2730 uint16_t
2731 qede_rxtx_pkts_dummy(__rte_unused void *p_rxq,
2732                      __rte_unused struct rte_mbuf **pkts,
2733                      __rte_unused uint16_t nb_pkts)
2734 {
2735         return 0;
2736 }
2737
2738
2739 /* this function does a fake walk through over completion queue
2740  * to calculate number of BDs used by HW.
2741  * At the end, it restores the state of completion queue.
2742  */
2743 static uint16_t
2744 qede_parse_fp_cqe(struct qede_rx_queue *rxq)
2745 {
2746         uint16_t hw_comp_cons, sw_comp_cons, bd_count = 0;
2747         union eth_rx_cqe *cqe, *orig_cqe = NULL;
2748
2749         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
2750         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
2751
2752         if (hw_comp_cons == sw_comp_cons)
2753                 return 0;
2754
2755         /* Get the CQE from the completion ring */
2756         cqe = (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
2757         orig_cqe = cqe;
2758
2759         while (sw_comp_cons != hw_comp_cons) {
2760                 switch (cqe->fast_path_regular.type) {
2761                 case ETH_RX_CQE_TYPE_REGULAR:
2762                         bd_count += cqe->fast_path_regular.bd_num;
2763                         break;
2764                 case ETH_RX_CQE_TYPE_TPA_END:
2765                         bd_count += cqe->fast_path_tpa_end.num_of_bds;
2766                         break;
2767                 default:
2768                         break;
2769                 }
2770
2771                 cqe =
2772                 (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
2773                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
2774         }
2775
2776         /* revert comp_ring to original state */
2777         ecore_chain_set_cons(&rxq->rx_comp_ring, sw_comp_cons, orig_cqe);
2778
2779         return bd_count;
2780 }
2781
2782 int
2783 qede_rx_descriptor_status(void *p_rxq, uint16_t offset)
2784 {
2785         uint16_t hw_bd_cons, sw_bd_cons, sw_bd_prod;
2786         uint16_t produced, consumed;
2787         struct qede_rx_queue *rxq = p_rxq;
2788
2789         if (offset > rxq->nb_rx_desc)
2790                 return -EINVAL;
2791
2792         sw_bd_cons = ecore_chain_get_cons_idx(&rxq->rx_bd_ring);
2793         sw_bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
2794
2795         /* find BDs used by HW from completion queue elements */
2796         hw_bd_cons = sw_bd_cons + qede_parse_fp_cqe(rxq);
2797
2798         if (hw_bd_cons < sw_bd_cons)
2799                 /* wraparound case */
2800                 consumed = (0xffff - sw_bd_cons) + hw_bd_cons;
2801         else
2802                 consumed = hw_bd_cons - sw_bd_cons;
2803
2804         if (offset <= consumed)
2805                 return RTE_ETH_RX_DESC_DONE;
2806
2807         if (sw_bd_prod < sw_bd_cons)
2808                 /* wraparound case */
2809                 produced = (0xffff - sw_bd_cons) + sw_bd_prod;
2810         else
2811                 produced = sw_bd_prod - sw_bd_cons;
2812
2813         if (offset <= produced)
2814                 return RTE_ETH_RX_DESC_AVAIL;
2815
2816         return RTE_ETH_RX_DESC_UNAVAIL;
2817 }