drivers/net/qede/qede_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include <rte_net.h>
   8 #include "qede_rxtx.h"
   9
  10 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
  11 {
  12         struct rte_mbuf *new_mb = NULL;
  13         struct eth_rx_bd *rx_bd;
  14         dma_addr_t mapping;
  15         uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
  16
  17         new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
  18         if (unlikely(!new_mb)) {
  19                 PMD_RX_LOG(ERR, rxq,
  20                            "Failed to allocate rx buffer "
  21                            "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
  22                            idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
  23                            rte_mempool_avail_count(rxq->mb_pool),
  24                            rte_mempool_in_use_count(rxq->mb_pool));
  25                 return -ENOMEM;
  26         }
  27         rxq->sw_rx_ring[idx].mbuf = new_mb;
  28         rxq->sw_rx_ring[idx].page_offset = 0;
  29         mapping = rte_mbuf_data_iova_default(new_mb);
  30         /* Advance PROD and get BD pointer */
  31         rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
  32         rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
  33         rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
  34         rxq->sw_rx_prod++;
  35         return 0;
  36 }
  37
  38 #define QEDE_MAX_BULK_ALLOC_COUNT 512
  39
  40 static inline int qede_alloc_rx_bulk_mbufs(struct qede_rx_queue *rxq, int count)
  41 {
  42         void *obj_p[QEDE_MAX_BULK_ALLOC_COUNT] __rte_cache_aligned;
  43         struct rte_mbuf *mbuf = NULL;
  44         struct eth_rx_bd *rx_bd;
  45         dma_addr_t mapping;
  46         int i, ret = 0;
  47         uint16_t idx;
  48
  49         if (count > QEDE_MAX_BULK_ALLOC_COUNT)
  50                 count = QEDE_MAX_BULK_ALLOC_COUNT;
  51
  52         ret = rte_mempool_get_bulk(rxq->mb_pool, obj_p, count);
  53         if (unlikely(ret)) {
  54                 PMD_RX_LOG(ERR, rxq,
  55                            "Failed to allocate %d rx buffers "
  56                             "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
  57                             count,
  58                             rxq->sw_rx_prod & NUM_RX_BDS(rxq),
  59                             rxq->sw_rx_cons & NUM_RX_BDS(rxq),
  60                             rte_mempool_avail_count(rxq->mb_pool),
  61                             rte_mempool_in_use_count(rxq->mb_pool));
  62                 return -ENOMEM;
  63         }
  64
  65         for (i = 0; i < count; i++) {
  66                 mbuf = obj_p[i];
  67                 if (likely(i < count - 1))
  68                         rte_prefetch0(obj_p[i + 1]);
  69
  70                 idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
  71                 rxq->sw_rx_ring[idx].mbuf = mbuf;
  72                 rxq->sw_rx_ring[idx].page_offset = 0;
  73                 mapping = rte_mbuf_data_iova_default(mbuf);
  74                 rx_bd = (struct eth_rx_bd *)
  75                         ecore_chain_produce(&rxq->rx_bd_ring);
  76                 rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
  77                 rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
  78                 rxq->sw_rx_prod++;
  79         }
  80
  81         return 0;
  82 }
  83
  84 /* Criterias for calculating Rx buffer size -
  85  * 1) rx_buf_size should not exceed the size of mbuf
  86  * 2) In scattered_rx mode - minimum rx_buf_size should be
  87  *    (MTU + Maximum L2 Header Size + 2) / ETH_RX_MAX_BUFF_PER_PKT
  88  * 3) In regular mode - minimum rx_buf_size should be
  89  *    (MTU + Maximum L2 Header Size + 2)
  90  *    In above cases +2 corrosponds to 2 bytes padding in front of L2
  91  *    header.
  92  * 4) rx_buf_size should be cacheline-size aligned. So considering
  93  *    criteria 1, we need to adjust the size to floor instead of ceil,
  94  *    so that we don't exceed mbuf size while ceiling rx_buf_size.
  95  */
  96 int
  97 qede_calc_rx_buf_size(struct rte_eth_dev *dev, uint16_t mbufsz,
  98                       uint16_t max_frame_size)
  99 {
 100         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
 101         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 102         int rx_buf_size;
 103
 104         if (dev->data->scattered_rx) {
 105                 /* per HW limitation, only ETH_RX_MAX_BUFF_PER_PKT number of
 106                  * bufferes can be used for single packet. So need to make sure
 107                  * mbuf size is sufficient enough for this.
 108                  */
 109                 if ((mbufsz * ETH_RX_MAX_BUFF_PER_PKT) <
 110                      (max_frame_size + QEDE_ETH_OVERHEAD)) {
 111                         DP_ERR(edev, "mbuf %d size is not enough to hold max fragments (%d) for max rx packet length (%d)\n",
 112                                mbufsz, ETH_RX_MAX_BUFF_PER_PKT, max_frame_size);
 113                         return -EINVAL;
 114                 }
 115
 116                 rx_buf_size = RTE_MAX(mbufsz,
 117                                       (max_frame_size + QEDE_ETH_OVERHEAD) /
 118                                        ETH_RX_MAX_BUFF_PER_PKT);
 119         } else {
 120                 rx_buf_size = max_frame_size + QEDE_ETH_OVERHEAD;
 121         }
 122
 123         /* Align to cache-line size if needed */
 124         return QEDE_FLOOR_TO_CACHE_LINE_SIZE(rx_buf_size);
 125 }
 126
 127 static struct qede_rx_queue *
 128 qede_alloc_rx_queue_mem(struct rte_eth_dev *dev,
 129                         uint16_t queue_idx,
 130                         uint16_t nb_desc,
 131                         unsigned int socket_id,
 132                         struct rte_mempool *mp,
 133                         uint16_t bufsz)
 134 {
 135         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
 136         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 137         struct qede_rx_queue *rxq;
 138         size_t size;
 139         int rc;
 140
 141         /* First allocate the rx queue data structure */
 142         rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
 143                                  RTE_CACHE_LINE_SIZE, socket_id);
 144
 145         if (!rxq) {
 146                 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
 147                           socket_id);
 148                 return NULL;
 149         }
 150
 151         rxq->qdev = qdev;
 152         rxq->mb_pool = mp;
 153         rxq->nb_rx_desc = nb_desc;
 154         rxq->queue_id = queue_idx;
 155         rxq->port_id = dev->data->port_id;
 156
 157
 158         rxq->rx_buf_size = bufsz;
 159
 160         DP_INFO(edev, "mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\n",
 161                 qdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);
 162
 163         /* Allocate the parallel driver ring for Rx buffers */
 164         size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
 165         rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
 166                                              RTE_CACHE_LINE_SIZE, socket_id);
 167         if (!rxq->sw_rx_ring) {
 168                 DP_ERR(edev, "Memory allocation fails for sw_rx_ring on"
 169                        " socket %u\n", socket_id);
 170                 rte_free(rxq);
 171                 return NULL;
 172         }
 173
 174         /* Allocate FW Rx ring  */
 175         rc = qdev->ops->common->chain_alloc(edev,
 176                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 177                                             ECORE_CHAIN_MODE_NEXT_PTR,
 178                                             ECORE_CHAIN_CNT_TYPE_U16,
 179                                             rxq->nb_rx_desc,
 180                                             sizeof(struct eth_rx_bd),
 181                                             &rxq->rx_bd_ring,
 182                                             NULL);
 183
 184         if (rc != ECORE_SUCCESS) {
 185                 DP_ERR(edev, "Memory allocation fails for RX BD ring"
 186                        " on socket %u\n", socket_id);
 187                 rte_free(rxq->sw_rx_ring);
 188                 rte_free(rxq);
 189                 return NULL;
 190         }
 191
 192         /* Allocate FW completion ring */
 193         rc = qdev->ops->common->chain_alloc(edev,
 194                                             ECORE_CHAIN_USE_TO_CONSUME,
 195                                             ECORE_CHAIN_MODE_PBL,
 196                                             ECORE_CHAIN_CNT_TYPE_U16,
 197                                             rxq->nb_rx_desc,
 198                                             sizeof(union eth_rx_cqe),
 199                                             &rxq->rx_comp_ring,
 200                                             NULL);
 201
 202         if (rc != ECORE_SUCCESS) {
 203                 DP_ERR(edev, "Memory allocation fails for RX CQE ring"
 204                        " on socket %u\n", socket_id);
 205                 qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);
 206                 rte_free(rxq->sw_rx_ring);
 207                 rte_free(rxq);
 208                 return NULL;
 209         }
 210
 211         return rxq;
 212 }
 213
 214 int
 215 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qid,
 216                     uint16_t nb_desc, unsigned int socket_id,
 217                     __rte_unused const struct rte_eth_rxconf *rx_conf,
 218                     struct rte_mempool *mp)
 219 {
 220         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
 221         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 222         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
 223         struct qede_rx_queue *rxq;
 224         uint16_t max_rx_pkt_len;
 225         uint16_t bufsz;
 226         int rc;
 227
 228         PMD_INIT_FUNC_TRACE(edev);
 229
 230         /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
 231         if (!rte_is_power_of_2(nb_desc)) {
 232                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 233                           nb_desc);
 234                 return -EINVAL;
 235         }
 236
 237         /* Free memory prior to re-allocation if needed... */
 238         if (dev->data->rx_queues[qid] != NULL) {
 239                 qede_rx_queue_release(dev->data->rx_queues[qid]);
 240                 dev->data->rx_queues[qid] = NULL;
 241         }
 242
 243         max_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len;
 244
 245         /* Fix up RX buffer size */
 246         bufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 247         /* cache align the mbuf size to simplfy rx_buf_size calculation */
 248         bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
 249         if ((rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) ||
 250             (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {
 251                 if (!dev->data->scattered_rx) {
 252                         DP_INFO(edev, "Forcing scatter-gather mode\n");
 253                         dev->data->scattered_rx = 1;
 254                 }
 255         }
 256
 257         rc = qede_calc_rx_buf_size(dev, bufsz, max_rx_pkt_len);
 258         if (rc < 0)
 259                 return rc;
 260
 261         bufsz = rc;
 262
 263         if (ECORE_IS_CMT(edev)) {
 264                 rxq = qede_alloc_rx_queue_mem(dev, qid * 2, nb_desc,
 265                                               socket_id, mp, bufsz);
 266                 if (!rxq)
 267                         return -ENOMEM;
 268
 269                 qdev->fp_array[qid * 2].rxq = rxq;
 270                 rxq = qede_alloc_rx_queue_mem(dev, qid * 2 + 1, nb_desc,
 271                                               socket_id, mp, bufsz);
 272                 if (!rxq)
 273                         return -ENOMEM;
 274
 275                 qdev->fp_array[qid * 2 + 1].rxq = rxq;
 276                 /* provide per engine fp struct as rx queue */
 277                 dev->data->rx_queues[qid] = &qdev->fp_array_cmt[qid];
 278         } else {
 279                 rxq = qede_alloc_rx_queue_mem(dev, qid, nb_desc,
 280                                               socket_id, mp, bufsz);
 281                 if (!rxq)
 282                         return -ENOMEM;
 283
 284                 dev->data->rx_queues[qid] = rxq;
 285                 qdev->fp_array[qid].rxq = rxq;
 286         }
 287
 288         DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
 289                   qid, nb_desc, rxq->rx_buf_size, socket_id);
 290
 291         return 0;
 292 }
 293
 294 static void
 295 qede_rx_queue_reset(__rte_unused struct qede_dev *qdev,
 296                     struct qede_rx_queue *rxq)
 297 {
 298         DP_INFO(&qdev->edev, "Reset RX queue %u\n", rxq->queue_id);
 299         ecore_chain_reset(&rxq->rx_bd_ring);
 300         ecore_chain_reset(&rxq->rx_comp_ring);
 301         rxq->sw_rx_prod = 0;
 302         rxq->sw_rx_cons = 0;
 303         *rxq->hw_cons_ptr = 0;
 304 }
 305
 306 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
 307 {
 308         uint16_t i;
 309
 310         if (rxq->sw_rx_ring) {
 311                 for (i = 0; i < rxq->nb_rx_desc; i++) {
 312                         if (rxq->sw_rx_ring[i].mbuf) {
 313                                 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
 314                                 rxq->sw_rx_ring[i].mbuf = NULL;
 315                         }
 316                 }
 317         }
 318 }
 319
 320 static void _qede_rx_queue_release(struct qede_dev *qdev,
 321                                    struct ecore_dev *edev,
 322                                    struct qede_rx_queue *rxq)
 323 {
 324         qede_rx_queue_release_mbufs(rxq);
 325         qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);
 326         qdev->ops->common->chain_free(edev, &rxq->rx_comp_ring);
 327         rte_free(rxq->sw_rx_ring);
 328         rte_free(rxq);
 329 }
 330
 331 void qede_rx_queue_release(void *rx_queue)
 332 {
 333         struct qede_rx_queue *rxq = rx_queue;
 334         struct qede_fastpath_cmt *fp_cmt;
 335         struct qede_dev *qdev;
 336         struct ecore_dev *edev;
 337
 338         if (rxq) {
 339                 qdev = rxq->qdev;
 340                 edev = QEDE_INIT_EDEV(qdev);
 341                 PMD_INIT_FUNC_TRACE(edev);
 342                 if (ECORE_IS_CMT(edev)) {
 343                         fp_cmt = rx_queue;
 344                         _qede_rx_queue_release(qdev, edev, fp_cmt->fp0->rxq);
 345                         _qede_rx_queue_release(qdev, edev, fp_cmt->fp1->rxq);
 346                 } else {
 347                         _qede_rx_queue_release(qdev, edev, rxq);
 348                 }
 349         }
 350 }
 351
 352 /* Stops a given RX queue in the HW */
 353 static int qede_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 354 {
 355         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 356         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 357         struct ecore_hwfn *p_hwfn;
 358         struct qede_rx_queue *rxq;
 359         int hwfn_index;
 360         int rc;
 361
 362         if (rx_queue_id < qdev->num_rx_queues) {
 363                 rxq = qdev->fp_array[rx_queue_id].rxq;
 364                 hwfn_index = rx_queue_id % edev->num_hwfns;
 365                 p_hwfn = &edev->hwfns[hwfn_index];
 366                 rc = ecore_eth_rx_queue_stop(p_hwfn, rxq->handle,
 367                                 true, false);
 368                 if (rc != ECORE_SUCCESS) {
 369                         DP_ERR(edev, "RX queue %u stop fails\n", rx_queue_id);
 370                         return -1;
 371                 }
 372                 qede_rx_queue_release_mbufs(rxq);
 373                 qede_rx_queue_reset(qdev, rxq);
 374                 eth_dev->data->rx_queue_state[rx_queue_id] =
 375                         RTE_ETH_QUEUE_STATE_STOPPED;
 376                 DP_INFO(edev, "RX queue %u stopped\n", rx_queue_id);
 377         } else {
 378                 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
 379                 rc = -EINVAL;
 380         }
 381
 382         return rc;
 383 }
 384
 385 static struct qede_tx_queue *
 386 qede_alloc_tx_queue_mem(struct rte_eth_dev *dev,
 387                         uint16_t queue_idx,
 388                         uint16_t nb_desc,
 389                         unsigned int socket_id,
 390                         const struct rte_eth_txconf *tx_conf)
 391 {
 392         struct qede_dev *qdev = dev->data->dev_private;
 393         struct ecore_dev *edev = &qdev->edev;
 394         struct qede_tx_queue *txq;
 395         int rc;
 396         size_t sw_tx_ring_size;
 397
 398         txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
 399                                  RTE_CACHE_LINE_SIZE, socket_id);
 400
 401         if (txq == NULL) {
 402                 DP_ERR(edev,
 403                        "Unable to allocate memory for txq on socket %u",
 404                        socket_id);
 405                 return NULL;
 406         }
 407
 408         txq->nb_tx_desc = nb_desc;
 409         txq->qdev = qdev;
 410         txq->port_id = dev->data->port_id;
 411
 412         rc = qdev->ops->common->chain_alloc(edev,
 413                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 414                                             ECORE_CHAIN_MODE_PBL,
 415                                             ECORE_CHAIN_CNT_TYPE_U16,
 416                                             txq->nb_tx_desc,
 417                                             sizeof(union eth_tx_bd_types),
 418                                             &txq->tx_pbl,
 419                                             NULL);
 420         if (rc != ECORE_SUCCESS) {
 421                 DP_ERR(edev,
 422                        "Unable to allocate memory for txbd ring on socket %u",
 423                        socket_id);
 424                 qede_tx_queue_release(txq);
 425                 return NULL;
 426         }
 427
 428         /* Allocate software ring */
 429         sw_tx_ring_size = sizeof(txq->sw_tx_ring) * txq->nb_tx_desc;
 430         txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
 431                                              sw_tx_ring_size,
 432                                              RTE_CACHE_LINE_SIZE, socket_id);
 433
 434         if (!txq->sw_tx_ring) {
 435                 DP_ERR(edev,
 436                        "Unable to allocate memory for txbd ring on socket %u",
 437                        socket_id);
 438                 qdev->ops->common->chain_free(edev, &txq->tx_pbl);
 439                 qede_tx_queue_release(txq);
 440                 return NULL;
 441         }
 442
 443         txq->queue_id = queue_idx;
 444
 445         txq->nb_tx_avail = txq->nb_tx_desc;
 446
 447         txq->tx_free_thresh =
 448             tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
 449             (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
 450
 451         DP_INFO(edev,
 452                   "txq %u num_desc %u tx_free_thresh %u socket %u\n",
 453                   queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
 454         return txq;
 455 }
 456
 457 int
 458 qede_tx_queue_setup(struct rte_eth_dev *dev,
 459                     uint16_t queue_idx,
 460                     uint16_t nb_desc,
 461                     unsigned int socket_id,
 462                     const struct rte_eth_txconf *tx_conf)
 463 {
 464         struct qede_dev *qdev = dev->data->dev_private;
 465         struct ecore_dev *edev = &qdev->edev;
 466         struct qede_tx_queue *txq;
 467
 468         PMD_INIT_FUNC_TRACE(edev);
 469
 470         if (!rte_is_power_of_2(nb_desc)) {
 471                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 472                        nb_desc);
 473                 return -EINVAL;
 474         }
 475
 476         /* Free memory prior to re-allocation if needed... */
 477         if (dev->data->tx_queues[queue_idx] != NULL) {
 478                 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
 479                 dev->data->tx_queues[queue_idx] = NULL;
 480         }
 481
 482         if (ECORE_IS_CMT(edev)) {
 483                 txq = qede_alloc_tx_queue_mem(dev, queue_idx * 2, nb_desc,
 484                                               socket_id, tx_conf);
 485                 if (!txq)
 486                         return -ENOMEM;
 487
 488                 qdev->fp_array[queue_idx * 2].txq = txq;
 489                 txq = qede_alloc_tx_queue_mem(dev, (queue_idx * 2) + 1, nb_desc,
 490                                               socket_id, tx_conf);
 491                 if (!txq)
 492                         return -ENOMEM;
 493
 494                 qdev->fp_array[(queue_idx * 2) + 1].txq = txq;
 495                 dev->data->tx_queues[queue_idx] =
 496                                         &qdev->fp_array_cmt[queue_idx];
 497         } else {
 498                 txq = qede_alloc_tx_queue_mem(dev, queue_idx, nb_desc,
 499                                               socket_id, tx_conf);
 500                 if (!txq)
 501                         return -ENOMEM;
 502
 503                 dev->data->tx_queues[queue_idx] = txq;
 504                 qdev->fp_array[queue_idx].txq = txq;
 505         }
 506
 507         return 0;
 508 }
 509
 510 static void
 511 qede_tx_queue_reset(__rte_unused struct qede_dev *qdev,
 512                     struct qede_tx_queue *txq)
 513 {
 514         DP_INFO(&qdev->edev, "Reset TX queue %u\n", txq->queue_id);
 515         ecore_chain_reset(&txq->tx_pbl);
 516         txq->sw_tx_cons = 0;
 517         txq->sw_tx_prod = 0;
 518         *txq->hw_cons_ptr = 0;
 519 }
 520
 521 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
 522 {
 523         uint16_t i;
 524
 525         if (txq->sw_tx_ring) {
 526                 for (i = 0; i < txq->nb_tx_desc; i++) {
 527                         if (txq->sw_tx_ring[i]) {
 528                                 rte_pktmbuf_free(txq->sw_tx_ring[i]);
 529                                 txq->sw_tx_ring[i] = NULL;
 530                         }
 531                 }
 532         }
 533 }
 534
 535 static void _qede_tx_queue_release(struct qede_dev *qdev,
 536                                    struct ecore_dev *edev,
 537                                    struct qede_tx_queue *txq)
 538 {
 539         qede_tx_queue_release_mbufs(txq);
 540         qdev->ops->common->chain_free(edev, &txq->tx_pbl);
 541         rte_free(txq->sw_tx_ring);
 542         rte_free(txq);
 543 }
 544
 545 void qede_tx_queue_release(void *tx_queue)
 546 {
 547         struct qede_tx_queue *txq = tx_queue;
 548         struct qede_fastpath_cmt *fp_cmt;
 549         struct qede_dev *qdev;
 550         struct ecore_dev *edev;
 551
 552         if (txq) {
 553                 qdev = txq->qdev;
 554                 edev = QEDE_INIT_EDEV(qdev);
 555                 PMD_INIT_FUNC_TRACE(edev);
 556
 557                 if (ECORE_IS_CMT(edev)) {
 558                         fp_cmt = tx_queue;
 559                         _qede_tx_queue_release(qdev, edev, fp_cmt->fp0->txq);
 560                         _qede_tx_queue_release(qdev, edev, fp_cmt->fp1->txq);
 561                 } else {
 562                         _qede_tx_queue_release(qdev, edev, txq);
 563                 }
 564         }
 565 }
 566
 567 /* This function allocates fast-path status block memory */
 568 static int
 569 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
 570                   uint16_t sb_id)
 571 {
 572         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 573         struct status_block *sb_virt;
 574         dma_addr_t sb_phys;
 575         int rc;
 576
 577         sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys,
 578                                           sizeof(struct status_block));
 579         if (!sb_virt) {
 580                 DP_ERR(edev, "Status block allocation failed\n");
 581                 return -ENOMEM;
 582         }
 583         rc = qdev->ops->common->sb_init(edev, sb_info, sb_virt,
 584                                         sb_phys, sb_id);
 585         if (rc) {
 586                 DP_ERR(edev, "Status block initialization failed\n");
 587                 OSAL_DMA_FREE_COHERENT(edev, sb_virt, sb_phys,
 588                                        sizeof(struct status_block));
 589                 return rc;
 590         }
 591
 592         return 0;
 593 }
 594
 595 int qede_alloc_fp_resc(struct qede_dev *qdev)
 596 {
 597         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 598         struct qede_fastpath *fp;
 599         uint32_t num_sbs;
 600         uint16_t sb_idx;
 601         int i;
 602
 603         PMD_INIT_FUNC_TRACE(edev);
 604
 605         if (IS_VF(edev))
 606                 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
 607         else
 608                 num_sbs = ecore_cxt_get_proto_cid_count
 609                           (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL);
 610
 611         if (num_sbs == 0) {
 612                 DP_ERR(edev, "No status blocks available\n");
 613                 return -EINVAL;
 614         }
 615
 616         qdev->fp_array = rte_calloc("fp", QEDE_RXTX_MAX(qdev),
 617                                 sizeof(*qdev->fp_array), RTE_CACHE_LINE_SIZE);
 618
 619         if (!qdev->fp_array) {
 620                 DP_ERR(edev, "fp array allocation failed\n");
 621                 return -ENOMEM;
 622         }
 623
 624         memset((void *)qdev->fp_array, 0, QEDE_RXTX_MAX(qdev) *
 625                         sizeof(*qdev->fp_array));
 626
 627         if (ECORE_IS_CMT(edev)) {
 628                 qdev->fp_array_cmt = rte_calloc("fp_cmt",
 629                                                 QEDE_RXTX_MAX(qdev) / 2,
 630                                                 sizeof(*qdev->fp_array_cmt),
 631                                                 RTE_CACHE_LINE_SIZE);
 632
 633                 if (!qdev->fp_array_cmt) {
 634                         DP_ERR(edev, "fp array for CMT allocation failed\n");
 635                         return -ENOMEM;
 636                 }
 637
 638                 memset((void *)qdev->fp_array_cmt, 0,
 639                        (QEDE_RXTX_MAX(qdev) / 2) * sizeof(*qdev->fp_array_cmt));
 640
 641                 /* Establish the mapping of fp_array with fp_array_cmt */
 642                 for (i = 0; i < QEDE_RXTX_MAX(qdev) / 2; i++) {
 643                         qdev->fp_array_cmt[i].qdev = qdev;
 644                         qdev->fp_array_cmt[i].fp0 = &qdev->fp_array[i * 2];
 645                         qdev->fp_array_cmt[i].fp1 = &qdev->fp_array[i * 2 + 1];
 646                 }
 647         }
 648
 649         for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
 650                 fp = &qdev->fp_array[sb_idx];
 651                 fp->sb_info = rte_calloc("sb", 1, sizeof(struct ecore_sb_info),
 652                                 RTE_CACHE_LINE_SIZE);
 653                 if (!fp->sb_info) {
 654                         DP_ERR(edev, "FP sb_info allocation fails\n");
 655                         return -1;
 656                 }
 657                 if (qede_alloc_mem_sb(qdev, fp->sb_info, sb_idx)) {
 658                         DP_ERR(edev, "FP status block allocation fails\n");
 659                         return -1;
 660                 }
 661                 DP_INFO(edev, "sb_info idx 0x%x initialized\n",
 662                                 fp->sb_info->igu_sb_id);
 663         }
 664
 665         return 0;
 666 }
 667
 668 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
 669 {
 670         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 671         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 672         struct qede_fastpath *fp;
 673         uint16_t sb_idx;
 674         uint8_t i;
 675
 676         PMD_INIT_FUNC_TRACE(edev);
 677
 678         for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
 679                 fp = &qdev->fp_array[sb_idx];
 680                 if (fp->sb_info) {
 681                         DP_INFO(edev, "Free sb_info index 0x%x\n",
 682                                         fp->sb_info->igu_sb_id);
 683                         OSAL_DMA_FREE_COHERENT(edev, fp->sb_info->sb_virt,
 684                                 fp->sb_info->sb_phys,
 685                                 sizeof(struct status_block));
 686                         rte_free(fp->sb_info);
 687                         fp->sb_info = NULL;
 688                 }
 689         }
 690
 691         /* Free packet buffers and ring memories */
 692         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 693                 if (eth_dev->data->rx_queues[i]) {
 694                         qede_rx_queue_release(eth_dev->data->rx_queues[i]);
 695                         eth_dev->data->rx_queues[i] = NULL;
 696                 }
 697         }
 698
 699         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
 700                 if (eth_dev->data->tx_queues[i]) {
 701                         qede_tx_queue_release(eth_dev->data->tx_queues[i]);
 702                         eth_dev->data->tx_queues[i] = NULL;
 703                 }
 704         }
 705
 706         if (qdev->fp_array)
 707                 rte_free(qdev->fp_array);
 708         qdev->fp_array = NULL;
 709
 710         if (qdev->fp_array_cmt)
 711                 rte_free(qdev->fp_array_cmt);
 712         qdev->fp_array_cmt = NULL;
 713 }
 714
 715 static inline void
 716 qede_update_rx_prod(__rte_unused struct qede_dev *edev,
 717                     struct qede_rx_queue *rxq)
 718 {
 719         uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
 720         uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
 721         struct eth_rx_prod_data rx_prods = { 0 };
 722
 723         /* Update producers */
 724         rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
 725         rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
 726
 727         /* Make sure that the BD and SGE data is updated before updating the
 728          * producers since FW might read the BD/SGE right after the producer
 729          * is updated.
 730          */
 731         rte_wmb();
 732
 733         internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
 734                         (uint32_t *)&rx_prods);
 735
 736         /* mmiowb is needed to synchronize doorbell writes from more than one
 737          * processor. It guarantees that the write arrives to the device before
 738          * the napi lock is released and another qede_poll is called (possibly
 739          * on another CPU). Without this barrier, the next doorbell can bypass
 740          * this doorbell. This is applicable to IA64/Altix systems.
 741          */
 742         rte_wmb();
 743
 744         PMD_RX_LOG(DEBUG, rxq, "bd_prod %u  cqe_prod %u", bd_prod, cqe_prod);
 745 }
 746
 747 /* Starts a given RX queue in HW */
 748 static int
 749 qede_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 750 {
 751         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 752         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 753         struct ecore_queue_start_common_params params;
 754         struct ecore_rxq_start_ret_params ret_params;
 755         struct qede_rx_queue *rxq;
 756         struct qede_fastpath *fp;
 757         struct ecore_hwfn *p_hwfn;
 758         dma_addr_t p_phys_table;
 759         uint16_t page_cnt;
 760         uint16_t j;
 761         int hwfn_index;
 762         int rc;
 763
 764         if (rx_queue_id < qdev->num_rx_queues) {
 765                 fp = &qdev->fp_array[rx_queue_id];
 766                 rxq = fp->rxq;
 767                 /* Allocate buffers for the Rx ring */
 768                 for (j = 0; j < rxq->nb_rx_desc; j++) {
 769                         rc = qede_alloc_rx_buffer(rxq);
 770                         if (rc) {
 771                                 DP_ERR(edev, "RX buffer allocation failed"
 772                                                 " for rxq = %u\n", rx_queue_id);
 773                                 return -ENOMEM;
 774                         }
 775                 }
 776                 /* disable interrupts */
 777                 ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
 778                 /* Prepare ramrod */
 779                 memset(&params, 0, sizeof(params));
 780                 params.queue_id = rx_queue_id / edev->num_hwfns;
 781                 params.vport_id = 0;
 782                 params.stats_id = params.vport_id;
 783                 params.p_sb = fp->sb_info;
 784                 DP_INFO(edev, "rxq %u igu_sb_id 0x%x\n",
 785                                 fp->rxq->queue_id, fp->sb_info->igu_sb_id);
 786                 params.sb_idx = RX_PI;
 787                 hwfn_index = rx_queue_id % edev->num_hwfns;
 788                 p_hwfn = &edev->hwfns[hwfn_index];
 789                 p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->rx_comp_ring);
 790                 page_cnt = ecore_chain_get_page_cnt(&fp->rxq->rx_comp_ring);
 791                 memset(&ret_params, 0, sizeof(ret_params));
 792                 rc = ecore_eth_rx_queue_start(p_hwfn,
 793                                 p_hwfn->hw_info.opaque_fid,
 794                                 &params, fp->rxq->rx_buf_size,
 795                                 fp->rxq->rx_bd_ring.p_phys_addr,
 796                                 p_phys_table, page_cnt,
 797                                 &ret_params);
 798                 if (rc) {
 799                         DP_ERR(edev, "RX queue %u could not be started, rc = %d\n",
 800                                         rx_queue_id, rc);
 801                         return -1;
 802                 }
 803                 /* Update with the returned parameters */
 804                 fp->rxq->hw_rxq_prod_addr = ret_params.p_prod;
 805                 fp->rxq->handle = ret_params.p_handle;
 806
 807                 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_pi_array[RX_PI];
 808                 qede_update_rx_prod(qdev, fp->rxq);
 809                 eth_dev->data->rx_queue_state[rx_queue_id] =
 810                         RTE_ETH_QUEUE_STATE_STARTED;
 811                 DP_INFO(edev, "RX queue %u started\n", rx_queue_id);
 812         } else {
 813                 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
 814                 rc = -EINVAL;
 815         }
 816
 817         return rc;
 818 }
 819
 820 static int
 821 qede_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 822 {
 823         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 824         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 825         struct ecore_queue_start_common_params params;
 826         struct ecore_txq_start_ret_params ret_params;
 827         struct ecore_hwfn *p_hwfn;
 828         dma_addr_t p_phys_table;
 829         struct qede_tx_queue *txq;
 830         struct qede_fastpath *fp;
 831         uint16_t page_cnt;
 832         int hwfn_index;
 833         int rc;
 834
 835         if (tx_queue_id < qdev->num_tx_queues) {
 836                 fp = &qdev->fp_array[tx_queue_id];
 837                 txq = fp->txq;
 838                 memset(&params, 0, sizeof(params));
 839                 params.queue_id = tx_queue_id / edev->num_hwfns;
 840                 params.vport_id = 0;
 841                 params.stats_id = params.vport_id;
 842                 params.p_sb = fp->sb_info;
 843                 DP_INFO(edev, "txq %u igu_sb_id 0x%x\n",
 844                                 fp->txq->queue_id, fp->sb_info->igu_sb_id);
 845                 params.sb_idx = TX_PI(0); /* tc = 0 */
 846                 p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
 847                 page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
 848                 hwfn_index = tx_queue_id % edev->num_hwfns;
 849                 p_hwfn = &edev->hwfns[hwfn_index];
 850                 if (qdev->dev_info.is_legacy)
 851                         fp->txq->is_legacy = true;
 852                 rc = ecore_eth_tx_queue_start(p_hwfn,
 853                                 p_hwfn->hw_info.opaque_fid,
 854                                 &params, 0 /* tc */,
 855                                 p_phys_table, page_cnt,
 856                                 &ret_params);
 857                 if (rc != ECORE_SUCCESS) {
 858                         DP_ERR(edev, "TX queue %u couldn't be started, rc=%d\n",
 859                                         tx_queue_id, rc);
 860                         return -1;
 861                 }
 862                 txq->doorbell_addr = ret_params.p_doorbell;
 863                 txq->handle = ret_params.p_handle;
 864
 865                 txq->hw_cons_ptr = &fp->sb_info->sb_pi_array[TX_PI(0)];
 866                 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_DEST,
 867                                 DB_DEST_XCM);
 868                 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
 869                                 DB_AGG_CMD_SET);
 870                 SET_FIELD(txq->tx_db.data.params,
 871                                 ETH_DB_DATA_AGG_VAL_SEL,
 872                                 DQ_XCM_ETH_TX_BD_PROD_CMD);
 873                 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
 874                 eth_dev->data->tx_queue_state[tx_queue_id] =
 875                         RTE_ETH_QUEUE_STATE_STARTED;
 876                 DP_INFO(edev, "TX queue %u started\n", tx_queue_id);
 877         } else {
 878                 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
 879                 rc = -EINVAL;
 880         }
 881
 882         return rc;
 883 }
 884
 885 static inline void
 886 qede_process_tx_compl(__rte_unused struct ecore_dev *edev,
 887                       struct qede_tx_queue *txq)
 888 {
 889         uint16_t hw_bd_cons;
 890         uint16_t sw_tx_cons;
 891         uint16_t remaining;
 892         uint16_t mask;
 893         struct rte_mbuf *mbuf;
 894         uint16_t nb_segs;
 895         uint16_t idx;
 896         uint16_t first_idx;
 897
 898         rte_compiler_barrier();
 899         sw_tx_cons = ecore_chain_get_cons_idx(&txq->tx_pbl);
 900         hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
 901 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
 902         PMD_TX_LOG(DEBUG, txq, "Tx Completions = %u\n",
 903                    abs(hw_bd_cons - sw_tx_cons));
 904 #endif
 905
 906         mask = NUM_TX_BDS(txq);
 907         idx = txq->sw_tx_cons & mask;
 908
 909         remaining = hw_bd_cons - sw_tx_cons;
 910         txq->nb_tx_avail += remaining;
 911         first_idx = idx;
 912
 913         while (remaining) {
 914                 mbuf = txq->sw_tx_ring[idx];
 915                 RTE_ASSERT(mbuf);
 916                 nb_segs = mbuf->nb_segs;
 917                 remaining -= nb_segs;
 918
 919                 PMD_TX_LOG(DEBUG, txq, "nb_segs to free %u\n", nb_segs);
 920
 921                 while (nb_segs) {
 922                         ecore_chain_consume(&txq->tx_pbl);
 923                         nb_segs--;
 924                 }
 925
 926                 idx = (idx + 1) & mask;
 927                 PMD_TX_LOG(DEBUG, txq, "Freed tx packet\n");
 928         }
 929         txq->sw_tx_cons = idx;
 930
 931         if (first_idx > idx) {
 932                 rte_pktmbuf_free_bulk(&txq->sw_tx_ring[first_idx],
 933                                                           mask - first_idx + 1);
 934                 rte_pktmbuf_free_bulk(&txq->sw_tx_ring[0], idx);
 935         } else {
 936                 rte_pktmbuf_free_bulk(&txq->sw_tx_ring[first_idx],
 937                                                           idx - first_idx);
 938         }
 939 }
 940
 941 static int qede_drain_txq(struct qede_dev *qdev,
 942                           struct qede_tx_queue *txq, bool allow_drain)
 943 {
 944         struct ecore_dev *edev = &qdev->edev;
 945         int rc, cnt = 1000;
 946
 947         while (txq->sw_tx_cons != txq->sw_tx_prod) {
 948                 qede_process_tx_compl(edev, txq);
 949                 if (!cnt) {
 950                         if (allow_drain) {
 951                                 DP_ERR(edev, "Tx queue[%u] is stuck,"
 952                                           "requesting MCP to drain\n",
 953                                           txq->queue_id);
 954                                 rc = qdev->ops->common->drain(edev);
 955                                 if (rc)
 956                                         return rc;
 957                                 return qede_drain_txq(qdev, txq, false);
 958                         }
 959                         DP_ERR(edev, "Timeout waiting for tx queue[%d]:"
 960                                   "PROD=%d, CONS=%d\n",
 961                                   txq->queue_id, txq->sw_tx_prod,
 962                                   txq->sw_tx_cons);
 963                         return -1;
 964                 }
 965                 cnt--;
 966                 DELAY(1000);
 967                 rte_compiler_barrier();
 968         }
 969
 970         /* FW finished processing, wait for HW to transmit all tx packets */
 971         DELAY(2000);
 972
 973         return 0;
 974 }
 975
 976 /* Stops a given TX queue in the HW */
 977 static int qede_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 978 {
 979         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 980         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 981         struct ecore_hwfn *p_hwfn;
 982         struct qede_tx_queue *txq;
 983         int hwfn_index;
 984         int rc;
 985
 986         if (tx_queue_id < qdev->num_tx_queues) {
 987                 txq = qdev->fp_array[tx_queue_id].txq;
 988                 /* Drain txq */
 989                 if (qede_drain_txq(qdev, txq, true))
 990                         return -1; /* For the lack of retcodes */
 991                 /* Stop txq */
 992                 hwfn_index = tx_queue_id % edev->num_hwfns;
 993                 p_hwfn = &edev->hwfns[hwfn_index];
 994                 rc = ecore_eth_tx_queue_stop(p_hwfn, txq->handle);
 995                 if (rc != ECORE_SUCCESS) {
 996                         DP_ERR(edev, "TX queue %u stop fails\n", tx_queue_id);
 997                         return -1;
 998                 }
 999                 qede_tx_queue_release_mbufs(txq);
1000                 qede_tx_queue_reset(qdev, txq);
1001                 eth_dev->data->tx_queue_state[tx_queue_id] =
1002                         RTE_ETH_QUEUE_STATE_STOPPED;
1003                 DP_INFO(edev, "TX queue %u stopped\n", tx_queue_id);
1004         } else {
1005                 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
1006                 rc = -EINVAL;
1007         }
1008
1009         return rc;
1010 }
1011
1012 int qede_start_queues(struct rte_eth_dev *eth_dev)
1013 {
1014         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1015         uint8_t id;
1016         int rc = -1;
1017
1018         for (id = 0; id < qdev->num_rx_queues; id++) {
1019                 rc = qede_rx_queue_start(eth_dev, id);
1020                 if (rc != ECORE_SUCCESS)
1021                         return -1;
1022         }
1023
1024         for (id = 0; id < qdev->num_tx_queues; id++) {
1025                 rc = qede_tx_queue_start(eth_dev, id);
1026                 if (rc != ECORE_SUCCESS)
1027                         return -1;
1028         }
1029
1030         return rc;
1031 }
1032
1033 void qede_stop_queues(struct rte_eth_dev *eth_dev)
1034 {
1035         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1036         uint8_t id;
1037
1038         /* Stopping RX/TX queues */
1039         for (id = 0; id < qdev->num_tx_queues; id++)
1040                 qede_tx_queue_stop(eth_dev, id);
1041
1042         for (id = 0; id < qdev->num_rx_queues; id++)
1043                 qede_rx_queue_stop(eth_dev, id);
1044 }
1045
1046 static inline bool qede_tunn_exist(uint16_t flag)
1047 {
1048         return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
1049                     PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
1050 }
1051
1052 static inline uint8_t qede_check_tunn_csum_l3(uint16_t flag)
1053 {
1054         return !!((PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
1055                 PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT) & flag);
1056 }
1057
1058 /*
1059  * qede_check_tunn_csum_l4:
1060  * Returns:
1061  * 1 : If L4 csum is enabled AND if the validation has failed.
1062  * 0 : Otherwise
1063  */
1064 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
1065 {
1066         if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
1067              PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
1068                 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
1069                         PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
1070
1071         return 0;
1072 }
1073
1074 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
1075 {
1076         if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1077              PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
1078                 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1079                            PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
1080
1081         return 0;
1082 }
1083
1084 /* Returns outer L2, L3 and L4 packet_type for tunneled packets */
1085 static inline uint32_t qede_rx_cqe_to_pkt_type_outer(struct rte_mbuf *m)
1086 {
1087         uint32_t packet_type = RTE_PTYPE_UNKNOWN;
1088         struct rte_ether_hdr *eth_hdr;
1089         struct rte_ipv4_hdr *ipv4_hdr;
1090         struct rte_ipv6_hdr *ipv6_hdr;
1091         struct rte_vlan_hdr *vlan_hdr;
1092         uint16_t ethertype;
1093         bool vlan_tagged = 0;
1094         uint16_t len;
1095
1096         eth_hdr = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
1097         len = sizeof(struct rte_ether_hdr);
1098         ethertype = rte_cpu_to_be_16(eth_hdr->ether_type);
1099
1100          /* Note: Valid only if VLAN stripping is disabled */
1101         if (ethertype == RTE_ETHER_TYPE_VLAN) {
1102                 vlan_tagged = 1;
1103                 vlan_hdr = (struct rte_vlan_hdr *)(eth_hdr + 1);
1104                 len += sizeof(struct rte_vlan_hdr);
1105                 ethertype = rte_cpu_to_be_16(vlan_hdr->eth_proto);
1106         }
1107
1108         if (ethertype == RTE_ETHER_TYPE_IPV4) {
1109                 packet_type |= RTE_PTYPE_L3_IPV4;
1110                 ipv4_hdr = rte_pktmbuf_mtod_offset(m,
1111                                         struct rte_ipv4_hdr *, len);
1112                 if (ipv4_hdr->next_proto_id == IPPROTO_TCP)
1113                         packet_type |= RTE_PTYPE_L4_TCP;
1114                 else if (ipv4_hdr->next_proto_id == IPPROTO_UDP)
1115                         packet_type |= RTE_PTYPE_L4_UDP;
1116         } else if (ethertype == RTE_ETHER_TYPE_IPV6) {
1117                 packet_type |= RTE_PTYPE_L3_IPV6;
1118                 ipv6_hdr = rte_pktmbuf_mtod_offset(m,
1119                                                 struct rte_ipv6_hdr *, len);
1120                 if (ipv6_hdr->proto == IPPROTO_TCP)
1121                         packet_type |= RTE_PTYPE_L4_TCP;
1122                 else if (ipv6_hdr->proto == IPPROTO_UDP)
1123                         packet_type |= RTE_PTYPE_L4_UDP;
1124         }
1125
1126         if (vlan_tagged)
1127                 packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
1128         else
1129                 packet_type |= RTE_PTYPE_L2_ETHER;
1130
1131         return packet_type;
1132 }
1133
1134 static inline uint32_t qede_rx_cqe_to_pkt_type_inner(uint16_t flags)
1135 {
1136         uint16_t val;
1137
1138         /* Lookup table */
1139         static const uint32_t
1140         ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
1141                 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_INNER_L3_IPV4          |
1142                                        RTE_PTYPE_INNER_L2_ETHER,
1143                 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_INNER_L3_IPV6          |
1144                                        RTE_PTYPE_INNER_L2_ETHER,
1145                 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_INNER_L3_IPV4      |
1146                                            RTE_PTYPE_INNER_L4_TCP       |
1147                                            RTE_PTYPE_INNER_L2_ETHER,
1148                 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_INNER_L3_IPV6      |
1149                                            RTE_PTYPE_INNER_L4_TCP       |
1150                                            RTE_PTYPE_INNER_L2_ETHER,
1151                 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_INNER_L3_IPV4      |
1152                                            RTE_PTYPE_INNER_L4_UDP       |
1153                                            RTE_PTYPE_INNER_L2_ETHER,
1154                 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_INNER_L3_IPV6      |
1155                                            RTE_PTYPE_INNER_L4_UDP       |
1156                                            RTE_PTYPE_INNER_L2_ETHER,
1157                 /* Frags with no VLAN */
1158                 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_INNER_L3_IPV4     |
1159                                             RTE_PTYPE_INNER_L4_FRAG     |
1160                                             RTE_PTYPE_INNER_L2_ETHER,
1161                 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_INNER_L3_IPV6     |
1162                                             RTE_PTYPE_INNER_L4_FRAG     |
1163                                             RTE_PTYPE_INNER_L2_ETHER,
1164                 /* VLANs */
1165                 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_INNER_L3_IPV4     |
1166                                             RTE_PTYPE_INNER_L2_ETHER_VLAN,
1167                 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_INNER_L3_IPV6     |
1168                                             RTE_PTYPE_INNER_L2_ETHER_VLAN,
1169                 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
1170                                                 RTE_PTYPE_INNER_L4_TCP  |
1171                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1172                 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
1173                                                 RTE_PTYPE_INNER_L4_TCP  |
1174                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1175                 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
1176                                                 RTE_PTYPE_INNER_L4_UDP  |
1177                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1178                 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
1179                                                 RTE_PTYPE_INNER_L4_UDP  |
1180                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1181                 /* Frags with VLAN */
1182                 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV4 |
1183                                                  RTE_PTYPE_INNER_L4_FRAG |
1184                                                  RTE_PTYPE_INNER_L2_ETHER_VLAN,
1185                 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV6 |
1186                                                  RTE_PTYPE_INNER_L4_FRAG |
1187                                                  RTE_PTYPE_INNER_L2_ETHER_VLAN,
1188         };
1189
1190         /* Bits (0..3) provides L3/L4 protocol type */
1191         /* Bits (4,5) provides frag and VLAN info */
1192         val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
1193                PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
1194                (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
1195                 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) |
1196                (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1197                 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) |
1198                 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK <<
1199                  PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags;
1200
1201         if (val < QEDE_PKT_TYPE_MAX)
1202                 return ptype_lkup_tbl[val];
1203
1204         return RTE_PTYPE_UNKNOWN;
1205 }
1206
1207 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
1208 {
1209         uint16_t val;
1210
1211         /* Lookup table */
1212         static const uint32_t
1213         ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
1214                 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L2_ETHER,
1215                 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L2_ETHER,
1216                 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4    |
1217                                            RTE_PTYPE_L4_TCP     |
1218                                            RTE_PTYPE_L2_ETHER,
1219                 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6    |
1220                                            RTE_PTYPE_L4_TCP     |
1221                                            RTE_PTYPE_L2_ETHER,
1222                 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4    |
1223                                            RTE_PTYPE_L4_UDP     |
1224                                            RTE_PTYPE_L2_ETHER,
1225                 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6    |
1226                                            RTE_PTYPE_L4_UDP     |
1227                                            RTE_PTYPE_L2_ETHER,
1228                 /* Frags with no VLAN */
1229                 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_L3_IPV4   |
1230                                             RTE_PTYPE_L4_FRAG   |
1231                                             RTE_PTYPE_L2_ETHER,
1232                 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_L3_IPV6   |
1233                                             RTE_PTYPE_L4_FRAG   |
1234                                             RTE_PTYPE_L2_ETHER,
1235                 /* VLANs */
1236                 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_L3_IPV4           |
1237                                             RTE_PTYPE_L2_ETHER_VLAN,
1238                 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_L3_IPV6           |
1239                                             RTE_PTYPE_L2_ETHER_VLAN,
1240                 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_L3_IPV4       |
1241                                                 RTE_PTYPE_L4_TCP        |
1242                                                 RTE_PTYPE_L2_ETHER_VLAN,
1243                 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_L3_IPV6       |
1244                                                 RTE_PTYPE_L4_TCP        |
1245                                                 RTE_PTYPE_L2_ETHER_VLAN,
1246                 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_L3_IPV4       |
1247                                                 RTE_PTYPE_L4_UDP        |
1248                                                 RTE_PTYPE_L2_ETHER_VLAN,
1249                 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_L3_IPV6       |
1250                                                 RTE_PTYPE_L4_UDP        |
1251                                                 RTE_PTYPE_L2_ETHER_VLAN,
1252                 /* Frags with VLAN */
1253                 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_L3_IPV4      |
1254                                                  RTE_PTYPE_L4_FRAG      |
1255                                                  RTE_PTYPE_L2_ETHER_VLAN,
1256                 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_L3_IPV6      |
1257                                                  RTE_PTYPE_L4_FRAG      |
1258                                                  RTE_PTYPE_L2_ETHER_VLAN,
1259         };
1260
1261         /* Bits (0..3) provides L3/L4 protocol type */
1262         /* Bits (4,5) provides frag and VLAN info */
1263         val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
1264                PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
1265                (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
1266                 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) |
1267                (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1268                 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) |
1269                 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK <<
1270                  PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags;
1271
1272         if (val < QEDE_PKT_TYPE_MAX)
1273                 return ptype_lkup_tbl[val];
1274
1275         return RTE_PTYPE_UNKNOWN;
1276 }
1277
1278 static inline uint8_t
1279 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
1280 {
1281         struct rte_ipv4_hdr *ip;
1282         uint16_t pkt_csum;
1283         uint16_t calc_csum;
1284         uint16_t val;
1285
1286         val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1287                 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
1288
1289         if (unlikely(val)) {
1290                 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
1291                 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
1292                         ip = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
1293                                            sizeof(struct rte_ether_hdr));
1294                         pkt_csum = ip->hdr_checksum;
1295                         ip->hdr_checksum = 0;
1296                         calc_csum = rte_ipv4_cksum(ip);
1297                         ip->hdr_checksum = pkt_csum;
1298                         return (calc_csum != pkt_csum);
1299                 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
1300                         return 1;
1301                 }
1302         }
1303         return 0;
1304 }
1305
1306 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
1307 {
1308         ecore_chain_consume(&rxq->rx_bd_ring);
1309         rxq->sw_rx_cons++;
1310 }
1311
1312 static inline void
1313 qede_reuse_page(__rte_unused struct qede_dev *qdev,
1314                 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
1315 {
1316         struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
1317         uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
1318         struct qede_rx_entry *curr_prod;
1319         dma_addr_t new_mapping;
1320
1321         curr_prod = &rxq->sw_rx_ring[idx];
1322         *curr_prod = *curr_cons;
1323
1324         new_mapping = rte_mbuf_data_iova_default(curr_prod->mbuf) +
1325                       curr_prod->page_offset;
1326
1327         rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
1328         rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
1329
1330         rxq->sw_rx_prod++;
1331 }
1332
1333 static inline void
1334 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
1335                         struct qede_dev *qdev, uint8_t count)
1336 {
1337         struct qede_rx_entry *curr_cons;
1338
1339         for (; count > 0; count--) {
1340                 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
1341                 qede_reuse_page(qdev, rxq, curr_cons);
1342                 qede_rx_bd_ring_consume(rxq);
1343         }
1344 }
1345
1346 static inline void
1347 qede_rx_process_tpa_cmn_cont_end_cqe(__rte_unused struct qede_dev *qdev,
1348                                      struct qede_rx_queue *rxq,
1349                                      uint8_t agg_index, uint16_t len)
1350 {
1351         struct qede_agg_info *tpa_info;
1352         struct rte_mbuf *curr_frag; /* Pointer to currently filled TPA seg */
1353         uint16_t cons_idx;
1354
1355         /* Under certain conditions it is possible that FW may not consume
1356          * additional or new BD. So decision to consume the BD must be made
1357          * based on len_list[0].
1358          */
1359         if (rte_le_to_cpu_16(len)) {
1360                 tpa_info = &rxq->tpa_info[agg_index];
1361                 cons_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1362                 curr_frag = rxq->sw_rx_ring[cons_idx].mbuf;
1363                 assert(curr_frag);
1364                 curr_frag->nb_segs = 1;
1365                 curr_frag->pkt_len = rte_le_to_cpu_16(len);
1366                 curr_frag->data_len = curr_frag->pkt_len;
1367                 tpa_info->tpa_tail->next = curr_frag;
1368                 tpa_info->tpa_tail = curr_frag;
1369                 qede_rx_bd_ring_consume(rxq);
1370                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1371                         PMD_RX_LOG(ERR, rxq, "mbuf allocation fails\n");
1372                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1373                         rxq->rx_alloc_errors++;
1374                 }
1375         }
1376 }
1377
1378 static inline void
1379 qede_rx_process_tpa_cont_cqe(struct qede_dev *qdev,
1380                              struct qede_rx_queue *rxq,
1381                              struct eth_fast_path_rx_tpa_cont_cqe *cqe)
1382 {
1383         PMD_RX_LOG(INFO, rxq, "TPA cont[%d] - len [%d]\n",
1384                    cqe->tpa_agg_index, rte_le_to_cpu_16(cqe->len_list[0]));
1385         /* only len_list[0] will have value */
1386         qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
1387                                              cqe->len_list[0]);
1388 }
1389
1390 static inline void
1391 qede_rx_process_tpa_end_cqe(struct qede_dev *qdev,
1392                             struct qede_rx_queue *rxq,
1393                             struct eth_fast_path_rx_tpa_end_cqe *cqe)
1394 {
1395         struct rte_mbuf *rx_mb; /* Pointer to head of the chained agg */
1396
1397         qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
1398                                              cqe->len_list[0]);
1399         /* Update total length and frags based on end TPA */
1400         rx_mb = rxq->tpa_info[cqe->tpa_agg_index].tpa_head;
1401         /* TODO:  Add Sanity Checks */
1402         rx_mb->nb_segs = cqe->num_of_bds;
1403         rx_mb->pkt_len = cqe->total_packet_len;
1404
1405         PMD_RX_LOG(INFO, rxq, "TPA End[%d] reason %d cqe_len %d nb_segs %d"
1406                    " pkt_len %d\n", cqe->tpa_agg_index, cqe->end_reason,
1407                    rte_le_to_cpu_16(cqe->len_list[0]), rx_mb->nb_segs,
1408                    rx_mb->pkt_len);
1409 }
1410
1411 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
1412 {
1413         uint32_t val;
1414
1415         /* Lookup table */
1416         static const uint32_t
1417         ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
1418                 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
1419                 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
1420                 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
1421                 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
1422                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
1423                                 RTE_PTYPE_TUNNEL_GENEVE,
1424                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
1425                                 RTE_PTYPE_TUNNEL_GRE,
1426                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
1427                                 RTE_PTYPE_TUNNEL_VXLAN,
1428                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
1429                                 RTE_PTYPE_TUNNEL_GENEVE,
1430                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
1431                                 RTE_PTYPE_TUNNEL_GRE,
1432                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
1433                                 RTE_PTYPE_TUNNEL_VXLAN,
1434                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
1435                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1436                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
1437                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1438                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
1439                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1440                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
1441                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1442                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
1443                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1444                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
1445                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1446                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
1447                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1448                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
1449                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1450                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
1451                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1452                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
1453                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1454                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
1455                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1456                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
1457                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1458         };
1459
1460         /* Cover bits[4-0] to include tunn_type and next protocol */
1461         val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
1462                 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
1463                 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
1464                 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
1465
1466         if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
1467                 return ptype_tunn_lkup_tbl[val];
1468         else
1469                 return RTE_PTYPE_UNKNOWN;
1470 }
1471
1472 static inline int
1473 qede_process_sg_pkts(void *p_rxq,  struct rte_mbuf *rx_mb,
1474                      uint8_t num_segs, uint16_t pkt_len)
1475 {
1476         struct qede_rx_queue *rxq = p_rxq;
1477         struct qede_dev *qdev = rxq->qdev;
1478         register struct rte_mbuf *seg1 = NULL;
1479         register struct rte_mbuf *seg2 = NULL;
1480         uint16_t sw_rx_index;
1481         uint16_t cur_size;
1482
1483         seg1 = rx_mb;
1484         while (num_segs) {
1485                 cur_size = pkt_len > rxq->rx_buf_size ? rxq->rx_buf_size :
1486                                                         pkt_len;
1487                 if (unlikely(!cur_size)) {
1488                         PMD_RX_LOG(ERR, rxq, "Length is 0 while %u BDs"
1489                                    " left for mapping jumbo\n", num_segs);
1490                         qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
1491                         return -EINVAL;
1492                 }
1493                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1494                 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
1495                 qede_rx_bd_ring_consume(rxq);
1496                 pkt_len -= cur_size;
1497                 seg2->data_len = cur_size;
1498                 seg1->next = seg2;
1499                 seg1 = seg1->next;
1500                 num_segs--;
1501                 rxq->rx_segs++;
1502         }
1503
1504         return 0;
1505 }
1506
1507 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1508 static inline void
1509 print_rx_bd_info(struct rte_mbuf *m, struct qede_rx_queue *rxq,
1510                  uint8_t bitfield)
1511 {
1512         PMD_RX_LOG(INFO, rxq,
1513                 "len 0x%04x bf 0x%04x hash_val 0x%x"
1514                 " ol_flags 0x%04lx l2=%s l3=%s l4=%s tunn=%s"
1515                 " inner_l2=%s inner_l3=%s inner_l4=%s\n",
1516                 m->data_len, bitfield, m->hash.rss,
1517                 (unsigned long)m->ol_flags,
1518                 rte_get_ptype_l2_name(m->packet_type),
1519                 rte_get_ptype_l3_name(m->packet_type),
1520                 rte_get_ptype_l4_name(m->packet_type),
1521                 rte_get_ptype_tunnel_name(m->packet_type),
1522                 rte_get_ptype_inner_l2_name(m->packet_type),
1523                 rte_get_ptype_inner_l3_name(m->packet_type),
1524                 rte_get_ptype_inner_l4_name(m->packet_type));
1525 }
1526 #endif
1527
1528 uint16_t
1529 qede_recv_pkts_regular(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1530 {
1531         struct eth_fast_path_rx_reg_cqe *fp_cqe = NULL;
1532         register struct rte_mbuf *rx_mb = NULL;
1533         struct qede_rx_queue *rxq = p_rxq;
1534         struct qede_dev *qdev = rxq->qdev;
1535         struct ecore_dev *edev = &qdev->edev;
1536         union eth_rx_cqe *cqe;
1537         uint64_t ol_flags;
1538         enum eth_rx_cqe_type cqe_type;
1539         int rss_enable = qdev->rss_enable;
1540         int rx_alloc_count = 0;
1541         uint32_t packet_type;
1542         uint32_t rss_hash;
1543         uint16_t vlan_tci, port_id;
1544         uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index, num_rx_bds;
1545         uint16_t rx_pkt = 0;
1546         uint16_t pkt_len = 0;
1547         uint16_t len; /* Length of first BD */
1548         uint16_t preload_idx;
1549         uint16_t parse_flag;
1550 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1551         uint8_t bitfield_val;
1552 #endif
1553         uint8_t offset, flags, bd_num;
1554
1555
1556         /* Allocate buffers that we used in previous loop */
1557         if (rxq->rx_alloc_count) {
1558                 if (unlikely(qede_alloc_rx_bulk_mbufs(rxq,
1559                              rxq->rx_alloc_count))) {
1560                         struct rte_eth_dev *dev;
1561
1562                         PMD_RX_LOG(ERR, rxq,
1563                                    "New buffer allocation failed,"
1564                                    "dropping incoming packetn");
1565                         dev = &rte_eth_devices[rxq->port_id];
1566                         dev->data->rx_mbuf_alloc_failed +=
1567                                                         rxq->rx_alloc_count;
1568                         rxq->rx_alloc_errors += rxq->rx_alloc_count;
1569                         return 0;
1570                 }
1571                 qede_update_rx_prod(qdev, rxq);
1572                 rxq->rx_alloc_count = 0;
1573         }
1574
1575         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
1576         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1577
1578         rte_rmb();
1579
1580         if (hw_comp_cons == sw_comp_cons)
1581                 return 0;
1582
1583         num_rx_bds =  NUM_RX_BDS(rxq);
1584         port_id = rxq->port_id;
1585
1586         while (sw_comp_cons != hw_comp_cons) {
1587                 ol_flags = 0;
1588                 packet_type = RTE_PTYPE_UNKNOWN;
1589                 vlan_tci = 0;
1590                 rss_hash = 0;
1591
1592                 /* Get the CQE from the completion ring */
1593                 cqe =
1594                     (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
1595                 cqe_type = cqe->fast_path_regular.type;
1596                 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type);
1597
1598                 if (likely(cqe_type == ETH_RX_CQE_TYPE_REGULAR)) {
1599                         fp_cqe = &cqe->fast_path_regular;
1600                 } else {
1601                         if (cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH) {
1602                                 PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n");
1603                                 ecore_eth_cqe_completion
1604                                         (&edev->hwfns[rxq->queue_id %
1605                                                       edev->num_hwfns],
1606                                          (struct eth_slow_path_rx_cqe *)cqe);
1607                         }
1608                         goto next_cqe;
1609                 }
1610
1611                 /* Get the data from the SW ring */
1612                 sw_rx_index = rxq->sw_rx_cons & num_rx_bds;
1613                 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
1614                 assert(rx_mb != NULL);
1615
1616                 parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);
1617                 offset = fp_cqe->placement_offset;
1618                 len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
1619                 pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1620                 vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1621                 rss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash);
1622                 bd_num = fp_cqe->bd_num;
1623 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1624                 bitfield_val = fp_cqe->bitfields;
1625 #endif
1626
1627                 if (unlikely(qede_tunn_exist(parse_flag))) {
1628                         PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n");
1629                         if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1630                                 PMD_RX_LOG(ERR, rxq,
1631                                             "L4 csum failed, flags = 0x%x\n",
1632                                             parse_flag);
1633                                 rxq->rx_hw_errors++;
1634                                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1635                         } else {
1636                                 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1637                         }
1638
1639                         if (unlikely(qede_check_tunn_csum_l3(parse_flag))) {
1640                                 PMD_RX_LOG(ERR, rxq,
1641                                         "Outer L3 csum failed, flags = 0x%x\n",
1642                                         parse_flag);
1643                                 rxq->rx_hw_errors++;
1644                                 ol_flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
1645                         } else {
1646                                 ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1647                         }
1648
1649                         flags = fp_cqe->tunnel_pars_flags.flags;
1650
1651                         /* Tunnel_type */
1652                         packet_type =
1653                                 qede_rx_cqe_to_tunn_pkt_type(flags);
1654
1655                         /* Inner header */
1656                         packet_type |=
1657                               qede_rx_cqe_to_pkt_type_inner(parse_flag);
1658
1659                         /* Outer L3/L4 types is not available in CQE */
1660                         packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1661
1662                         /* Outer L3/L4 types is not available in CQE.
1663                          * Need to add offset to parse correctly,
1664                          */
1665                         rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1666                         packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1667                 } else {
1668                         packet_type |= qede_rx_cqe_to_pkt_type(parse_flag);
1669                 }
1670
1671                 /* Common handling for non-tunnel packets and for inner
1672                  * headers in the case of tunnel.
1673                  */
1674                 if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1675                         PMD_RX_LOG(ERR, rxq,
1676                                     "L4 csum failed, flags = 0x%x\n",
1677                                     parse_flag);
1678                         rxq->rx_hw_errors++;
1679                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
1680                 } else {
1681                         ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1682                 }
1683                 if (unlikely(qede_check_notunn_csum_l3(rx_mb, parse_flag))) {
1684                         PMD_RX_LOG(ERR, rxq, "IP csum failed, flags = 0x%x\n",
1685                                    parse_flag);
1686                         rxq->rx_hw_errors++;
1687                         ol_flags |= PKT_RX_IP_CKSUM_BAD;
1688                 } else {
1689                         ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1690                 }
1691
1692                 if (unlikely(CQE_HAS_VLAN(parse_flag) ||
1693                              CQE_HAS_OUTER_VLAN(parse_flag))) {
1694                         /* Note: FW doesn't indicate Q-in-Q packet */
1695                         ol_flags |= PKT_RX_VLAN;
1696                         if (qdev->vlan_strip_flg) {
1697                                 ol_flags |= PKT_RX_VLAN_STRIPPED;
1698                                 rx_mb->vlan_tci = vlan_tci;
1699                         }
1700                 }
1701
1702                 if (rss_enable) {
1703                         ol_flags |= PKT_RX_RSS_HASH;
1704                         rx_mb->hash.rss = rss_hash;
1705                 }
1706
1707                 rx_alloc_count++;
1708                 qede_rx_bd_ring_consume(rxq);
1709
1710                 /* Prefetch next mbuf while processing current one. */
1711                 preload_idx = rxq->sw_rx_cons & num_rx_bds;
1712                 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1713
1714                 /* Update rest of the MBUF fields */
1715                 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1716                 rx_mb->port = port_id;
1717                 rx_mb->ol_flags = ol_flags;
1718                 rx_mb->data_len = len;
1719                 rx_mb->packet_type = packet_type;
1720 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1721                 print_rx_bd_info(rx_mb, rxq, bitfield_val);
1722 #endif
1723                 rx_mb->nb_segs = bd_num;
1724                 rx_mb->pkt_len = pkt_len;
1725
1726                 rx_pkts[rx_pkt] = rx_mb;
1727                 rx_pkt++;
1728
1729 next_cqe:
1730                 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1731                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1732                 if (rx_pkt == nb_pkts) {
1733                         PMD_RX_LOG(DEBUG, rxq,
1734                                    "Budget reached nb_pkts=%u received=%u",
1735                                    rx_pkt, nb_pkts);
1736                         break;
1737                 }
1738         }
1739
1740         /* Request number of bufferes to be allocated in next loop */
1741         rxq->rx_alloc_count = rx_alloc_count;
1742
1743         rxq->rcv_pkts += rx_pkt;
1744         rxq->rx_segs += rx_pkt;
1745         PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
1746
1747         return rx_pkt;
1748 }
1749
1750 uint16_t
1751 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1752 {
1753         struct qede_rx_queue *rxq = p_rxq;
1754         struct qede_dev *qdev = rxq->qdev;
1755         struct ecore_dev *edev = &qdev->edev;
1756         uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
1757         uint16_t rx_pkt = 0;
1758         union eth_rx_cqe *cqe;
1759         struct eth_fast_path_rx_reg_cqe *fp_cqe = NULL;
1760         register struct rte_mbuf *rx_mb = NULL;
1761         register struct rte_mbuf *seg1 = NULL;
1762         enum eth_rx_cqe_type cqe_type;
1763         uint16_t pkt_len = 0; /* Sum of all BD segments */
1764         uint16_t len; /* Length of first BD */
1765         uint8_t num_segs = 1;
1766         uint16_t preload_idx;
1767         uint16_t parse_flag;
1768 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1769         uint8_t bitfield_val;
1770 #endif
1771         uint8_t tunn_parse_flag;
1772         struct eth_fast_path_rx_tpa_start_cqe *cqe_start_tpa;
1773         uint64_t ol_flags;
1774         uint32_t packet_type;
1775         uint16_t vlan_tci;
1776         bool tpa_start_flg;
1777         uint8_t offset, tpa_agg_idx, flags;
1778         struct qede_agg_info *tpa_info = NULL;
1779         uint32_t rss_hash;
1780         int rx_alloc_count = 0;
1781
1782
1783         /* Allocate buffers that we used in previous loop */
1784         if (rxq->rx_alloc_count) {
1785                 if (unlikely(qede_alloc_rx_bulk_mbufs(rxq,
1786                              rxq->rx_alloc_count))) {
1787                         struct rte_eth_dev *dev;
1788
1789                         PMD_RX_LOG(ERR, rxq,
1790                                    "New buffer allocation failed,"
1791                                    "dropping incoming packetn");
1792                         dev = &rte_eth_devices[rxq->port_id];
1793                         dev->data->rx_mbuf_alloc_failed +=
1794                                                         rxq->rx_alloc_count;
1795                         rxq->rx_alloc_errors += rxq->rx_alloc_count;
1796                         return 0;
1797                 }
1798                 qede_update_rx_prod(qdev, rxq);
1799                 rxq->rx_alloc_count = 0;
1800         }
1801
1802         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
1803         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1804
1805         rte_rmb();
1806
1807         if (hw_comp_cons == sw_comp_cons)
1808                 return 0;
1809
1810         while (sw_comp_cons != hw_comp_cons) {
1811                 ol_flags = 0;
1812                 packet_type = RTE_PTYPE_UNKNOWN;
1813                 vlan_tci = 0;
1814                 tpa_start_flg = false;
1815                 rss_hash = 0;
1816
1817                 /* Get the CQE from the completion ring */
1818                 cqe =
1819                     (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
1820                 cqe_type = cqe->fast_path_regular.type;
1821                 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type);
1822
1823                 switch (cqe_type) {
1824                 case ETH_RX_CQE_TYPE_REGULAR:
1825                         fp_cqe = &cqe->fast_path_regular;
1826                 break;
1827                 case ETH_RX_CQE_TYPE_TPA_START:
1828                         cqe_start_tpa = &cqe->fast_path_tpa_start;
1829                         tpa_info = &rxq->tpa_info[cqe_start_tpa->tpa_agg_index];
1830                         tpa_start_flg = true;
1831                         /* Mark it as LRO packet */
1832                         ol_flags |= PKT_RX_LRO;
1833                         /* In split mode,  seg_len is same as len_on_first_bd
1834                          * and bw_ext_bd_len_list will be empty since there are
1835                          * no additional buffers
1836                          */
1837                         PMD_RX_LOG(INFO, rxq,
1838                          "TPA start[%d] - len_on_first_bd %d header %d"
1839                          " [bd_list[0] %d], [seg_len %d]\n",
1840                          cqe_start_tpa->tpa_agg_index,
1841                          rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd),
1842                          cqe_start_tpa->header_len,
1843                          rte_le_to_cpu_16(cqe_start_tpa->bw_ext_bd_len_list[0]),
1844                          rte_le_to_cpu_16(cqe_start_tpa->seg_len));
1845
1846                 break;
1847                 case ETH_RX_CQE_TYPE_TPA_CONT:
1848                         qede_rx_process_tpa_cont_cqe(qdev, rxq,
1849                                                      &cqe->fast_path_tpa_cont);
1850                         goto next_cqe;
1851                 case ETH_RX_CQE_TYPE_TPA_END:
1852                         qede_rx_process_tpa_end_cqe(qdev, rxq,
1853                                                     &cqe->fast_path_tpa_end);
1854                         tpa_agg_idx = cqe->fast_path_tpa_end.tpa_agg_index;
1855                         tpa_info = &rxq->tpa_info[tpa_agg_idx];
1856                         rx_mb = rxq->tpa_info[tpa_agg_idx].tpa_head;
1857                         goto tpa_end;
1858                 case ETH_RX_CQE_TYPE_SLOW_PATH:
1859                         PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n");
1860                         ecore_eth_cqe_completion(
1861                                 &edev->hwfns[rxq->queue_id % edev->num_hwfns],
1862                                 (struct eth_slow_path_rx_cqe *)cqe);
1863                         /* fall-thru */
1864                 default:
1865                         goto next_cqe;
1866                 }
1867
1868                 /* Get the data from the SW ring */
1869                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1870                 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
1871                 assert(rx_mb != NULL);
1872
1873                 /* Handle regular CQE or TPA start CQE */
1874                 if (!tpa_start_flg) {
1875                         parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);
1876                         offset = fp_cqe->placement_offset;
1877                         len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
1878                         pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1879                         vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1880                         rss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash);
1881 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1882                         bitfield_val = fp_cqe->bitfields;
1883 #endif
1884                 } else {
1885                         parse_flag =
1886                             rte_le_to_cpu_16(cqe_start_tpa->pars_flags.flags);
1887                         offset = cqe_start_tpa->placement_offset;
1888                         /* seg_len = len_on_first_bd */
1889                         len = rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd);
1890                         vlan_tci = rte_le_to_cpu_16(cqe_start_tpa->vlan_tag);
1891 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1892                         bitfield_val = cqe_start_tpa->bitfields;
1893 #endif
1894                         rss_hash = rte_le_to_cpu_32(cqe_start_tpa->rss_hash);
1895                 }
1896                 if (qede_tunn_exist(parse_flag)) {
1897                         PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n");
1898                         if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1899                                 PMD_RX_LOG(ERR, rxq,
1900                                             "L4 csum failed, flags = 0x%x\n",
1901                                             parse_flag);
1902                                 rxq->rx_hw_errors++;
1903                                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1904                         } else {
1905                                 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1906                         }
1907
1908                         if (unlikely(qede_check_tunn_csum_l3(parse_flag))) {
1909                                 PMD_RX_LOG(ERR, rxq,
1910                                         "Outer L3 csum failed, flags = 0x%x\n",
1911                                         parse_flag);
1912                                   rxq->rx_hw_errors++;
1913                                   ol_flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
1914                         } else {
1915                                   ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1916                         }
1917
1918                         if (tpa_start_flg)
1919                                 flags = cqe_start_tpa->tunnel_pars_flags.flags;
1920                         else
1921                                 flags = fp_cqe->tunnel_pars_flags.flags;
1922                         tunn_parse_flag = flags;
1923
1924                         /* Tunnel_type */
1925                         packet_type =
1926                                 qede_rx_cqe_to_tunn_pkt_type(tunn_parse_flag);
1927
1928                         /* Inner header */
1929                         packet_type |=
1930                               qede_rx_cqe_to_pkt_type_inner(parse_flag);
1931
1932                         /* Outer L3/L4 types is not available in CQE */
1933                         packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1934
1935                         /* Outer L3/L4 types is not available in CQE.
1936                          * Need to add offset to parse correctly,
1937                          */
1938                         rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1939                         packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1940                 } else {
1941                         packet_type |= qede_rx_cqe_to_pkt_type(parse_flag);
1942                 }
1943
1944                 /* Common handling for non-tunnel packets and for inner
1945                  * headers in the case of tunnel.
1946                  */
1947                 if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1948                         PMD_RX_LOG(ERR, rxq,
1949                                     "L4 csum failed, flags = 0x%x\n",
1950                                     parse_flag);
1951                         rxq->rx_hw_errors++;
1952                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
1953                 } else {
1954                         ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1955                 }
1956                 if (unlikely(qede_check_notunn_csum_l3(rx_mb, parse_flag))) {
1957                         PMD_RX_LOG(ERR, rxq, "IP csum failed, flags = 0x%x\n",
1958                                    parse_flag);
1959                         rxq->rx_hw_errors++;
1960                         ol_flags |= PKT_RX_IP_CKSUM_BAD;
1961                 } else {
1962                         ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1963                 }
1964
1965                 if (CQE_HAS_VLAN(parse_flag) ||
1966                     CQE_HAS_OUTER_VLAN(parse_flag)) {
1967                         /* Note: FW doesn't indicate Q-in-Q packet */
1968                         ol_flags |= PKT_RX_VLAN;
1969                         if (qdev->vlan_strip_flg) {
1970                                 ol_flags |= PKT_RX_VLAN_STRIPPED;
1971                                 rx_mb->vlan_tci = vlan_tci;
1972                         }
1973                 }
1974
1975                 /* RSS Hash */
1976                 if (qdev->rss_enable) {
1977                         ol_flags |= PKT_RX_RSS_HASH;
1978                         rx_mb->hash.rss = rss_hash;
1979                 }
1980
1981                 rx_alloc_count++;
1982                 qede_rx_bd_ring_consume(rxq);
1983
1984                 if (!tpa_start_flg && fp_cqe->bd_num > 1) {
1985                         PMD_RX_LOG(DEBUG, rxq, "Jumbo-over-BD packet: %02x BDs"
1986                                    " len on first: %04x Total Len: %04x",
1987                                    fp_cqe->bd_num, len, pkt_len);
1988                         num_segs = fp_cqe->bd_num - 1;
1989                         seg1 = rx_mb;
1990                         if (qede_process_sg_pkts(p_rxq, seg1, num_segs,
1991                                                  pkt_len - len))
1992                                 goto next_cqe;
1993
1994                         rx_alloc_count += num_segs;
1995                         rxq->rx_segs += num_segs;
1996                 }
1997                 rxq->rx_segs++; /* for the first segment */
1998
1999                 /* Prefetch next mbuf while processing current one. */
2000                 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
2001                 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
2002
2003                 /* Update rest of the MBUF fields */
2004                 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
2005                 rx_mb->port = rxq->port_id;
2006                 rx_mb->ol_flags = ol_flags;
2007                 rx_mb->data_len = len;
2008                 rx_mb->packet_type = packet_type;
2009 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
2010                 print_rx_bd_info(rx_mb, rxq, bitfield_val);
2011 #endif
2012                 if (!tpa_start_flg) {
2013                         rx_mb->nb_segs = fp_cqe->bd_num;
2014                         rx_mb->pkt_len = pkt_len;
2015                 } else {
2016                         /* store ref to the updated mbuf */
2017                         tpa_info->tpa_head = rx_mb;
2018                         tpa_info->tpa_tail = tpa_info->tpa_head;
2019                 }
2020                 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
2021 tpa_end:
2022                 if (!tpa_start_flg) {
2023                         rx_pkts[rx_pkt] = rx_mb;
2024                         rx_pkt++;
2025                 }
2026 next_cqe:
2027                 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
2028                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
2029                 if (rx_pkt == nb_pkts) {
2030                         PMD_RX_LOG(DEBUG, rxq,
2031                                    "Budget reached nb_pkts=%u received=%u",
2032                                    rx_pkt, nb_pkts);
2033                         break;
2034                 }
2035         }
2036
2037         /* Request number of bufferes to be allocated in next loop */
2038         rxq->rx_alloc_count = rx_alloc_count;
2039
2040         rxq->rcv_pkts += rx_pkt;
2041
2042         PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
2043
2044         return rx_pkt;
2045 }
2046
2047 uint16_t
2048 qede_recv_pkts_cmt(void *p_fp_cmt, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2049 {
2050         struct qede_fastpath_cmt *fp_cmt = p_fp_cmt;
2051         uint16_t eng0_pkts, eng1_pkts;
2052
2053         eng0_pkts = nb_pkts / 2;
2054
2055         eng0_pkts = qede_recv_pkts(fp_cmt->fp0->rxq, rx_pkts, eng0_pkts);
2056
2057         eng1_pkts = nb_pkts - eng0_pkts;
2058
2059         eng1_pkts = qede_recv_pkts(fp_cmt->fp1->rxq, rx_pkts + eng0_pkts,
2060                                    eng1_pkts);
2061
2062         return eng0_pkts + eng1_pkts;
2063 }
2064
2065 /* Populate scatter gather buffer descriptor fields */
2066 static inline uint16_t
2067 qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg,
2068                   struct eth_tx_2nd_bd **bd2, struct eth_tx_3rd_bd **bd3,
2069                   uint16_t start_seg)
2070 {
2071         struct qede_tx_queue *txq = p_txq;
2072         struct eth_tx_bd *tx_bd = NULL;
2073         dma_addr_t mapping;
2074         uint16_t nb_segs = 0;
2075
2076         /* Check for scattered buffers */
2077         while (m_seg) {
2078                 if (start_seg == 0) {
2079                         if (!*bd2) {
2080                                 *bd2 = (struct eth_tx_2nd_bd *)
2081                                         ecore_chain_produce(&txq->tx_pbl);
2082                                 memset(*bd2, 0, sizeof(struct eth_tx_2nd_bd));
2083                                 nb_segs++;
2084                         }
2085                         mapping = rte_mbuf_data_iova(m_seg);
2086                         QEDE_BD_SET_ADDR_LEN(*bd2, mapping, m_seg->data_len);
2087                         PMD_TX_LOG(DEBUG, txq, "BD2 len %04x", m_seg->data_len);
2088                 } else if (start_seg == 1) {
2089                         if (!*bd3) {
2090                                 *bd3 = (struct eth_tx_3rd_bd *)
2091                                         ecore_chain_produce(&txq->tx_pbl);
2092                                 memset(*bd3, 0, sizeof(struct eth_tx_3rd_bd));
2093                                 nb_segs++;
2094                         }
2095                         mapping = rte_mbuf_data_iova(m_seg);
2096                         QEDE_BD_SET_ADDR_LEN(*bd3, mapping, m_seg->data_len);
2097                         PMD_TX_LOG(DEBUG, txq, "BD3 len %04x", m_seg->data_len);
2098                 } else {
2099                         tx_bd = (struct eth_tx_bd *)
2100                                 ecore_chain_produce(&txq->tx_pbl);
2101                         memset(tx_bd, 0, sizeof(*tx_bd));
2102                         nb_segs++;
2103                         mapping = rte_mbuf_data_iova(m_seg);
2104                         QEDE_BD_SET_ADDR_LEN(tx_bd, mapping, m_seg->data_len);
2105                         PMD_TX_LOG(DEBUG, txq, "BD len %04x", m_seg->data_len);
2106                 }
2107                 start_seg++;
2108                 m_seg = m_seg->next;
2109         }
2110
2111         /* Return total scattered buffers */
2112         return nb_segs;
2113 }
2114
2115 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2116 static inline void
2117 print_tx_bd_info(struct qede_tx_queue *txq,
2118                  struct eth_tx_1st_bd *bd1,
2119                  struct eth_tx_2nd_bd *bd2,
2120                  struct eth_tx_3rd_bd *bd3,
2121                  uint64_t tx_ol_flags)
2122 {
2123         char ol_buf[256] = { 0 }; /* for verbose prints */
2124
2125         if (bd1)
2126                 PMD_TX_LOG(INFO, txq,
2127                    "BD1: nbytes=0x%04x nbds=0x%04x bd_flags=0x%04x bf=0x%04x",
2128                    rte_cpu_to_le_16(bd1->nbytes), bd1->data.nbds,
2129                    bd1->data.bd_flags.bitfields,
2130                    rte_cpu_to_le_16(bd1->data.bitfields));
2131         if (bd2)
2132                 PMD_TX_LOG(INFO, txq,
2133                    "BD2: nbytes=0x%04x bf1=0x%04x bf2=0x%04x tunn_ip=0x%04x\n",
2134                    rte_cpu_to_le_16(bd2->nbytes), bd2->data.bitfields1,
2135                    bd2->data.bitfields2, bd2->data.tunn_ip_size);
2136         if (bd3)
2137                 PMD_TX_LOG(INFO, txq,
2138                    "BD3: nbytes=0x%04x bf=0x%04x MSS=0x%04x "
2139                    "tunn_l4_hdr_start_offset_w=0x%04x tunn_hdr_size=0x%04x\n",
2140                    rte_cpu_to_le_16(bd3->nbytes),
2141                    rte_cpu_to_le_16(bd3->data.bitfields),
2142                    rte_cpu_to_le_16(bd3->data.lso_mss),
2143                    bd3->data.tunn_l4_hdr_start_offset_w,
2144                    bd3->data.tunn_hdr_size_w);
2145
2146         rte_get_tx_ol_flag_list(tx_ol_flags, ol_buf, sizeof(ol_buf));
2147         PMD_TX_LOG(INFO, txq, "TX offloads = %s\n", ol_buf);
2148 }
2149 #endif
2150
2151 /* TX prepare to check packets meets TX conditions */
2152 uint16_t
2153 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2154 qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
2155                     uint16_t nb_pkts)
2156 {
2157         struct qede_tx_queue *txq = p_txq;
2158 #else
2159 qede_xmit_prep_pkts(__rte_unused void *p_txq, struct rte_mbuf **tx_pkts,
2160                     uint16_t nb_pkts)
2161 {
2162 #endif
2163         uint64_t ol_flags;
2164         struct rte_mbuf *m;
2165         uint16_t i;
2166 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2167         int ret;
2168 #endif
2169
2170         for (i = 0; i < nb_pkts; i++) {
2171                 m = tx_pkts[i];
2172                 ol_flags = m->ol_flags;
2173                 if (ol_flags & PKT_TX_TCP_SEG) {
2174                         if (m->nb_segs >= ETH_TX_MAX_BDS_PER_LSO_PACKET) {
2175                                 rte_errno = EINVAL;
2176                                 break;
2177                         }
2178                         /* TBD: confirm its ~9700B for both ? */
2179                         if (m->tso_segsz > ETH_TX_MAX_NON_LSO_PKT_LEN) {
2180                                 rte_errno = EINVAL;
2181                                 break;
2182                         }
2183                 } else {
2184                         if (m->nb_segs >= ETH_TX_MAX_BDS_PER_NON_LSO_PACKET) {
2185                                 rte_errno = EINVAL;
2186                                 break;
2187                         }
2188                 }
2189                 if (ol_flags & QEDE_TX_OFFLOAD_NOTSUP_MASK) {
2190                         /* We support only limited tunnel protocols */
2191                         if (ol_flags & PKT_TX_TUNNEL_MASK) {
2192                                 uint64_t temp;
2193
2194                                 temp = ol_flags & PKT_TX_TUNNEL_MASK;
2195                                 if (temp == PKT_TX_TUNNEL_VXLAN ||
2196                                     temp == PKT_TX_TUNNEL_GENEVE ||
2197                                     temp == PKT_TX_TUNNEL_MPLSINUDP ||
2198                                     temp == PKT_TX_TUNNEL_GRE)
2199                                         continue;
2200                         }
2201
2202                         rte_errno = ENOTSUP;
2203                         break;
2204                 }
2205
2206 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2207                 ret = rte_validate_tx_offload(m);
2208                 if (ret != 0) {
2209                         rte_errno = -ret;
2210                         break;
2211                 }
2212 #endif
2213         }
2214
2215 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2216         if (unlikely(i != nb_pkts))
2217                 PMD_TX_LOG(ERR, txq, "TX prepare failed for %u\n",
2218                            nb_pkts - i);
2219 #endif
2220         return i;
2221 }
2222
2223 #define MPLSINUDP_HDR_SIZE                      (12)
2224
2225 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2226 static inline void
2227 qede_mpls_tunn_tx_sanity_check(struct rte_mbuf *mbuf,
2228                                struct qede_tx_queue *txq)
2229 {
2230         if (((mbuf->outer_l2_len + mbuf->outer_l3_len) / 2) > 0xff)
2231                 PMD_TX_LOG(ERR, txq, "tunn_l4_hdr_start_offset overflow\n");
2232         if (((mbuf->outer_l2_len + mbuf->outer_l3_len +
2233                 MPLSINUDP_HDR_SIZE) / 2) > 0xff)
2234                 PMD_TX_LOG(ERR, txq, "tunn_hdr_size overflow\n");
2235         if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE) / 2) >
2236                 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK)
2237                 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
2238         if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2) >
2239                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
2240                 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
2241 }
2242 #endif
2243
2244 uint16_t
2245 qede_xmit_pkts_regular(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2246 {
2247         struct qede_tx_queue *txq = p_txq;
2248         struct qede_dev *qdev = txq->qdev;
2249         struct ecore_dev *edev = &qdev->edev;
2250         struct eth_tx_1st_bd *bd1;
2251         struct eth_tx_2nd_bd *bd2;
2252         struct eth_tx_3rd_bd *bd3;
2253         struct rte_mbuf *m_seg = NULL;
2254         struct rte_mbuf *mbuf;
2255         struct rte_mbuf **sw_tx_ring;
2256         uint16_t nb_tx_pkts;
2257         uint16_t bd_prod;
2258         uint16_t idx;
2259         uint16_t nb_frags = 0;
2260         uint16_t nb_pkt_sent = 0;
2261         uint8_t nbds;
2262         uint64_t tx_ol_flags;
2263         /* BD1 */
2264         uint16_t bd1_bf;
2265         uint8_t bd1_bd_flags_bf;
2266
2267         if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
2268                 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
2269                            nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
2270                 qede_process_tx_compl(edev, txq);
2271         }
2272
2273         nb_tx_pkts  = nb_pkts;
2274         bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2275         sw_tx_ring = txq->sw_tx_ring;
2276
2277         while (nb_tx_pkts--) {
2278                 /* Init flags/values */
2279                 nbds = 0;
2280                 bd1 = NULL;
2281                 bd2 = NULL;
2282                 bd3 = NULL;
2283                 bd1_bf = 0;
2284                 bd1_bd_flags_bf = 0;
2285                 nb_frags = 0;
2286
2287                 mbuf = *tx_pkts++;
2288                 assert(mbuf);
2289
2290
2291                 /* Check minimum TX BDS availability against available BDs */
2292                 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs))
2293                         break;
2294
2295                 tx_ol_flags = mbuf->ol_flags;
2296                 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
2297
2298                 if (unlikely(txq->nb_tx_avail <
2299                                 ETH_TX_MIN_BDS_PER_NON_LSO_PKT))
2300                         break;
2301                 bd1_bf |=
2302                        (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
2303                         << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
2304
2305                 /* Offload the IP checksum in the hardware */
2306                 if (tx_ol_flags & PKT_TX_IP_CKSUM)
2307                         bd1_bd_flags_bf |=
2308                                 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
2309
2310                 /* L4 checksum offload (tcp or udp) */
2311                 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
2312                     (tx_ol_flags & (PKT_TX_UDP_CKSUM | PKT_TX_TCP_CKSUM)))
2313                         bd1_bd_flags_bf |=
2314                                 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
2315
2316                 /* Fill the entry in the SW ring and the BDs in the FW ring */
2317                 idx = TX_PROD(txq);
2318                 sw_tx_ring[idx] = mbuf;
2319
2320                 /* BD1 */
2321                 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
2322                 memset(bd1, 0, sizeof(struct eth_tx_1st_bd));
2323                 nbds++;
2324
2325                 /* Map MBUF linear data for DMA and set in the BD1 */
2326                 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2327                                      mbuf->data_len);
2328                 bd1->data.bitfields = rte_cpu_to_le_16(bd1_bf);
2329                 bd1->data.bd_flags.bitfields = bd1_bd_flags_bf;
2330
2331                 /* Handle fragmented MBUF */
2332                 if (unlikely(mbuf->nb_segs > 1)) {
2333                         m_seg = mbuf->next;
2334
2335                         /* Encode scatter gather buffer descriptors */
2336                         nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3,
2337                                                      nbds - 1);
2338                 }
2339
2340                 bd1->data.nbds = nbds + nb_frags;
2341
2342                 txq->nb_tx_avail -= bd1->data.nbds;
2343                 txq->sw_tx_prod++;
2344                 bd_prod =
2345                     rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2346 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2347                 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);
2348 #endif
2349                 nb_pkt_sent++;
2350                 txq->xmit_pkts++;
2351         }
2352
2353         /* Write value of prod idx into bd_prod */
2354         txq->tx_db.data.bd_prod = bd_prod;
2355         rte_wmb();
2356         rte_compiler_barrier();
2357         DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
2358         rte_wmb();
2359
2360         /* Check again for Tx completions */
2361         qede_process_tx_compl(edev, txq);
2362
2363         PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d",
2364                    nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());
2365
2366         return nb_pkt_sent;
2367 }
2368
2369 uint16_t
2370 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2371 {
2372         struct qede_tx_queue *txq = p_txq;
2373         struct qede_dev *qdev = txq->qdev;
2374         struct ecore_dev *edev = &qdev->edev;
2375         struct rte_mbuf *mbuf;
2376         struct rte_mbuf *m_seg = NULL;
2377         uint16_t nb_tx_pkts;
2378         uint16_t bd_prod;
2379         uint16_t idx;
2380         uint16_t nb_frags;
2381         uint16_t nb_pkt_sent = 0;
2382         uint8_t nbds;
2383         bool lso_flg;
2384         bool mplsoudp_flg;
2385         __rte_unused bool tunn_flg;
2386         bool tunn_ipv6_ext_flg;
2387         struct eth_tx_1st_bd *bd1;
2388         struct eth_tx_2nd_bd *bd2;
2389         struct eth_tx_3rd_bd *bd3;
2390         uint64_t tx_ol_flags;
2391         uint16_t hdr_size;
2392         /* BD1 */
2393         uint16_t bd1_bf;
2394         uint8_t bd1_bd_flags_bf;
2395         uint16_t vlan;
2396         /* BD2 */
2397         uint16_t bd2_bf1;
2398         uint16_t bd2_bf2;
2399         /* BD3 */
2400         uint16_t mss;
2401         uint16_t bd3_bf;
2402
2403         uint8_t tunn_l4_hdr_start_offset;
2404         uint8_t tunn_hdr_size;
2405         uint8_t inner_l2_hdr_size;
2406         uint16_t inner_l4_hdr_offset;
2407
2408         if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
2409                 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
2410                            nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
2411                 qede_process_tx_compl(edev, txq);
2412         }
2413
2414         nb_tx_pkts  = nb_pkts;
2415         bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2416         while (nb_tx_pkts--) {
2417                 /* Init flags/values */
2418                 tunn_flg = false;
2419                 lso_flg = false;
2420                 nbds = 0;
2421                 vlan = 0;
2422                 bd1 = NULL;
2423                 bd2 = NULL;
2424                 bd3 = NULL;
2425                 hdr_size = 0;
2426                 bd1_bf = 0;
2427                 bd1_bd_flags_bf = 0;
2428                 bd2_bf1 = 0;
2429                 bd2_bf2 = 0;
2430                 mss = 0;
2431                 bd3_bf = 0;
2432                 mplsoudp_flg = false;
2433                 tunn_ipv6_ext_flg = false;
2434                 tunn_hdr_size = 0;
2435                 tunn_l4_hdr_start_offset = 0;
2436
2437                 mbuf = *tx_pkts++;
2438                 assert(mbuf);
2439
2440                 /* Check minimum TX BDS availability against available BDs */
2441                 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs))
2442                         break;
2443
2444                 tx_ol_flags = mbuf->ol_flags;
2445                 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
2446
2447                 /* TX prepare would have already checked supported tunnel Tx
2448                  * offloads. Don't rely on pkt_type marked by Rx, instead use
2449                  * tx_ol_flags to decide.
2450                  */
2451                 tunn_flg = !!(tx_ol_flags & PKT_TX_TUNNEL_MASK);
2452
2453                 if (tunn_flg) {
2454                         /* Check against max which is Tunnel IPv6 + ext */
2455                         if (unlikely(txq->nb_tx_avail <
2456                                 ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT))
2457                                         break;
2458
2459                         /* First indicate its a tunnel pkt */
2460                         bd1_bf |= ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
2461                                   ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
2462                         /* Legacy FW had flipped behavior in regard to this bit
2463                          * i.e. it needed to set to prevent FW from touching
2464                          * encapsulated packets when it didn't need to.
2465                          */
2466                         if (unlikely(txq->is_legacy)) {
2467                                 bd1_bf ^= 1 <<
2468                                         ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
2469                         }
2470
2471                         /* Outer IP checksum offload */
2472                         if (tx_ol_flags & (PKT_TX_OUTER_IP_CKSUM |
2473                                            PKT_TX_OUTER_IPV4)) {
2474                                 bd1_bd_flags_bf |=
2475                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
2476                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
2477                         }
2478
2479                         /**
2480                          * Currently, only inner checksum offload in MPLS-in-UDP
2481                          * tunnel with one MPLS label is supported. Both outer
2482                          * and inner layers  lengths need to be provided in
2483                          * mbuf.
2484                          */
2485                         if ((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
2486                                                 PKT_TX_TUNNEL_MPLSINUDP) {
2487                                 mplsoudp_flg = true;
2488 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2489                                 qede_mpls_tunn_tx_sanity_check(mbuf, txq);
2490 #endif
2491                                 /* Outer L4 offset in two byte words */
2492                                 tunn_l4_hdr_start_offset =
2493                                   (mbuf->outer_l2_len + mbuf->outer_l3_len) / 2;
2494                                 /* Tunnel header size in two byte words */
2495                                 tunn_hdr_size = (mbuf->outer_l2_len +
2496                                                 mbuf->outer_l3_len +
2497                                                 MPLSINUDP_HDR_SIZE) / 2;
2498                                 /* Inner L2 header size in two byte words */
2499                                 inner_l2_hdr_size = (mbuf->l2_len -
2500                                                 MPLSINUDP_HDR_SIZE) / 2;
2501                                 /* Inner L4 header offset from the beggining
2502                                  * of inner packet in two byte words
2503                                  */
2504                                 inner_l4_hdr_offset = (mbuf->l2_len -
2505                                         MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2;
2506
2507                                 /* Inner L2 size and address type */
2508                                 bd2_bf1 |= (inner_l2_hdr_size &
2509                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK) <<
2510                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT;
2511                                 bd2_bf1 |= (UNICAST_ADDRESS &
2512                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK) <<
2513                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT;
2514                                 /* Treated as IPv6+Ext */
2515                                 bd2_bf1 |=
2516                                     1 << ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT;
2517
2518                                 /* Mark inner IPv6 if present */
2519                                 if (tx_ol_flags & PKT_TX_IPV6)
2520                                         bd2_bf1 |=
2521                                                 1 << ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT;
2522
2523                                 /* Inner L4 offsets */
2524                                 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
2525                                      (tx_ol_flags & (PKT_TX_UDP_CKSUM |
2526                                                         PKT_TX_TCP_CKSUM))) {
2527                                         /* Determines if BD3 is needed */
2528                                         tunn_ipv6_ext_flg = true;
2529                                         if ((tx_ol_flags & PKT_TX_L4_MASK) ==
2530                                                         PKT_TX_UDP_CKSUM) {
2531                                                 bd2_bf1 |=
2532                                                         1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
2533                                         }
2534
2535                                         /* TODO other pseudo checksum modes are
2536                                          * not supported
2537                                          */
2538                                         bd2_bf1 |=
2539                                         ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
2540                                         ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT;
2541                                         bd2_bf2 |= (inner_l4_hdr_offset &
2542                                                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK) <<
2543                                                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
2544                                 }
2545                         } /* End MPLSoUDP */
2546                 } /* End Tunnel handling */
2547
2548                 if (tx_ol_flags & PKT_TX_TCP_SEG) {
2549                         lso_flg = true;
2550                         if (unlikely(txq->nb_tx_avail <
2551                                                 ETH_TX_MIN_BDS_PER_LSO_PKT))
2552                                 break;
2553                         /* For LSO, packet header and payload must reside on
2554                          * buffers pointed by different BDs. Using BD1 for HDR
2555                          * and BD2 onwards for data.
2556                          */
2557                         hdr_size = mbuf->l2_len + mbuf->l3_len + mbuf->l4_len;
2558                         if (tunn_flg)
2559                                 hdr_size += mbuf->outer_l2_len +
2560                                             mbuf->outer_l3_len;
2561
2562                         bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT;
2563                         bd1_bd_flags_bf |=
2564                                         1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
2565                         /* PKT_TX_TCP_SEG implies PKT_TX_TCP_CKSUM */
2566                         bd1_bd_flags_bf |=
2567                                         1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
2568                         mss = rte_cpu_to_le_16(mbuf->tso_segsz);
2569                         /* Using one header BD */
2570                         bd3_bf |= rte_cpu_to_le_16(1 <<
2571                                         ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
2572                 } else {
2573                         if (unlikely(txq->nb_tx_avail <
2574                                         ETH_TX_MIN_BDS_PER_NON_LSO_PKT))
2575                                 break;
2576                         bd1_bf |=
2577                                (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
2578                                 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
2579                 }
2580
2581                 /* Descriptor based VLAN insertion */
2582                 if (tx_ol_flags & PKT_TX_VLAN_PKT) {
2583                         vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
2584                         bd1_bd_flags_bf |=
2585                             1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
2586                 }
2587
2588                 /* Offload the IP checksum in the hardware */
2589                 if (tx_ol_flags & PKT_TX_IP_CKSUM) {
2590                         bd1_bd_flags_bf |=
2591                                 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
2592                         /* There's no DPDK flag to request outer-L4 csum
2593                          * offload. But in the case of tunnel if inner L3 or L4
2594                          * csum offload is requested then we need to force
2595                          * recalculation of L4 tunnel header csum also.
2596                          */
2597                         if (tunn_flg && ((tx_ol_flags & PKT_TX_TUNNEL_MASK) !=
2598                                                         PKT_TX_TUNNEL_GRE)) {
2599                                 bd1_bd_flags_bf |=
2600                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
2601                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
2602                         }
2603                 }
2604
2605                 /* L4 checksum offload (tcp or udp) */
2606                 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
2607                     (tx_ol_flags & (PKT_TX_UDP_CKSUM | PKT_TX_TCP_CKSUM))) {
2608                         bd1_bd_flags_bf |=
2609                                 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
2610                         /* There's no DPDK flag to request outer-L4 csum
2611                          * offload. But in the case of tunnel if inner L3 or L4
2612                          * csum offload is requested then we need to force
2613                          * recalculation of L4 tunnel header csum also.
2614                          */
2615                         if (tunn_flg) {
2616                                 bd1_bd_flags_bf |=
2617                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
2618                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
2619                         }
2620                 }
2621
2622                 /* Fill the entry in the SW ring and the BDs in the FW ring */
2623                 idx = TX_PROD(txq);
2624                 txq->sw_tx_ring[idx] = mbuf;
2625
2626                 /* BD1 */
2627                 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
2628                 memset(bd1, 0, sizeof(struct eth_tx_1st_bd));
2629                 nbds++;
2630
2631                 /* Map MBUF linear data for DMA and set in the BD1 */
2632                 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2633                                      mbuf->data_len);
2634                 bd1->data.bitfields = rte_cpu_to_le_16(bd1_bf);
2635                 bd1->data.bd_flags.bitfields = bd1_bd_flags_bf;
2636                 bd1->data.vlan = vlan;
2637
2638                 if (lso_flg || mplsoudp_flg) {
2639                         bd2 = (struct eth_tx_2nd_bd *)ecore_chain_produce
2640                                                         (&txq->tx_pbl);
2641                         memset(bd2, 0, sizeof(struct eth_tx_2nd_bd));
2642                         nbds++;
2643
2644                         /* BD1 */
2645                         QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2646                                              hdr_size);
2647                         /* BD2 */
2648                         QEDE_BD_SET_ADDR_LEN(bd2, (hdr_size +
2649                                              rte_mbuf_data_iova(mbuf)),
2650                                              mbuf->data_len - hdr_size);
2651                         bd2->data.bitfields1 = rte_cpu_to_le_16(bd2_bf1);
2652                         if (mplsoudp_flg) {
2653                                 bd2->data.bitfields2 =
2654                                         rte_cpu_to_le_16(bd2_bf2);
2655                                 /* Outer L3 size */
2656                                 bd2->data.tunn_ip_size =
2657                                         rte_cpu_to_le_16(mbuf->outer_l3_len);
2658                         }
2659                         /* BD3 */
2660                         if (lso_flg || (mplsoudp_flg && tunn_ipv6_ext_flg)) {
2661                                 bd3 = (struct eth_tx_3rd_bd *)
2662                                         ecore_chain_produce(&txq->tx_pbl);
2663                                 memset(bd3, 0, sizeof(struct eth_tx_3rd_bd));
2664                                 nbds++;
2665                                 bd3->data.bitfields = rte_cpu_to_le_16(bd3_bf);
2666                                 if (lso_flg)
2667                                         bd3->data.lso_mss = mss;
2668                                 if (mplsoudp_flg) {
2669                                         bd3->data.tunn_l4_hdr_start_offset_w =
2670                                                 tunn_l4_hdr_start_offset;
2671                                         bd3->data.tunn_hdr_size_w =
2672                                                 tunn_hdr_size;
2673                                 }
2674                         }
2675                 }
2676
2677                 /* Handle fragmented MBUF */
2678                 m_seg = mbuf->next;
2679
2680                 /* Encode scatter gather buffer descriptors if required */
2681                 nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3, nbds - 1);
2682                 bd1->data.nbds = nbds + nb_frags;
2683
2684                 txq->nb_tx_avail -= bd1->data.nbds;
2685                 txq->sw_tx_prod++;
2686                 bd_prod =
2687                     rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2688 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2689                 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);
2690 #endif
2691                 nb_pkt_sent++;
2692                 txq->xmit_pkts++;
2693         }
2694
2695         /* Write value of prod idx into bd_prod */
2696         txq->tx_db.data.bd_prod = bd_prod;
2697         rte_wmb();
2698         rte_compiler_barrier();
2699         DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
2700         rte_wmb();
2701
2702         /* Check again for Tx completions */
2703         qede_process_tx_compl(edev, txq);
2704
2705         PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d",
2706                    nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());
2707
2708         return nb_pkt_sent;
2709 }
2710
2711 uint16_t
2712 qede_xmit_pkts_cmt(void *p_fp_cmt, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2713 {
2714         struct qede_fastpath_cmt *fp_cmt = p_fp_cmt;
2715         uint16_t eng0_pkts, eng1_pkts;
2716
2717         eng0_pkts = nb_pkts / 2;
2718
2719         eng0_pkts = qede_xmit_pkts(fp_cmt->fp0->txq, tx_pkts, eng0_pkts);
2720
2721         eng1_pkts = nb_pkts - eng0_pkts;
2722
2723         eng1_pkts = qede_xmit_pkts(fp_cmt->fp1->txq, tx_pkts + eng0_pkts,
2724                                    eng1_pkts);
2725
2726         return eng0_pkts + eng1_pkts;
2727 }
2728
2729 uint16_t
2730 qede_rxtx_pkts_dummy(__rte_unused void *p_rxq,
2731                      __rte_unused struct rte_mbuf **pkts,
2732                      __rte_unused uint16_t nb_pkts)
2733 {
2734         return 0;
2735 }
2736
2737
2738 /* this function does a fake walk through over completion queue
2739  * to calculate number of BDs used by HW.
2740  * At the end, it restores the state of completion queue.
2741  */
2742 static uint16_t
2743 qede_parse_fp_cqe(struct qede_rx_queue *rxq)
2744 {
2745         uint16_t hw_comp_cons, sw_comp_cons, bd_count = 0;
2746         union eth_rx_cqe *cqe, *orig_cqe = NULL;
2747
2748         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
2749         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
2750
2751         if (hw_comp_cons == sw_comp_cons)
2752                 return 0;
2753
2754         /* Get the CQE from the completion ring */
2755         cqe = (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
2756         orig_cqe = cqe;
2757
2758         while (sw_comp_cons != hw_comp_cons) {
2759                 switch (cqe->fast_path_regular.type) {
2760                 case ETH_RX_CQE_TYPE_REGULAR:
2761                         bd_count += cqe->fast_path_regular.bd_num;
2762                         break;
2763                 case ETH_RX_CQE_TYPE_TPA_END:
2764                         bd_count += cqe->fast_path_tpa_end.num_of_bds;
2765                         break;
2766                 default:
2767                         break;
2768                 }
2769
2770                 cqe =
2771                 (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
2772                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
2773         }
2774
2775         /* revert comp_ring to original state */
2776         ecore_chain_set_cons(&rxq->rx_comp_ring, sw_comp_cons, orig_cqe);
2777
2778         return bd_count;
2779 }
2780
2781 int
2782 qede_rx_descriptor_status(void *p_rxq, uint16_t offset)
2783 {
2784         uint16_t hw_bd_cons, sw_bd_cons, sw_bd_prod;
2785         uint16_t produced, consumed;
2786         struct qede_rx_queue *rxq = p_rxq;
2787
2788         if (offset > rxq->nb_rx_desc)
2789                 return -EINVAL;
2790
2791         sw_bd_cons = ecore_chain_get_cons_idx(&rxq->rx_bd_ring);
2792         sw_bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
2793
2794         /* find BDs used by HW from completion queue elements */
2795         hw_bd_cons = sw_bd_cons + qede_parse_fp_cqe(rxq);
2796
2797         if (hw_bd_cons < sw_bd_cons)
2798                 /* wraparound case */
2799                 consumed = (0xffff - sw_bd_cons) + hw_bd_cons;
2800         else
2801                 consumed = hw_bd_cons - sw_bd_cons;
2802
2803         if (offset <= consumed)
2804                 return RTE_ETH_RX_DESC_DONE;
2805
2806         if (sw_bd_prod < sw_bd_cons)
2807                 /* wraparound case */
2808                 produced = (0xffff - sw_bd_cons) + sw_bd_prod;
2809         else
2810                 produced = sw_bd_prod - sw_bd_cons;
2811
2812         if (offset <= produced)
2813                 return RTE_ETH_RX_DESC_AVAIL;
2814
2815         return RTE_ETH_RX_DESC_UNAVAIL;
2816 }