1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
10 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
12 struct rte_mbuf *new_mb = NULL;
13 struct eth_rx_bd *rx_bd;
15 uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
17 new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
18 if (unlikely(!new_mb)) {
20 "Failed to allocate rx buffer "
21 "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
22 idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
23 rte_mempool_avail_count(rxq->mb_pool),
24 rte_mempool_in_use_count(rxq->mb_pool));
27 rxq->sw_rx_ring[idx] = new_mb;
28 mapping = rte_mbuf_data_iova_default(new_mb);
29 /* Advance PROD and get BD pointer */
30 rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
31 rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
32 rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
37 #define QEDE_MAX_BULK_ALLOC_COUNT 512
39 static inline int qede_alloc_rx_bulk_mbufs(struct qede_rx_queue *rxq, int count)
41 struct rte_mbuf *mbuf = NULL;
42 struct eth_rx_bd *rx_bd;
46 uint16_t mask = NUM_RX_BDS(rxq);
48 if (count > QEDE_MAX_BULK_ALLOC_COUNT)
49 count = QEDE_MAX_BULK_ALLOC_COUNT;
51 idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
53 if (count > mask - idx + 1)
54 count = mask - idx + 1;
56 ret = rte_mempool_get_bulk(rxq->mb_pool, (void **)&rxq->sw_rx_ring[idx],
61 "Failed to allocate %d rx buffers "
62 "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
64 rxq->sw_rx_prod & NUM_RX_BDS(rxq),
65 rxq->sw_rx_cons & NUM_RX_BDS(rxq),
66 rte_mempool_avail_count(rxq->mb_pool),
67 rte_mempool_in_use_count(rxq->mb_pool));
71 for (i = 0; i < count; i++) {
72 rte_prefetch0(rxq->sw_rx_ring[(idx + 1) & NUM_RX_BDS(rxq)]);
73 mbuf = rxq->sw_rx_ring[idx & NUM_RX_BDS(rxq)];
75 mapping = rte_mbuf_data_iova_default(mbuf);
76 rx_bd = (struct eth_rx_bd *)
77 ecore_chain_produce(&rxq->rx_bd_ring);
78 rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
79 rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
82 rxq->sw_rx_prod = idx;
87 /* Criterias for calculating Rx buffer size -
88 * 1) rx_buf_size should not exceed the size of mbuf
89 * 2) In scattered_rx mode - minimum rx_buf_size should be
90 * (MTU + Maximum L2 Header Size + 2) / ETH_RX_MAX_BUFF_PER_PKT
91 * 3) In regular mode - minimum rx_buf_size should be
92 * (MTU + Maximum L2 Header Size + 2)
93 * In above cases +2 corresponds to 2 bytes padding in front of L2
95 * 4) rx_buf_size should be cacheline-size aligned. So considering
96 * criteria 1, we need to adjust the size to floor instead of ceil,
97 * so that we don't exceed mbuf size while ceiling rx_buf_size.
100 qede_calc_rx_buf_size(struct rte_eth_dev *dev, uint16_t mbufsz,
101 uint16_t max_frame_size)
103 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
104 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
107 if (dev->data->scattered_rx) {
108 /* per HW limitation, only ETH_RX_MAX_BUFF_PER_PKT number of
109 * buffers can be used for single packet. So need to make sure
110 * mbuf size is sufficient enough for this.
112 if ((mbufsz * ETH_RX_MAX_BUFF_PER_PKT) <
113 (max_frame_size + QEDE_ETH_OVERHEAD)) {
114 DP_ERR(edev, "mbuf %d size is not enough to hold max fragments (%d) for max rx packet length (%d)\n",
115 mbufsz, ETH_RX_MAX_BUFF_PER_PKT, max_frame_size);
119 rx_buf_size = RTE_MAX(mbufsz,
120 (max_frame_size + QEDE_ETH_OVERHEAD) /
121 ETH_RX_MAX_BUFF_PER_PKT);
123 rx_buf_size = max_frame_size + QEDE_ETH_OVERHEAD;
126 /* Align to cache-line size if needed */
127 return QEDE_FLOOR_TO_CACHE_LINE_SIZE(rx_buf_size);
130 static struct qede_rx_queue *
131 qede_alloc_rx_queue_mem(struct rte_eth_dev *dev,
134 unsigned int socket_id,
135 struct rte_mempool *mp,
138 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
139 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
140 struct qede_rx_queue *rxq;
144 /* First allocate the rx queue data structure */
145 rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
146 RTE_CACHE_LINE_SIZE, socket_id);
149 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
156 rxq->nb_rx_desc = nb_desc;
157 rxq->queue_id = queue_idx;
158 rxq->port_id = dev->data->port_id;
161 rxq->rx_buf_size = bufsz;
163 DP_INFO(edev, "mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\n",
164 qdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);
166 /* Allocate the parallel driver ring for Rx buffers */
167 size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
168 rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
169 RTE_CACHE_LINE_SIZE, socket_id);
170 if (!rxq->sw_rx_ring) {
171 DP_ERR(edev, "Memory allocation fails for sw_rx_ring on"
172 " socket %u\n", socket_id);
177 /* Allocate FW Rx ring */
178 rc = qdev->ops->common->chain_alloc(edev,
179 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
180 ECORE_CHAIN_MODE_NEXT_PTR,
181 ECORE_CHAIN_CNT_TYPE_U16,
183 sizeof(struct eth_rx_bd),
187 if (rc != ECORE_SUCCESS) {
188 DP_ERR(edev, "Memory allocation fails for RX BD ring"
189 " on socket %u\n", socket_id);
190 rte_free(rxq->sw_rx_ring);
195 /* Allocate FW completion ring */
196 rc = qdev->ops->common->chain_alloc(edev,
197 ECORE_CHAIN_USE_TO_CONSUME,
198 ECORE_CHAIN_MODE_PBL,
199 ECORE_CHAIN_CNT_TYPE_U16,
201 sizeof(union eth_rx_cqe),
205 if (rc != ECORE_SUCCESS) {
206 DP_ERR(edev, "Memory allocation fails for RX CQE ring"
207 " on socket %u\n", socket_id);
208 qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);
209 rte_free(rxq->sw_rx_ring);
218 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qid,
219 uint16_t nb_desc, unsigned int socket_id,
220 __rte_unused const struct rte_eth_rxconf *rx_conf,
221 struct rte_mempool *mp)
223 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
224 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
225 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
226 struct qede_rx_queue *rxq;
227 uint16_t max_rx_pktlen;
231 PMD_INIT_FUNC_TRACE(edev);
233 /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
234 if (!rte_is_power_of_2(nb_desc)) {
235 DP_ERR(edev, "Ring size %u is not power of 2\n",
240 /* Free memory prior to re-allocation if needed... */
241 if (dev->data->rx_queues[qid] != NULL) {
242 qede_rx_queue_release(dev->data->rx_queues[qid]);
243 dev->data->rx_queues[qid] = NULL;
246 max_rx_pktlen = dev->data->mtu + RTE_ETHER_HDR_LEN;
248 /* Fix up RX buffer size */
249 bufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
250 /* cache align the mbuf size to simplify rx_buf_size calculation */
251 bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
252 if ((rxmode->offloads & RTE_ETH_RX_OFFLOAD_SCATTER) ||
253 (max_rx_pktlen + QEDE_ETH_OVERHEAD) > bufsz) {
254 if (!dev->data->scattered_rx) {
255 DP_INFO(edev, "Forcing scatter-gather mode\n");
256 dev->data->scattered_rx = 1;
260 rc = qede_calc_rx_buf_size(dev, bufsz, max_rx_pktlen);
266 if (ECORE_IS_CMT(edev)) {
267 rxq = qede_alloc_rx_queue_mem(dev, qid * 2, nb_desc,
268 socket_id, mp, bufsz);
272 qdev->fp_array[qid * 2].rxq = rxq;
273 rxq = qede_alloc_rx_queue_mem(dev, qid * 2 + 1, nb_desc,
274 socket_id, mp, bufsz);
278 qdev->fp_array[qid * 2 + 1].rxq = rxq;
279 /* provide per engine fp struct as rx queue */
280 dev->data->rx_queues[qid] = &qdev->fp_array_cmt[qid];
282 rxq = qede_alloc_rx_queue_mem(dev, qid, nb_desc,
283 socket_id, mp, bufsz);
287 dev->data->rx_queues[qid] = rxq;
288 qdev->fp_array[qid].rxq = rxq;
291 DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
292 qid, nb_desc, rxq->rx_buf_size, socket_id);
298 qede_rx_queue_reset(__rte_unused struct qede_dev *qdev,
299 struct qede_rx_queue *rxq)
301 DP_INFO(&qdev->edev, "Reset RX queue %u\n", rxq->queue_id);
302 ecore_chain_reset(&rxq->rx_bd_ring);
303 ecore_chain_reset(&rxq->rx_comp_ring);
306 *rxq->hw_cons_ptr = 0;
309 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
313 if (rxq->sw_rx_ring) {
314 for (i = 0; i < rxq->nb_rx_desc; i++) {
315 if (rxq->sw_rx_ring[i]) {
316 rte_pktmbuf_free(rxq->sw_rx_ring[i]);
317 rxq->sw_rx_ring[i] = NULL;
323 static void _qede_rx_queue_release(struct qede_dev *qdev,
324 struct ecore_dev *edev,
325 struct qede_rx_queue *rxq)
327 qede_rx_queue_release_mbufs(rxq);
328 qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);
329 qdev->ops->common->chain_free(edev, &rxq->rx_comp_ring);
330 rte_free(rxq->sw_rx_ring);
334 void qede_rx_queue_release(void *rx_queue)
336 struct qede_rx_queue *rxq = rx_queue;
337 struct qede_fastpath_cmt *fp_cmt;
338 struct qede_dev *qdev;
339 struct ecore_dev *edev;
343 edev = QEDE_INIT_EDEV(qdev);
344 PMD_INIT_FUNC_TRACE(edev);
345 if (ECORE_IS_CMT(edev)) {
347 _qede_rx_queue_release(qdev, edev, fp_cmt->fp0->rxq);
348 _qede_rx_queue_release(qdev, edev, fp_cmt->fp1->rxq);
350 _qede_rx_queue_release(qdev, edev, rxq);
355 /* Stops a given RX queue in the HW */
356 static int qede_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
358 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
359 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
360 struct ecore_hwfn *p_hwfn;
361 struct qede_rx_queue *rxq;
365 if (rx_queue_id < qdev->num_rx_queues) {
366 rxq = qdev->fp_array[rx_queue_id].rxq;
367 hwfn_index = rx_queue_id % edev->num_hwfns;
368 p_hwfn = &edev->hwfns[hwfn_index];
369 rc = ecore_eth_rx_queue_stop(p_hwfn, rxq->handle,
371 if (rc != ECORE_SUCCESS) {
372 DP_ERR(edev, "RX queue %u stop fails\n", rx_queue_id);
375 qede_rx_queue_release_mbufs(rxq);
376 qede_rx_queue_reset(qdev, rxq);
377 eth_dev->data->rx_queue_state[rx_queue_id] =
378 RTE_ETH_QUEUE_STATE_STOPPED;
379 DP_INFO(edev, "RX queue %u stopped\n", rx_queue_id);
381 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
388 static struct qede_tx_queue *
389 qede_alloc_tx_queue_mem(struct rte_eth_dev *dev,
392 unsigned int socket_id,
393 const struct rte_eth_txconf *tx_conf)
395 struct qede_dev *qdev = dev->data->dev_private;
396 struct ecore_dev *edev = &qdev->edev;
397 struct qede_tx_queue *txq;
399 size_t sw_tx_ring_size;
401 txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
402 RTE_CACHE_LINE_SIZE, socket_id);
406 "Unable to allocate memory for txq on socket %u",
411 txq->nb_tx_desc = nb_desc;
413 txq->port_id = dev->data->port_id;
415 rc = qdev->ops->common->chain_alloc(edev,
416 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
417 ECORE_CHAIN_MODE_PBL,
418 ECORE_CHAIN_CNT_TYPE_U16,
420 sizeof(union eth_tx_bd_types),
423 if (rc != ECORE_SUCCESS) {
425 "Unable to allocate memory for txbd ring on socket %u",
427 qede_tx_queue_release(txq);
431 /* Allocate software ring */
432 sw_tx_ring_size = sizeof(txq->sw_tx_ring) * txq->nb_tx_desc;
433 txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
435 RTE_CACHE_LINE_SIZE, socket_id);
437 if (!txq->sw_tx_ring) {
439 "Unable to allocate memory for txbd ring on socket %u",
441 qdev->ops->common->chain_free(edev, &txq->tx_pbl);
442 qede_tx_queue_release(txq);
446 txq->queue_id = queue_idx;
448 txq->nb_tx_avail = txq->nb_tx_desc;
450 txq->tx_free_thresh =
451 tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
452 (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
455 "txq %u num_desc %u tx_free_thresh %u socket %u\n",
456 queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
461 qede_tx_queue_setup(struct rte_eth_dev *dev,
464 unsigned int socket_id,
465 const struct rte_eth_txconf *tx_conf)
467 struct qede_dev *qdev = dev->data->dev_private;
468 struct ecore_dev *edev = &qdev->edev;
469 struct qede_tx_queue *txq;
471 PMD_INIT_FUNC_TRACE(edev);
473 if (!rte_is_power_of_2(nb_desc)) {
474 DP_ERR(edev, "Ring size %u is not power of 2\n",
479 /* Free memory prior to re-allocation if needed... */
480 if (dev->data->tx_queues[queue_idx] != NULL) {
481 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
482 dev->data->tx_queues[queue_idx] = NULL;
485 if (ECORE_IS_CMT(edev)) {
486 txq = qede_alloc_tx_queue_mem(dev, queue_idx * 2, nb_desc,
491 qdev->fp_array[queue_idx * 2].txq = txq;
492 txq = qede_alloc_tx_queue_mem(dev, (queue_idx * 2) + 1, nb_desc,
497 qdev->fp_array[(queue_idx * 2) + 1].txq = txq;
498 dev->data->tx_queues[queue_idx] =
499 &qdev->fp_array_cmt[queue_idx];
501 txq = qede_alloc_tx_queue_mem(dev, queue_idx, nb_desc,
506 dev->data->tx_queues[queue_idx] = txq;
507 qdev->fp_array[queue_idx].txq = txq;
514 qede_tx_queue_reset(__rte_unused struct qede_dev *qdev,
515 struct qede_tx_queue *txq)
517 DP_INFO(&qdev->edev, "Reset TX queue %u\n", txq->queue_id);
518 ecore_chain_reset(&txq->tx_pbl);
521 *txq->hw_cons_ptr = 0;
524 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
528 if (txq->sw_tx_ring) {
529 for (i = 0; i < txq->nb_tx_desc; i++) {
530 if (txq->sw_tx_ring[i]) {
531 rte_pktmbuf_free(txq->sw_tx_ring[i]);
532 txq->sw_tx_ring[i] = NULL;
538 static void _qede_tx_queue_release(struct qede_dev *qdev,
539 struct ecore_dev *edev,
540 struct qede_tx_queue *txq)
542 qede_tx_queue_release_mbufs(txq);
543 qdev->ops->common->chain_free(edev, &txq->tx_pbl);
544 rte_free(txq->sw_tx_ring);
548 void qede_tx_queue_release(void *tx_queue)
550 struct qede_tx_queue *txq = tx_queue;
551 struct qede_fastpath_cmt *fp_cmt;
552 struct qede_dev *qdev;
553 struct ecore_dev *edev;
557 edev = QEDE_INIT_EDEV(qdev);
558 PMD_INIT_FUNC_TRACE(edev);
560 if (ECORE_IS_CMT(edev)) {
562 _qede_tx_queue_release(qdev, edev, fp_cmt->fp0->txq);
563 _qede_tx_queue_release(qdev, edev, fp_cmt->fp1->txq);
565 _qede_tx_queue_release(qdev, edev, txq);
570 /* This function allocates fast-path status block memory */
572 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
575 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
576 struct status_block *sb_virt;
580 sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys,
581 sizeof(struct status_block));
583 DP_ERR(edev, "Status block allocation failed\n");
586 rc = qdev->ops->common->sb_init(edev, sb_info, sb_virt,
589 DP_ERR(edev, "Status block initialization failed\n");
590 OSAL_DMA_FREE_COHERENT(edev, sb_virt, sb_phys,
591 sizeof(struct status_block));
598 int qede_alloc_fp_resc(struct qede_dev *qdev)
600 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
601 struct qede_fastpath *fp;
606 PMD_INIT_FUNC_TRACE(edev);
609 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
611 num_sbs = ecore_cxt_get_proto_cid_count
612 (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL);
615 DP_ERR(edev, "No status blocks available\n");
619 qdev->fp_array = rte_calloc("fp", QEDE_RXTX_MAX(qdev),
620 sizeof(*qdev->fp_array), RTE_CACHE_LINE_SIZE);
622 if (!qdev->fp_array) {
623 DP_ERR(edev, "fp array allocation failed\n");
627 memset((void *)qdev->fp_array, 0, QEDE_RXTX_MAX(qdev) *
628 sizeof(*qdev->fp_array));
630 if (ECORE_IS_CMT(edev)) {
631 qdev->fp_array_cmt = rte_calloc("fp_cmt",
632 QEDE_RXTX_MAX(qdev) / 2,
633 sizeof(*qdev->fp_array_cmt),
634 RTE_CACHE_LINE_SIZE);
636 if (!qdev->fp_array_cmt) {
637 DP_ERR(edev, "fp array for CMT allocation failed\n");
641 memset((void *)qdev->fp_array_cmt, 0,
642 (QEDE_RXTX_MAX(qdev) / 2) * sizeof(*qdev->fp_array_cmt));
644 /* Establish the mapping of fp_array with fp_array_cmt */
645 for (i = 0; i < QEDE_RXTX_MAX(qdev) / 2; i++) {
646 qdev->fp_array_cmt[i].qdev = qdev;
647 qdev->fp_array_cmt[i].fp0 = &qdev->fp_array[i * 2];
648 qdev->fp_array_cmt[i].fp1 = &qdev->fp_array[i * 2 + 1];
652 for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
653 fp = &qdev->fp_array[sb_idx];
654 fp->sb_info = rte_calloc("sb", 1, sizeof(struct ecore_sb_info),
655 RTE_CACHE_LINE_SIZE);
657 DP_ERR(edev, "FP sb_info allocation fails\n");
660 if (qede_alloc_mem_sb(qdev, fp->sb_info, sb_idx)) {
661 DP_ERR(edev, "FP status block allocation fails\n");
664 DP_INFO(edev, "sb_info idx 0x%x initialized\n",
665 fp->sb_info->igu_sb_id);
671 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
673 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
674 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
675 struct qede_fastpath *fp;
679 PMD_INIT_FUNC_TRACE(edev);
681 for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
682 fp = &qdev->fp_array[sb_idx];
684 DP_INFO(edev, "Free sb_info index 0x%x\n",
685 fp->sb_info->igu_sb_id);
686 OSAL_DMA_FREE_COHERENT(edev, fp->sb_info->sb_virt,
687 fp->sb_info->sb_phys,
688 sizeof(struct status_block));
689 rte_free(fp->sb_info);
694 /* Free packet buffers and ring memories */
695 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
696 if (eth_dev->data->rx_queues[i]) {
697 qede_rx_queue_release(eth_dev->data->rx_queues[i]);
698 eth_dev->data->rx_queues[i] = NULL;
702 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
703 if (eth_dev->data->tx_queues[i]) {
704 qede_tx_queue_release(eth_dev->data->tx_queues[i]);
705 eth_dev->data->tx_queues[i] = NULL;
709 rte_free(qdev->fp_array);
710 qdev->fp_array = NULL;
712 rte_free(qdev->fp_array_cmt);
713 qdev->fp_array_cmt = NULL;
717 qede_update_rx_prod(__rte_unused struct qede_dev *edev,
718 struct qede_rx_queue *rxq)
720 uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
721 uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
722 struct eth_rx_prod_data rx_prods;
724 /* Update producers */
725 memset(&rx_prods, 0, sizeof(rx_prods));
726 rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
727 rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
729 /* Make sure that the BD and SGE data is updated before updating the
730 * producers since FW might read the BD/SGE right after the producer
735 internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
736 (uint32_t *)&rx_prods);
738 /* mmiowb is needed to synchronize doorbell writes from more than one
739 * processor. It guarantees that the write arrives to the device before
740 * the napi lock is released and another qede_poll is called (possibly
741 * on another CPU). Without this barrier, the next doorbell can bypass
742 * this doorbell. This is applicable to IA64/Altix systems.
746 PMD_RX_LOG(DEBUG, rxq, "bd_prod %u cqe_prod %u", bd_prod, cqe_prod);
749 /* Starts a given RX queue in HW */
751 qede_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
753 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
754 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
755 struct ecore_queue_start_common_params params;
756 struct ecore_rxq_start_ret_params ret_params;
757 struct qede_rx_queue *rxq;
758 struct qede_fastpath *fp;
759 struct ecore_hwfn *p_hwfn;
760 dma_addr_t p_phys_table;
766 if (rx_queue_id < qdev->num_rx_queues) {
767 fp = &qdev->fp_array[rx_queue_id];
769 /* Allocate buffers for the Rx ring */
770 for (j = 0; j < rxq->nb_rx_desc; j++) {
771 rc = qede_alloc_rx_buffer(rxq);
773 DP_ERR(edev, "RX buffer allocation failed"
774 " for rxq = %u\n", rx_queue_id);
778 /* disable interrupts */
779 ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
781 memset(¶ms, 0, sizeof(params));
782 params.queue_id = rx_queue_id / edev->num_hwfns;
784 params.stats_id = params.vport_id;
785 params.p_sb = fp->sb_info;
786 DP_INFO(edev, "rxq %u igu_sb_id 0x%x\n",
787 fp->rxq->queue_id, fp->sb_info->igu_sb_id);
788 params.sb_idx = RX_PI;
789 hwfn_index = rx_queue_id % edev->num_hwfns;
790 p_hwfn = &edev->hwfns[hwfn_index];
791 p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->rx_comp_ring);
792 page_cnt = ecore_chain_get_page_cnt(&fp->rxq->rx_comp_ring);
793 memset(&ret_params, 0, sizeof(ret_params));
794 rc = ecore_eth_rx_queue_start(p_hwfn,
795 p_hwfn->hw_info.opaque_fid,
796 ¶ms, fp->rxq->rx_buf_size,
797 fp->rxq->rx_bd_ring.p_phys_addr,
798 p_phys_table, page_cnt,
801 DP_ERR(edev, "RX queue %u could not be started, rc = %d\n",
805 /* Update with the returned parameters */
806 fp->rxq->hw_rxq_prod_addr = ret_params.p_prod;
807 fp->rxq->handle = ret_params.p_handle;
809 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_pi_array[RX_PI];
810 qede_update_rx_prod(qdev, fp->rxq);
811 eth_dev->data->rx_queue_state[rx_queue_id] =
812 RTE_ETH_QUEUE_STATE_STARTED;
813 DP_INFO(edev, "RX queue %u started\n", rx_queue_id);
815 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
823 qede_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
825 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
826 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
827 struct ecore_queue_start_common_params params;
828 struct ecore_txq_start_ret_params ret_params;
829 struct ecore_hwfn *p_hwfn;
830 dma_addr_t p_phys_table;
831 struct qede_tx_queue *txq;
832 struct qede_fastpath *fp;
837 if (tx_queue_id < qdev->num_tx_queues) {
838 fp = &qdev->fp_array[tx_queue_id];
840 memset(¶ms, 0, sizeof(params));
841 params.queue_id = tx_queue_id / edev->num_hwfns;
843 params.stats_id = params.vport_id;
844 params.p_sb = fp->sb_info;
845 DP_INFO(edev, "txq %u igu_sb_id 0x%x\n",
846 fp->txq->queue_id, fp->sb_info->igu_sb_id);
847 params.sb_idx = TX_PI(0); /* tc = 0 */
848 p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
849 page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
850 hwfn_index = tx_queue_id % edev->num_hwfns;
851 p_hwfn = &edev->hwfns[hwfn_index];
852 if (qdev->dev_info.is_legacy)
853 fp->txq->is_legacy = true;
854 rc = ecore_eth_tx_queue_start(p_hwfn,
855 p_hwfn->hw_info.opaque_fid,
857 p_phys_table, page_cnt,
859 if (rc != ECORE_SUCCESS) {
860 DP_ERR(edev, "TX queue %u couldn't be started, rc=%d\n",
864 txq->doorbell_addr = ret_params.p_doorbell;
865 txq->handle = ret_params.p_handle;
867 txq->hw_cons_ptr = &fp->sb_info->sb_pi_array[TX_PI(0)];
868 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_DEST,
870 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
872 SET_FIELD(txq->tx_db.data.params,
873 ETH_DB_DATA_AGG_VAL_SEL,
874 DQ_XCM_ETH_TX_BD_PROD_CMD);
875 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
876 eth_dev->data->tx_queue_state[tx_queue_id] =
877 RTE_ETH_QUEUE_STATE_STARTED;
878 DP_INFO(edev, "TX queue %u started\n", tx_queue_id);
880 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
888 qede_free_tx_pkt(struct qede_tx_queue *txq)
890 struct rte_mbuf *mbuf;
895 mbuf = txq->sw_tx_ring[idx];
897 nb_segs = mbuf->nb_segs;
898 PMD_TX_LOG(DEBUG, txq, "nb_segs to free %u\n", nb_segs);
900 /* It's like consuming rxbuf in recv() */
901 ecore_chain_consume(&txq->tx_pbl);
905 rte_pktmbuf_free(mbuf);
906 txq->sw_tx_ring[idx] = NULL;
908 PMD_TX_LOG(DEBUG, txq, "Freed tx packet\n");
910 ecore_chain_consume(&txq->tx_pbl);
916 qede_process_tx_compl(__rte_unused struct ecore_dev *edev,
917 struct qede_tx_queue *txq)
920 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
924 hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
925 /* read barrier prevents speculative execution on stale data */
928 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
929 sw_tx_cons = ecore_chain_get_cons_idx(&txq->tx_pbl);
930 PMD_TX_LOG(DEBUG, txq, "Tx Completions = %u\n",
931 abs(hw_bd_cons - sw_tx_cons));
933 while (hw_bd_cons != ecore_chain_get_cons_idx(&txq->tx_pbl))
934 qede_free_tx_pkt(txq);
937 static int qede_drain_txq(struct qede_dev *qdev,
938 struct qede_tx_queue *txq, bool allow_drain)
940 struct ecore_dev *edev = &qdev->edev;
943 while (txq->sw_tx_cons != txq->sw_tx_prod) {
944 qede_process_tx_compl(edev, txq);
947 DP_ERR(edev, "Tx queue[%u] is stuck,"
948 "requesting MCP to drain\n",
950 rc = qdev->ops->common->drain(edev);
953 return qede_drain_txq(qdev, txq, false);
955 DP_ERR(edev, "Timeout waiting for tx queue[%d]:"
956 "PROD=%d, CONS=%d\n",
957 txq->queue_id, txq->sw_tx_prod,
963 rte_compiler_barrier();
966 /* FW finished processing, wait for HW to transmit all tx packets */
972 /* Stops a given TX queue in the HW */
973 static int qede_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
975 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
976 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
977 struct ecore_hwfn *p_hwfn;
978 struct qede_tx_queue *txq;
982 if (tx_queue_id < qdev->num_tx_queues) {
983 txq = qdev->fp_array[tx_queue_id].txq;
985 if (qede_drain_txq(qdev, txq, true))
986 return -1; /* For the lack of retcodes */
988 hwfn_index = tx_queue_id % edev->num_hwfns;
989 p_hwfn = &edev->hwfns[hwfn_index];
990 rc = ecore_eth_tx_queue_stop(p_hwfn, txq->handle);
991 if (rc != ECORE_SUCCESS) {
992 DP_ERR(edev, "TX queue %u stop fails\n", tx_queue_id);
995 qede_tx_queue_release_mbufs(txq);
996 qede_tx_queue_reset(qdev, txq);
997 eth_dev->data->tx_queue_state[tx_queue_id] =
998 RTE_ETH_QUEUE_STATE_STOPPED;
999 DP_INFO(edev, "TX queue %u stopped\n", tx_queue_id);
1001 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
1008 int qede_start_queues(struct rte_eth_dev *eth_dev)
1010 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1014 for (id = 0; id < qdev->num_rx_queues; id++) {
1015 rc = qede_rx_queue_start(eth_dev, id);
1016 if (rc != ECORE_SUCCESS)
1020 for (id = 0; id < qdev->num_tx_queues; id++) {
1021 rc = qede_tx_queue_start(eth_dev, id);
1022 if (rc != ECORE_SUCCESS)
1029 void qede_stop_queues(struct rte_eth_dev *eth_dev)
1031 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1034 /* Stopping RX/TX queues */
1035 for (id = 0; id < qdev->num_tx_queues; id++)
1036 qede_tx_queue_stop(eth_dev, id);
1038 for (id = 0; id < qdev->num_rx_queues; id++)
1039 qede_rx_queue_stop(eth_dev, id);
1042 static inline bool qede_tunn_exist(uint16_t flag)
1044 return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
1045 PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
1048 static inline uint8_t qede_check_tunn_csum_l3(uint16_t flag)
1050 return !!((PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
1051 PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT) & flag);
1055 * qede_check_tunn_csum_l4:
1057 * 1 : If L4 csum is enabled AND if the validation has failed.
1060 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
1062 if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
1063 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
1064 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
1065 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
1070 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
1072 if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1073 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
1074 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1075 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
1080 /* Returns outer L2, L3 and L4 packet_type for tunneled packets */
1081 static inline uint32_t qede_rx_cqe_to_pkt_type_outer(struct rte_mbuf *m)
1083 uint32_t packet_type = RTE_PTYPE_UNKNOWN;
1084 struct rte_ether_hdr *eth_hdr;
1085 struct rte_ipv4_hdr *ipv4_hdr;
1086 struct rte_ipv6_hdr *ipv6_hdr;
1087 struct rte_vlan_hdr *vlan_hdr;
1089 bool vlan_tagged = 0;
1092 eth_hdr = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
1093 len = sizeof(struct rte_ether_hdr);
1094 ethertype = rte_cpu_to_be_16(eth_hdr->ether_type);
1096 /* Note: Valid only if VLAN stripping is disabled */
1097 if (ethertype == RTE_ETHER_TYPE_VLAN) {
1099 vlan_hdr = (struct rte_vlan_hdr *)(eth_hdr + 1);
1100 len += sizeof(struct rte_vlan_hdr);
1101 ethertype = rte_cpu_to_be_16(vlan_hdr->eth_proto);
1104 if (ethertype == RTE_ETHER_TYPE_IPV4) {
1105 packet_type |= RTE_PTYPE_L3_IPV4;
1106 ipv4_hdr = rte_pktmbuf_mtod_offset(m,
1107 struct rte_ipv4_hdr *, len);
1108 if (ipv4_hdr->next_proto_id == IPPROTO_TCP)
1109 packet_type |= RTE_PTYPE_L4_TCP;
1110 else if (ipv4_hdr->next_proto_id == IPPROTO_UDP)
1111 packet_type |= RTE_PTYPE_L4_UDP;
1112 } else if (ethertype == RTE_ETHER_TYPE_IPV6) {
1113 packet_type |= RTE_PTYPE_L3_IPV6;
1114 ipv6_hdr = rte_pktmbuf_mtod_offset(m,
1115 struct rte_ipv6_hdr *, len);
1116 if (ipv6_hdr->proto == IPPROTO_TCP)
1117 packet_type |= RTE_PTYPE_L4_TCP;
1118 else if (ipv6_hdr->proto == IPPROTO_UDP)
1119 packet_type |= RTE_PTYPE_L4_UDP;
1123 packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
1125 packet_type |= RTE_PTYPE_L2_ETHER;
1130 static inline uint32_t qede_rx_cqe_to_pkt_type_inner(uint16_t flags)
1135 static const uint32_t
1136 ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
1137 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_INNER_L3_IPV4 |
1138 RTE_PTYPE_INNER_L2_ETHER,
1139 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_INNER_L3_IPV6 |
1140 RTE_PTYPE_INNER_L2_ETHER,
1141 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_INNER_L3_IPV4 |
1142 RTE_PTYPE_INNER_L4_TCP |
1143 RTE_PTYPE_INNER_L2_ETHER,
1144 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_INNER_L3_IPV6 |
1145 RTE_PTYPE_INNER_L4_TCP |
1146 RTE_PTYPE_INNER_L2_ETHER,
1147 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_INNER_L3_IPV4 |
1148 RTE_PTYPE_INNER_L4_UDP |
1149 RTE_PTYPE_INNER_L2_ETHER,
1150 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_INNER_L3_IPV6 |
1151 RTE_PTYPE_INNER_L4_UDP |
1152 RTE_PTYPE_INNER_L2_ETHER,
1153 /* Frags with no VLAN */
1154 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_INNER_L3_IPV4 |
1155 RTE_PTYPE_INNER_L4_FRAG |
1156 RTE_PTYPE_INNER_L2_ETHER,
1157 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_INNER_L3_IPV6 |
1158 RTE_PTYPE_INNER_L4_FRAG |
1159 RTE_PTYPE_INNER_L2_ETHER,
1161 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
1162 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1163 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
1164 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1165 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
1166 RTE_PTYPE_INNER_L4_TCP |
1167 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1168 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
1169 RTE_PTYPE_INNER_L4_TCP |
1170 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1171 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
1172 RTE_PTYPE_INNER_L4_UDP |
1173 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1174 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
1175 RTE_PTYPE_INNER_L4_UDP |
1176 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1177 /* Frags with VLAN */
1178 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV4 |
1179 RTE_PTYPE_INNER_L4_FRAG |
1180 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1181 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV6 |
1182 RTE_PTYPE_INNER_L4_FRAG |
1183 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1186 /* Bits (0..3) provides L3/L4 protocol type */
1187 /* Bits (4,5) provides frag and VLAN info */
1188 val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
1189 PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
1190 (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
1191 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) |
1192 (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1193 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) |
1194 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK <<
1195 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags;
1197 if (val < QEDE_PKT_TYPE_MAX)
1198 return ptype_lkup_tbl[val];
1200 return RTE_PTYPE_UNKNOWN;
1203 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
1208 static const uint32_t
1209 ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
1210 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L2_ETHER,
1211 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L2_ETHER,
1212 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4 |
1215 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6 |
1218 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4 |
1221 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6 |
1224 /* Frags with no VLAN */
1225 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_L3_IPV4 |
1228 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_L3_IPV6 |
1232 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_L3_IPV4 |
1233 RTE_PTYPE_L2_ETHER_VLAN,
1234 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_L3_IPV6 |
1235 RTE_PTYPE_L2_ETHER_VLAN,
1236 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_L3_IPV4 |
1238 RTE_PTYPE_L2_ETHER_VLAN,
1239 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_L3_IPV6 |
1241 RTE_PTYPE_L2_ETHER_VLAN,
1242 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_L3_IPV4 |
1244 RTE_PTYPE_L2_ETHER_VLAN,
1245 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_L3_IPV6 |
1247 RTE_PTYPE_L2_ETHER_VLAN,
1248 /* Frags with VLAN */
1249 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_L3_IPV4 |
1251 RTE_PTYPE_L2_ETHER_VLAN,
1252 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_L3_IPV6 |
1254 RTE_PTYPE_L2_ETHER_VLAN,
1257 /* Bits (0..3) provides L3/L4 protocol type */
1258 /* Bits (4,5) provides frag and VLAN info */
1259 val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
1260 PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
1261 (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
1262 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) |
1263 (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1264 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) |
1265 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK <<
1266 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags;
1268 if (val < QEDE_PKT_TYPE_MAX)
1269 return ptype_lkup_tbl[val];
1271 return RTE_PTYPE_UNKNOWN;
1274 static inline uint8_t
1275 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
1277 struct rte_ipv4_hdr *ip;
1282 val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1283 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
1285 if (unlikely(val)) {
1286 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
1287 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
1288 ip = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
1289 sizeof(struct rte_ether_hdr));
1290 pkt_csum = ip->hdr_checksum;
1291 ip->hdr_checksum = 0;
1292 calc_csum = rte_ipv4_cksum(ip);
1293 ip->hdr_checksum = pkt_csum;
1294 return (calc_csum != pkt_csum);
1295 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
1302 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
1304 ecore_chain_consume(&rxq->rx_bd_ring);
1309 qede_reuse_page(__rte_unused struct qede_dev *qdev,
1310 struct qede_rx_queue *rxq, struct rte_mbuf *curr_cons)
1312 struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
1313 uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
1314 dma_addr_t new_mapping;
1316 rxq->sw_rx_ring[idx] = curr_cons;
1318 new_mapping = rte_mbuf_data_iova_default(curr_cons);
1320 rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
1321 rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
1327 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
1328 struct qede_dev *qdev, uint8_t count)
1330 struct rte_mbuf *curr_cons;
1332 for (; count > 0; count--) {
1333 curr_cons = rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
1334 qede_reuse_page(qdev, rxq, curr_cons);
1335 qede_rx_bd_ring_consume(rxq);
1340 qede_rx_process_tpa_cmn_cont_end_cqe(__rte_unused struct qede_dev *qdev,
1341 struct qede_rx_queue *rxq,
1342 uint8_t agg_index, uint16_t len)
1344 struct qede_agg_info *tpa_info;
1345 struct rte_mbuf *curr_frag; /* Pointer to currently filled TPA seg */
1348 /* Under certain conditions it is possible that FW may not consume
1349 * additional or new BD. So decision to consume the BD must be made
1350 * based on len_list[0].
1352 if (rte_le_to_cpu_16(len)) {
1353 tpa_info = &rxq->tpa_info[agg_index];
1354 cons_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1355 curr_frag = rxq->sw_rx_ring[cons_idx];
1357 curr_frag->nb_segs = 1;
1358 curr_frag->pkt_len = rte_le_to_cpu_16(len);
1359 curr_frag->data_len = curr_frag->pkt_len;
1360 tpa_info->tpa_tail->next = curr_frag;
1361 tpa_info->tpa_tail = curr_frag;
1362 qede_rx_bd_ring_consume(rxq);
1363 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1364 PMD_RX_LOG(ERR, rxq, "mbuf allocation fails\n");
1365 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1366 rxq->rx_alloc_errors++;
1372 qede_rx_process_tpa_cont_cqe(struct qede_dev *qdev,
1373 struct qede_rx_queue *rxq,
1374 struct eth_fast_path_rx_tpa_cont_cqe *cqe)
1376 PMD_RX_LOG(INFO, rxq, "TPA cont[%d] - len [%d]\n",
1377 cqe->tpa_agg_index, rte_le_to_cpu_16(cqe->len_list[0]));
1378 /* only len_list[0] will have value */
1379 qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
1384 qede_rx_process_tpa_end_cqe(struct qede_dev *qdev,
1385 struct qede_rx_queue *rxq,
1386 struct eth_fast_path_rx_tpa_end_cqe *cqe)
1388 struct rte_mbuf *rx_mb; /* Pointer to head of the chained agg */
1390 qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
1392 /* Update total length and frags based on end TPA */
1393 rx_mb = rxq->tpa_info[cqe->tpa_agg_index].tpa_head;
1394 /* TODO: Add Sanity Checks */
1395 rx_mb->nb_segs = cqe->num_of_bds;
1396 rx_mb->pkt_len = cqe->total_packet_len;
1398 PMD_RX_LOG(INFO, rxq, "TPA End[%d] reason %d cqe_len %d nb_segs %d"
1399 " pkt_len %d\n", cqe->tpa_agg_index, cqe->end_reason,
1400 rte_le_to_cpu_16(cqe->len_list[0]), rx_mb->nb_segs,
1404 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
1409 static const uint32_t
1410 ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
1411 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
1412 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
1413 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
1414 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
1415 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
1416 RTE_PTYPE_TUNNEL_GENEVE,
1417 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
1418 RTE_PTYPE_TUNNEL_GRE,
1419 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
1420 RTE_PTYPE_TUNNEL_VXLAN,
1421 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
1422 RTE_PTYPE_TUNNEL_GENEVE,
1423 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
1424 RTE_PTYPE_TUNNEL_GRE,
1425 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
1426 RTE_PTYPE_TUNNEL_VXLAN,
1427 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
1428 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1429 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
1430 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1431 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
1432 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1433 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
1434 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1435 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
1436 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1437 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
1438 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1439 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
1440 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1441 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
1442 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1443 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
1444 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1445 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
1446 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1447 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
1448 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1449 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
1450 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1453 /* Cover bits[4-0] to include tunn_type and next protocol */
1454 val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
1455 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
1456 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
1457 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
1459 if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
1460 return ptype_tunn_lkup_tbl[val];
1462 return RTE_PTYPE_UNKNOWN;
1466 qede_process_sg_pkts(void *p_rxq, struct rte_mbuf *rx_mb,
1467 uint8_t num_segs, uint16_t pkt_len)
1469 struct qede_rx_queue *rxq = p_rxq;
1470 struct qede_dev *qdev = rxq->qdev;
1471 register struct rte_mbuf *seg1 = NULL;
1472 register struct rte_mbuf *seg2 = NULL;
1473 uint16_t sw_rx_index;
1478 cur_size = pkt_len > rxq->rx_buf_size ? rxq->rx_buf_size :
1480 if (unlikely(!cur_size)) {
1481 PMD_RX_LOG(ERR, rxq, "Length is 0 while %u BDs"
1482 " left for mapping jumbo\n", num_segs);
1483 qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
1486 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1487 seg2 = rxq->sw_rx_ring[sw_rx_index];
1488 qede_rx_bd_ring_consume(rxq);
1489 pkt_len -= cur_size;
1490 seg2->data_len = cur_size;
1500 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1502 print_rx_bd_info(struct rte_mbuf *m, struct qede_rx_queue *rxq,
1505 PMD_RX_LOG(INFO, rxq,
1506 "len 0x%04x bf 0x%04x hash_val 0x%x"
1507 " ol_flags 0x%04lx l2=%s l3=%s l4=%s tunn=%s"
1508 " inner_l2=%s inner_l3=%s inner_l4=%s\n",
1509 m->data_len, bitfield, m->hash.rss,
1510 (unsigned long)m->ol_flags,
1511 rte_get_ptype_l2_name(m->packet_type),
1512 rte_get_ptype_l3_name(m->packet_type),
1513 rte_get_ptype_l4_name(m->packet_type),
1514 rte_get_ptype_tunnel_name(m->packet_type),
1515 rte_get_ptype_inner_l2_name(m->packet_type),
1516 rte_get_ptype_inner_l3_name(m->packet_type),
1517 rte_get_ptype_inner_l4_name(m->packet_type));
1522 qede_recv_pkts_regular(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1524 struct eth_fast_path_rx_reg_cqe *fp_cqe = NULL;
1525 register struct rte_mbuf *rx_mb = NULL;
1526 struct qede_rx_queue *rxq = p_rxq;
1527 struct qede_dev *qdev = rxq->qdev;
1528 struct ecore_dev *edev = &qdev->edev;
1529 union eth_rx_cqe *cqe;
1531 enum eth_rx_cqe_type cqe_type;
1532 int rss_enable = qdev->rss_enable;
1533 int rx_alloc_count = 0;
1534 uint32_t packet_type;
1536 uint16_t vlan_tci, port_id;
1537 uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index, num_rx_bds;
1538 uint16_t rx_pkt = 0;
1539 uint16_t pkt_len = 0;
1540 uint16_t len; /* Length of first BD */
1541 uint16_t preload_idx;
1542 uint16_t parse_flag;
1543 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1544 uint8_t bitfield_val;
1546 uint8_t offset, flags, bd_num;
1549 /* Allocate buffers that we used in previous loop */
1550 if (rxq->rx_alloc_count) {
1551 if (unlikely(qede_alloc_rx_bulk_mbufs(rxq,
1552 rxq->rx_alloc_count))) {
1553 struct rte_eth_dev *dev;
1555 PMD_RX_LOG(ERR, rxq,
1556 "New buffer allocation failed,"
1557 "dropping incoming packetn");
1558 dev = &rte_eth_devices[rxq->port_id];
1559 dev->data->rx_mbuf_alloc_failed +=
1560 rxq->rx_alloc_count;
1561 rxq->rx_alloc_errors += rxq->rx_alloc_count;
1564 qede_update_rx_prod(qdev, rxq);
1565 rxq->rx_alloc_count = 0;
1568 hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
1569 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1573 if (hw_comp_cons == sw_comp_cons)
1576 num_rx_bds = NUM_RX_BDS(rxq);
1577 port_id = rxq->port_id;
1579 while (sw_comp_cons != hw_comp_cons) {
1581 packet_type = RTE_PTYPE_UNKNOWN;
1585 /* Get the CQE from the completion ring */
1587 (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
1588 cqe_type = cqe->fast_path_regular.type;
1589 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type);
1591 if (likely(cqe_type == ETH_RX_CQE_TYPE_REGULAR)) {
1592 fp_cqe = &cqe->fast_path_regular;
1594 if (cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH) {
1595 PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n");
1596 ecore_eth_cqe_completion
1597 (&edev->hwfns[rxq->queue_id %
1599 (struct eth_slow_path_rx_cqe *)cqe);
1604 /* Get the data from the SW ring */
1605 sw_rx_index = rxq->sw_rx_cons & num_rx_bds;
1606 rx_mb = rxq->sw_rx_ring[sw_rx_index];
1607 assert(rx_mb != NULL);
1609 parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);
1610 offset = fp_cqe->placement_offset;
1611 len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
1612 pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1613 vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1614 rss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash);
1615 bd_num = fp_cqe->bd_num;
1616 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1617 bitfield_val = fp_cqe->bitfields;
1620 if (unlikely(qede_tunn_exist(parse_flag))) {
1621 PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n");
1622 if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1623 PMD_RX_LOG(ERR, rxq,
1624 "L4 csum failed, flags = 0x%x\n",
1626 rxq->rx_hw_errors++;
1627 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1629 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1632 if (unlikely(qede_check_tunn_csum_l3(parse_flag))) {
1633 PMD_RX_LOG(ERR, rxq,
1634 "Outer L3 csum failed, flags = 0x%x\n",
1636 rxq->rx_hw_errors++;
1637 ol_flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
1639 ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1642 flags = fp_cqe->tunnel_pars_flags.flags;
1646 qede_rx_cqe_to_tunn_pkt_type(flags);
1650 qede_rx_cqe_to_pkt_type_inner(parse_flag);
1652 /* Outer L3/L4 types is not available in CQE */
1653 packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1655 /* Outer L3/L4 types is not available in CQE.
1656 * Need to add offset to parse correctly,
1658 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1659 packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1661 packet_type |= qede_rx_cqe_to_pkt_type(parse_flag);
1664 /* Common handling for non-tunnel packets and for inner
1665 * headers in the case of tunnel.
1667 if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1668 PMD_RX_LOG(ERR, rxq,
1669 "L4 csum failed, flags = 0x%x\n",
1671 rxq->rx_hw_errors++;
1672 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1674 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1676 if (unlikely(qede_check_notunn_csum_l3(rx_mb, parse_flag))) {
1677 PMD_RX_LOG(ERR, rxq, "IP csum failed, flags = 0x%x\n",
1679 rxq->rx_hw_errors++;
1680 ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1682 ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1685 if (unlikely(CQE_HAS_VLAN(parse_flag) ||
1686 CQE_HAS_OUTER_VLAN(parse_flag))) {
1687 /* Note: FW doesn't indicate Q-in-Q packet */
1688 ol_flags |= RTE_MBUF_F_RX_VLAN;
1689 if (qdev->vlan_strip_flg) {
1690 ol_flags |= RTE_MBUF_F_RX_VLAN_STRIPPED;
1691 rx_mb->vlan_tci = vlan_tci;
1696 ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
1697 rx_mb->hash.rss = rss_hash;
1701 qede_rx_bd_ring_consume(rxq);
1703 /* Prefetch next mbuf while processing current one. */
1704 preload_idx = rxq->sw_rx_cons & num_rx_bds;
1705 rte_prefetch0(rxq->sw_rx_ring[preload_idx]);
1707 /* Update rest of the MBUF fields */
1708 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1709 rx_mb->port = port_id;
1710 rx_mb->ol_flags = ol_flags;
1711 rx_mb->data_len = len;
1712 rx_mb->packet_type = packet_type;
1713 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1714 print_rx_bd_info(rx_mb, rxq, bitfield_val);
1716 rx_mb->nb_segs = bd_num;
1717 rx_mb->pkt_len = pkt_len;
1719 rx_pkts[rx_pkt] = rx_mb;
1723 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1724 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1725 if (rx_pkt == nb_pkts) {
1726 PMD_RX_LOG(DEBUG, rxq,
1727 "Budget reached nb_pkts=%u received=%u",
1733 /* Request number of buffers to be allocated in next loop */
1734 rxq->rx_alloc_count = rx_alloc_count;
1736 rxq->rcv_pkts += rx_pkt;
1737 rxq->rx_segs += rx_pkt;
1738 PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
1744 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1746 struct qede_rx_queue *rxq = p_rxq;
1747 struct qede_dev *qdev = rxq->qdev;
1748 struct ecore_dev *edev = &qdev->edev;
1749 uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
1750 uint16_t rx_pkt = 0;
1751 union eth_rx_cqe *cqe;
1752 struct eth_fast_path_rx_reg_cqe *fp_cqe = NULL;
1753 register struct rte_mbuf *rx_mb = NULL;
1754 register struct rte_mbuf *seg1 = NULL;
1755 enum eth_rx_cqe_type cqe_type;
1756 uint16_t pkt_len = 0; /* Sum of all BD segments */
1757 uint16_t len; /* Length of first BD */
1758 uint8_t num_segs = 1;
1759 uint16_t preload_idx;
1760 uint16_t parse_flag;
1761 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1762 uint8_t bitfield_val;
1764 uint8_t tunn_parse_flag;
1765 struct eth_fast_path_rx_tpa_start_cqe *cqe_start_tpa;
1767 uint32_t packet_type;
1770 uint8_t offset, tpa_agg_idx, flags;
1771 struct qede_agg_info *tpa_info = NULL;
1773 int rx_alloc_count = 0;
1776 /* Allocate buffers that we used in previous loop */
1777 if (rxq->rx_alloc_count) {
1778 if (unlikely(qede_alloc_rx_bulk_mbufs(rxq,
1779 rxq->rx_alloc_count))) {
1780 struct rte_eth_dev *dev;
1782 PMD_RX_LOG(ERR, rxq,
1783 "New buffer allocation failed,"
1784 "dropping incoming packetn");
1785 dev = &rte_eth_devices[rxq->port_id];
1786 dev->data->rx_mbuf_alloc_failed +=
1787 rxq->rx_alloc_count;
1788 rxq->rx_alloc_errors += rxq->rx_alloc_count;
1791 qede_update_rx_prod(qdev, rxq);
1792 rxq->rx_alloc_count = 0;
1795 hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
1796 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1800 if (hw_comp_cons == sw_comp_cons)
1803 while (sw_comp_cons != hw_comp_cons) {
1805 packet_type = RTE_PTYPE_UNKNOWN;
1807 tpa_start_flg = false;
1810 /* Get the CQE from the completion ring */
1812 (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
1813 cqe_type = cqe->fast_path_regular.type;
1814 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type);
1817 case ETH_RX_CQE_TYPE_REGULAR:
1818 fp_cqe = &cqe->fast_path_regular;
1820 case ETH_RX_CQE_TYPE_TPA_START:
1821 cqe_start_tpa = &cqe->fast_path_tpa_start;
1822 tpa_info = &rxq->tpa_info[cqe_start_tpa->tpa_agg_index];
1823 tpa_start_flg = true;
1824 /* Mark it as LRO packet */
1825 ol_flags |= RTE_MBUF_F_RX_LRO;
1826 /* In split mode, seg_len is same as len_on_first_bd
1827 * and bw_ext_bd_len_list will be empty since there are
1828 * no additional buffers
1830 PMD_RX_LOG(INFO, rxq,
1831 "TPA start[%d] - len_on_first_bd %d header %d"
1832 " [bd_list[0] %d], [seg_len %d]\n",
1833 cqe_start_tpa->tpa_agg_index,
1834 rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd),
1835 cqe_start_tpa->header_len,
1836 rte_le_to_cpu_16(cqe_start_tpa->bw_ext_bd_len_list[0]),
1837 rte_le_to_cpu_16(cqe_start_tpa->seg_len));
1840 case ETH_RX_CQE_TYPE_TPA_CONT:
1841 qede_rx_process_tpa_cont_cqe(qdev, rxq,
1842 &cqe->fast_path_tpa_cont);
1844 case ETH_RX_CQE_TYPE_TPA_END:
1845 qede_rx_process_tpa_end_cqe(qdev, rxq,
1846 &cqe->fast_path_tpa_end);
1847 tpa_agg_idx = cqe->fast_path_tpa_end.tpa_agg_index;
1848 tpa_info = &rxq->tpa_info[tpa_agg_idx];
1849 rx_mb = rxq->tpa_info[tpa_agg_idx].tpa_head;
1851 case ETH_RX_CQE_TYPE_SLOW_PATH:
1852 PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n");
1853 ecore_eth_cqe_completion(
1854 &edev->hwfns[rxq->queue_id % edev->num_hwfns],
1855 (struct eth_slow_path_rx_cqe *)cqe);
1861 /* Get the data from the SW ring */
1862 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1863 rx_mb = rxq->sw_rx_ring[sw_rx_index];
1864 assert(rx_mb != NULL);
1866 /* Handle regular CQE or TPA start CQE */
1867 if (!tpa_start_flg) {
1868 parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);
1869 offset = fp_cqe->placement_offset;
1870 len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
1871 pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1872 vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1873 rss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash);
1874 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1875 bitfield_val = fp_cqe->bitfields;
1879 rte_le_to_cpu_16(cqe_start_tpa->pars_flags.flags);
1880 offset = cqe_start_tpa->placement_offset;
1881 /* seg_len = len_on_first_bd */
1882 len = rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd);
1883 vlan_tci = rte_le_to_cpu_16(cqe_start_tpa->vlan_tag);
1884 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1885 bitfield_val = cqe_start_tpa->bitfields;
1887 rss_hash = rte_le_to_cpu_32(cqe_start_tpa->rss_hash);
1889 if (qede_tunn_exist(parse_flag)) {
1890 PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n");
1891 if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1892 PMD_RX_LOG(ERR, rxq,
1893 "L4 csum failed, flags = 0x%x\n",
1895 rxq->rx_hw_errors++;
1896 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1898 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1901 if (unlikely(qede_check_tunn_csum_l3(parse_flag))) {
1902 PMD_RX_LOG(ERR, rxq,
1903 "Outer L3 csum failed, flags = 0x%x\n",
1905 rxq->rx_hw_errors++;
1906 ol_flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
1908 ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1912 flags = cqe_start_tpa->tunnel_pars_flags.flags;
1914 flags = fp_cqe->tunnel_pars_flags.flags;
1915 tunn_parse_flag = flags;
1919 qede_rx_cqe_to_tunn_pkt_type(tunn_parse_flag);
1923 qede_rx_cqe_to_pkt_type_inner(parse_flag);
1925 /* Outer L3/L4 types is not available in CQE */
1926 packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1928 /* Outer L3/L4 types is not available in CQE.
1929 * Need to add offset to parse correctly,
1931 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1932 packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1934 packet_type |= qede_rx_cqe_to_pkt_type(parse_flag);
1937 /* Common handling for non-tunnel packets and for inner
1938 * headers in the case of tunnel.
1940 if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1941 PMD_RX_LOG(ERR, rxq,
1942 "L4 csum failed, flags = 0x%x\n",
1944 rxq->rx_hw_errors++;
1945 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1947 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1949 if (unlikely(qede_check_notunn_csum_l3(rx_mb, parse_flag))) {
1950 PMD_RX_LOG(ERR, rxq, "IP csum failed, flags = 0x%x\n",
1952 rxq->rx_hw_errors++;
1953 ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1955 ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1958 if (CQE_HAS_VLAN(parse_flag) ||
1959 CQE_HAS_OUTER_VLAN(parse_flag)) {
1960 /* Note: FW doesn't indicate Q-in-Q packet */
1961 ol_flags |= RTE_MBUF_F_RX_VLAN;
1962 if (qdev->vlan_strip_flg) {
1963 ol_flags |= RTE_MBUF_F_RX_VLAN_STRIPPED;
1964 rx_mb->vlan_tci = vlan_tci;
1969 if (qdev->rss_enable) {
1970 ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
1971 rx_mb->hash.rss = rss_hash;
1975 qede_rx_bd_ring_consume(rxq);
1977 if (!tpa_start_flg && fp_cqe->bd_num > 1) {
1978 PMD_RX_LOG(DEBUG, rxq, "Jumbo-over-BD packet: %02x BDs"
1979 " len on first: %04x Total Len: %04x",
1980 fp_cqe->bd_num, len, pkt_len);
1981 num_segs = fp_cqe->bd_num - 1;
1983 if (qede_process_sg_pkts(p_rxq, seg1, num_segs,
1987 rx_alloc_count += num_segs;
1988 rxq->rx_segs += num_segs;
1990 rxq->rx_segs++; /* for the first segment */
1992 /* Prefetch next mbuf while processing current one. */
1993 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1994 rte_prefetch0(rxq->sw_rx_ring[preload_idx]);
1996 /* Update rest of the MBUF fields */
1997 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1998 rx_mb->port = rxq->port_id;
1999 rx_mb->ol_flags = ol_flags;
2000 rx_mb->data_len = len;
2001 rx_mb->packet_type = packet_type;
2002 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
2003 print_rx_bd_info(rx_mb, rxq, bitfield_val);
2005 if (!tpa_start_flg) {
2006 rx_mb->nb_segs = fp_cqe->bd_num;
2007 rx_mb->pkt_len = pkt_len;
2009 /* store ref to the updated mbuf */
2010 tpa_info->tpa_head = rx_mb;
2011 tpa_info->tpa_tail = tpa_info->tpa_head;
2013 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
2015 if (!tpa_start_flg) {
2016 rx_pkts[rx_pkt] = rx_mb;
2020 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
2021 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
2022 if (rx_pkt == nb_pkts) {
2023 PMD_RX_LOG(DEBUG, rxq,
2024 "Budget reached nb_pkts=%u received=%u",
2030 /* Request number of buffers to be allocated in next loop */
2031 rxq->rx_alloc_count = rx_alloc_count;
2033 rxq->rcv_pkts += rx_pkt;
2035 PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
2041 qede_recv_pkts_cmt(void *p_fp_cmt, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2043 struct qede_fastpath_cmt *fp_cmt = p_fp_cmt;
2044 uint16_t eng0_pkts, eng1_pkts;
2046 eng0_pkts = nb_pkts / 2;
2048 eng0_pkts = qede_recv_pkts(fp_cmt->fp0->rxq, rx_pkts, eng0_pkts);
2050 eng1_pkts = nb_pkts - eng0_pkts;
2052 eng1_pkts = qede_recv_pkts(fp_cmt->fp1->rxq, rx_pkts + eng0_pkts,
2055 return eng0_pkts + eng1_pkts;
2058 /* Populate scatter gather buffer descriptor fields */
2059 static inline uint16_t
2060 qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg,
2061 struct eth_tx_2nd_bd **bd2, struct eth_tx_3rd_bd **bd3,
2064 struct qede_tx_queue *txq = p_txq;
2065 struct eth_tx_bd *tx_bd = NULL;
2067 uint16_t nb_segs = 0;
2069 /* Check for scattered buffers */
2071 if (start_seg == 0) {
2073 *bd2 = (struct eth_tx_2nd_bd *)
2074 ecore_chain_produce(&txq->tx_pbl);
2075 memset(*bd2, 0, sizeof(struct eth_tx_2nd_bd));
2078 mapping = rte_mbuf_data_iova(m_seg);
2079 QEDE_BD_SET_ADDR_LEN(*bd2, mapping, m_seg->data_len);
2080 PMD_TX_LOG(DEBUG, txq, "BD2 len %04x", m_seg->data_len);
2081 } else if (start_seg == 1) {
2083 *bd3 = (struct eth_tx_3rd_bd *)
2084 ecore_chain_produce(&txq->tx_pbl);
2085 memset(*bd3, 0, sizeof(struct eth_tx_3rd_bd));
2088 mapping = rte_mbuf_data_iova(m_seg);
2089 QEDE_BD_SET_ADDR_LEN(*bd3, mapping, m_seg->data_len);
2090 PMD_TX_LOG(DEBUG, txq, "BD3 len %04x", m_seg->data_len);
2092 tx_bd = (struct eth_tx_bd *)
2093 ecore_chain_produce(&txq->tx_pbl);
2094 memset(tx_bd, 0, sizeof(*tx_bd));
2096 mapping = rte_mbuf_data_iova(m_seg);
2097 QEDE_BD_SET_ADDR_LEN(tx_bd, mapping, m_seg->data_len);
2098 PMD_TX_LOG(DEBUG, txq, "BD len %04x", m_seg->data_len);
2101 m_seg = m_seg->next;
2104 /* Return total scattered buffers */
2108 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2110 print_tx_bd_info(struct qede_tx_queue *txq,
2111 struct eth_tx_1st_bd *bd1,
2112 struct eth_tx_2nd_bd *bd2,
2113 struct eth_tx_3rd_bd *bd3,
2114 uint64_t tx_ol_flags)
2116 char ol_buf[256] = { 0 }; /* for verbose prints */
2119 PMD_TX_LOG(INFO, txq,
2120 "BD1: nbytes=0x%04x nbds=0x%04x bd_flags=0x%04x bf=0x%04x",
2121 rte_cpu_to_le_16(bd1->nbytes), bd1->data.nbds,
2122 bd1->data.bd_flags.bitfields,
2123 rte_cpu_to_le_16(bd1->data.bitfields));
2125 PMD_TX_LOG(INFO, txq,
2126 "BD2: nbytes=0x%04x bf1=0x%04x bf2=0x%04x tunn_ip=0x%04x\n",
2127 rte_cpu_to_le_16(bd2->nbytes), bd2->data.bitfields1,
2128 bd2->data.bitfields2, bd2->data.tunn_ip_size);
2130 PMD_TX_LOG(INFO, txq,
2131 "BD3: nbytes=0x%04x bf=0x%04x MSS=0x%04x "
2132 "tunn_l4_hdr_start_offset_w=0x%04x tunn_hdr_size=0x%04x\n",
2133 rte_cpu_to_le_16(bd3->nbytes),
2134 rte_cpu_to_le_16(bd3->data.bitfields),
2135 rte_cpu_to_le_16(bd3->data.lso_mss),
2136 bd3->data.tunn_l4_hdr_start_offset_w,
2137 bd3->data.tunn_hdr_size_w);
2139 rte_get_tx_ol_flag_list(tx_ol_flags, ol_buf, sizeof(ol_buf));
2140 PMD_TX_LOG(INFO, txq, "TX offloads = %s\n", ol_buf);
2144 /* TX prepare to check packets meets TX conditions */
2146 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2147 qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
2150 struct qede_tx_queue *txq = p_txq;
2152 qede_xmit_prep_pkts(__rte_unused void *p_txq, struct rte_mbuf **tx_pkts,
2159 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2163 for (i = 0; i < nb_pkts; i++) {
2165 ol_flags = m->ol_flags;
2166 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2167 if (m->nb_segs >= ETH_TX_MAX_BDS_PER_LSO_PACKET) {
2171 /* TBD: confirm its ~9700B for both ? */
2172 if (m->tso_segsz > ETH_TX_MAX_NON_LSO_PKT_LEN) {
2177 if (m->nb_segs >= ETH_TX_MAX_BDS_PER_NON_LSO_PACKET) {
2182 if (ol_flags & QEDE_TX_OFFLOAD_NOTSUP_MASK) {
2183 /* We support only limited tunnel protocols */
2184 if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
2187 temp = ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK;
2188 if (temp == RTE_MBUF_F_TX_TUNNEL_VXLAN ||
2189 temp == RTE_MBUF_F_TX_TUNNEL_GENEVE ||
2190 temp == RTE_MBUF_F_TX_TUNNEL_MPLSINUDP ||
2191 temp == RTE_MBUF_F_TX_TUNNEL_GRE)
2195 rte_errno = ENOTSUP;
2199 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2200 ret = rte_validate_tx_offload(m);
2208 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2209 if (unlikely(i != nb_pkts))
2210 PMD_TX_LOG(ERR, txq, "TX prepare failed for %u\n",
2216 #define MPLSINUDP_HDR_SIZE (12)
2218 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2220 qede_mpls_tunn_tx_sanity_check(struct rte_mbuf *mbuf,
2221 struct qede_tx_queue *txq)
2223 if (((mbuf->outer_l2_len + mbuf->outer_l3_len) / 2) > 0xff)
2224 PMD_TX_LOG(ERR, txq, "tunn_l4_hdr_start_offset overflow\n");
2225 if (((mbuf->outer_l2_len + mbuf->outer_l3_len +
2226 MPLSINUDP_HDR_SIZE) / 2) > 0xff)
2227 PMD_TX_LOG(ERR, txq, "tunn_hdr_size overflow\n");
2228 if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE) / 2) >
2229 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK)
2230 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
2231 if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2) >
2232 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
2233 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
2238 qede_xmit_pkts_regular(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2240 struct qede_tx_queue *txq = p_txq;
2241 struct qede_dev *qdev = txq->qdev;
2242 struct ecore_dev *edev = &qdev->edev;
2243 struct eth_tx_1st_bd *bd1;
2244 struct eth_tx_2nd_bd *bd2;
2245 struct eth_tx_3rd_bd *bd3;
2246 struct rte_mbuf *m_seg = NULL;
2247 struct rte_mbuf *mbuf;
2248 struct rte_mbuf **sw_tx_ring;
2249 uint16_t nb_tx_pkts;
2252 uint16_t nb_frags = 0;
2253 uint16_t nb_pkt_sent = 0;
2255 uint64_t tx_ol_flags;
2258 uint8_t bd1_bd_flags_bf;
2260 if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
2261 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
2262 nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
2263 qede_process_tx_compl(edev, txq);
2266 nb_tx_pkts = nb_pkts;
2267 bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2268 sw_tx_ring = txq->sw_tx_ring;
2270 while (nb_tx_pkts--) {
2271 /* Init flags/values */
2277 bd1_bd_flags_bf = 0;
2284 /* Check minimum TX BDS availability against available BDs */
2285 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs))
2288 tx_ol_flags = mbuf->ol_flags;
2289 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
2291 if (unlikely(txq->nb_tx_avail <
2292 ETH_TX_MIN_BDS_PER_NON_LSO_PKT))
2295 (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
2296 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
2298 /* Offload the IP checksum in the hardware */
2299 if (tx_ol_flags & RTE_MBUF_F_TX_IP_CKSUM)
2301 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
2303 /* L4 checksum offload (tcp or udp) */
2304 if ((tx_ol_flags & (RTE_MBUF_F_TX_IPV4 | RTE_MBUF_F_TX_IPV6)) &&
2305 (tx_ol_flags & (RTE_MBUF_F_TX_UDP_CKSUM | RTE_MBUF_F_TX_TCP_CKSUM)))
2307 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
2309 /* Fill the entry in the SW ring and the BDs in the FW ring */
2311 sw_tx_ring[idx] = mbuf;
2314 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
2315 memset(bd1, 0, sizeof(struct eth_tx_1st_bd));
2318 /* Map MBUF linear data for DMA and set in the BD1 */
2319 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2321 bd1->data.bitfields = rte_cpu_to_le_16(bd1_bf);
2322 bd1->data.bd_flags.bitfields = bd1_bd_flags_bf;
2324 /* Handle fragmented MBUF */
2325 if (unlikely(mbuf->nb_segs > 1)) {
2328 /* Encode scatter gather buffer descriptors */
2329 nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3,
2333 bd1->data.nbds = nbds + nb_frags;
2335 txq->nb_tx_avail -= bd1->data.nbds;
2338 rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2339 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2340 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);
2346 /* Write value of prod idx into bd_prod */
2347 txq->tx_db.data.bd_prod = bd_prod;
2349 rte_compiler_barrier();
2350 DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
2353 /* Check again for Tx completions */
2354 qede_process_tx_compl(edev, txq);
2356 PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d",
2357 nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());
2363 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2365 struct qede_tx_queue *txq = p_txq;
2366 struct qede_dev *qdev = txq->qdev;
2367 struct ecore_dev *edev = &qdev->edev;
2368 struct rte_mbuf *mbuf;
2369 struct rte_mbuf *m_seg = NULL;
2370 uint16_t nb_tx_pkts;
2374 uint16_t nb_pkt_sent = 0;
2378 __rte_unused bool tunn_flg;
2379 bool tunn_ipv6_ext_flg;
2380 struct eth_tx_1st_bd *bd1;
2381 struct eth_tx_2nd_bd *bd2;
2382 struct eth_tx_3rd_bd *bd3;
2383 uint64_t tx_ol_flags;
2387 uint8_t bd1_bd_flags_bf;
2396 uint8_t tunn_l4_hdr_start_offset;
2397 uint8_t tunn_hdr_size;
2398 uint8_t inner_l2_hdr_size;
2399 uint16_t inner_l4_hdr_offset;
2401 if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
2402 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
2403 nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
2404 qede_process_tx_compl(edev, txq);
2407 nb_tx_pkts = nb_pkts;
2408 bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2409 while (nb_tx_pkts--) {
2410 /* Init flags/values */
2420 bd1_bd_flags_bf = 0;
2425 mplsoudp_flg = false;
2426 tunn_ipv6_ext_flg = false;
2428 tunn_l4_hdr_start_offset = 0;
2433 /* Check minimum TX BDS availability against available BDs */
2434 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs))
2437 tx_ol_flags = mbuf->ol_flags;
2438 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
2440 /* TX prepare would have already checked supported tunnel Tx
2441 * offloads. Don't rely on pkt_type marked by Rx, instead use
2442 * tx_ol_flags to decide.
2444 tunn_flg = !!(tx_ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK);
2447 /* Check against max which is Tunnel IPv6 + ext */
2448 if (unlikely(txq->nb_tx_avail <
2449 ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT))
2452 /* First indicate its a tunnel pkt */
2453 bd1_bf |= ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
2454 ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
2455 /* Legacy FW had flipped behavior in regard to this bit
2456 * i.e. it needed to set to prevent FW from touching
2457 * encapsulated packets when it didn't need to.
2459 if (unlikely(txq->is_legacy)) {
2461 ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
2464 /* Outer IP checksum offload */
2465 if (tx_ol_flags & (RTE_MBUF_F_TX_OUTER_IP_CKSUM |
2466 RTE_MBUF_F_TX_OUTER_IPV4)) {
2468 ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
2469 ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
2473 * Currently, only inner checksum offload in MPLS-in-UDP
2474 * tunnel with one MPLS label is supported. Both outer
2475 * and inner layers lengths need to be provided in
2478 if ((tx_ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) ==
2479 RTE_MBUF_F_TX_TUNNEL_MPLSINUDP) {
2480 mplsoudp_flg = true;
2481 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2482 qede_mpls_tunn_tx_sanity_check(mbuf, txq);
2484 /* Outer L4 offset in two byte words */
2485 tunn_l4_hdr_start_offset =
2486 (mbuf->outer_l2_len + mbuf->outer_l3_len) / 2;
2487 /* Tunnel header size in two byte words */
2488 tunn_hdr_size = (mbuf->outer_l2_len +
2489 mbuf->outer_l3_len +
2490 MPLSINUDP_HDR_SIZE) / 2;
2491 /* Inner L2 header size in two byte words */
2492 inner_l2_hdr_size = (mbuf->l2_len -
2493 MPLSINUDP_HDR_SIZE) / 2;
2494 /* Inner L4 header offset from the beginning
2495 * of inner packet in two byte words
2497 inner_l4_hdr_offset = (mbuf->l2_len -
2498 MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2;
2500 /* Inner L2 size and address type */
2501 bd2_bf1 |= (inner_l2_hdr_size &
2502 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK) <<
2503 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT;
2504 bd2_bf1 |= (UNICAST_ADDRESS &
2505 ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK) <<
2506 ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT;
2507 /* Treated as IPv6+Ext */
2509 1 << ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT;
2511 /* Mark inner IPv6 if present */
2512 if (tx_ol_flags & RTE_MBUF_F_TX_IPV6)
2514 1 << ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT;
2516 /* Inner L4 offsets */
2517 if ((tx_ol_flags & (RTE_MBUF_F_TX_IPV4 | RTE_MBUF_F_TX_IPV6)) &&
2518 (tx_ol_flags & (RTE_MBUF_F_TX_UDP_CKSUM |
2519 RTE_MBUF_F_TX_TCP_CKSUM))) {
2520 /* Determines if BD3 is needed */
2521 tunn_ipv6_ext_flg = true;
2522 if ((tx_ol_flags & RTE_MBUF_F_TX_L4_MASK) ==
2523 RTE_MBUF_F_TX_UDP_CKSUM) {
2525 1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
2528 /* TODO other pseudo checksum modes are
2532 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
2533 ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT;
2534 bd2_bf2 |= (inner_l4_hdr_offset &
2535 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK) <<
2536 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
2538 } /* End MPLSoUDP */
2539 } /* End Tunnel handling */
2541 if (tx_ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2543 if (unlikely(txq->nb_tx_avail <
2544 ETH_TX_MIN_BDS_PER_LSO_PKT))
2546 /* For LSO, packet header and payload must reside on
2547 * buffers pointed by different BDs. Using BD1 for HDR
2548 * and BD2 onwards for data.
2550 hdr_size = mbuf->l2_len + mbuf->l3_len + mbuf->l4_len;
2552 hdr_size += mbuf->outer_l2_len +
2555 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT;
2557 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
2558 /* RTE_MBUF_F_TX_TCP_SEG implies RTE_MBUF_F_TX_TCP_CKSUM */
2560 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
2561 mss = rte_cpu_to_le_16(mbuf->tso_segsz);
2562 /* Using one header BD */
2563 bd3_bf |= rte_cpu_to_le_16(1 <<
2564 ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
2566 if (unlikely(txq->nb_tx_avail <
2567 ETH_TX_MIN_BDS_PER_NON_LSO_PKT))
2570 (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
2571 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
2574 /* Descriptor based VLAN insertion */
2575 if (tx_ol_flags & RTE_MBUF_F_TX_VLAN) {
2576 vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
2578 1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
2581 /* Offload the IP checksum in the hardware */
2582 if (tx_ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
2584 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
2585 /* There's no DPDK flag to request outer-L4 csum
2586 * offload. But in the case of tunnel if inner L3 or L4
2587 * csum offload is requested then we need to force
2588 * recalculation of L4 tunnel header csum also.
2590 if (tunn_flg && ((tx_ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) !=
2591 RTE_MBUF_F_TX_TUNNEL_GRE)) {
2593 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
2594 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
2598 /* L4 checksum offload (tcp or udp) */
2599 if ((tx_ol_flags & (RTE_MBUF_F_TX_IPV4 | RTE_MBUF_F_TX_IPV6)) &&
2600 (tx_ol_flags & (RTE_MBUF_F_TX_UDP_CKSUM | RTE_MBUF_F_TX_TCP_CKSUM))) {
2602 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
2603 /* There's no DPDK flag to request outer-L4 csum
2604 * offload. But in the case of tunnel if inner L3 or L4
2605 * csum offload is requested then we need to force
2606 * recalculation of L4 tunnel header csum also.
2610 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
2611 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
2615 /* Fill the entry in the SW ring and the BDs in the FW ring */
2617 txq->sw_tx_ring[idx] = mbuf;
2620 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
2621 memset(bd1, 0, sizeof(struct eth_tx_1st_bd));
2624 /* Map MBUF linear data for DMA and set in the BD1 */
2625 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2627 bd1->data.bitfields = rte_cpu_to_le_16(bd1_bf);
2628 bd1->data.bd_flags.bitfields = bd1_bd_flags_bf;
2629 bd1->data.vlan = vlan;
2631 if (lso_flg || mplsoudp_flg) {
2632 bd2 = (struct eth_tx_2nd_bd *)ecore_chain_produce
2634 memset(bd2, 0, sizeof(struct eth_tx_2nd_bd));
2638 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2641 QEDE_BD_SET_ADDR_LEN(bd2, (hdr_size +
2642 rte_mbuf_data_iova(mbuf)),
2643 mbuf->data_len - hdr_size);
2644 bd2->data.bitfields1 = rte_cpu_to_le_16(bd2_bf1);
2646 bd2->data.bitfields2 =
2647 rte_cpu_to_le_16(bd2_bf2);
2649 bd2->data.tunn_ip_size =
2650 rte_cpu_to_le_16(mbuf->outer_l3_len);
2653 if (lso_flg || (mplsoudp_flg && tunn_ipv6_ext_flg)) {
2654 bd3 = (struct eth_tx_3rd_bd *)
2655 ecore_chain_produce(&txq->tx_pbl);
2656 memset(bd3, 0, sizeof(struct eth_tx_3rd_bd));
2658 bd3->data.bitfields = rte_cpu_to_le_16(bd3_bf);
2660 bd3->data.lso_mss = mss;
2662 bd3->data.tunn_l4_hdr_start_offset_w =
2663 tunn_l4_hdr_start_offset;
2664 bd3->data.tunn_hdr_size_w =
2670 /* Handle fragmented MBUF */
2673 /* Encode scatter gather buffer descriptors if required */
2674 nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3, nbds - 1);
2675 bd1->data.nbds = nbds + nb_frags;
2677 txq->nb_tx_avail -= bd1->data.nbds;
2680 rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2681 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2682 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);
2688 /* Write value of prod idx into bd_prod */
2689 txq->tx_db.data.bd_prod = bd_prod;
2691 rte_compiler_barrier();
2692 DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
2695 /* Check again for Tx completions */
2696 qede_process_tx_compl(edev, txq);
2698 PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d",
2699 nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());
2705 qede_xmit_pkts_cmt(void *p_fp_cmt, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2707 struct qede_fastpath_cmt *fp_cmt = p_fp_cmt;
2708 uint16_t eng0_pkts, eng1_pkts;
2710 eng0_pkts = nb_pkts / 2;
2712 eng0_pkts = qede_xmit_pkts(fp_cmt->fp0->txq, tx_pkts, eng0_pkts);
2714 eng1_pkts = nb_pkts - eng0_pkts;
2716 eng1_pkts = qede_xmit_pkts(fp_cmt->fp1->txq, tx_pkts + eng0_pkts,
2719 return eng0_pkts + eng1_pkts;
2722 /* this function does a fake walk through over completion queue
2723 * to calculate number of BDs used by HW.
2724 * At the end, it restores the state of completion queue.
2727 qede_parse_fp_cqe(struct qede_rx_queue *rxq)
2729 uint16_t hw_comp_cons, sw_comp_cons, bd_count = 0;
2730 union eth_rx_cqe *cqe, *orig_cqe = NULL;
2732 hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
2733 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
2735 if (hw_comp_cons == sw_comp_cons)
2738 /* Get the CQE from the completion ring */
2739 cqe = (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
2742 while (sw_comp_cons != hw_comp_cons) {
2743 switch (cqe->fast_path_regular.type) {
2744 case ETH_RX_CQE_TYPE_REGULAR:
2745 bd_count += cqe->fast_path_regular.bd_num;
2747 case ETH_RX_CQE_TYPE_TPA_END:
2748 bd_count += cqe->fast_path_tpa_end.num_of_bds;
2755 (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
2756 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
2759 /* revert comp_ring to original state */
2760 ecore_chain_set_cons(&rxq->rx_comp_ring, sw_comp_cons, orig_cqe);
2766 qede_rx_descriptor_status(void *p_rxq, uint16_t offset)
2768 uint16_t hw_bd_cons, sw_bd_cons, sw_bd_prod;
2769 uint16_t produced, consumed;
2770 struct qede_rx_queue *rxq = p_rxq;
2772 if (offset > rxq->nb_rx_desc)
2775 sw_bd_cons = ecore_chain_get_cons_idx(&rxq->rx_bd_ring);
2776 sw_bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
2778 /* find BDs used by HW from completion queue elements */
2779 hw_bd_cons = sw_bd_cons + qede_parse_fp_cqe(rxq);
2781 if (hw_bd_cons < sw_bd_cons)
2782 /* wraparound case */
2783 consumed = (0xffff - sw_bd_cons) + hw_bd_cons;
2785 consumed = hw_bd_cons - sw_bd_cons;
2787 if (offset <= consumed)
2788 return RTE_ETH_RX_DESC_DONE;
2790 if (sw_bd_prod < sw_bd_cons)
2791 /* wraparound case */
2792 produced = (0xffff - sw_bd_cons) + sw_bd_prod;
2794 produced = sw_bd_prod - sw_bd_cons;
2796 if (offset <= produced)
2797 return RTE_ETH_RX_DESC_AVAIL;
2799 return RTE_ETH_RX_DESC_UNAVAIL;