2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
13 #include "qede_ethdev.h"
15 /* Ring Descriptors */
16 #define RX_RING_SIZE_POW 16 /* 64K */
17 #define RX_RING_SIZE (1ULL << RX_RING_SIZE_POW)
18 #define NUM_RX_BDS_MAX (RX_RING_SIZE - 1)
19 #define NUM_RX_BDS_MIN 128
20 #define NUM_RX_BDS_DEF NUM_RX_BDS_MAX
21 #define NUM_RX_BDS(q) (q->nb_rx_desc - 1)
23 #define TX_RING_SIZE_POW 16 /* 64K */
24 #define TX_RING_SIZE (1ULL << TX_RING_SIZE_POW)
25 #define NUM_TX_BDS_MAX (TX_RING_SIZE - 1)
26 #define NUM_TX_BDS_MIN 128
27 #define NUM_TX_BDS_DEF NUM_TX_BDS_MAX
28 #define NUM_TX_BDS(q) (q->nb_tx_desc - 1)
30 #define TX_CONS(txq) (txq->sw_tx_cons & NUM_TX_BDS(txq))
31 #define TX_PROD(txq) (txq->sw_tx_prod & NUM_TX_BDS(txq))
33 /* Number of TX BDs per packet used currently */
34 #define MAX_NUM_TX_BDS 1
36 #define QEDE_DEFAULT_TX_FREE_THRESH 32
38 #define QEDE_CSUM_ERROR (1 << 0)
39 #define QEDE_CSUM_UNNECESSARY (1 << 1)
40 #define QEDE_TUNN_CSUM_UNNECESSARY (1 << 2)
42 #define QEDE_BD_SET_ADDR_LEN(bd, maddr, len) \
44 (bd)->addr.hi = rte_cpu_to_le_32(U64_HI(maddr)); \
45 (bd)->addr.lo = rte_cpu_to_le_32(U64_LO(maddr)); \
46 (bd)->nbytes = rte_cpu_to_le_16(len); \
49 #define CQE_HAS_VLAN(flags) \
50 ((flags) & (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK \
51 << PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT))
53 #define CQE_HAS_OUTER_VLAN(flags) \
54 ((flags) & (PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK \
55 << PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT))
57 /* Max supported alignment is 256 (8 shift)
58 * minimal alignment shift 6 is optimal for 57xxx HW performance
60 #define QEDE_L1_CACHE_SHIFT 6
61 #define QEDE_RX_ALIGN_SHIFT (RTE_MAX(6, RTE_MIN(8, QEDE_L1_CACHE_SHIFT)))
62 #define QEDE_FW_RX_ALIGN_END (1UL << QEDE_RX_ALIGN_SHIFT)
64 #define QEDE_ETH_OVERHEAD (ETHER_HDR_LEN + 8 + 8 + QEDE_FW_RX_ALIGN_END)
66 /* TBD: Excluding IPV6 */
67 #define QEDE_RSS_OFFLOAD_ALL (ETH_RSS_IPV4 | ETH_RSS_NONFRAG_IPV4_TCP | \
68 ETH_RSS_NONFRAG_IPV4_UDP)
70 #define QEDE_TXQ_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS)
74 #define for_each_rss(i) for (i = 0; i < qdev->num_rss; i++)
77 * RX BD descriptor ring
79 struct qede_rx_entry {
80 struct rte_mbuf *mbuf;
82 /* allows expansion .. */
86 * Structure associated with each RX queue.
88 struct qede_rx_queue {
89 struct rte_mempool *mb_pool;
90 struct ecore_chain rx_bd_ring;
91 struct ecore_chain rx_comp_ring;
92 uint16_t *hw_cons_ptr;
93 void OSAL_IOMEM *hw_rxq_prod_addr;
94 struct qede_rx_entry *sw_rx_ring;
100 uint16_t rx_buf_size;
101 uint64_t rx_hw_errors;
102 uint64_t rx_alloc_errors;
103 struct qede_dev *qdev;
107 * TX BD descriptor ring
109 struct qede_tx_entry {
110 struct rte_mbuf *mbuf;
115 struct eth_db_data data;
119 struct qede_tx_queue {
120 struct ecore_chain tx_pbl;
121 struct qede_tx_entry *sw_tx_ring;
123 uint16_t nb_tx_avail;
124 uint16_t tx_free_thresh;
126 uint16_t *hw_cons_ptr;
129 void OSAL_IOMEM *doorbell_addr;
130 volatile union db_prod tx_db;
132 uint64_t txq_counter;
133 struct qede_dev *qdev;
136 struct qede_fastpath {
137 struct qede_dev *qdev;
139 struct ecore_sb_info *sb_info;
140 struct qede_rx_queue *rxq;
141 struct qede_tx_queue *txqs[MAX_NUM_TC];
146 * RX/TX function prototypes
148 int qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
149 uint16_t nb_desc, unsigned int socket_id,
150 const struct rte_eth_rxconf *rx_conf,
151 struct rte_mempool *mp);
153 int qede_tx_queue_setup(struct rte_eth_dev *dev,
156 unsigned int socket_id,
157 const struct rte_eth_txconf *tx_conf);
159 void qede_rx_queue_release(void *rx_queue);
161 void qede_tx_queue_release(void *tx_queue);
163 int qede_dev_start(struct rte_eth_dev *eth_dev);
165 void qede_dev_stop(struct rte_eth_dev *eth_dev);
167 void qede_reset_fp_rings(struct qede_dev *qdev);
169 void qede_free_fp_arrays(struct qede_dev *qdev);
171 void qede_free_mem_load(struct qede_dev *qdev);
173 uint16_t qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
176 uint16_t qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts,
179 #endif /* _QEDE_RXTX_H_ */