2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
13 #include "qede_ethdev.h"
15 /* Ring Descriptors */
16 #define RX_RING_SIZE_POW 16 /* 64K */
17 #define RX_RING_SIZE (1ULL << RX_RING_SIZE_POW)
18 #define NUM_RX_BDS_MAX (RX_RING_SIZE - 1)
19 #define NUM_RX_BDS_MIN 128
20 #define NUM_RX_BDS_DEF NUM_RX_BDS_MAX
21 #define NUM_RX_BDS(q) (q->nb_rx_desc - 1)
23 #define TX_RING_SIZE_POW 16 /* 64K */
24 #define TX_RING_SIZE (1ULL << TX_RING_SIZE_POW)
25 #define NUM_TX_BDS_MAX (TX_RING_SIZE - 1)
26 #define NUM_TX_BDS_MIN 128
27 #define NUM_TX_BDS_DEF NUM_TX_BDS_MAX
28 #define NUM_TX_BDS(q) (q->nb_tx_desc - 1)
30 #define TX_CONS(txq) (txq->sw_tx_cons & NUM_TX_BDS(txq))
31 #define TX_PROD(txq) (txq->sw_tx_prod & NUM_TX_BDS(txq))
33 #define QEDE_DEFAULT_TX_FREE_THRESH 32
35 #define QEDE_CSUM_ERROR (1 << 0)
36 #define QEDE_CSUM_UNNECESSARY (1 << 1)
37 #define QEDE_TUNN_CSUM_UNNECESSARY (1 << 2)
39 #define QEDE_BD_SET_ADDR_LEN(bd, maddr, len) \
41 (bd)->addr.hi = rte_cpu_to_le_32(U64_HI(maddr)); \
42 (bd)->addr.lo = rte_cpu_to_le_32(U64_LO(maddr)); \
43 (bd)->nbytes = rte_cpu_to_le_16(len); \
46 #define CQE_HAS_VLAN(flags) \
47 ((flags) & (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK \
48 << PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT))
50 #define CQE_HAS_OUTER_VLAN(flags) \
51 ((flags) & (PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK \
52 << PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT))
54 #define QEDE_MIN_RX_BUFF_SIZE (1024)
55 #define QEDE_VLAN_TAG_SIZE (4)
56 #define QEDE_LLC_SNAP_HDR_LEN (8)
58 /* Max supported alignment is 256 (8 shift)
59 * minimal alignment shift 6 is optimal for 57xxx HW performance
61 #define QEDE_L1_CACHE_SHIFT 6
62 #define QEDE_RX_ALIGN_SHIFT (RTE_MAX(6, RTE_MIN(8, QEDE_L1_CACHE_SHIFT)))
63 #define QEDE_FW_RX_ALIGN_END (1UL << QEDE_RX_ALIGN_SHIFT)
64 #define QEDE_CEIL_TO_CACHE_LINE_SIZE(n) (((n) + (QEDE_FW_RX_ALIGN_END - 1)) & \
65 ~(QEDE_FW_RX_ALIGN_END - 1))
66 /* Note: QEDE_LLC_SNAP_HDR_LEN is optional */
67 #define QEDE_ETH_OVERHEAD ((ETHER_HDR_LEN) + ((2 * QEDE_VLAN_TAG_SIZE)) \
68 + (QEDE_LLC_SNAP_HDR_LEN))
70 #define QEDE_RSS_OFFLOAD_ALL (ETH_RSS_IPV4 |\
71 ETH_RSS_NONFRAG_IPV4_TCP |\
72 ETH_RSS_NONFRAG_IPV4_UDP |\
74 ETH_RSS_NONFRAG_IPV6_TCP |\
75 ETH_RSS_NONFRAG_IPV6_UDP |\
78 #define QEDE_TXQ_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS)
80 #define for_each_rss(i) for (i = 0; i < qdev->num_rx_queues; i++)
81 #define for_each_tss(i) for (i = 0; i < qdev->num_tx_queues; i++)
82 #define QEDE_RXTX_MAX(qdev) \
83 (RTE_MAX(QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev)))
85 /* Macros for non-tunnel packet types lkup table */
86 #define QEDE_PKT_TYPE_UNKNOWN 0x0
87 #define QEDE_PKT_TYPE_MAX 0x3f
89 #define QEDE_PKT_TYPE_IPV4 0x1
90 #define QEDE_PKT_TYPE_IPV6 0x2
91 #define QEDE_PKT_TYPE_IPV4_TCP 0x5
92 #define QEDE_PKT_TYPE_IPV6_TCP 0x6
93 #define QEDE_PKT_TYPE_IPV4_UDP 0x9
94 #define QEDE_PKT_TYPE_IPV6_UDP 0xa
96 /* For frag pkts, corresponding IP bits is set */
97 #define QEDE_PKT_TYPE_IPV4_FRAG 0x11
98 #define QEDE_PKT_TYPE_IPV6_FRAG 0x12
100 #define QEDE_PKT_TYPE_IPV4_VLAN 0x21
101 #define QEDE_PKT_TYPE_IPV6_VLAN 0x22
102 #define QEDE_PKT_TYPE_IPV4_TCP_VLAN 0x25
103 #define QEDE_PKT_TYPE_IPV6_TCP_VLAN 0x26
104 #define QEDE_PKT_TYPE_IPV4_UDP_VLAN 0x29
105 #define QEDE_PKT_TYPE_IPV6_UDP_VLAN 0x2a
107 #define QEDE_PKT_TYPE_IPV4_VLAN_FRAG 0x31
108 #define QEDE_PKT_TYPE_IPV6_VLAN_FRAG 0x32
110 /* Macros for tunneled packets with next protocol lkup table */
111 #define QEDE_PKT_TYPE_TUNN_GENEVE 0x1
112 #define QEDE_PKT_TYPE_TUNN_GRE 0x2
113 #define QEDE_PKT_TYPE_TUNN_VXLAN 0x3
115 /* Bit 2 is don't care bit */
116 #define QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE 0x9
117 #define QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE 0xa
118 #define QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN 0xb
120 #define QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE 0xd
121 #define QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE 0xe
122 #define QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN 0xf
125 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE 0x11
126 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE 0x12
127 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN 0x13
129 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE 0x15
130 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE 0x16
131 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN 0x17
134 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE 0x19
135 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE 0x1a
136 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN 0x1b
138 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE 0x1d
139 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE 0x1e
140 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN 0x1f
142 #define QEDE_PKT_TYPE_TUNN_MAX_TYPE 0x20 /* 2^5 */
144 #define QEDE_TX_CSUM_OFFLOAD_MASK (PKT_TX_IP_CKSUM | \
147 PKT_TX_OUTER_IP_CKSUM | \
150 #define QEDE_TX_OFFLOAD_MASK (QEDE_TX_CSUM_OFFLOAD_MASK | \
153 PKT_TX_TUNNEL_VXLAN | \
154 PKT_TX_TUNNEL_MPLSINUDP)
156 #define QEDE_TX_OFFLOAD_NOTSUP_MASK \
157 (PKT_TX_OFFLOAD_MASK ^ QEDE_TX_OFFLOAD_MASK)
160 * RX BD descriptor ring
162 struct qede_rx_entry {
163 struct rte_mbuf *mbuf;
164 uint32_t page_offset;
165 /* allows expansion .. */
168 /* TPA related structures */
169 struct qede_agg_info {
170 struct rte_mbuf *tpa_head; /* Pointer to first TPA segment */
171 struct rte_mbuf *tpa_tail; /* Pointer to last TPA segment */
175 * Structure associated with each RX queue.
177 struct qede_rx_queue {
178 struct rte_mempool *mb_pool;
179 struct ecore_chain rx_bd_ring;
180 struct ecore_chain rx_comp_ring;
181 uint16_t *hw_cons_ptr;
182 void OSAL_IOMEM *hw_rxq_prod_addr;
183 struct qede_rx_entry *sw_rx_ring;
184 struct ecore_sb_info *sb_info;
190 uint16_t rx_buf_size;
193 uint64_t rx_hw_errors;
194 uint64_t rx_alloc_errors;
195 struct qede_agg_info tpa_info[ETH_TPA_MAX_AGGS_NUM];
196 struct qede_dev *qdev;
201 * TX BD descriptor ring
203 struct qede_tx_entry {
204 struct rte_mbuf *mbuf;
209 struct eth_db_data data;
213 struct qede_tx_queue {
214 struct ecore_chain tx_pbl;
215 struct qede_tx_entry *sw_tx_ring;
217 uint16_t nb_tx_avail;
218 uint16_t tx_free_thresh;
220 uint16_t *hw_cons_ptr;
223 void OSAL_IOMEM *doorbell_addr;
224 volatile union db_prod tx_db;
228 struct qede_dev *qdev;
232 struct qede_fastpath {
233 struct ecore_sb_info *sb_info;
234 struct qede_rx_queue *rxq;
235 struct qede_tx_queue *txq;
239 * RX/TX function prototypes
241 int qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
242 uint16_t nb_desc, unsigned int socket_id,
243 const struct rte_eth_rxconf *rx_conf,
244 struct rte_mempool *mp);
246 int qede_tx_queue_setup(struct rte_eth_dev *dev,
249 unsigned int socket_id,
250 const struct rte_eth_txconf *tx_conf);
252 void qede_rx_queue_release(void *rx_queue);
254 void qede_tx_queue_release(void *tx_queue);
256 uint16_t qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
259 uint16_t qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
262 uint16_t qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts,
265 uint16_t qede_rxtx_pkts_dummy(void *p_rxq,
266 struct rte_mbuf **pkts,
269 int qede_start_queues(struct rte_eth_dev *eth_dev);
271 void qede_stop_queues(struct rte_eth_dev *eth_dev);
273 /* Fastpath resource alloc/dealloc helpers */
274 int qede_alloc_fp_resc(struct qede_dev *qdev);
276 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev);
278 #endif /* _QEDE_RXTX_H_ */