1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
11 #include "qede_ethdev.h"
13 /* Ring Descriptors */
14 #define RX_RING_SIZE_POW 16 /* 64K */
15 #define RX_RING_SIZE (1ULL << RX_RING_SIZE_POW)
16 #define NUM_RX_BDS_MAX (RX_RING_SIZE - 1)
17 #define NUM_RX_BDS_MIN 128
18 #define NUM_RX_BDS_DEF NUM_RX_BDS_MAX
19 #define NUM_RX_BDS(q) (q->nb_rx_desc - 1)
21 #define TX_RING_SIZE_POW 16 /* 64K */
22 #define TX_RING_SIZE (1ULL << TX_RING_SIZE_POW)
23 #define NUM_TX_BDS_MAX (TX_RING_SIZE - 1)
24 #define NUM_TX_BDS_MIN 128
25 #define NUM_TX_BDS_DEF NUM_TX_BDS_MAX
26 #define NUM_TX_BDS(q) (q->nb_tx_desc - 1)
28 #define TX_CONS(txq) (txq->sw_tx_cons & NUM_TX_BDS(txq))
29 #define TX_PROD(txq) (txq->sw_tx_prod & NUM_TX_BDS(txq))
31 #define QEDE_DEFAULT_TX_FREE_THRESH 32
33 #define QEDE_CSUM_ERROR (1 << 0)
34 #define QEDE_CSUM_UNNECESSARY (1 << 1)
35 #define QEDE_TUNN_CSUM_UNNECESSARY (1 << 2)
37 #define QEDE_BD_SET_ADDR_LEN(bd, maddr, len) \
39 (bd)->addr.hi = rte_cpu_to_le_32(U64_HI(maddr)); \
40 (bd)->addr.lo = rte_cpu_to_le_32(U64_LO(maddr)); \
41 (bd)->nbytes = rte_cpu_to_le_16(len); \
44 #define CQE_HAS_VLAN(flags) \
45 ((flags) & (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK \
46 << PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT))
48 #define CQE_HAS_OUTER_VLAN(flags) \
49 ((flags) & (PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK \
50 << PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT))
52 #define QEDE_MIN_RX_BUFF_SIZE (1024)
53 #define QEDE_VLAN_TAG_SIZE (4)
54 #define QEDE_LLC_SNAP_HDR_LEN (8)
56 /* Max supported alignment is 256 (8 shift)
57 * minimal alignment shift 6 is optimal for 57xxx HW performance
59 #define QEDE_L1_CACHE_SHIFT 6
60 #define QEDE_RX_ALIGN_SHIFT (RTE_MAX(6, RTE_MIN(8, QEDE_L1_CACHE_SHIFT)))
61 #define QEDE_FW_RX_ALIGN_END (1UL << QEDE_RX_ALIGN_SHIFT)
62 #define QEDE_CEIL_TO_CACHE_LINE_SIZE(n) (((n) + (QEDE_FW_RX_ALIGN_END - 1)) & \
63 ~(QEDE_FW_RX_ALIGN_END - 1))
64 /* Note: QEDE_LLC_SNAP_HDR_LEN is optional */
65 #define QEDE_ETH_OVERHEAD (((2 * QEDE_VLAN_TAG_SIZE)) - (ETHER_CRC_LEN) \
66 + (QEDE_LLC_SNAP_HDR_LEN))
68 #define QEDE_RSS_OFFLOAD_ALL (ETH_RSS_IPV4 |\
69 ETH_RSS_NONFRAG_IPV4_TCP |\
70 ETH_RSS_NONFRAG_IPV4_UDP |\
72 ETH_RSS_NONFRAG_IPV6_TCP |\
73 ETH_RSS_NONFRAG_IPV6_UDP |\
77 #define for_each_rss(i) for (i = 0; i < qdev->num_rx_queues; i++)
78 #define for_each_tss(i) for (i = 0; i < qdev->num_tx_queues; i++)
79 #define QEDE_RXTX_MAX(qdev) \
80 (RTE_MAX(QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev)))
82 /* Macros for non-tunnel packet types lkup table */
83 #define QEDE_PKT_TYPE_UNKNOWN 0x0
84 #define QEDE_PKT_TYPE_MAX 0x3f
86 #define QEDE_PKT_TYPE_IPV4 0x1
87 #define QEDE_PKT_TYPE_IPV6 0x2
88 #define QEDE_PKT_TYPE_IPV4_TCP 0x5
89 #define QEDE_PKT_TYPE_IPV6_TCP 0x6
90 #define QEDE_PKT_TYPE_IPV4_UDP 0x9
91 #define QEDE_PKT_TYPE_IPV6_UDP 0xa
93 /* For frag pkts, corresponding IP bits is set */
94 #define QEDE_PKT_TYPE_IPV4_FRAG 0x11
95 #define QEDE_PKT_TYPE_IPV6_FRAG 0x12
97 #define QEDE_PKT_TYPE_IPV4_VLAN 0x21
98 #define QEDE_PKT_TYPE_IPV6_VLAN 0x22
99 #define QEDE_PKT_TYPE_IPV4_TCP_VLAN 0x25
100 #define QEDE_PKT_TYPE_IPV6_TCP_VLAN 0x26
101 #define QEDE_PKT_TYPE_IPV4_UDP_VLAN 0x29
102 #define QEDE_PKT_TYPE_IPV6_UDP_VLAN 0x2a
104 #define QEDE_PKT_TYPE_IPV4_VLAN_FRAG 0x31
105 #define QEDE_PKT_TYPE_IPV6_VLAN_FRAG 0x32
107 /* Macros for tunneled packets with next protocol lkup table */
108 #define QEDE_PKT_TYPE_TUNN_GENEVE 0x1
109 #define QEDE_PKT_TYPE_TUNN_GRE 0x2
110 #define QEDE_PKT_TYPE_TUNN_VXLAN 0x3
112 /* Bit 2 is don't care bit */
113 #define QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE 0x9
114 #define QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE 0xa
115 #define QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN 0xb
117 #define QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE 0xd
118 #define QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE 0xe
119 #define QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN 0xf
122 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE 0x11
123 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE 0x12
124 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN 0x13
126 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE 0x15
127 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE 0x16
128 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN 0x17
131 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE 0x19
132 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE 0x1a
133 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN 0x1b
135 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE 0x1d
136 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE 0x1e
137 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN 0x1f
139 #define QEDE_PKT_TYPE_TUNN_MAX_TYPE 0x20 /* 2^5 */
141 #define QEDE_TX_CSUM_OFFLOAD_MASK (PKT_TX_IP_CKSUM | \
144 PKT_TX_OUTER_IP_CKSUM | \
147 #define QEDE_TX_OFFLOAD_MASK (QEDE_TX_CSUM_OFFLOAD_MASK | \
149 PKT_TX_TUNNEL_VXLAN | \
150 PKT_TX_TUNNEL_GENEVE | \
151 PKT_TX_TUNNEL_MPLSINUDP | \
154 #define QEDE_TX_OFFLOAD_NOTSUP_MASK \
155 (PKT_TX_OFFLOAD_MASK ^ QEDE_TX_OFFLOAD_MASK)
158 * RX BD descriptor ring
160 struct qede_rx_entry {
161 struct rte_mbuf *mbuf;
162 uint32_t page_offset;
163 /* allows expansion .. */
166 /* TPA related structures */
167 struct qede_agg_info {
168 struct rte_mbuf *tpa_head; /* Pointer to first TPA segment */
169 struct rte_mbuf *tpa_tail; /* Pointer to last TPA segment */
173 * Structure associated with each RX queue.
175 struct qede_rx_queue {
176 struct rte_mempool *mb_pool;
177 struct ecore_chain rx_bd_ring;
178 struct ecore_chain rx_comp_ring;
179 uint16_t *hw_cons_ptr;
180 void OSAL_IOMEM *hw_rxq_prod_addr;
181 struct qede_rx_entry *sw_rx_ring;
182 struct ecore_sb_info *sb_info;
188 uint16_t rx_buf_size;
191 uint64_t rx_hw_errors;
192 uint64_t rx_alloc_errors;
193 struct qede_agg_info tpa_info[ETH_TPA_MAX_AGGS_NUM];
194 struct qede_dev *qdev;
199 * TX BD descriptor ring
201 struct qede_tx_entry {
202 struct rte_mbuf *mbuf;
207 struct eth_db_data data;
211 struct qede_tx_queue {
212 struct ecore_chain tx_pbl;
213 struct qede_tx_entry *sw_tx_ring;
215 uint16_t nb_tx_avail;
216 uint16_t tx_free_thresh;
218 uint16_t *hw_cons_ptr;
221 void OSAL_IOMEM *doorbell_addr;
222 volatile union db_prod tx_db;
226 struct qede_dev *qdev;
230 struct qede_fastpath {
231 struct ecore_sb_info *sb_info;
232 struct qede_rx_queue *rxq;
233 struct qede_tx_queue *txq;
237 * RX/TX function prototypes
239 int qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
240 uint16_t nb_desc, unsigned int socket_id,
241 const struct rte_eth_rxconf *rx_conf,
242 struct rte_mempool *mp);
244 int qede_tx_queue_setup(struct rte_eth_dev *dev,
247 unsigned int socket_id,
248 const struct rte_eth_txconf *tx_conf);
250 void qede_rx_queue_release(void *rx_queue);
252 void qede_tx_queue_release(void *tx_queue);
254 uint16_t qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
257 uint16_t qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
260 uint16_t qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts,
263 uint16_t qede_rxtx_pkts_dummy(void *p_rxq,
264 struct rte_mbuf **pkts,
267 int qede_start_queues(struct rte_eth_dev *eth_dev);
269 void qede_stop_queues(struct rte_eth_dev *eth_dev);
271 /* Fastpath resource alloc/dealloc helpers */
272 int qede_alloc_fp_resc(struct qede_dev *qdev);
274 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev);
276 #endif /* _QEDE_RXTX_H_ */