2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
13 #include "qede_ethdev.h"
15 /* Ring Descriptors */
16 #define RX_RING_SIZE_POW 16 /* 64K */
17 #define RX_RING_SIZE (1ULL << RX_RING_SIZE_POW)
18 #define NUM_RX_BDS_MAX (RX_RING_SIZE - 1)
19 #define NUM_RX_BDS_MIN 128
20 #define NUM_RX_BDS_DEF NUM_RX_BDS_MAX
21 #define NUM_RX_BDS(q) (q->nb_rx_desc - 1)
23 #define TX_RING_SIZE_POW 16 /* 64K */
24 #define TX_RING_SIZE (1ULL << TX_RING_SIZE_POW)
25 #define NUM_TX_BDS_MAX (TX_RING_SIZE - 1)
26 #define NUM_TX_BDS_MIN 128
27 #define NUM_TX_BDS_DEF NUM_TX_BDS_MAX
28 #define NUM_TX_BDS(q) (q->nb_tx_desc - 1)
30 #define TX_CONS(txq) (txq->sw_tx_cons & NUM_TX_BDS(txq))
31 #define TX_PROD(txq) (txq->sw_tx_prod & NUM_TX_BDS(txq))
33 #define QEDE_DEFAULT_TX_FREE_THRESH 32
35 #define QEDE_CSUM_ERROR (1 << 0)
36 #define QEDE_CSUM_UNNECESSARY (1 << 1)
37 #define QEDE_TUNN_CSUM_UNNECESSARY (1 << 2)
39 #define QEDE_BD_SET_ADDR_LEN(bd, maddr, len) \
41 (bd)->addr.hi = rte_cpu_to_le_32(U64_HI(maddr)); \
42 (bd)->addr.lo = rte_cpu_to_le_32(U64_LO(maddr)); \
43 (bd)->nbytes = rte_cpu_to_le_16(len); \
46 #define CQE_HAS_VLAN(flags) \
47 ((flags) & (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK \
48 << PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT))
50 #define CQE_HAS_OUTER_VLAN(flags) \
51 ((flags) & (PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK \
52 << PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT))
54 #define QEDE_MIN_RX_BUFF_SIZE (1024)
55 #define QEDE_VLAN_TAG_SIZE (4)
56 #define QEDE_LLC_SNAP_HDR_LEN (8)
58 /* Max supported alignment is 256 (8 shift)
59 * minimal alignment shift 6 is optimal for 57xxx HW performance
61 #define QEDE_L1_CACHE_SHIFT 6
62 #define QEDE_RX_ALIGN_SHIFT (RTE_MAX(6, RTE_MIN(8, QEDE_L1_CACHE_SHIFT)))
63 #define QEDE_FW_RX_ALIGN_END (1UL << QEDE_RX_ALIGN_SHIFT)
64 #define QEDE_CEIL_TO_CACHE_LINE_SIZE(n) (((n) + (QEDE_FW_RX_ALIGN_END - 1)) & \
65 ~(QEDE_FW_RX_ALIGN_END - 1))
66 /* Note: QEDE_LLC_SNAP_HDR_LEN is optional */
67 #define QEDE_ETH_OVERHEAD ((ETHER_HDR_LEN) + ((2 * QEDE_VLAN_TAG_SIZE)) \
68 + (QEDE_LLC_SNAP_HDR_LEN))
70 #define QEDE_RSS_OFFLOAD_ALL (ETH_RSS_IPV4 |\
71 ETH_RSS_NONFRAG_IPV4_TCP |\
72 ETH_RSS_NONFRAG_IPV4_UDP |\
74 ETH_RSS_NONFRAG_IPV6_TCP |\
75 ETH_RSS_NONFRAG_IPV6_UDP |\
78 #define QEDE_TXQ_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS)
80 #define for_each_rss(i) for (i = 0; i < qdev->num_rx_queues; i++)
81 #define for_each_tss(i) for (i = 0; i < qdev->num_tx_queues; i++)
82 #define QEDE_RXTX_MAX(qdev) \
83 (RTE_MAX(QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev)))
85 /* Macros for non-tunnel packet types lkup table */
86 #define QEDE_PKT_TYPE_UNKNOWN 0x0
87 #define QEDE_PKT_TYPE_MAX 0xf
88 #define QEDE_PKT_TYPE_IPV4 0x1
89 #define QEDE_PKT_TYPE_IPV6 0x2
90 #define QEDE_PKT_TYPE_IPV4_TCP 0x5
91 #define QEDE_PKT_TYPE_IPV6_TCP 0x6
92 #define QEDE_PKT_TYPE_IPV4_UDP 0x9
93 #define QEDE_PKT_TYPE_IPV6_UDP 0xa
95 /* Macros for tunneled packets with next protocol lkup table */
96 #define QEDE_PKT_TYPE_TUNN_GENEVE 0x1
97 #define QEDE_PKT_TYPE_TUNN_GRE 0x2
98 #define QEDE_PKT_TYPE_TUNN_VXLAN 0x3
100 /* Bit 2 is don't care bit */
101 #define QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE 0x9
102 #define QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE 0xa
103 #define QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN 0xb
105 #define QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE 0xd
106 #define QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE 0xe
107 #define QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN 0xf
110 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE 0x11
111 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE 0x12
112 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN 0x13
114 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE 0x15
115 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE 0x16
116 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN 0x17
119 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE 0x19
120 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE 0x1a
121 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN 0x1b
123 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE 0x1d
124 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE 0x1e
125 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN 0x1f
127 #define QEDE_PKT_TYPE_TUNN_MAX_TYPE 0x20 /* 2^5 */
129 #define QEDE_TX_CSUM_OFFLOAD_MASK (PKT_TX_IP_CKSUM | \
132 PKT_TX_OUTER_IP_CKSUM | \
135 #define QEDE_TX_OFFLOAD_MASK (QEDE_TX_CSUM_OFFLOAD_MASK | \
140 #define QEDE_TX_OFFLOAD_NOTSUP_MASK \
141 (PKT_TX_OFFLOAD_MASK ^ QEDE_TX_OFFLOAD_MASK)
144 * RX BD descriptor ring
146 struct qede_rx_entry {
147 struct rte_mbuf *mbuf;
148 uint32_t page_offset;
149 /* allows expansion .. */
152 /* TPA related structures */
153 struct qede_agg_info {
154 struct rte_mbuf *tpa_head; /* Pointer to first TPA segment */
155 struct rte_mbuf *tpa_tail; /* Pointer to last TPA segment */
159 * Structure associated with each RX queue.
161 struct qede_rx_queue {
162 struct rte_mempool *mb_pool;
163 struct ecore_chain rx_bd_ring;
164 struct ecore_chain rx_comp_ring;
165 uint16_t *hw_cons_ptr;
166 void OSAL_IOMEM *hw_rxq_prod_addr;
167 struct qede_rx_entry *sw_rx_ring;
168 struct ecore_sb_info *sb_info;
174 uint16_t rx_buf_size;
177 uint64_t rx_hw_errors;
178 uint64_t rx_alloc_errors;
179 struct qede_agg_info tpa_info[ETH_TPA_MAX_AGGS_NUM];
180 struct qede_dev *qdev;
185 * TX BD descriptor ring
187 struct qede_tx_entry {
188 struct rte_mbuf *mbuf;
193 struct eth_db_data data;
197 struct qede_tx_queue {
198 struct ecore_chain tx_pbl;
199 struct qede_tx_entry *sw_tx_ring;
201 uint16_t nb_tx_avail;
202 uint16_t tx_free_thresh;
204 uint16_t *hw_cons_ptr;
207 void OSAL_IOMEM *doorbell_addr;
208 volatile union db_prod tx_db;
212 struct qede_dev *qdev;
216 struct qede_fastpath {
217 struct ecore_sb_info *sb_info;
218 struct qede_rx_queue *rxq;
219 struct qede_tx_queue *txq;
223 * RX/TX function prototypes
225 int qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
226 uint16_t nb_desc, unsigned int socket_id,
227 const struct rte_eth_rxconf *rx_conf,
228 struct rte_mempool *mp);
230 int qede_tx_queue_setup(struct rte_eth_dev *dev,
233 unsigned int socket_id,
234 const struct rte_eth_txconf *tx_conf);
236 void qede_rx_queue_release(void *rx_queue);
238 void qede_tx_queue_release(void *tx_queue);
240 uint16_t qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
243 uint16_t qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
246 uint16_t qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts,
249 uint16_t qede_rxtx_pkts_dummy(void *p_rxq,
250 struct rte_mbuf **pkts,
253 int qede_start_queues(struct rte_eth_dev *eth_dev);
255 void qede_stop_queues(struct rte_eth_dev *eth_dev);
257 /* Fastpath resource alloc/dealloc helpers */
258 int qede_alloc_fp_resc(struct qede_dev *qdev);
260 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev);
262 #endif /* _QEDE_RXTX_H_ */