2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
13 #include "qede_ethdev.h"
15 /* Ring Descriptors */
16 #define RX_RING_SIZE_POW 16 /* 64K */
17 #define RX_RING_SIZE (1ULL << RX_RING_SIZE_POW)
18 #define NUM_RX_BDS_MAX (RX_RING_SIZE - 1)
19 #define NUM_RX_BDS_MIN 128
20 #define NUM_RX_BDS_DEF NUM_RX_BDS_MAX
21 #define NUM_RX_BDS(q) (q->nb_rx_desc - 1)
23 #define TX_RING_SIZE_POW 16 /* 64K */
24 #define TX_RING_SIZE (1ULL << TX_RING_SIZE_POW)
25 #define NUM_TX_BDS_MAX (TX_RING_SIZE - 1)
26 #define NUM_TX_BDS_MIN 128
27 #define NUM_TX_BDS_DEF NUM_TX_BDS_MAX
28 #define NUM_TX_BDS(q) (q->nb_tx_desc - 1)
30 #define TX_CONS(txq) (txq->sw_tx_cons & NUM_TX_BDS(txq))
31 #define TX_PROD(txq) (txq->sw_tx_prod & NUM_TX_BDS(txq))
33 #define QEDE_DEFAULT_TX_FREE_THRESH 32
35 #define QEDE_CSUM_ERROR (1 << 0)
36 #define QEDE_CSUM_UNNECESSARY (1 << 1)
37 #define QEDE_TUNN_CSUM_UNNECESSARY (1 << 2)
39 #define QEDE_BD_SET_ADDR_LEN(bd, maddr, len) \
41 (bd)->addr.hi = rte_cpu_to_le_32(U64_HI(maddr)); \
42 (bd)->addr.lo = rte_cpu_to_le_32(U64_LO(maddr)); \
43 (bd)->nbytes = rte_cpu_to_le_16(len); \
44 /* FW 8.10.x specific change */ \
45 (bd)->data.bitfields = ((len) & \
46 ETH_TX_DATA_1ST_BD_PKT_LEN_MASK) \
47 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT; \
50 #define CQE_HAS_VLAN(flags) \
51 ((flags) & (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK \
52 << PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT))
54 #define CQE_HAS_OUTER_VLAN(flags) \
55 ((flags) & (PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK \
56 << PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT))
58 /* Max supported alignment is 256 (8 shift)
59 * minimal alignment shift 6 is optimal for 57xxx HW performance
61 #define QEDE_L1_CACHE_SHIFT 6
62 #define QEDE_RX_ALIGN_SHIFT (RTE_MAX(6, RTE_MIN(8, QEDE_L1_CACHE_SHIFT)))
63 #define QEDE_FW_RX_ALIGN_END (1UL << QEDE_RX_ALIGN_SHIFT)
65 #define QEDE_ETH_OVERHEAD (ETHER_HDR_LEN + 8 + 8 + QEDE_FW_RX_ALIGN_END)
67 #define QEDE_RSS_OFFLOAD_ALL (ETH_RSS_IPV4 |\
68 ETH_RSS_NONFRAG_IPV4_TCP |\
69 ETH_RSS_NONFRAG_IPV4_UDP |\
71 ETH_RSS_NONFRAG_IPV6_TCP |\
72 ETH_RSS_NONFRAG_IPV6_UDP |\
75 #define QEDE_TXQ_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS)
79 #define for_each_queue(i) for (i = 0; i < qdev->num_queues; i++)
82 /* Macros for non-tunnel packet types lkup table */
83 #define QEDE_PKT_TYPE_UNKNOWN 0x0
84 #define QEDE_PKT_TYPE_MAX 0xf
85 #define QEDE_PKT_TYPE_IPV4 0x1
86 #define QEDE_PKT_TYPE_IPV6 0x2
87 #define QEDE_PKT_TYPE_IPV4_TCP 0x5
88 #define QEDE_PKT_TYPE_IPV6_TCP 0x6
89 #define QEDE_PKT_TYPE_IPV4_UDP 0x9
90 #define QEDE_PKT_TYPE_IPV6_UDP 0xa
92 /* Macros for tunneled packets with next protocol lkup table */
93 #define QEDE_PKT_TYPE_TUNN_GENEVE 0x1
94 #define QEDE_PKT_TYPE_TUNN_GRE 0x2
95 #define QEDE_PKT_TYPE_TUNN_VXLAN 0x3
97 /* Bit 2 is don't care bit */
98 #define QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE 0x9
99 #define QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE 0xa
100 #define QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN 0xb
102 #define QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE 0xd
103 #define QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE 0xe
104 #define QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN 0xf
107 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE 0x11
108 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE 0x12
109 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN 0x13
111 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE 0x15
112 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE 0x16
113 #define QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN 0x17
116 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE 0x19
117 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE 0x1a
118 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN 0x1b
120 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE 0x1d
121 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE 0x1e
122 #define QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN 0x1f
124 #define QEDE_PKT_TYPE_TUNN_MAX_TYPE 0x20 /* 2^5 */
127 * RX BD descriptor ring
129 struct qede_rx_entry {
130 struct rte_mbuf *mbuf;
131 uint32_t page_offset;
132 /* allows expansion .. */
136 * Structure associated with each RX queue.
138 struct qede_rx_queue {
139 struct rte_mempool *mb_pool;
140 struct ecore_chain rx_bd_ring;
141 struct ecore_chain rx_comp_ring;
142 uint16_t *hw_cons_ptr;
143 void OSAL_IOMEM *hw_rxq_prod_addr;
144 struct qede_rx_entry *sw_rx_ring;
150 uint16_t rx_buf_size;
153 uint64_t rx_hw_errors;
154 uint64_t rx_alloc_errors;
155 struct qede_dev *qdev;
159 * TX BD descriptor ring
161 struct qede_tx_entry {
162 struct rte_mbuf *mbuf;
167 struct eth_db_data data;
171 struct qede_tx_queue {
172 struct ecore_chain tx_pbl;
173 struct qede_tx_entry *sw_tx_ring;
175 uint16_t nb_tx_avail;
176 uint16_t tx_free_thresh;
178 uint16_t *hw_cons_ptr;
181 void OSAL_IOMEM *doorbell_addr;
182 volatile union db_prod tx_db;
186 struct qede_dev *qdev;
189 struct qede_fastpath {
190 struct qede_dev *qdev;
193 struct ecore_sb_info *sb_info;
194 struct qede_rx_queue *rxq;
195 struct qede_tx_queue *txqs[MAX_NUM_TC];
200 * RX/TX function prototypes
202 int qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
203 uint16_t nb_desc, unsigned int socket_id,
204 const struct rte_eth_rxconf *rx_conf,
205 struct rte_mempool *mp);
207 int qede_tx_queue_setup(struct rte_eth_dev *dev,
210 unsigned int socket_id,
211 const struct rte_eth_txconf *tx_conf);
213 void qede_rx_queue_release(void *rx_queue);
215 void qede_tx_queue_release(void *tx_queue);
217 int qede_dev_start(struct rte_eth_dev *eth_dev);
219 void qede_dev_stop(struct rte_eth_dev *eth_dev);
221 int qede_reset_fp_rings(struct qede_dev *qdev);
223 void qede_free_fp_arrays(struct qede_dev *qdev);
225 void qede_free_mem_load(struct rte_eth_dev *eth_dev);
227 uint16_t qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
230 uint16_t qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts,
233 /* Fastpath resource alloc/dealloc helpers */
234 int qede_alloc_fp_resc(struct qede_dev *qdev);
236 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev);
238 #endif /* _QEDE_RXTX_H_ */