1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
9 #if EFSYS_OPT_MON_STATS
13 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
16 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
18 (_eep)->ee_stat[_stat]++; \
19 _NOTE(CONSTANTCONDITION) \
22 #define EFX_EV_QSTAT_INCR(_eep, _stat)
26 * Non-interrupting event queue requires interrrupting event queue to
27 * refer to for wake-up events even if wake ups are never used.
28 * It could be even non-allocated event queue.
30 #define EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX (0)
32 static __checkReturn boolean_t
35 __in efx_qword_t *eqp,
36 __in const efx_ev_callbacks_t *eecp,
39 static __checkReturn boolean_t
42 __in efx_qword_t *eqp,
43 __in const efx_ev_callbacks_t *eecp,
46 static __checkReturn boolean_t
49 __in efx_qword_t *eqp,
50 __in const efx_ev_callbacks_t *eecp,
53 static __checkReturn boolean_t
56 __in efx_qword_t *eqp,
57 __in const efx_ev_callbacks_t *eecp,
60 static __checkReturn boolean_t
63 __in efx_qword_t *eqp,
64 __in const efx_ev_callbacks_t *eecp,
68 static __checkReturn efx_rc_t
71 __in uint32_t instance,
73 __in uint32_t timer_ns)
76 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_EVQ_TMR_IN_LEN,
77 MC_CMD_SET_EVQ_TMR_OUT_LEN);
80 req.emr_cmd = MC_CMD_SET_EVQ_TMR;
81 req.emr_in_buf = payload;
82 req.emr_in_length = MC_CMD_SET_EVQ_TMR_IN_LEN;
83 req.emr_out_buf = payload;
84 req.emr_out_length = MC_CMD_SET_EVQ_TMR_OUT_LEN;
86 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_INSTANCE, instance);
87 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, timer_ns);
88 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, timer_ns);
89 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_MODE, mode);
91 efx_mcdi_execute(enp, &req);
93 if (req.emr_rc != 0) {
98 if (req.emr_out_length_used < MC_CMD_SET_EVQ_TMR_OUT_LEN) {
108 EFSYS_PROBE1(fail1, efx_rc_t, rc);
113 static __checkReturn efx_rc_t
116 __in unsigned int instance,
117 __in efsys_mem_t *esmp,
122 __in boolean_t low_latency)
125 EFX_MCDI_DECLARE_BUF(payload,
126 MC_CMD_INIT_EVQ_IN_LEN(EFX_EVQ_NBUFS(EF10_EVQ_MAXNEVS)),
127 MC_CMD_INIT_EVQ_OUT_LEN);
128 efx_qword_t *dma_addr;
132 boolean_t interrupting;
136 npages = EFX_EVQ_NBUFS(nevs);
137 if (MC_CMD_INIT_EVQ_IN_LEN(npages) > MC_CMD_INIT_EVQ_IN_LENMAX) {
142 req.emr_cmd = MC_CMD_INIT_EVQ;
143 req.emr_in_buf = payload;
144 req.emr_in_length = MC_CMD_INIT_EVQ_IN_LEN(npages);
145 req.emr_out_buf = payload;
146 req.emr_out_length = MC_CMD_INIT_EVQ_OUT_LEN;
148 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_SIZE, nevs);
149 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_INSTANCE, instance);
150 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_IRQ_NUM, irq);
152 interrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
153 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
156 * On Huntington RX and TX event batching can only be requested together
157 * (even if the datapath firmware doesn't actually support RX
158 * batching). If event cut through is enabled no RX batching will occur.
160 * So always enable RX and TX event batching, and enable event cut
161 * through if we want low latency operation.
163 switch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {
164 case EFX_EVQ_FLAGS_TYPE_AUTO:
165 ev_cut_through = low_latency ? 1 : 0;
167 case EFX_EVQ_FLAGS_TYPE_THROUGHPUT:
170 case EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:
177 MCDI_IN_POPULATE_DWORD_6(req, INIT_EVQ_IN_FLAGS,
178 INIT_EVQ_IN_FLAG_INTERRUPTING, interrupting,
179 INIT_EVQ_IN_FLAG_RPTR_DOS, 0,
180 INIT_EVQ_IN_FLAG_INT_ARMD, 0,
181 INIT_EVQ_IN_FLAG_CUT_THRU, ev_cut_through,
182 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
183 INIT_EVQ_IN_FLAG_TX_MERGE, 1);
185 /* If the value is zero then disable the timer */
187 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
188 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
189 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, 0);
190 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, 0);
194 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
197 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
198 MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF);
199 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, ticks);
200 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, ticks);
203 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_MODE,
204 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
205 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_THRSHLD, 0);
207 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_IN_DMA_ADDR);
208 addr = EFSYS_MEM_ADDR(esmp);
210 for (i = 0; i < npages; i++) {
211 EFX_POPULATE_QWORD_2(*dma_addr,
212 EFX_DWORD_1, (uint32_t)(addr >> 32),
213 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
216 addr += EFX_BUF_SIZE;
219 efx_mcdi_execute(enp, &req);
221 if (req.emr_rc != 0) {
226 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_OUT_LEN) {
231 /* NOTE: ignore the returned IRQ param as firmware does not set it. */
244 EFSYS_PROBE1(fail1, efx_rc_t, rc);
250 static __checkReturn efx_rc_t
251 efx_mcdi_init_evq_v2(
253 __in unsigned int instance,
254 __in efsys_mem_t *esmp,
261 EFX_MCDI_DECLARE_BUF(payload,
262 MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_EVQ_NBUFS(EF10_EVQ_MAXNEVS)),
263 MC_CMD_INIT_EVQ_V2_OUT_LEN);
264 boolean_t interrupting;
265 unsigned int evq_type;
266 efx_qword_t *dma_addr;
272 npages = EFX_EVQ_NBUFS(nevs);
273 if (MC_CMD_INIT_EVQ_V2_IN_LEN(npages) > MC_CMD_INIT_EVQ_V2_IN_LENMAX) {
278 req.emr_cmd = MC_CMD_INIT_EVQ;
279 req.emr_in_buf = payload;
280 req.emr_in_length = MC_CMD_INIT_EVQ_V2_IN_LEN(npages);
281 req.emr_out_buf = payload;
282 req.emr_out_length = MC_CMD_INIT_EVQ_V2_OUT_LEN;
284 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_SIZE, nevs);
285 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_INSTANCE, instance);
286 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_IRQ_NUM, irq);
288 interrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
289 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
291 switch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {
292 case EFX_EVQ_FLAGS_TYPE_AUTO:
293 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO;
295 case EFX_EVQ_FLAGS_TYPE_THROUGHPUT:
296 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT;
298 case EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:
299 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY;
305 MCDI_IN_POPULATE_DWORD_4(req, INIT_EVQ_V2_IN_FLAGS,
306 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, interrupting,
307 INIT_EVQ_V2_IN_FLAG_RPTR_DOS, 0,
308 INIT_EVQ_V2_IN_FLAG_INT_ARMD, 0,
309 INIT_EVQ_V2_IN_FLAG_TYPE, evq_type);
311 /* If the value is zero then disable the timer */
313 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE,
314 MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS);
315 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, 0);
316 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, 0);
320 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
323 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE,
324 MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF);
325 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, ticks);
326 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, ticks);
329 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_MODE,
330 MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS);
331 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_THRSHLD, 0);
333 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_V2_IN_DMA_ADDR);
334 addr = EFSYS_MEM_ADDR(esmp);
336 for (i = 0; i < npages; i++) {
337 EFX_POPULATE_QWORD_2(*dma_addr,
338 EFX_DWORD_1, (uint32_t)(addr >> 32),
339 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
342 addr += EFX_BUF_SIZE;
345 efx_mcdi_execute(enp, &req);
347 if (req.emr_rc != 0) {
352 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_V2_OUT_LEN) {
357 /* NOTE: ignore the returned IRQ param as firmware does not set it. */
359 EFSYS_PROBE1(mcdi_evq_flags, uint32_t,
360 MCDI_OUT_DWORD(req, INIT_EVQ_V2_OUT_FLAGS));
373 EFSYS_PROBE1(fail1, efx_rc_t, rc);
378 static __checkReturn efx_rc_t
381 __in uint32_t instance)
384 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FINI_EVQ_IN_LEN,
385 MC_CMD_FINI_EVQ_OUT_LEN);
388 req.emr_cmd = MC_CMD_FINI_EVQ;
389 req.emr_in_buf = payload;
390 req.emr_in_length = MC_CMD_FINI_EVQ_IN_LEN;
391 req.emr_out_buf = payload;
392 req.emr_out_length = MC_CMD_FINI_EVQ_OUT_LEN;
394 MCDI_IN_SET_DWORD(req, FINI_EVQ_IN_INSTANCE, instance);
396 efx_mcdi_execute_quiet(enp, &req);
398 if (req.emr_rc != 0) {
407 * EALREADY is not an error, but indicates that the MC has rebooted and
408 * that the EVQ has already been destroyed.
411 EFSYS_PROBE1(fail1, efx_rc_t, rc);
418 __checkReturn efx_rc_t
422 _NOTE(ARGUNUSED(enp))
430 _NOTE(ARGUNUSED(enp))
433 __checkReturn efx_rc_t
436 __in unsigned int index,
437 __in efsys_mem_t *esmp,
444 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
448 _NOTE(ARGUNUSED(id)) /* buftbl id managed by MC */
449 EFSYS_ASSERT(ISP2(encp->enc_evq_max_nevs));
450 EFSYS_ASSERT(ISP2(encp->enc_evq_min_nevs));
453 (ndescs < encp->enc_evq_min_nevs) ||
454 (ndescs > encp->enc_evq_max_nevs)) {
459 if (index >= encp->enc_evq_limit) {
464 if (us > encp->enc_evq_timer_max_us) {
469 /* Set up the handler table */
470 eep->ee_rx = ef10_ev_rx;
471 eep->ee_tx = ef10_ev_tx;
472 eep->ee_driver = ef10_ev_driver;
473 eep->ee_drv_gen = ef10_ev_drv_gen;
474 eep->ee_mcdi = ef10_ev_mcdi;
476 /* Set up the event queue */
477 /* INIT_EVQ expects function-relative vector number */
478 if ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
479 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT) {
481 } else if (index == EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX) {
483 flags = (flags & ~EFX_EVQ_FLAGS_NOTIFY_MASK) |
484 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT;
486 irq = EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX;
490 * Interrupts may be raised for events immediately after the queue is
491 * created. See bug58606.
494 if (encp->enc_init_evq_v2_supported) {
496 * On Medford the low latency license is required to enable RX
497 * and event cut through and to disable RX batching. If event
498 * queue type in flags is auto, we let the firmware decide the
499 * settings to use. If the adapter has a low latency license,
500 * it will choose the best settings for low latency, otherwise
501 * it will choose the best settings for throughput.
503 rc = efx_mcdi_init_evq_v2(enp, index, esmp, ndescs, irq, us,
509 * On Huntington we need to specify the settings to use.
510 * If event queue type in flags is auto, we favour throughput
511 * if the adapter is running virtualization supporting firmware
512 * (i.e. the full featured firmware variant)
513 * and latency otherwise. The Ethernet Virtual Bridging
514 * capability is used to make this decision. (Note though that
515 * the low latency firmware variant is also best for
516 * throughput and corresponding type should be specified
519 boolean_t low_latency = encp->enc_datapath_cap_evb ? 0 : 1;
520 rc = efx_mcdi_init_evq(enp, index, esmp, ndescs, irq, us, flags,
537 EFSYS_PROBE1(fail1, efx_rc_t, rc);
546 efx_nic_t *enp = eep->ee_enp;
548 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
549 enp->en_family == EFX_FAMILY_MEDFORD ||
550 enp->en_family == EFX_FAMILY_MEDFORD2);
552 (void) efx_mcdi_fini_evq(enp, eep->ee_index);
555 __checkReturn efx_rc_t
558 __in unsigned int count)
560 efx_nic_t *enp = eep->ee_enp;
564 rptr = count & eep->ee_mask;
566 if (enp->en_nic_cfg.enc_bug35388_workaround) {
567 EFX_STATIC_ASSERT(EF10_EVQ_MINNEVS >
568 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
569 EFX_STATIC_ASSERT(EF10_EVQ_MAXNEVS <
570 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
572 EFX_POPULATE_DWORD_2(dword,
573 ERF_DD_EVQ_IND_RPTR_FLAGS,
574 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
576 (rptr >> ERF_DD_EVQ_IND_RPTR_WIDTH));
577 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
580 EFX_POPULATE_DWORD_2(dword,
581 ERF_DD_EVQ_IND_RPTR_FLAGS,
582 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
584 rptr & ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
585 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
588 EFX_POPULATE_DWORD_1(dword, ERF_DZ_EVQ_RPTR, rptr);
589 EFX_BAR_VI_WRITED(enp, ER_DZ_EVQ_RPTR_REG, eep->ee_index,
596 static __checkReturn efx_rc_t
597 efx_mcdi_driver_event(
600 __in efx_qword_t data)
603 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_DRIVER_EVENT_IN_LEN,
604 MC_CMD_DRIVER_EVENT_OUT_LEN);
607 req.emr_cmd = MC_CMD_DRIVER_EVENT;
608 req.emr_in_buf = payload;
609 req.emr_in_length = MC_CMD_DRIVER_EVENT_IN_LEN;
610 req.emr_out_buf = payload;
611 req.emr_out_length = MC_CMD_DRIVER_EVENT_OUT_LEN;
613 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_EVQ, evq);
615 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_LO,
616 EFX_QWORD_FIELD(data, EFX_DWORD_0));
617 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_HI,
618 EFX_QWORD_FIELD(data, EFX_DWORD_1));
620 efx_mcdi_execute(enp, &req);
622 if (req.emr_rc != 0) {
630 EFSYS_PROBE1(fail1, efx_rc_t, rc);
640 efx_nic_t *enp = eep->ee_enp;
643 EFX_POPULATE_QWORD_3(event,
644 ESF_DZ_DRV_CODE, ESE_DZ_EV_CODE_DRV_GEN_EV,
645 ESF_DZ_DRV_SUB_CODE, 0,
646 ESF_DZ_DRV_SUB_DATA_DW0, (uint32_t)data);
648 (void) efx_mcdi_driver_event(enp, eep->ee_index, event);
651 __checkReturn efx_rc_t
654 __in unsigned int us)
656 efx_nic_t *enp = eep->ee_enp;
657 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
662 /* Check that hardware and MCDI use the same timer MODE values */
663 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_DIS ==
664 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS);
665 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_IMMED_START ==
666 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START);
667 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_TRIG_START ==
668 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START);
669 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_INT_HLDOFF ==
670 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF);
672 if (us > encp->enc_evq_timer_max_us) {
677 /* If the value is zero then disable the timer */
679 mode = FFE_CZ_TIMER_MODE_DIS;
681 mode = FFE_CZ_TIMER_MODE_INT_HLDOFF;
684 if (encp->enc_bug61265_workaround) {
685 uint32_t ns = us * 1000;
687 rc = efx_mcdi_set_evq_tmr(enp, eep->ee_index, mode, ns);
693 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
696 if (encp->enc_bug35388_workaround) {
697 EFX_POPULATE_DWORD_3(dword,
698 ERF_DD_EVQ_IND_TIMER_FLAGS,
699 EFE_DD_EVQ_IND_TIMER_FLAGS,
700 ERF_DD_EVQ_IND_TIMER_MODE, mode,
701 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
702 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT,
703 eep->ee_index, &dword, 0);
706 * NOTE: The TMR_REL field introduced in Medford2 is
707 * ignored on earlier EF10 controllers. See bug66418
708 * comment 9 for details.
710 EFX_POPULATE_DWORD_3(dword,
711 ERF_DZ_TC_TIMER_MODE, mode,
712 ERF_DZ_TC_TIMER_VAL, ticks,
713 ERF_FZ_TC_TMR_REL_VAL, ticks);
714 EFX_BAR_VI_WRITED(enp, ER_DZ_EVQ_TMR_REG,
715 eep->ee_index, &dword, 0);
726 EFSYS_PROBE1(fail1, efx_rc_t, rc);
734 ef10_ev_qstats_update(
736 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
740 for (id = 0; id < EV_NQSTATS; id++) {
741 efsys_stat_t *essp = &stat[id];
743 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
744 eep->ee_stat[id] = 0;
747 #endif /* EFSYS_OPT_QSTATS */
749 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
751 static __checkReturn boolean_t
752 ef10_ev_rx_packed_stream(
754 __in efx_qword_t *eqp,
755 __in const efx_ev_callbacks_t *eecp,
759 uint32_t pkt_count_lbits;
761 boolean_t should_abort;
762 efx_evq_rxq_state_t *eersp;
763 unsigned int pkt_count;
764 unsigned int current_id;
765 boolean_t new_buffer;
767 pkt_count_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
768 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
769 new_buffer = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_EV_ROTATE);
773 eersp = &eep->ee_rxq_state[label];
776 * RX_DSC_PTR_LBITS has least significant bits of the global
777 * (not per-buffer) packet counter. It is guaranteed that
778 * maximum number of completed packets fits in lbits-mask.
779 * So, modulo lbits-mask arithmetic should be used to calculate
780 * packet counter increment.
782 pkt_count = (pkt_count_lbits - eersp->eers_rx_stream_npackets) &
783 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
784 eersp->eers_rx_stream_npackets += pkt_count;
787 flags |= EFX_PKT_PACKED_STREAM_NEW_BUFFER;
788 #if EFSYS_OPT_RX_PACKED_STREAM
790 * If both packed stream and equal stride super-buffer
791 * modes are compiled in, in theory credits should be
792 * be maintained for packed stream only, but right now
793 * these modes are not distinguished in the event queue
794 * Rx queue state and it is OK to increment the counter
795 * regardless (it might be event cheaper than branching
796 * since neighbour structure member are updated as well).
798 eersp->eers_rx_packed_stream_credits++;
800 eersp->eers_rx_read_ptr++;
802 current_id = eersp->eers_rx_read_ptr & eersp->eers_rx_mask;
804 /* Check for errors that invalidate checksum and L3/L4 fields */
805 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TRUNC_ERR) != 0) {
806 /* RX frame truncated */
807 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
808 flags |= EFX_DISCARD;
811 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
812 /* Bad Ethernet frame CRC */
813 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
814 flags |= EFX_DISCARD;
818 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
819 flags |= EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE;
823 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR))
824 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
826 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR))
827 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
830 /* If we're not discarding the packet then it is ok */
831 if (~flags & EFX_DISCARD)
832 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
834 EFSYS_ASSERT(eecp->eec_rx_ps != NULL);
835 should_abort = eecp->eec_rx_ps(arg, label, current_id, pkt_count,
838 return (should_abort);
841 #endif /* EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER */
843 static __checkReturn boolean_t
846 __in efx_qword_t *eqp,
847 __in const efx_ev_callbacks_t *eecp,
850 efx_nic_t *enp = eep->ee_enp;
854 uint32_t eth_tag_class;
857 uint32_t next_read_lbits;
860 boolean_t should_abort;
861 efx_evq_rxq_state_t *eersp;
862 unsigned int desc_count;
863 unsigned int last_used_id;
865 EFX_EV_QSTAT_INCR(eep, EV_RX);
867 /* Discard events after RXQ/TXQ errors, or hardware not available */
868 if (enp->en_reset_flags &
869 (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR | EFX_RESET_HW_UNAVAIL))
872 /* Basic packet information */
873 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
874 eersp = &eep->ee_rxq_state[label];
876 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
878 * Packed stream events are very different,
879 * so handle them separately
881 if (eersp->eers_rx_packed_stream)
882 return (ef10_ev_rx_packed_stream(eep, eqp, eecp, arg));
885 size = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_BYTES);
886 cont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);
887 next_read_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
888 eth_tag_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ETH_TAG_CLASS);
889 mac_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS);
890 l3_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L3_CLASS);
893 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is only
894 * 2 bits wide on Medford2. Check it is safe to use the Medford2 field
895 * and values for all EF10 controllers.
897 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN == ESF_DE_RX_L4_CLASS_LBN);
898 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
899 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
900 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN == ESE_DE_L4_CLASS_UNKNOWN);
902 l4_class = EFX_QWORD_FIELD(*eqp, ESF_FZ_RX_L4_CLASS);
904 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DROP_EVENT) != 0) {
905 /* Drop this event */
912 * This may be part of a scattered frame, or it may be a
913 * truncated frame if scatter is disabled on this RXQ.
914 * Overlength frames can be received if e.g. a VF is configured
915 * for 1500 MTU but connected to a port set to 9000 MTU
917 * FIXME: There is not yet any driver that supports scatter on
918 * Huntington. Scatter support is required for OSX.
920 flags |= EFX_PKT_CONT;
923 if (mac_class == ESE_DZ_MAC_CLASS_UCAST)
924 flags |= EFX_PKT_UNICAST;
926 /* Increment the count of descriptors read */
927 desc_count = (next_read_lbits - eersp->eers_rx_read_ptr) &
928 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
929 eersp->eers_rx_read_ptr += desc_count;
932 * FIXME: add error checking to make sure this a batched event.
933 * This could also be an aborted scatter, see Bug36629.
935 if (desc_count > 1) {
936 EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);
937 flags |= EFX_PKT_PREFIX_LEN;
940 /* Calculate the index of the last descriptor consumed */
941 last_used_id = (eersp->eers_rx_read_ptr - 1) & eersp->eers_rx_mask;
943 /* Check for errors that invalidate checksum and L3/L4 fields */
944 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TRUNC_ERR) != 0) {
945 /* RX frame truncated */
946 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
947 flags |= EFX_DISCARD;
950 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
951 /* Bad Ethernet frame CRC */
952 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
953 flags |= EFX_DISCARD;
956 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
958 * Hardware parse failed, due to malformed headers
959 * or headers that are too long for the parser.
960 * Headers and checksums must be validated by the host.
962 /* TODO: EFX_EV_QSTAT_INCR(eep, EV_RX_PARSE_INCOMPLETE); */
966 if ((eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN1) ||
967 (eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN2)) {
968 flags |= EFX_PKT_VLAN_TAGGED;
972 case ESE_DZ_L3_CLASS_IP4:
973 case ESE_DZ_L3_CLASS_IP4_FRAG:
974 flags |= EFX_PKT_IPV4;
975 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR)) {
976 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
978 flags |= EFX_CKSUM_IPV4;
982 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
983 * only 2 bits wide on Medford2. Check it is safe to use the
984 * Medford2 field and values for all EF10 controllers.
986 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
987 ESF_DE_RX_L4_CLASS_LBN);
988 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
989 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
990 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
991 ESE_DE_L4_CLASS_UNKNOWN);
993 if (l4_class == ESE_FZ_L4_CLASS_TCP) {
994 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
995 flags |= EFX_PKT_TCP;
996 } else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
997 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
998 flags |= EFX_PKT_UDP;
1000 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
1004 case ESE_DZ_L3_CLASS_IP6:
1005 case ESE_DZ_L3_CLASS_IP6_FRAG:
1006 flags |= EFX_PKT_IPV6;
1009 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
1010 * only 2 bits wide on Medford2. Check it is safe to use the
1011 * Medford2 field and values for all EF10 controllers.
1013 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
1014 ESF_DE_RX_L4_CLASS_LBN);
1015 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
1016 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
1017 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
1018 ESE_DE_L4_CLASS_UNKNOWN);
1020 if (l4_class == ESE_FZ_L4_CLASS_TCP) {
1021 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
1022 flags |= EFX_PKT_TCP;
1023 } else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
1024 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
1025 flags |= EFX_PKT_UDP;
1027 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
1032 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
1036 if (flags & (EFX_PKT_TCP | EFX_PKT_UDP)) {
1037 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
1038 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
1040 flags |= EFX_CKSUM_TCPUDP;
1045 /* If we're not discarding the packet then it is ok */
1046 if (~flags & EFX_DISCARD)
1047 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
1049 EFSYS_ASSERT(eecp->eec_rx != NULL);
1050 should_abort = eecp->eec_rx(arg, label, last_used_id, size, flags);
1052 return (should_abort);
1055 static __checkReturn boolean_t
1057 __in efx_evq_t *eep,
1058 __in efx_qword_t *eqp,
1059 __in const efx_ev_callbacks_t *eecp,
1062 efx_nic_t *enp = eep->ee_enp;
1065 boolean_t should_abort;
1067 EFX_EV_QSTAT_INCR(eep, EV_TX);
1069 /* Discard events after RXQ/TXQ errors, or hardware not available */
1070 if (enp->en_reset_flags &
1071 (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR | EFX_RESET_HW_UNAVAIL))
1074 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DROP_EVENT) != 0) {
1075 /* Drop this event */
1079 /* Per-packet TX completion (was per-descriptor for Falcon/Siena) */
1080 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DESCR_INDX);
1081 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_QLABEL);
1083 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
1085 EFSYS_ASSERT(eecp->eec_tx != NULL);
1086 should_abort = eecp->eec_tx(arg, label, id);
1088 return (should_abort);
1091 static __checkReturn boolean_t
1093 __in efx_evq_t *eep,
1094 __in efx_qword_t *eqp,
1095 __in const efx_ev_callbacks_t *eecp,
1099 boolean_t should_abort;
1101 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
1102 should_abort = B_FALSE;
1104 code = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_CODE);
1106 case ESE_DZ_DRV_TIMER_EV: {
1109 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_TMR_ID);
1111 EFSYS_ASSERT(eecp->eec_timer != NULL);
1112 should_abort = eecp->eec_timer(arg, id);
1116 case ESE_DZ_DRV_WAKE_UP_EV: {
1119 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_EVQ_ID);
1121 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
1122 should_abort = eecp->eec_wake_up(arg, id);
1126 case ESE_DZ_DRV_START_UP_EV:
1127 EFSYS_ASSERT(eecp->eec_initialized != NULL);
1128 should_abort = eecp->eec_initialized(arg);
1132 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1133 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1134 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1138 return (should_abort);
1141 static __checkReturn boolean_t
1143 __in efx_evq_t *eep,
1144 __in efx_qword_t *eqp,
1145 __in const efx_ev_callbacks_t *eecp,
1149 boolean_t should_abort;
1151 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1152 should_abort = B_FALSE;
1154 data = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_DATA_DW0);
1155 if (data >= ((uint32_t)1 << 16)) {
1156 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1157 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1158 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1163 EFSYS_ASSERT(eecp->eec_software != NULL);
1164 should_abort = eecp->eec_software(arg, (uint16_t)data);
1166 return (should_abort);
1169 static __checkReturn boolean_t
1171 __in efx_evq_t *eep,
1172 __in efx_qword_t *eqp,
1173 __in const efx_ev_callbacks_t *eecp,
1176 efx_nic_t *enp = eep->ee_enp;
1178 boolean_t should_abort = B_FALSE;
1180 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1182 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1184 case MCDI_EVENT_CODE_BADSSERT:
1185 efx_mcdi_ev_death(enp, EINTR);
1188 case MCDI_EVENT_CODE_CMDDONE:
1189 efx_mcdi_ev_cpl(enp,
1190 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1191 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1192 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1195 #if EFSYS_OPT_MCDI_PROXY_AUTH
1196 case MCDI_EVENT_CODE_PROXY_RESPONSE:
1198 * This event notifies a function that an authorization request
1199 * has been processed. If the request was authorized then the
1200 * function can now re-send the original MCDI request.
1201 * See SF-113652-SW "SR-IOV Proxied Network Access Control".
1203 efx_mcdi_ev_proxy_response(enp,
1204 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_HANDLE),
1205 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_RC));
1207 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
1209 case MCDI_EVENT_CODE_LINKCHANGE: {
1210 efx_link_mode_t link_mode;
1212 ef10_phy_link_ev(enp, eqp, &link_mode);
1213 should_abort = eecp->eec_link_change(arg, link_mode);
1217 case MCDI_EVENT_CODE_SENSOREVT: {
1218 #if EFSYS_OPT_MON_STATS
1220 efx_mon_stat_value_t value;
1223 /* Decode monitor stat for MCDI sensor (if supported) */
1224 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) {
1225 /* Report monitor stat change */
1226 should_abort = eecp->eec_monitor(arg, id, value);
1227 } else if (rc == ENOTSUP) {
1228 should_abort = eecp->eec_exception(arg,
1229 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1230 MCDI_EV_FIELD(eqp, DATA));
1232 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
1238 case MCDI_EVENT_CODE_SCHEDERR:
1239 /* Informational only */
1242 case MCDI_EVENT_CODE_REBOOT:
1243 /* Falcon/Siena only (should not been seen with Huntington). */
1244 efx_mcdi_ev_death(enp, EIO);
1247 case MCDI_EVENT_CODE_MC_REBOOT:
1248 /* MC_REBOOT event is used for Huntington (EF10) and later. */
1249 efx_mcdi_ev_death(enp, EIO);
1252 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1253 #if EFSYS_OPT_MAC_STATS
1254 if (eecp->eec_mac_stats != NULL) {
1255 eecp->eec_mac_stats(arg,
1256 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1261 case MCDI_EVENT_CODE_FWALERT: {
1262 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1264 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1265 should_abort = eecp->eec_exception(arg,
1266 EFX_EXCEPTION_FWALERT_SRAM,
1267 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1269 should_abort = eecp->eec_exception(arg,
1270 EFX_EXCEPTION_UNKNOWN_FWALERT,
1271 MCDI_EV_FIELD(eqp, DATA));
1275 case MCDI_EVENT_CODE_TX_ERR: {
1277 * After a TXQ error is detected, firmware sends a TX_ERR event.
1278 * This may be followed by TX completions (which we discard),
1279 * and then finally by a TX_FLUSH event. Firmware destroys the
1280 * TXQ automatically after sending the TX_FLUSH event.
1282 enp->en_reset_flags |= EFX_RESET_TXQ_ERR;
1284 EFSYS_PROBE2(tx_descq_err,
1285 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1286 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1288 /* Inform the driver that a reset is required. */
1289 eecp->eec_exception(arg, EFX_EXCEPTION_TX_ERROR,
1290 MCDI_EV_FIELD(eqp, TX_ERR_DATA));
1294 case MCDI_EVENT_CODE_TX_FLUSH: {
1295 uint32_t txq_index = MCDI_EV_FIELD(eqp, TX_FLUSH_TXQ);
1298 * EF10 firmware sends two TX_FLUSH events: one to the txq's
1299 * event queue, and one to evq 0 (with TX_FLUSH_TO_DRIVER set).
1300 * We want to wait for all completions, so ignore the events
1301 * with TX_FLUSH_TO_DRIVER.
1303 if (MCDI_EV_FIELD(eqp, TX_FLUSH_TO_DRIVER) != 0) {
1304 should_abort = B_FALSE;
1308 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
1310 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
1312 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
1313 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
1317 case MCDI_EVENT_CODE_RX_ERR: {
1319 * After an RXQ error is detected, firmware sends an RX_ERR
1320 * event. This may be followed by RX events (which we discard),
1321 * and then finally by an RX_FLUSH event. Firmware destroys the
1322 * RXQ automatically after sending the RX_FLUSH event.
1324 enp->en_reset_flags |= EFX_RESET_RXQ_ERR;
1326 EFSYS_PROBE2(rx_descq_err,
1327 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1328 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1330 /* Inform the driver that a reset is required. */
1331 eecp->eec_exception(arg, EFX_EXCEPTION_RX_ERROR,
1332 MCDI_EV_FIELD(eqp, RX_ERR_DATA));
1336 case MCDI_EVENT_CODE_RX_FLUSH: {
1337 uint32_t rxq_index = MCDI_EV_FIELD(eqp, RX_FLUSH_RXQ);
1340 * EF10 firmware sends two RX_FLUSH events: one to the rxq's
1341 * event queue, and one to evq 0 (with RX_FLUSH_TO_DRIVER set).
1342 * We want to wait for all completions, so ignore the events
1343 * with RX_FLUSH_TO_DRIVER.
1345 if (MCDI_EV_FIELD(eqp, RX_FLUSH_TO_DRIVER) != 0) {
1346 should_abort = B_FALSE;
1350 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
1352 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
1354 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
1355 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
1360 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1361 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1362 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1366 return (should_abort);
1370 ef10_ev_rxlabel_init(
1371 __in efx_evq_t *eep,
1372 __in efx_rxq_t *erp,
1373 __in unsigned int label,
1374 __in efx_rxq_type_t type)
1376 efx_evq_rxq_state_t *eersp;
1377 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1378 boolean_t packed_stream = (type == EFX_RXQ_TYPE_PACKED_STREAM);
1379 boolean_t es_super_buffer = (type == EFX_RXQ_TYPE_ES_SUPER_BUFFER);
1382 _NOTE(ARGUNUSED(type))
1383 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1384 eersp = &eep->ee_rxq_state[label];
1386 EFSYS_ASSERT3U(eersp->eers_rx_mask, ==, 0);
1388 #if EFSYS_OPT_RX_PACKED_STREAM
1390 * For packed stream modes, the very first event will
1391 * have a new buffer flag set, so it will be incremented,
1392 * yielding the correct pointer. That results in a simpler
1393 * code than trying to detect start-of-the-world condition
1394 * in the event handler.
1396 eersp->eers_rx_read_ptr = packed_stream ? ~0 : 0;
1398 eersp->eers_rx_read_ptr = 0;
1400 eersp->eers_rx_mask = erp->er_mask;
1401 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1402 eersp->eers_rx_stream_npackets = 0;
1403 eersp->eers_rx_packed_stream = packed_stream || es_super_buffer;
1405 #if EFSYS_OPT_RX_PACKED_STREAM
1406 if (packed_stream) {
1407 eersp->eers_rx_packed_stream_credits = (eep->ee_mask + 1) /
1408 EFX_DIV_ROUND_UP(EFX_RX_PACKED_STREAM_MEM_PER_CREDIT,
1409 EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE);
1410 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, !=, 0);
1412 * A single credit is allocated to the queue when it is started.
1413 * It is immediately spent by the first packet which has NEW
1414 * BUFFER flag set, though, but still we shall take into
1415 * account, as to not wrap around the maximum number of credits
1418 eersp->eers_rx_packed_stream_credits--;
1419 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, <=,
1420 EFX_RX_PACKED_STREAM_MAX_CREDITS);
1426 ef10_ev_rxlabel_fini(
1427 __in efx_evq_t *eep,
1428 __in unsigned int label)
1430 efx_evq_rxq_state_t *eersp;
1432 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1433 eersp = &eep->ee_rxq_state[label];
1435 EFSYS_ASSERT3U(eersp->eers_rx_mask, !=, 0);
1437 eersp->eers_rx_read_ptr = 0;
1438 eersp->eers_rx_mask = 0;
1439 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1440 eersp->eers_rx_stream_npackets = 0;
1441 eersp->eers_rx_packed_stream = B_FALSE;
1443 #if EFSYS_OPT_RX_PACKED_STREAM
1444 eersp->eers_rx_packed_stream_credits = 0;
1448 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */