1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
9 #if EFSYS_OPT_MON_STATS
13 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
16 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
18 (_eep)->ee_stat[_stat]++; \
19 _NOTE(CONSTANTCONDITION) \
22 #define EFX_EV_QSTAT_INCR(_eep, _stat)
26 * Non-interrupting event queue requires interrrupting event queue to
27 * refer to for wake-up events even if wake ups are never used.
28 * It could be even non-allocated event queue.
30 #define EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX (0)
32 static __checkReturn boolean_t
35 __in efx_qword_t *eqp,
36 __in const efx_ev_callbacks_t *eecp,
39 static __checkReturn boolean_t
42 __in efx_qword_t *eqp,
43 __in const efx_ev_callbacks_t *eecp,
46 static __checkReturn boolean_t
49 __in efx_qword_t *eqp,
50 __in const efx_ev_callbacks_t *eecp,
53 static __checkReturn boolean_t
56 __in efx_qword_t *eqp,
57 __in const efx_ev_callbacks_t *eecp,
60 static __checkReturn boolean_t
63 __in efx_qword_t *eqp,
64 __in const efx_ev_callbacks_t *eecp,
68 static __checkReturn efx_rc_t
71 __in uint32_t instance,
73 __in uint32_t timer_ns)
76 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_EVQ_TMR_IN_LEN,
77 MC_CMD_SET_EVQ_TMR_OUT_LEN);
80 req.emr_cmd = MC_CMD_SET_EVQ_TMR;
81 req.emr_in_buf = payload;
82 req.emr_in_length = MC_CMD_SET_EVQ_TMR_IN_LEN;
83 req.emr_out_buf = payload;
84 req.emr_out_length = MC_CMD_SET_EVQ_TMR_OUT_LEN;
86 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_INSTANCE, instance);
87 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, timer_ns);
88 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, timer_ns);
89 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_MODE, mode);
91 efx_mcdi_execute(enp, &req);
93 if (req.emr_rc != 0) {
98 if (req.emr_out_length_used < MC_CMD_SET_EVQ_TMR_OUT_LEN) {
108 EFSYS_PROBE1(fail1, efx_rc_t, rc);
113 static __checkReturn efx_rc_t
116 __in unsigned int instance,
117 __in efsys_mem_t *esmp,
122 __in boolean_t low_latency)
125 EFX_MCDI_DECLARE_BUF(payload,
126 MC_CMD_INIT_EVQ_IN_LEN(EFX_EVQ_NBUFS(EFX_EVQ_MAXNEVS)),
127 MC_CMD_INIT_EVQ_OUT_LEN);
128 efx_qword_t *dma_addr;
132 boolean_t interrupting;
136 npages = EFX_EVQ_NBUFS(nevs);
137 if (MC_CMD_INIT_EVQ_IN_LEN(npages) > MC_CMD_INIT_EVQ_IN_LENMAX) {
142 req.emr_cmd = MC_CMD_INIT_EVQ;
143 req.emr_in_buf = payload;
144 req.emr_in_length = MC_CMD_INIT_EVQ_IN_LEN(npages);
145 req.emr_out_buf = payload;
146 req.emr_out_length = MC_CMD_INIT_EVQ_OUT_LEN;
148 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_SIZE, nevs);
149 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_INSTANCE, instance);
150 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_IRQ_NUM, irq);
152 interrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
153 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
156 * On Huntington RX and TX event batching can only be requested together
157 * (even if the datapath firmware doesn't actually support RX
158 * batching). If event cut through is enabled no RX batching will occur.
160 * So always enable RX and TX event batching, and enable event cut
161 * through if we want low latency operation.
163 switch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {
164 case EFX_EVQ_FLAGS_TYPE_AUTO:
165 ev_cut_through = low_latency ? 1 : 0;
167 case EFX_EVQ_FLAGS_TYPE_THROUGHPUT:
170 case EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:
177 MCDI_IN_POPULATE_DWORD_6(req, INIT_EVQ_IN_FLAGS,
178 INIT_EVQ_IN_FLAG_INTERRUPTING, interrupting,
179 INIT_EVQ_IN_FLAG_RPTR_DOS, 0,
180 INIT_EVQ_IN_FLAG_INT_ARMD, 0,
181 INIT_EVQ_IN_FLAG_CUT_THRU, ev_cut_through,
182 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
183 INIT_EVQ_IN_FLAG_TX_MERGE, 1);
185 /* If the value is zero then disable the timer */
187 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
188 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
189 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, 0);
190 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, 0);
194 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
197 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
198 MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF);
199 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, ticks);
200 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, ticks);
203 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_MODE,
204 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
205 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_THRSHLD, 0);
207 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_IN_DMA_ADDR);
208 addr = EFSYS_MEM_ADDR(esmp);
210 for (i = 0; i < npages; i++) {
211 EFX_POPULATE_QWORD_2(*dma_addr,
212 EFX_DWORD_1, (uint32_t)(addr >> 32),
213 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
216 addr += EFX_BUF_SIZE;
219 efx_mcdi_execute(enp, &req);
221 if (req.emr_rc != 0) {
226 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_OUT_LEN) {
231 /* NOTE: ignore the returned IRQ param as firmware does not set it. */
244 EFSYS_PROBE1(fail1, efx_rc_t, rc);
250 static __checkReturn efx_rc_t
251 efx_mcdi_init_evq_v2(
253 __in unsigned int instance,
254 __in efsys_mem_t *esmp,
261 EFX_MCDI_DECLARE_BUF(payload,
262 MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_EVQ_NBUFS(EFX_EVQ_MAXNEVS)),
263 MC_CMD_INIT_EVQ_V2_OUT_LEN);
264 boolean_t interrupting;
265 unsigned int evq_type;
266 efx_qword_t *dma_addr;
272 npages = EFX_EVQ_NBUFS(nevs);
273 if (MC_CMD_INIT_EVQ_V2_IN_LEN(npages) > MC_CMD_INIT_EVQ_V2_IN_LENMAX) {
278 req.emr_cmd = MC_CMD_INIT_EVQ;
279 req.emr_in_buf = payload;
280 req.emr_in_length = MC_CMD_INIT_EVQ_V2_IN_LEN(npages);
281 req.emr_out_buf = payload;
282 req.emr_out_length = MC_CMD_INIT_EVQ_V2_OUT_LEN;
284 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_SIZE, nevs);
285 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_INSTANCE, instance);
286 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_IRQ_NUM, irq);
288 interrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
289 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
291 switch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {
292 case EFX_EVQ_FLAGS_TYPE_AUTO:
293 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO;
295 case EFX_EVQ_FLAGS_TYPE_THROUGHPUT:
296 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT;
298 case EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:
299 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY;
305 MCDI_IN_POPULATE_DWORD_4(req, INIT_EVQ_V2_IN_FLAGS,
306 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, interrupting,
307 INIT_EVQ_V2_IN_FLAG_RPTR_DOS, 0,
308 INIT_EVQ_V2_IN_FLAG_INT_ARMD, 0,
309 INIT_EVQ_V2_IN_FLAG_TYPE, evq_type);
311 /* If the value is zero then disable the timer */
313 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE,
314 MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS);
315 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, 0);
316 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, 0);
320 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
323 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE,
324 MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF);
325 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, ticks);
326 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, ticks);
329 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_MODE,
330 MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS);
331 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_THRSHLD, 0);
333 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_V2_IN_DMA_ADDR);
334 addr = EFSYS_MEM_ADDR(esmp);
336 for (i = 0; i < npages; i++) {
337 EFX_POPULATE_QWORD_2(*dma_addr,
338 EFX_DWORD_1, (uint32_t)(addr >> 32),
339 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
342 addr += EFX_BUF_SIZE;
345 efx_mcdi_execute(enp, &req);
347 if (req.emr_rc != 0) {
352 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_V2_OUT_LEN) {
357 /* NOTE: ignore the returned IRQ param as firmware does not set it. */
359 EFSYS_PROBE1(mcdi_evq_flags, uint32_t,
360 MCDI_OUT_DWORD(req, INIT_EVQ_V2_OUT_FLAGS));
373 EFSYS_PROBE1(fail1, efx_rc_t, rc);
378 static __checkReturn efx_rc_t
381 __in uint32_t instance)
384 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FINI_EVQ_IN_LEN,
385 MC_CMD_FINI_EVQ_OUT_LEN);
388 req.emr_cmd = MC_CMD_FINI_EVQ;
389 req.emr_in_buf = payload;
390 req.emr_in_length = MC_CMD_FINI_EVQ_IN_LEN;
391 req.emr_out_buf = payload;
392 req.emr_out_length = MC_CMD_FINI_EVQ_OUT_LEN;
394 MCDI_IN_SET_DWORD(req, FINI_EVQ_IN_INSTANCE, instance);
396 efx_mcdi_execute_quiet(enp, &req);
398 if (req.emr_rc != 0) {
407 * EALREADY is not an error, but indicates that the MC has rebooted and
408 * that the EVQ has already been destroyed.
411 EFSYS_PROBE1(fail1, efx_rc_t, rc);
418 __checkReturn efx_rc_t
422 _NOTE(ARGUNUSED(enp))
430 _NOTE(ARGUNUSED(enp))
433 __checkReturn efx_rc_t
436 __in unsigned int index,
437 __in efsys_mem_t *esmp,
444 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
448 _NOTE(ARGUNUSED(id)) /* buftbl id managed by MC */
449 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
450 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
453 (ndescs < EFX_EVQ_MINNEVS) || (ndescs > EFX_EVQ_MAXNEVS)) {
458 if (index >= encp->enc_evq_limit) {
463 if (us > encp->enc_evq_timer_max_us) {
468 /* Set up the handler table */
469 eep->ee_rx = ef10_ev_rx;
470 eep->ee_tx = ef10_ev_tx;
471 eep->ee_driver = ef10_ev_driver;
472 eep->ee_drv_gen = ef10_ev_drv_gen;
473 eep->ee_mcdi = ef10_ev_mcdi;
475 /* Set up the event queue */
476 /* INIT_EVQ expects function-relative vector number */
477 if ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
478 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT) {
480 } else if (index == EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX) {
482 flags = (flags & ~EFX_EVQ_FLAGS_NOTIFY_MASK) |
483 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT;
485 irq = EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX;
489 * Interrupts may be raised for events immediately after the queue is
490 * created. See bug58606.
493 if (encp->enc_init_evq_v2_supported) {
495 * On Medford the low latency license is required to enable RX
496 * and event cut through and to disable RX batching. If event
497 * queue type in flags is auto, we let the firmware decide the
498 * settings to use. If the adapter has a low latency license,
499 * it will choose the best settings for low latency, otherwise
500 * it will choose the best settings for throughput.
502 rc = efx_mcdi_init_evq_v2(enp, index, esmp, ndescs, irq, us,
508 * On Huntington we need to specify the settings to use.
509 * If event queue type in flags is auto, we favour throughput
510 * if the adapter is running virtualization supporting firmware
511 * (i.e. the full featured firmware variant)
512 * and latency otherwise. The Ethernet Virtual Bridging
513 * capability is used to make this decision. (Note though that
514 * the low latency firmware variant is also best for
515 * throughput and corresponding type should be specified
518 boolean_t low_latency = encp->enc_datapath_cap_evb ? 0 : 1;
519 rc = efx_mcdi_init_evq(enp, index, esmp, ndescs, irq, us, flags,
536 EFSYS_PROBE1(fail1, efx_rc_t, rc);
545 efx_nic_t *enp = eep->ee_enp;
547 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
548 enp->en_family == EFX_FAMILY_MEDFORD ||
549 enp->en_family == EFX_FAMILY_MEDFORD2);
551 (void) efx_mcdi_fini_evq(enp, eep->ee_index);
554 __checkReturn efx_rc_t
557 __in unsigned int count)
559 efx_nic_t *enp = eep->ee_enp;
563 rptr = count & eep->ee_mask;
565 if (enp->en_nic_cfg.enc_bug35388_workaround) {
566 EFX_STATIC_ASSERT(EFX_EVQ_MINNEVS >
567 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
568 EFX_STATIC_ASSERT(EFX_EVQ_MAXNEVS <
569 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
571 EFX_POPULATE_DWORD_2(dword,
572 ERF_DD_EVQ_IND_RPTR_FLAGS,
573 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
575 (rptr >> ERF_DD_EVQ_IND_RPTR_WIDTH));
576 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
579 EFX_POPULATE_DWORD_2(dword,
580 ERF_DD_EVQ_IND_RPTR_FLAGS,
581 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
583 rptr & ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
584 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
587 EFX_POPULATE_DWORD_1(dword, ERF_DZ_EVQ_RPTR, rptr);
588 EFX_BAR_VI_WRITED(enp, ER_DZ_EVQ_RPTR_REG, eep->ee_index,
595 static __checkReturn efx_rc_t
596 efx_mcdi_driver_event(
599 __in efx_qword_t data)
602 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_DRIVER_EVENT_IN_LEN,
603 MC_CMD_DRIVER_EVENT_OUT_LEN);
606 req.emr_cmd = MC_CMD_DRIVER_EVENT;
607 req.emr_in_buf = payload;
608 req.emr_in_length = MC_CMD_DRIVER_EVENT_IN_LEN;
609 req.emr_out_buf = payload;
610 req.emr_out_length = MC_CMD_DRIVER_EVENT_OUT_LEN;
612 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_EVQ, evq);
614 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_LO,
615 EFX_QWORD_FIELD(data, EFX_DWORD_0));
616 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_HI,
617 EFX_QWORD_FIELD(data, EFX_DWORD_1));
619 efx_mcdi_execute(enp, &req);
621 if (req.emr_rc != 0) {
629 EFSYS_PROBE1(fail1, efx_rc_t, rc);
639 efx_nic_t *enp = eep->ee_enp;
642 EFX_POPULATE_QWORD_3(event,
643 ESF_DZ_DRV_CODE, ESE_DZ_EV_CODE_DRV_GEN_EV,
644 ESF_DZ_DRV_SUB_CODE, 0,
645 ESF_DZ_DRV_SUB_DATA_DW0, (uint32_t)data);
647 (void) efx_mcdi_driver_event(enp, eep->ee_index, event);
650 __checkReturn efx_rc_t
653 __in unsigned int us)
655 efx_nic_t *enp = eep->ee_enp;
656 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
661 /* Check that hardware and MCDI use the same timer MODE values */
662 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_DIS ==
663 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS);
664 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_IMMED_START ==
665 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START);
666 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_TRIG_START ==
667 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START);
668 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_INT_HLDOFF ==
669 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF);
671 if (us > encp->enc_evq_timer_max_us) {
676 /* If the value is zero then disable the timer */
678 mode = FFE_CZ_TIMER_MODE_DIS;
680 mode = FFE_CZ_TIMER_MODE_INT_HLDOFF;
683 if (encp->enc_bug61265_workaround) {
684 uint32_t ns = us * 1000;
686 rc = efx_mcdi_set_evq_tmr(enp, eep->ee_index, mode, ns);
692 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
695 if (encp->enc_bug35388_workaround) {
696 EFX_POPULATE_DWORD_3(dword,
697 ERF_DD_EVQ_IND_TIMER_FLAGS,
698 EFE_DD_EVQ_IND_TIMER_FLAGS,
699 ERF_DD_EVQ_IND_TIMER_MODE, mode,
700 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
701 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT,
702 eep->ee_index, &dword, 0);
705 * NOTE: The TMR_REL field introduced in Medford2 is
706 * ignored on earlier EF10 controllers. See bug66418
707 * comment 9 for details.
709 EFX_POPULATE_DWORD_3(dword,
710 ERF_DZ_TC_TIMER_MODE, mode,
711 ERF_DZ_TC_TIMER_VAL, ticks,
712 ERF_FZ_TC_TMR_REL_VAL, ticks);
713 EFX_BAR_VI_WRITED(enp, ER_DZ_EVQ_TMR_REG,
714 eep->ee_index, &dword, 0);
725 EFSYS_PROBE1(fail1, efx_rc_t, rc);
733 ef10_ev_qstats_update(
735 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
739 for (id = 0; id < EV_NQSTATS; id++) {
740 efsys_stat_t *essp = &stat[id];
742 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
743 eep->ee_stat[id] = 0;
746 #endif /* EFSYS_OPT_QSTATS */
748 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
750 static __checkReturn boolean_t
751 ef10_ev_rx_packed_stream(
753 __in efx_qword_t *eqp,
754 __in const efx_ev_callbacks_t *eecp,
758 uint32_t pkt_count_lbits;
760 boolean_t should_abort;
761 efx_evq_rxq_state_t *eersp;
762 unsigned int pkt_count;
763 unsigned int current_id;
764 boolean_t new_buffer;
766 pkt_count_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
767 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
768 new_buffer = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_EV_ROTATE);
772 eersp = &eep->ee_rxq_state[label];
775 * RX_DSC_PTR_LBITS has least significant bits of the global
776 * (not per-buffer) packet counter. It is guaranteed that
777 * maximum number of completed packets fits in lbits-mask.
778 * So, modulo lbits-mask arithmetic should be used to calculate
779 * packet counter increment.
781 pkt_count = (pkt_count_lbits - eersp->eers_rx_stream_npackets) &
782 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
783 eersp->eers_rx_stream_npackets += pkt_count;
786 flags |= EFX_PKT_PACKED_STREAM_NEW_BUFFER;
787 #if EFSYS_OPT_RX_PACKED_STREAM
789 * If both packed stream and equal stride super-buffer
790 * modes are compiled in, in theory credits should be
791 * be maintained for packed stream only, but right now
792 * these modes are not distinguished in the event queue
793 * Rx queue state and it is OK to increment the counter
794 * regardless (it might be event cheaper than branching
795 * since neighbour structure member are updated as well).
797 eersp->eers_rx_packed_stream_credits++;
799 eersp->eers_rx_read_ptr++;
801 current_id = eersp->eers_rx_read_ptr & eersp->eers_rx_mask;
803 /* Check for errors that invalidate checksum and L3/L4 fields */
804 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TRUNC_ERR) != 0) {
805 /* RX frame truncated */
806 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
807 flags |= EFX_DISCARD;
810 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
811 /* Bad Ethernet frame CRC */
812 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
813 flags |= EFX_DISCARD;
817 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
818 flags |= EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE;
822 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR))
823 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
825 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR))
826 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
829 /* If we're not discarding the packet then it is ok */
830 if (~flags & EFX_DISCARD)
831 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
833 EFSYS_ASSERT(eecp->eec_rx_ps != NULL);
834 should_abort = eecp->eec_rx_ps(arg, label, current_id, pkt_count,
837 return (should_abort);
840 #endif /* EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER */
842 static __checkReturn boolean_t
845 __in efx_qword_t *eqp,
846 __in const efx_ev_callbacks_t *eecp,
849 efx_nic_t *enp = eep->ee_enp;
853 uint32_t eth_tag_class;
856 uint32_t next_read_lbits;
859 boolean_t should_abort;
860 efx_evq_rxq_state_t *eersp;
861 unsigned int desc_count;
862 unsigned int last_used_id;
864 EFX_EV_QSTAT_INCR(eep, EV_RX);
866 /* Discard events after RXQ/TXQ errors */
867 if (enp->en_reset_flags & (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR))
870 /* Basic packet information */
871 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
872 eersp = &eep->ee_rxq_state[label];
874 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
876 * Packed stream events are very different,
877 * so handle them separately
879 if (eersp->eers_rx_packed_stream)
880 return (ef10_ev_rx_packed_stream(eep, eqp, eecp, arg));
883 size = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_BYTES);
884 cont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);
885 next_read_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
886 eth_tag_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ETH_TAG_CLASS);
887 mac_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS);
888 l3_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L3_CLASS);
891 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is only
892 * 2 bits wide on Medford2. Check it is safe to use the Medford2 field
893 * and values for all EF10 controllers.
895 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN == ESF_DE_RX_L4_CLASS_LBN);
896 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
897 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
898 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN == ESE_DE_L4_CLASS_UNKNOWN);
900 l4_class = EFX_QWORD_FIELD(*eqp, ESF_FZ_RX_L4_CLASS);
902 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DROP_EVENT) != 0) {
903 /* Drop this event */
910 * This may be part of a scattered frame, or it may be a
911 * truncated frame if scatter is disabled on this RXQ.
912 * Overlength frames can be received if e.g. a VF is configured
913 * for 1500 MTU but connected to a port set to 9000 MTU
915 * FIXME: There is not yet any driver that supports scatter on
916 * Huntington. Scatter support is required for OSX.
918 flags |= EFX_PKT_CONT;
921 if (mac_class == ESE_DZ_MAC_CLASS_UCAST)
922 flags |= EFX_PKT_UNICAST;
924 /* Increment the count of descriptors read */
925 desc_count = (next_read_lbits - eersp->eers_rx_read_ptr) &
926 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
927 eersp->eers_rx_read_ptr += desc_count;
930 * FIXME: add error checking to make sure this a batched event.
931 * This could also be an aborted scatter, see Bug36629.
933 if (desc_count > 1) {
934 EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);
935 flags |= EFX_PKT_PREFIX_LEN;
938 /* Calculate the index of the last descriptor consumed */
939 last_used_id = (eersp->eers_rx_read_ptr - 1) & eersp->eers_rx_mask;
941 /* Check for errors that invalidate checksum and L3/L4 fields */
942 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TRUNC_ERR) != 0) {
943 /* RX frame truncated */
944 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
945 flags |= EFX_DISCARD;
948 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
949 /* Bad Ethernet frame CRC */
950 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
951 flags |= EFX_DISCARD;
954 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
956 * Hardware parse failed, due to malformed headers
957 * or headers that are too long for the parser.
958 * Headers and checksums must be validated by the host.
960 /* TODO: EFX_EV_QSTAT_INCR(eep, EV_RX_PARSE_INCOMPLETE); */
964 if ((eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN1) ||
965 (eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN2)) {
966 flags |= EFX_PKT_VLAN_TAGGED;
970 case ESE_DZ_L3_CLASS_IP4:
971 case ESE_DZ_L3_CLASS_IP4_FRAG:
972 flags |= EFX_PKT_IPV4;
973 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR)) {
974 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
976 flags |= EFX_CKSUM_IPV4;
980 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
981 * only 2 bits wide on Medford2. Check it is safe to use the
982 * Medford2 field and values for all EF10 controllers.
984 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
985 ESF_DE_RX_L4_CLASS_LBN);
986 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
987 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
988 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
989 ESE_DE_L4_CLASS_UNKNOWN);
991 if (l4_class == ESE_FZ_L4_CLASS_TCP) {
992 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
993 flags |= EFX_PKT_TCP;
994 } else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
995 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
996 flags |= EFX_PKT_UDP;
998 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
1002 case ESE_DZ_L3_CLASS_IP6:
1003 case ESE_DZ_L3_CLASS_IP6_FRAG:
1004 flags |= EFX_PKT_IPV6;
1007 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
1008 * only 2 bits wide on Medford2. Check it is safe to use the
1009 * Medford2 field and values for all EF10 controllers.
1011 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
1012 ESF_DE_RX_L4_CLASS_LBN);
1013 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
1014 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
1015 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
1016 ESE_DE_L4_CLASS_UNKNOWN);
1018 if (l4_class == ESE_FZ_L4_CLASS_TCP) {
1019 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
1020 flags |= EFX_PKT_TCP;
1021 } else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
1022 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
1023 flags |= EFX_PKT_UDP;
1025 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
1030 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
1034 if (flags & (EFX_PKT_TCP | EFX_PKT_UDP)) {
1035 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
1036 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
1038 flags |= EFX_CKSUM_TCPUDP;
1043 /* If we're not discarding the packet then it is ok */
1044 if (~flags & EFX_DISCARD)
1045 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
1047 EFSYS_ASSERT(eecp->eec_rx != NULL);
1048 should_abort = eecp->eec_rx(arg, label, last_used_id, size, flags);
1050 return (should_abort);
1053 static __checkReturn boolean_t
1055 __in efx_evq_t *eep,
1056 __in efx_qword_t *eqp,
1057 __in const efx_ev_callbacks_t *eecp,
1060 efx_nic_t *enp = eep->ee_enp;
1063 boolean_t should_abort;
1065 EFX_EV_QSTAT_INCR(eep, EV_TX);
1067 /* Discard events after RXQ/TXQ errors */
1068 if (enp->en_reset_flags & (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR))
1071 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DROP_EVENT) != 0) {
1072 /* Drop this event */
1076 /* Per-packet TX completion (was per-descriptor for Falcon/Siena) */
1077 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DESCR_INDX);
1078 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_QLABEL);
1080 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
1082 EFSYS_ASSERT(eecp->eec_tx != NULL);
1083 should_abort = eecp->eec_tx(arg, label, id);
1085 return (should_abort);
1088 static __checkReturn boolean_t
1090 __in efx_evq_t *eep,
1091 __in efx_qword_t *eqp,
1092 __in const efx_ev_callbacks_t *eecp,
1096 boolean_t should_abort;
1098 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
1099 should_abort = B_FALSE;
1101 code = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_CODE);
1103 case ESE_DZ_DRV_TIMER_EV: {
1106 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_TMR_ID);
1108 EFSYS_ASSERT(eecp->eec_timer != NULL);
1109 should_abort = eecp->eec_timer(arg, id);
1113 case ESE_DZ_DRV_WAKE_UP_EV: {
1116 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_EVQ_ID);
1118 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
1119 should_abort = eecp->eec_wake_up(arg, id);
1123 case ESE_DZ_DRV_START_UP_EV:
1124 EFSYS_ASSERT(eecp->eec_initialized != NULL);
1125 should_abort = eecp->eec_initialized(arg);
1129 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1130 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1131 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1135 return (should_abort);
1138 static __checkReturn boolean_t
1140 __in efx_evq_t *eep,
1141 __in efx_qword_t *eqp,
1142 __in const efx_ev_callbacks_t *eecp,
1146 boolean_t should_abort;
1148 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1149 should_abort = B_FALSE;
1151 data = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_DATA_DW0);
1152 if (data >= ((uint32_t)1 << 16)) {
1153 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1154 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1155 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1160 EFSYS_ASSERT(eecp->eec_software != NULL);
1161 should_abort = eecp->eec_software(arg, (uint16_t)data);
1163 return (should_abort);
1166 static __checkReturn boolean_t
1168 __in efx_evq_t *eep,
1169 __in efx_qword_t *eqp,
1170 __in const efx_ev_callbacks_t *eecp,
1173 efx_nic_t *enp = eep->ee_enp;
1175 boolean_t should_abort = B_FALSE;
1177 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1179 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1181 case MCDI_EVENT_CODE_BADSSERT:
1182 efx_mcdi_ev_death(enp, EINTR);
1185 case MCDI_EVENT_CODE_CMDDONE:
1186 efx_mcdi_ev_cpl(enp,
1187 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1188 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1189 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1192 #if EFSYS_OPT_MCDI_PROXY_AUTH
1193 case MCDI_EVENT_CODE_PROXY_RESPONSE:
1195 * This event notifies a function that an authorization request
1196 * has been processed. If the request was authorized then the
1197 * function can now re-send the original MCDI request.
1198 * See SF-113652-SW "SR-IOV Proxied Network Access Control".
1200 efx_mcdi_ev_proxy_response(enp,
1201 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_HANDLE),
1202 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_RC));
1204 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
1206 case MCDI_EVENT_CODE_LINKCHANGE: {
1207 efx_link_mode_t link_mode;
1209 ef10_phy_link_ev(enp, eqp, &link_mode);
1210 should_abort = eecp->eec_link_change(arg, link_mode);
1214 case MCDI_EVENT_CODE_SENSOREVT: {
1215 #if EFSYS_OPT_MON_STATS
1217 efx_mon_stat_value_t value;
1220 /* Decode monitor stat for MCDI sensor (if supported) */
1221 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) {
1222 /* Report monitor stat change */
1223 should_abort = eecp->eec_monitor(arg, id, value);
1224 } else if (rc == ENOTSUP) {
1225 should_abort = eecp->eec_exception(arg,
1226 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1227 MCDI_EV_FIELD(eqp, DATA));
1229 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
1235 case MCDI_EVENT_CODE_SCHEDERR:
1236 /* Informational only */
1239 case MCDI_EVENT_CODE_REBOOT:
1240 /* Falcon/Siena only (should not been seen with Huntington). */
1241 efx_mcdi_ev_death(enp, EIO);
1244 case MCDI_EVENT_CODE_MC_REBOOT:
1245 /* MC_REBOOT event is used for Huntington (EF10) and later. */
1246 efx_mcdi_ev_death(enp, EIO);
1249 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1250 #if EFSYS_OPT_MAC_STATS
1251 if (eecp->eec_mac_stats != NULL) {
1252 eecp->eec_mac_stats(arg,
1253 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1258 case MCDI_EVENT_CODE_FWALERT: {
1259 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1261 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1262 should_abort = eecp->eec_exception(arg,
1263 EFX_EXCEPTION_FWALERT_SRAM,
1264 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1266 should_abort = eecp->eec_exception(arg,
1267 EFX_EXCEPTION_UNKNOWN_FWALERT,
1268 MCDI_EV_FIELD(eqp, DATA));
1272 case MCDI_EVENT_CODE_TX_ERR: {
1274 * After a TXQ error is detected, firmware sends a TX_ERR event.
1275 * This may be followed by TX completions (which we discard),
1276 * and then finally by a TX_FLUSH event. Firmware destroys the
1277 * TXQ automatically after sending the TX_FLUSH event.
1279 enp->en_reset_flags |= EFX_RESET_TXQ_ERR;
1281 EFSYS_PROBE2(tx_descq_err,
1282 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1283 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1285 /* Inform the driver that a reset is required. */
1286 eecp->eec_exception(arg, EFX_EXCEPTION_TX_ERROR,
1287 MCDI_EV_FIELD(eqp, TX_ERR_DATA));
1291 case MCDI_EVENT_CODE_TX_FLUSH: {
1292 uint32_t txq_index = MCDI_EV_FIELD(eqp, TX_FLUSH_TXQ);
1295 * EF10 firmware sends two TX_FLUSH events: one to the txq's
1296 * event queue, and one to evq 0 (with TX_FLUSH_TO_DRIVER set).
1297 * We want to wait for all completions, so ignore the events
1298 * with TX_FLUSH_TO_DRIVER.
1300 if (MCDI_EV_FIELD(eqp, TX_FLUSH_TO_DRIVER) != 0) {
1301 should_abort = B_FALSE;
1305 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
1307 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
1309 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
1310 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
1314 case MCDI_EVENT_CODE_RX_ERR: {
1316 * After an RXQ error is detected, firmware sends an RX_ERR
1317 * event. This may be followed by RX events (which we discard),
1318 * and then finally by an RX_FLUSH event. Firmware destroys the
1319 * RXQ automatically after sending the RX_FLUSH event.
1321 enp->en_reset_flags |= EFX_RESET_RXQ_ERR;
1323 EFSYS_PROBE2(rx_descq_err,
1324 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1325 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1327 /* Inform the driver that a reset is required. */
1328 eecp->eec_exception(arg, EFX_EXCEPTION_RX_ERROR,
1329 MCDI_EV_FIELD(eqp, RX_ERR_DATA));
1333 case MCDI_EVENT_CODE_RX_FLUSH: {
1334 uint32_t rxq_index = MCDI_EV_FIELD(eqp, RX_FLUSH_RXQ);
1337 * EF10 firmware sends two RX_FLUSH events: one to the rxq's
1338 * event queue, and one to evq 0 (with RX_FLUSH_TO_DRIVER set).
1339 * We want to wait for all completions, so ignore the events
1340 * with RX_FLUSH_TO_DRIVER.
1342 if (MCDI_EV_FIELD(eqp, RX_FLUSH_TO_DRIVER) != 0) {
1343 should_abort = B_FALSE;
1347 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
1349 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
1351 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
1352 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
1357 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1358 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1359 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1363 return (should_abort);
1367 ef10_ev_rxlabel_init(
1368 __in efx_evq_t *eep,
1369 __in efx_rxq_t *erp,
1370 __in unsigned int label,
1371 __in efx_rxq_type_t type)
1373 efx_evq_rxq_state_t *eersp;
1374 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1375 boolean_t packed_stream = (type == EFX_RXQ_TYPE_PACKED_STREAM);
1376 boolean_t es_super_buffer = (type == EFX_RXQ_TYPE_ES_SUPER_BUFFER);
1379 _NOTE(ARGUNUSED(type))
1380 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1381 eersp = &eep->ee_rxq_state[label];
1383 EFSYS_ASSERT3U(eersp->eers_rx_mask, ==, 0);
1385 #if EFSYS_OPT_RX_PACKED_STREAM
1387 * For packed stream modes, the very first event will
1388 * have a new buffer flag set, so it will be incremented,
1389 * yielding the correct pointer. That results in a simpler
1390 * code than trying to detect start-of-the-world condition
1391 * in the event handler.
1393 eersp->eers_rx_read_ptr = packed_stream ? ~0 : 0;
1395 eersp->eers_rx_read_ptr = 0;
1397 eersp->eers_rx_mask = erp->er_mask;
1398 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1399 eersp->eers_rx_stream_npackets = 0;
1400 eersp->eers_rx_packed_stream = packed_stream || es_super_buffer;
1402 #if EFSYS_OPT_RX_PACKED_STREAM
1403 if (packed_stream) {
1404 eersp->eers_rx_packed_stream_credits = (eep->ee_mask + 1) /
1405 EFX_DIV_ROUND_UP(EFX_RX_PACKED_STREAM_MEM_PER_CREDIT,
1406 EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE);
1407 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, !=, 0);
1409 * A single credit is allocated to the queue when it is started.
1410 * It is immediately spent by the first packet which has NEW
1411 * BUFFER flag set, though, but still we shall take into
1412 * account, as to not wrap around the maximum number of credits
1415 eersp->eers_rx_packed_stream_credits--;
1416 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, <=,
1417 EFX_RX_PACKED_STREAM_MAX_CREDITS);
1423 ef10_ev_rxlabel_fini(
1424 __in efx_evq_t *eep,
1425 __in unsigned int label)
1427 efx_evq_rxq_state_t *eersp;
1429 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1430 eersp = &eep->ee_rxq_state[label];
1432 EFSYS_ASSERT3U(eersp->eers_rx_mask, !=, 0);
1434 eersp->eers_rx_read_ptr = 0;
1435 eersp->eers_rx_mask = 0;
1436 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1437 eersp->eers_rx_stream_npackets = 0;
1438 eersp->eers_rx_packed_stream = B_FALSE;
1440 #if EFSYS_OPT_RX_PACKED_STREAM
1441 eersp->eers_rx_packed_stream_credits = 0;
1445 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */