1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
9 #if EFSYS_OPT_MON_STATS
13 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
16 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
18 (_eep)->ee_stat[_stat]++; \
19 _NOTE(CONSTANTCONDITION) \
22 #define EFX_EV_QSTAT_INCR(_eep, _stat)
26 * Non-interrupting event queue requires interrrupting event queue to
27 * refer to for wake-up events even if wake ups are never used.
28 * It could be even non-allocated event queue.
30 #define EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX (0)
32 static __checkReturn boolean_t
35 __in efx_qword_t *eqp,
36 __in const efx_ev_callbacks_t *eecp,
39 static __checkReturn boolean_t
42 __in efx_qword_t *eqp,
43 __in const efx_ev_callbacks_t *eecp,
46 static __checkReturn boolean_t
49 __in efx_qword_t *eqp,
50 __in const efx_ev_callbacks_t *eecp,
53 static __checkReturn boolean_t
56 __in efx_qword_t *eqp,
57 __in const efx_ev_callbacks_t *eecp,
60 static __checkReturn boolean_t
63 __in efx_qword_t *eqp,
64 __in const efx_ev_callbacks_t *eecp,
68 static __checkReturn efx_rc_t
71 __in uint32_t instance,
73 __in uint32_t timer_ns)
76 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_EVQ_TMR_IN_LEN,
77 MC_CMD_SET_EVQ_TMR_OUT_LEN);
80 req.emr_cmd = MC_CMD_SET_EVQ_TMR;
81 req.emr_in_buf = payload;
82 req.emr_in_length = MC_CMD_SET_EVQ_TMR_IN_LEN;
83 req.emr_out_buf = payload;
84 req.emr_out_length = MC_CMD_SET_EVQ_TMR_OUT_LEN;
86 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_INSTANCE, instance);
87 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, timer_ns);
88 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, timer_ns);
89 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_MODE, mode);
91 efx_mcdi_execute(enp, &req);
93 if (req.emr_rc != 0) {
98 if (req.emr_out_length_used < MC_CMD_SET_EVQ_TMR_OUT_LEN) {
108 EFSYS_PROBE1(fail1, efx_rc_t, rc);
113 static __checkReturn efx_rc_t
116 __in unsigned int instance,
117 __in efsys_mem_t *esmp,
122 __in boolean_t low_latency)
125 EFX_MCDI_DECLARE_BUF(payload,
126 MC_CMD_INIT_EVQ_IN_LEN(EF10_EVQ_MAXNBUFS),
127 MC_CMD_INIT_EVQ_OUT_LEN);
128 efx_qword_t *dma_addr;
132 boolean_t interrupting;
136 npages = efx_evq_nbufs(enp, nevs);
137 if (npages > EF10_EVQ_MAXNBUFS) {
142 req.emr_cmd = MC_CMD_INIT_EVQ;
143 req.emr_in_buf = payload;
144 req.emr_in_length = MC_CMD_INIT_EVQ_IN_LEN(npages);
145 req.emr_out_buf = payload;
146 req.emr_out_length = MC_CMD_INIT_EVQ_OUT_LEN;
148 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_SIZE, nevs);
149 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_INSTANCE, instance);
150 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_IRQ_NUM, irq);
152 interrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
153 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
156 * On Huntington RX and TX event batching can only be requested together
157 * (even if the datapath firmware doesn't actually support RX
158 * batching). If event cut through is enabled no RX batching will occur.
160 * So always enable RX and TX event batching, and enable event cut
161 * through if we want low latency operation.
163 switch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {
164 case EFX_EVQ_FLAGS_TYPE_AUTO:
165 ev_cut_through = low_latency ? 1 : 0;
167 case EFX_EVQ_FLAGS_TYPE_THROUGHPUT:
170 case EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:
177 MCDI_IN_POPULATE_DWORD_6(req, INIT_EVQ_IN_FLAGS,
178 INIT_EVQ_IN_FLAG_INTERRUPTING, interrupting,
179 INIT_EVQ_IN_FLAG_RPTR_DOS, 0,
180 INIT_EVQ_IN_FLAG_INT_ARMD, 0,
181 INIT_EVQ_IN_FLAG_CUT_THRU, ev_cut_through,
182 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
183 INIT_EVQ_IN_FLAG_TX_MERGE, 1);
185 /* If the value is zero then disable the timer */
187 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
188 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
189 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, 0);
190 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, 0);
194 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
197 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
198 MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF);
199 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, ticks);
200 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, ticks);
203 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_MODE,
204 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
205 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_THRSHLD, 0);
207 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_IN_DMA_ADDR);
208 addr = EFSYS_MEM_ADDR(esmp);
210 for (i = 0; i < npages; i++) {
211 EFX_POPULATE_QWORD_2(*dma_addr,
212 EFX_DWORD_1, (uint32_t)(addr >> 32),
213 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
216 addr += EFX_BUF_SIZE;
219 efx_mcdi_execute(enp, &req);
221 if (req.emr_rc != 0) {
226 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_OUT_LEN) {
231 /* NOTE: ignore the returned IRQ param as firmware does not set it. */
244 EFSYS_PROBE1(fail1, efx_rc_t, rc);
250 static __checkReturn efx_rc_t
251 efx_mcdi_init_evq_v2(
253 __in unsigned int instance,
254 __in efsys_mem_t *esmp,
261 EFX_MCDI_DECLARE_BUF(payload,
262 MC_CMD_INIT_EVQ_V2_IN_LEN(EF10_EVQ_MAXNBUFS),
263 MC_CMD_INIT_EVQ_V2_OUT_LEN);
264 boolean_t interrupting;
265 unsigned int evq_type;
266 efx_qword_t *dma_addr;
272 npages = efx_evq_nbufs(enp, nevs);
273 if (npages > EF10_EVQ_MAXNBUFS) {
278 req.emr_cmd = MC_CMD_INIT_EVQ;
279 req.emr_in_buf = payload;
280 req.emr_in_length = MC_CMD_INIT_EVQ_V2_IN_LEN(npages);
281 req.emr_out_buf = payload;
282 req.emr_out_length = MC_CMD_INIT_EVQ_V2_OUT_LEN;
284 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_SIZE, nevs);
285 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_INSTANCE, instance);
286 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_IRQ_NUM, irq);
288 interrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
289 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
291 switch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {
292 case EFX_EVQ_FLAGS_TYPE_AUTO:
293 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO;
295 case EFX_EVQ_FLAGS_TYPE_THROUGHPUT:
296 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT;
298 case EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:
299 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY;
305 MCDI_IN_POPULATE_DWORD_4(req, INIT_EVQ_V2_IN_FLAGS,
306 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, interrupting,
307 INIT_EVQ_V2_IN_FLAG_RPTR_DOS, 0,
308 INIT_EVQ_V2_IN_FLAG_INT_ARMD, 0,
309 INIT_EVQ_V2_IN_FLAG_TYPE, evq_type);
311 /* If the value is zero then disable the timer */
313 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE,
314 MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS);
315 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, 0);
316 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, 0);
320 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
323 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE,
324 MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF);
325 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, ticks);
326 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, ticks);
329 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_MODE,
330 MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS);
331 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_THRSHLD, 0);
333 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_V2_IN_DMA_ADDR);
334 addr = EFSYS_MEM_ADDR(esmp);
336 for (i = 0; i < npages; i++) {
337 EFX_POPULATE_QWORD_2(*dma_addr,
338 EFX_DWORD_1, (uint32_t)(addr >> 32),
339 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
342 addr += EFX_BUF_SIZE;
345 efx_mcdi_execute(enp, &req);
347 if (req.emr_rc != 0) {
352 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_V2_OUT_LEN) {
357 /* NOTE: ignore the returned IRQ param as firmware does not set it. */
359 EFSYS_PROBE1(mcdi_evq_flags, uint32_t,
360 MCDI_OUT_DWORD(req, INIT_EVQ_V2_OUT_FLAGS));
373 EFSYS_PROBE1(fail1, efx_rc_t, rc);
378 static __checkReturn efx_rc_t
381 __in uint32_t instance)
384 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FINI_EVQ_IN_LEN,
385 MC_CMD_FINI_EVQ_OUT_LEN);
388 req.emr_cmd = MC_CMD_FINI_EVQ;
389 req.emr_in_buf = payload;
390 req.emr_in_length = MC_CMD_FINI_EVQ_IN_LEN;
391 req.emr_out_buf = payload;
392 req.emr_out_length = MC_CMD_FINI_EVQ_OUT_LEN;
394 MCDI_IN_SET_DWORD(req, FINI_EVQ_IN_INSTANCE, instance);
396 efx_mcdi_execute_quiet(enp, &req);
398 if (req.emr_rc != 0) {
407 * EALREADY is not an error, but indicates that the MC has rebooted and
408 * that the EVQ has already been destroyed.
411 EFSYS_PROBE1(fail1, efx_rc_t, rc);
418 __checkReturn efx_rc_t
422 _NOTE(ARGUNUSED(enp))
430 _NOTE(ARGUNUSED(enp))
433 __checkReturn efx_rc_t
436 __in unsigned int index,
437 __in efsys_mem_t *esmp,
444 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
448 _NOTE(ARGUNUSED(id)) /* buftbl id managed by MC */
450 if (index >= encp->enc_evq_limit) {
455 if (us > encp->enc_evq_timer_max_us) {
460 /* Set up the handler table */
461 eep->ee_rx = ef10_ev_rx;
462 eep->ee_tx = ef10_ev_tx;
463 eep->ee_driver = ef10_ev_driver;
464 eep->ee_drv_gen = ef10_ev_drv_gen;
465 eep->ee_mcdi = ef10_ev_mcdi;
467 /* Set up the event queue */
468 /* INIT_EVQ expects function-relative vector number */
469 if ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
470 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT) {
472 } else if (index == EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX) {
474 flags = (flags & ~EFX_EVQ_FLAGS_NOTIFY_MASK) |
475 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT;
477 irq = EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX;
481 * Interrupts may be raised for events immediately after the queue is
482 * created. See bug58606.
485 if (encp->enc_init_evq_v2_supported) {
487 * On Medford the low latency license is required to enable RX
488 * and event cut through and to disable RX batching. If event
489 * queue type in flags is auto, we let the firmware decide the
490 * settings to use. If the adapter has a low latency license,
491 * it will choose the best settings for low latency, otherwise
492 * it will choose the best settings for throughput.
494 rc = efx_mcdi_init_evq_v2(enp, index, esmp, ndescs, irq, us,
500 * On Huntington we need to specify the settings to use.
501 * If event queue type in flags is auto, we favour throughput
502 * if the adapter is running virtualization supporting firmware
503 * (i.e. the full featured firmware variant)
504 * and latency otherwise. The Ethernet Virtual Bridging
505 * capability is used to make this decision. (Note though that
506 * the low latency firmware variant is also best for
507 * throughput and corresponding type should be specified
510 boolean_t low_latency = encp->enc_datapath_cap_evb ? 0 : 1;
511 rc = efx_mcdi_init_evq(enp, index, esmp, ndescs, irq, us, flags,
526 EFSYS_PROBE1(fail1, efx_rc_t, rc);
535 efx_nic_t *enp = eep->ee_enp;
537 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
538 enp->en_family == EFX_FAMILY_MEDFORD ||
539 enp->en_family == EFX_FAMILY_MEDFORD2);
541 (void) efx_mcdi_fini_evq(enp, eep->ee_index);
544 __checkReturn efx_rc_t
547 __in unsigned int count)
549 efx_nic_t *enp = eep->ee_enp;
553 rptr = count & eep->ee_mask;
555 if (enp->en_nic_cfg.enc_bug35388_workaround) {
556 EFX_STATIC_ASSERT(EF10_EVQ_MINNEVS >
557 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
558 EFX_STATIC_ASSERT(EF10_EVQ_MAXNEVS <
559 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
561 EFX_POPULATE_DWORD_2(dword,
562 ERF_DD_EVQ_IND_RPTR_FLAGS,
563 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
565 (rptr >> ERF_DD_EVQ_IND_RPTR_WIDTH));
566 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
569 EFX_POPULATE_DWORD_2(dword,
570 ERF_DD_EVQ_IND_RPTR_FLAGS,
571 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
573 rptr & ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
574 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
577 EFX_POPULATE_DWORD_1(dword, ERF_DZ_EVQ_RPTR, rptr);
578 EFX_BAR_VI_WRITED(enp, ER_DZ_EVQ_RPTR_REG, eep->ee_index,
585 static __checkReturn efx_rc_t
586 efx_mcdi_driver_event(
589 __in efx_qword_t data)
592 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_DRIVER_EVENT_IN_LEN,
593 MC_CMD_DRIVER_EVENT_OUT_LEN);
596 req.emr_cmd = MC_CMD_DRIVER_EVENT;
597 req.emr_in_buf = payload;
598 req.emr_in_length = MC_CMD_DRIVER_EVENT_IN_LEN;
599 req.emr_out_buf = payload;
600 req.emr_out_length = MC_CMD_DRIVER_EVENT_OUT_LEN;
602 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_EVQ, evq);
604 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_LO,
605 EFX_QWORD_FIELD(data, EFX_DWORD_0));
606 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_HI,
607 EFX_QWORD_FIELD(data, EFX_DWORD_1));
609 efx_mcdi_execute(enp, &req);
611 if (req.emr_rc != 0) {
619 EFSYS_PROBE1(fail1, efx_rc_t, rc);
629 efx_nic_t *enp = eep->ee_enp;
632 EFX_POPULATE_QWORD_3(event,
633 ESF_DZ_DRV_CODE, ESE_DZ_EV_CODE_DRV_GEN_EV,
634 ESF_DZ_DRV_SUB_CODE, 0,
635 ESF_DZ_DRV_SUB_DATA_DW0, (uint32_t)data);
637 (void) efx_mcdi_driver_event(enp, eep->ee_index, event);
640 __checkReturn efx_rc_t
643 __in unsigned int us)
645 efx_nic_t *enp = eep->ee_enp;
646 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
651 /* Check that hardware and MCDI use the same timer MODE values */
652 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_DIS ==
653 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS);
654 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_IMMED_START ==
655 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START);
656 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_TRIG_START ==
657 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START);
658 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_INT_HLDOFF ==
659 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF);
661 if (us > encp->enc_evq_timer_max_us) {
666 /* If the value is zero then disable the timer */
668 mode = FFE_CZ_TIMER_MODE_DIS;
670 mode = FFE_CZ_TIMER_MODE_INT_HLDOFF;
673 if (encp->enc_bug61265_workaround) {
674 uint32_t ns = us * 1000;
676 rc = efx_mcdi_set_evq_tmr(enp, eep->ee_index, mode, ns);
682 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
685 if (encp->enc_bug35388_workaround) {
686 EFX_POPULATE_DWORD_3(dword,
687 ERF_DD_EVQ_IND_TIMER_FLAGS,
688 EFE_DD_EVQ_IND_TIMER_FLAGS,
689 ERF_DD_EVQ_IND_TIMER_MODE, mode,
690 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
691 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT,
692 eep->ee_index, &dword, 0);
695 * NOTE: The TMR_REL field introduced in Medford2 is
696 * ignored on earlier EF10 controllers. See bug66418
697 * comment 9 for details.
699 EFX_POPULATE_DWORD_3(dword,
700 ERF_DZ_TC_TIMER_MODE, mode,
701 ERF_DZ_TC_TIMER_VAL, ticks,
702 ERF_FZ_TC_TMR_REL_VAL, ticks);
703 EFX_BAR_VI_WRITED(enp, ER_DZ_EVQ_TMR_REG,
704 eep->ee_index, &dword, 0);
715 EFSYS_PROBE1(fail1, efx_rc_t, rc);
723 ef10_ev_qstats_update(
725 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
729 for (id = 0; id < EV_NQSTATS; id++) {
730 efsys_stat_t *essp = &stat[id];
732 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
733 eep->ee_stat[id] = 0;
736 #endif /* EFSYS_OPT_QSTATS */
738 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
740 static __checkReturn boolean_t
741 ef10_ev_rx_packed_stream(
743 __in efx_qword_t *eqp,
744 __in const efx_ev_callbacks_t *eecp,
748 uint32_t pkt_count_lbits;
750 boolean_t should_abort;
751 efx_evq_rxq_state_t *eersp;
752 unsigned int pkt_count;
753 unsigned int current_id;
754 boolean_t new_buffer;
756 pkt_count_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
757 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
758 new_buffer = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_EV_ROTATE);
762 eersp = &eep->ee_rxq_state[label];
765 * RX_DSC_PTR_LBITS has least significant bits of the global
766 * (not per-buffer) packet counter. It is guaranteed that
767 * maximum number of completed packets fits in lbits-mask.
768 * So, modulo lbits-mask arithmetic should be used to calculate
769 * packet counter increment.
771 pkt_count = (pkt_count_lbits - eersp->eers_rx_stream_npackets) &
772 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
773 eersp->eers_rx_stream_npackets += pkt_count;
776 flags |= EFX_PKT_PACKED_STREAM_NEW_BUFFER;
777 #if EFSYS_OPT_RX_PACKED_STREAM
779 * If both packed stream and equal stride super-buffer
780 * modes are compiled in, in theory credits should be
781 * be maintained for packed stream only, but right now
782 * these modes are not distinguished in the event queue
783 * Rx queue state and it is OK to increment the counter
784 * regardless (it might be event cheaper than branching
785 * since neighbour structure member are updated as well).
787 eersp->eers_rx_packed_stream_credits++;
789 eersp->eers_rx_read_ptr++;
791 current_id = eersp->eers_rx_read_ptr & eersp->eers_rx_mask;
793 /* Check for errors that invalidate checksum and L3/L4 fields */
794 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TRUNC_ERR) != 0) {
795 /* RX frame truncated */
796 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
797 flags |= EFX_DISCARD;
800 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
801 /* Bad Ethernet frame CRC */
802 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
803 flags |= EFX_DISCARD;
807 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
808 flags |= EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE;
812 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR))
813 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
815 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR))
816 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
819 /* If we're not discarding the packet then it is ok */
820 if (~flags & EFX_DISCARD)
821 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
823 EFSYS_ASSERT(eecp->eec_rx_ps != NULL);
824 should_abort = eecp->eec_rx_ps(arg, label, current_id, pkt_count,
827 return (should_abort);
830 #endif /* EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER */
832 static __checkReturn boolean_t
835 __in efx_qword_t *eqp,
836 __in const efx_ev_callbacks_t *eecp,
839 efx_nic_t *enp = eep->ee_enp;
843 uint32_t eth_tag_class;
846 uint32_t next_read_lbits;
849 boolean_t should_abort;
850 efx_evq_rxq_state_t *eersp;
851 unsigned int desc_count;
852 unsigned int last_used_id;
854 EFX_EV_QSTAT_INCR(eep, EV_RX);
856 /* Discard events after RXQ/TXQ errors, or hardware not available */
857 if (enp->en_reset_flags &
858 (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR | EFX_RESET_HW_UNAVAIL))
861 /* Basic packet information */
862 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
863 eersp = &eep->ee_rxq_state[label];
865 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
867 * Packed stream events are very different,
868 * so handle them separately
870 if (eersp->eers_rx_packed_stream)
871 return (ef10_ev_rx_packed_stream(eep, eqp, eecp, arg));
874 size = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_BYTES);
875 cont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);
876 next_read_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
877 eth_tag_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ETH_TAG_CLASS);
878 mac_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS);
879 l3_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L3_CLASS);
882 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is only
883 * 2 bits wide on Medford2. Check it is safe to use the Medford2 field
884 * and values for all EF10 controllers.
886 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN == ESF_DE_RX_L4_CLASS_LBN);
887 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
888 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
889 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN == ESE_DE_L4_CLASS_UNKNOWN);
891 l4_class = EFX_QWORD_FIELD(*eqp, ESF_FZ_RX_L4_CLASS);
893 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DROP_EVENT) != 0) {
894 /* Drop this event */
901 * This may be part of a scattered frame, or it may be a
902 * truncated frame if scatter is disabled on this RXQ.
903 * Overlength frames can be received if e.g. a VF is configured
904 * for 1500 MTU but connected to a port set to 9000 MTU
906 * FIXME: There is not yet any driver that supports scatter on
907 * Huntington. Scatter support is required for OSX.
909 flags |= EFX_PKT_CONT;
912 if (mac_class == ESE_DZ_MAC_CLASS_UCAST)
913 flags |= EFX_PKT_UNICAST;
915 /* Increment the count of descriptors read */
916 desc_count = (next_read_lbits - eersp->eers_rx_read_ptr) &
917 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
918 eersp->eers_rx_read_ptr += desc_count;
921 * FIXME: add error checking to make sure this a batched event.
922 * This could also be an aborted scatter, see Bug36629.
924 if (desc_count > 1) {
925 EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);
926 flags |= EFX_PKT_PREFIX_LEN;
929 /* Calculate the index of the last descriptor consumed */
930 last_used_id = (eersp->eers_rx_read_ptr - 1) & eersp->eers_rx_mask;
932 /* Check for errors that invalidate checksum and L3/L4 fields */
933 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TRUNC_ERR) != 0) {
934 /* RX frame truncated */
935 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
936 flags |= EFX_DISCARD;
939 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
940 /* Bad Ethernet frame CRC */
941 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
942 flags |= EFX_DISCARD;
945 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
947 * Hardware parse failed, due to malformed headers
948 * or headers that are too long for the parser.
949 * Headers and checksums must be validated by the host.
951 /* TODO: EFX_EV_QSTAT_INCR(eep, EV_RX_PARSE_INCOMPLETE); */
955 if ((eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN1) ||
956 (eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN2)) {
957 flags |= EFX_PKT_VLAN_TAGGED;
961 case ESE_DZ_L3_CLASS_IP4:
962 case ESE_DZ_L3_CLASS_IP4_FRAG:
963 flags |= EFX_PKT_IPV4;
964 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR)) {
965 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
967 flags |= EFX_CKSUM_IPV4;
971 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
972 * only 2 bits wide on Medford2. Check it is safe to use the
973 * Medford2 field and values for all EF10 controllers.
975 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
976 ESF_DE_RX_L4_CLASS_LBN);
977 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
978 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
979 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
980 ESE_DE_L4_CLASS_UNKNOWN);
982 if (l4_class == ESE_FZ_L4_CLASS_TCP) {
983 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
984 flags |= EFX_PKT_TCP;
985 } else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
986 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
987 flags |= EFX_PKT_UDP;
989 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
993 case ESE_DZ_L3_CLASS_IP6:
994 case ESE_DZ_L3_CLASS_IP6_FRAG:
995 flags |= EFX_PKT_IPV6;
998 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
999 * only 2 bits wide on Medford2. Check it is safe to use the
1000 * Medford2 field and values for all EF10 controllers.
1002 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
1003 ESF_DE_RX_L4_CLASS_LBN);
1004 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
1005 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
1006 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
1007 ESE_DE_L4_CLASS_UNKNOWN);
1009 if (l4_class == ESE_FZ_L4_CLASS_TCP) {
1010 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
1011 flags |= EFX_PKT_TCP;
1012 } else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
1013 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
1014 flags |= EFX_PKT_UDP;
1016 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
1021 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
1025 if (flags & (EFX_PKT_TCP | EFX_PKT_UDP)) {
1026 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
1027 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
1029 flags |= EFX_CKSUM_TCPUDP;
1034 /* If we're not discarding the packet then it is ok */
1035 if (~flags & EFX_DISCARD)
1036 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
1038 EFSYS_ASSERT(eecp->eec_rx != NULL);
1039 should_abort = eecp->eec_rx(arg, label, last_used_id, size, flags);
1041 return (should_abort);
1044 static __checkReturn boolean_t
1046 __in efx_evq_t *eep,
1047 __in efx_qword_t *eqp,
1048 __in const efx_ev_callbacks_t *eecp,
1051 efx_nic_t *enp = eep->ee_enp;
1054 boolean_t should_abort;
1056 EFX_EV_QSTAT_INCR(eep, EV_TX);
1058 /* Discard events after RXQ/TXQ errors, or hardware not available */
1059 if (enp->en_reset_flags &
1060 (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR | EFX_RESET_HW_UNAVAIL))
1063 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DROP_EVENT) != 0) {
1064 /* Drop this event */
1068 /* Per-packet TX completion (was per-descriptor for Falcon/Siena) */
1069 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DESCR_INDX);
1070 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_QLABEL);
1072 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
1074 EFSYS_ASSERT(eecp->eec_tx != NULL);
1075 should_abort = eecp->eec_tx(arg, label, id);
1077 return (should_abort);
1080 static __checkReturn boolean_t
1082 __in efx_evq_t *eep,
1083 __in efx_qword_t *eqp,
1084 __in const efx_ev_callbacks_t *eecp,
1088 boolean_t should_abort;
1090 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
1091 should_abort = B_FALSE;
1093 code = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_CODE);
1095 case ESE_DZ_DRV_TIMER_EV: {
1098 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_TMR_ID);
1100 EFSYS_ASSERT(eecp->eec_timer != NULL);
1101 should_abort = eecp->eec_timer(arg, id);
1105 case ESE_DZ_DRV_WAKE_UP_EV: {
1108 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_EVQ_ID);
1110 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
1111 should_abort = eecp->eec_wake_up(arg, id);
1115 case ESE_DZ_DRV_START_UP_EV:
1116 EFSYS_ASSERT(eecp->eec_initialized != NULL);
1117 should_abort = eecp->eec_initialized(arg);
1121 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1122 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1123 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1127 return (should_abort);
1130 static __checkReturn boolean_t
1132 __in efx_evq_t *eep,
1133 __in efx_qword_t *eqp,
1134 __in const efx_ev_callbacks_t *eecp,
1138 boolean_t should_abort;
1140 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1141 should_abort = B_FALSE;
1143 data = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_DATA_DW0);
1144 if (data >= ((uint32_t)1 << 16)) {
1145 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1146 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1147 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1152 EFSYS_ASSERT(eecp->eec_software != NULL);
1153 should_abort = eecp->eec_software(arg, (uint16_t)data);
1155 return (should_abort);
1158 static __checkReturn boolean_t
1160 __in efx_evq_t *eep,
1161 __in efx_qword_t *eqp,
1162 __in const efx_ev_callbacks_t *eecp,
1165 efx_nic_t *enp = eep->ee_enp;
1167 boolean_t should_abort = B_FALSE;
1169 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1171 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1173 case MCDI_EVENT_CODE_BADSSERT:
1174 efx_mcdi_ev_death(enp, EINTR);
1177 case MCDI_EVENT_CODE_CMDDONE:
1178 efx_mcdi_ev_cpl(enp,
1179 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1180 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1181 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1184 #if EFSYS_OPT_MCDI_PROXY_AUTH
1185 case MCDI_EVENT_CODE_PROXY_RESPONSE:
1187 * This event notifies a function that an authorization request
1188 * has been processed. If the request was authorized then the
1189 * function can now re-send the original MCDI request.
1190 * See SF-113652-SW "SR-IOV Proxied Network Access Control".
1192 efx_mcdi_ev_proxy_response(enp,
1193 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_HANDLE),
1194 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_RC));
1196 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
1198 case MCDI_EVENT_CODE_LINKCHANGE: {
1199 efx_link_mode_t link_mode;
1201 ef10_phy_link_ev(enp, eqp, &link_mode);
1202 should_abort = eecp->eec_link_change(arg, link_mode);
1206 case MCDI_EVENT_CODE_SENSOREVT: {
1207 #if EFSYS_OPT_MON_STATS
1209 efx_mon_stat_value_t value;
1212 /* Decode monitor stat for MCDI sensor (if supported) */
1213 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) {
1214 /* Report monitor stat change */
1215 should_abort = eecp->eec_monitor(arg, id, value);
1216 } else if (rc == ENOTSUP) {
1217 should_abort = eecp->eec_exception(arg,
1218 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1219 MCDI_EV_FIELD(eqp, DATA));
1221 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
1227 case MCDI_EVENT_CODE_SCHEDERR:
1228 /* Informational only */
1231 case MCDI_EVENT_CODE_REBOOT:
1232 /* Falcon/Siena only (should not been seen with Huntington). */
1233 efx_mcdi_ev_death(enp, EIO);
1236 case MCDI_EVENT_CODE_MC_REBOOT:
1237 /* MC_REBOOT event is used for Huntington (EF10) and later. */
1238 efx_mcdi_ev_death(enp, EIO);
1241 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1242 #if EFSYS_OPT_MAC_STATS
1243 if (eecp->eec_mac_stats != NULL) {
1244 eecp->eec_mac_stats(arg,
1245 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1250 case MCDI_EVENT_CODE_FWALERT: {
1251 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1253 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1254 should_abort = eecp->eec_exception(arg,
1255 EFX_EXCEPTION_FWALERT_SRAM,
1256 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1258 should_abort = eecp->eec_exception(arg,
1259 EFX_EXCEPTION_UNKNOWN_FWALERT,
1260 MCDI_EV_FIELD(eqp, DATA));
1264 case MCDI_EVENT_CODE_TX_ERR: {
1266 * After a TXQ error is detected, firmware sends a TX_ERR event.
1267 * This may be followed by TX completions (which we discard),
1268 * and then finally by a TX_FLUSH event. Firmware destroys the
1269 * TXQ automatically after sending the TX_FLUSH event.
1271 enp->en_reset_flags |= EFX_RESET_TXQ_ERR;
1273 EFSYS_PROBE2(tx_descq_err,
1274 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1275 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1277 /* Inform the driver that a reset is required. */
1278 eecp->eec_exception(arg, EFX_EXCEPTION_TX_ERROR,
1279 MCDI_EV_FIELD(eqp, TX_ERR_DATA));
1283 case MCDI_EVENT_CODE_TX_FLUSH: {
1284 uint32_t txq_index = MCDI_EV_FIELD(eqp, TX_FLUSH_TXQ);
1287 * EF10 firmware sends two TX_FLUSH events: one to the txq's
1288 * event queue, and one to evq 0 (with TX_FLUSH_TO_DRIVER set).
1289 * We want to wait for all completions, so ignore the events
1290 * with TX_FLUSH_TO_DRIVER.
1292 if (MCDI_EV_FIELD(eqp, TX_FLUSH_TO_DRIVER) != 0) {
1293 should_abort = B_FALSE;
1297 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
1299 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
1301 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
1302 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
1306 case MCDI_EVENT_CODE_RX_ERR: {
1308 * After an RXQ error is detected, firmware sends an RX_ERR
1309 * event. This may be followed by RX events (which we discard),
1310 * and then finally by an RX_FLUSH event. Firmware destroys the
1311 * RXQ automatically after sending the RX_FLUSH event.
1313 enp->en_reset_flags |= EFX_RESET_RXQ_ERR;
1315 EFSYS_PROBE2(rx_descq_err,
1316 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1317 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1319 /* Inform the driver that a reset is required. */
1320 eecp->eec_exception(arg, EFX_EXCEPTION_RX_ERROR,
1321 MCDI_EV_FIELD(eqp, RX_ERR_DATA));
1325 case MCDI_EVENT_CODE_RX_FLUSH: {
1326 uint32_t rxq_index = MCDI_EV_FIELD(eqp, RX_FLUSH_RXQ);
1329 * EF10 firmware sends two RX_FLUSH events: one to the rxq's
1330 * event queue, and one to evq 0 (with RX_FLUSH_TO_DRIVER set).
1331 * We want to wait for all completions, so ignore the events
1332 * with RX_FLUSH_TO_DRIVER.
1334 if (MCDI_EV_FIELD(eqp, RX_FLUSH_TO_DRIVER) != 0) {
1335 should_abort = B_FALSE;
1339 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
1341 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
1343 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
1344 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
1349 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1350 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1351 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1355 return (should_abort);
1359 ef10_ev_rxlabel_init(
1360 __in efx_evq_t *eep,
1361 __in efx_rxq_t *erp,
1362 __in unsigned int label,
1363 __in efx_rxq_type_t type)
1365 efx_evq_rxq_state_t *eersp;
1366 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1367 boolean_t packed_stream = (type == EFX_RXQ_TYPE_PACKED_STREAM);
1368 boolean_t es_super_buffer = (type == EFX_RXQ_TYPE_ES_SUPER_BUFFER);
1371 _NOTE(ARGUNUSED(type))
1372 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1373 eersp = &eep->ee_rxq_state[label];
1375 EFSYS_ASSERT3U(eersp->eers_rx_mask, ==, 0);
1377 #if EFSYS_OPT_RX_PACKED_STREAM
1379 * For packed stream modes, the very first event will
1380 * have a new buffer flag set, so it will be incremented,
1381 * yielding the correct pointer. That results in a simpler
1382 * code than trying to detect start-of-the-world condition
1383 * in the event handler.
1385 eersp->eers_rx_read_ptr = packed_stream ? ~0 : 0;
1387 eersp->eers_rx_read_ptr = 0;
1389 eersp->eers_rx_mask = erp->er_mask;
1390 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1391 eersp->eers_rx_stream_npackets = 0;
1392 eersp->eers_rx_packed_stream = packed_stream || es_super_buffer;
1394 #if EFSYS_OPT_RX_PACKED_STREAM
1395 if (packed_stream) {
1396 eersp->eers_rx_packed_stream_credits = (eep->ee_mask + 1) /
1397 EFX_DIV_ROUND_UP(EFX_RX_PACKED_STREAM_MEM_PER_CREDIT,
1398 EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE);
1399 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, !=, 0);
1401 * A single credit is allocated to the queue when it is started.
1402 * It is immediately spent by the first packet which has NEW
1403 * BUFFER flag set, though, but still we shall take into
1404 * account, as to not wrap around the maximum number of credits
1407 eersp->eers_rx_packed_stream_credits--;
1408 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, <=,
1409 EFX_RX_PACKED_STREAM_MAX_CREDITS);
1415 ef10_ev_rxlabel_fini(
1416 __in efx_evq_t *eep,
1417 __in unsigned int label)
1419 efx_evq_rxq_state_t *eersp;
1421 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1422 eersp = &eep->ee_rxq_state[label];
1424 EFSYS_ASSERT3U(eersp->eers_rx_mask, !=, 0);
1426 eersp->eers_rx_read_ptr = 0;
1427 eersp->eers_rx_mask = 0;
1428 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1429 eersp->eers_rx_stream_npackets = 0;
1430 eersp->eers_rx_packed_stream = B_FALSE;
1432 #if EFSYS_OPT_RX_PACKED_STREAM
1433 eersp->eers_rx_packed_stream_credits = 0;
1437 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */