2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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28 * policies, either expressed or implied, of the FreeBSD Project.
33 #if EFSYS_OPT_MON_STATS
37 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
40 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
42 (_eep)->ee_stat[_stat]++; \
43 _NOTE(CONSTANTCONDITION) \
46 #define EFX_EV_QSTAT_INCR(_eep, _stat)
50 * Non-interrupting event queue requires interrrupting event queue to
51 * refer to for wake-up events even if wake ups are never used.
52 * It could be even non-allocated event queue.
54 #define EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX (0)
56 static __checkReturn boolean_t
59 __in efx_qword_t *eqp,
60 __in const efx_ev_callbacks_t *eecp,
63 static __checkReturn boolean_t
66 __in efx_qword_t *eqp,
67 __in const efx_ev_callbacks_t *eecp,
70 static __checkReturn boolean_t
73 __in efx_qword_t *eqp,
74 __in const efx_ev_callbacks_t *eecp,
77 static __checkReturn boolean_t
80 __in efx_qword_t *eqp,
81 __in const efx_ev_callbacks_t *eecp,
84 static __checkReturn boolean_t
87 __in efx_qword_t *eqp,
88 __in const efx_ev_callbacks_t *eecp,
92 static __checkReturn efx_rc_t
95 __in uint32_t instance,
97 __in uint32_t timer_ns)
100 uint8_t payload[MAX(MC_CMD_SET_EVQ_TMR_IN_LEN,
101 MC_CMD_SET_EVQ_TMR_OUT_LEN)];
104 (void) memset(payload, 0, sizeof (payload));
105 req.emr_cmd = MC_CMD_SET_EVQ_TMR;
106 req.emr_in_buf = payload;
107 req.emr_in_length = MC_CMD_SET_EVQ_TMR_IN_LEN;
108 req.emr_out_buf = payload;
109 req.emr_out_length = MC_CMD_SET_EVQ_TMR_OUT_LEN;
111 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_INSTANCE, instance);
112 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, timer_ns);
113 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, timer_ns);
114 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_MODE, mode);
116 efx_mcdi_execute(enp, &req);
118 if (req.emr_rc != 0) {
123 if (req.emr_out_length_used < MC_CMD_SET_EVQ_TMR_OUT_LEN) {
133 EFSYS_PROBE1(fail1, efx_rc_t, rc);
138 static __checkReturn efx_rc_t
141 __in unsigned int instance,
142 __in efsys_mem_t *esmp,
147 __in boolean_t low_latency)
151 MAX(MC_CMD_INIT_EVQ_IN_LEN(EFX_EVQ_NBUFS(EFX_EVQ_MAXNEVS)),
152 MC_CMD_INIT_EVQ_OUT_LEN)];
153 efx_qword_t *dma_addr;
157 boolean_t interrupting;
161 npages = EFX_EVQ_NBUFS(nevs);
162 if (MC_CMD_INIT_EVQ_IN_LEN(npages) > MC_CMD_INIT_EVQ_IN_LENMAX) {
167 (void) memset(payload, 0, sizeof (payload));
168 req.emr_cmd = MC_CMD_INIT_EVQ;
169 req.emr_in_buf = payload;
170 req.emr_in_length = MC_CMD_INIT_EVQ_IN_LEN(npages);
171 req.emr_out_buf = payload;
172 req.emr_out_length = MC_CMD_INIT_EVQ_OUT_LEN;
174 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_SIZE, nevs);
175 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_INSTANCE, instance);
176 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_IRQ_NUM, irq);
178 interrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
179 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
182 * On Huntington RX and TX event batching can only be requested together
183 * (even if the datapath firmware doesn't actually support RX
184 * batching). If event cut through is enabled no RX batching will occur.
186 * So always enable RX and TX event batching, and enable event cut
187 * through if we want low latency operation.
189 switch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {
190 case EFX_EVQ_FLAGS_TYPE_AUTO:
191 ev_cut_through = low_latency ? 1 : 0;
193 case EFX_EVQ_FLAGS_TYPE_THROUGHPUT:
196 case EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:
203 MCDI_IN_POPULATE_DWORD_6(req, INIT_EVQ_IN_FLAGS,
204 INIT_EVQ_IN_FLAG_INTERRUPTING, interrupting,
205 INIT_EVQ_IN_FLAG_RPTR_DOS, 0,
206 INIT_EVQ_IN_FLAG_INT_ARMD, 0,
207 INIT_EVQ_IN_FLAG_CUT_THRU, ev_cut_through,
208 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
209 INIT_EVQ_IN_FLAG_TX_MERGE, 1);
211 /* If the value is zero then disable the timer */
213 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
214 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
215 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, 0);
216 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, 0);
220 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
223 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
224 MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF);
225 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, ticks);
226 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, ticks);
229 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_MODE,
230 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
231 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_THRSHLD, 0);
233 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_IN_DMA_ADDR);
234 addr = EFSYS_MEM_ADDR(esmp);
236 for (i = 0; i < npages; i++) {
237 EFX_POPULATE_QWORD_2(*dma_addr,
238 EFX_DWORD_1, (uint32_t)(addr >> 32),
239 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
242 addr += EFX_BUF_SIZE;
245 efx_mcdi_execute(enp, &req);
247 if (req.emr_rc != 0) {
252 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_OUT_LEN) {
257 /* NOTE: ignore the returned IRQ param as firmware does not set it. */
270 EFSYS_PROBE1(fail1, efx_rc_t, rc);
276 static __checkReturn efx_rc_t
277 efx_mcdi_init_evq_v2(
279 __in unsigned int instance,
280 __in efsys_mem_t *esmp,
288 MAX(MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_EVQ_NBUFS(EFX_EVQ_MAXNEVS)),
289 MC_CMD_INIT_EVQ_V2_OUT_LEN)];
290 boolean_t interrupting;
291 unsigned int evq_type;
292 efx_qword_t *dma_addr;
298 npages = EFX_EVQ_NBUFS(nevs);
299 if (MC_CMD_INIT_EVQ_V2_IN_LEN(npages) > MC_CMD_INIT_EVQ_V2_IN_LENMAX) {
304 (void) memset(payload, 0, sizeof (payload));
305 req.emr_cmd = MC_CMD_INIT_EVQ;
306 req.emr_in_buf = payload;
307 req.emr_in_length = MC_CMD_INIT_EVQ_V2_IN_LEN(npages);
308 req.emr_out_buf = payload;
309 req.emr_out_length = MC_CMD_INIT_EVQ_V2_OUT_LEN;
311 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_SIZE, nevs);
312 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_INSTANCE, instance);
313 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_IRQ_NUM, irq);
315 interrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
316 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
318 switch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {
319 case EFX_EVQ_FLAGS_TYPE_AUTO:
320 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO;
322 case EFX_EVQ_FLAGS_TYPE_THROUGHPUT:
323 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT;
325 case EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:
326 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY;
332 MCDI_IN_POPULATE_DWORD_4(req, INIT_EVQ_V2_IN_FLAGS,
333 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, interrupting,
334 INIT_EVQ_V2_IN_FLAG_RPTR_DOS, 0,
335 INIT_EVQ_V2_IN_FLAG_INT_ARMD, 0,
336 INIT_EVQ_V2_IN_FLAG_TYPE, evq_type);
338 /* If the value is zero then disable the timer */
340 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE,
341 MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS);
342 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, 0);
343 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, 0);
347 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
350 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE,
351 MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF);
352 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, ticks);
353 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, ticks);
356 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_MODE,
357 MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS);
358 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_THRSHLD, 0);
360 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_V2_IN_DMA_ADDR);
361 addr = EFSYS_MEM_ADDR(esmp);
363 for (i = 0; i < npages; i++) {
364 EFX_POPULATE_QWORD_2(*dma_addr,
365 EFX_DWORD_1, (uint32_t)(addr >> 32),
366 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
369 addr += EFX_BUF_SIZE;
372 efx_mcdi_execute(enp, &req);
374 if (req.emr_rc != 0) {
379 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_V2_OUT_LEN) {
384 /* NOTE: ignore the returned IRQ param as firmware does not set it. */
386 EFSYS_PROBE1(mcdi_evq_flags, uint32_t,
387 MCDI_OUT_DWORD(req, INIT_EVQ_V2_OUT_FLAGS));
400 EFSYS_PROBE1(fail1, efx_rc_t, rc);
405 static __checkReturn efx_rc_t
408 __in uint32_t instance)
411 uint8_t payload[MAX(MC_CMD_FINI_EVQ_IN_LEN,
412 MC_CMD_FINI_EVQ_OUT_LEN)];
415 (void) memset(payload, 0, sizeof (payload));
416 req.emr_cmd = MC_CMD_FINI_EVQ;
417 req.emr_in_buf = payload;
418 req.emr_in_length = MC_CMD_FINI_EVQ_IN_LEN;
419 req.emr_out_buf = payload;
420 req.emr_out_length = MC_CMD_FINI_EVQ_OUT_LEN;
422 MCDI_IN_SET_DWORD(req, FINI_EVQ_IN_INSTANCE, instance);
424 efx_mcdi_execute_quiet(enp, &req);
426 if (req.emr_rc != 0) {
435 * EALREADY is not an error, but indicates that the MC has rebooted and
436 * that the EVQ has already been destroyed.
439 EFSYS_PROBE1(fail1, efx_rc_t, rc);
446 __checkReturn efx_rc_t
450 _NOTE(ARGUNUSED(enp))
458 _NOTE(ARGUNUSED(enp))
461 __checkReturn efx_rc_t
464 __in unsigned int index,
465 __in efsys_mem_t *esmp,
472 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
476 _NOTE(ARGUNUSED(id)) /* buftbl id managed by MC */
477 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
478 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
480 if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
485 if (index >= encp->enc_evq_limit) {
490 if (us > encp->enc_evq_timer_max_us) {
495 /* Set up the handler table */
496 eep->ee_rx = ef10_ev_rx;
497 eep->ee_tx = ef10_ev_tx;
498 eep->ee_driver = ef10_ev_driver;
499 eep->ee_drv_gen = ef10_ev_drv_gen;
500 eep->ee_mcdi = ef10_ev_mcdi;
502 /* Set up the event queue */
503 /* INIT_EVQ expects function-relative vector number */
504 if ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
505 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT) {
507 } else if (index == EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX) {
509 flags = (flags & ~EFX_EVQ_FLAGS_NOTIFY_MASK) |
510 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT;
512 irq = EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX;
516 * Interrupts may be raised for events immediately after the queue is
517 * created. See bug58606.
520 if (encp->enc_init_evq_v2_supported) {
522 * On Medford the low latency license is required to enable RX
523 * and event cut through and to disable RX batching. If event
524 * queue type in flags is auto, we let the firmware decide the
525 * settings to use. If the adapter has a low latency license,
526 * it will choose the best settings for low latency, otherwise
527 * it will choose the best settings for throughput.
529 rc = efx_mcdi_init_evq_v2(enp, index, esmp, n, irq, us, flags);
534 * On Huntington we need to specify the settings to use.
535 * If event queue type in flags is auto, we favour throughput
536 * if the adapter is running virtualization supporting firmware
537 * (i.e. the full featured firmware variant)
538 * and latency otherwise. The Ethernet Virtual Bridging
539 * capability is used to make this decision. (Note though that
540 * the low latency firmware variant is also best for
541 * throughput and corresponding type should be specified
544 boolean_t low_latency = encp->enc_datapath_cap_evb ? 0 : 1;
545 rc = efx_mcdi_init_evq(enp, index, esmp, n, irq, us, flags,
562 EFSYS_PROBE1(fail1, efx_rc_t, rc);
571 efx_nic_t *enp = eep->ee_enp;
573 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
574 enp->en_family == EFX_FAMILY_MEDFORD);
576 (void) efx_mcdi_fini_evq(eep->ee_enp, eep->ee_index);
579 __checkReturn efx_rc_t
582 __in unsigned int count)
584 efx_nic_t *enp = eep->ee_enp;
588 rptr = count & eep->ee_mask;
590 if (enp->en_nic_cfg.enc_bug35388_workaround) {
591 EFX_STATIC_ASSERT(EFX_EVQ_MINNEVS >
592 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
593 EFX_STATIC_ASSERT(EFX_EVQ_MAXNEVS <
594 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
596 EFX_POPULATE_DWORD_2(dword,
597 ERF_DD_EVQ_IND_RPTR_FLAGS,
598 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
600 (rptr >> ERF_DD_EVQ_IND_RPTR_WIDTH));
601 EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
604 EFX_POPULATE_DWORD_2(dword,
605 ERF_DD_EVQ_IND_RPTR_FLAGS,
606 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
608 rptr & ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
609 EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
612 EFX_POPULATE_DWORD_1(dword, ERF_DZ_EVQ_RPTR, rptr);
613 EFX_BAR_TBL_WRITED(enp, ER_DZ_EVQ_RPTR_REG, eep->ee_index,
620 static __checkReturn efx_rc_t
621 efx_mcdi_driver_event(
624 __in efx_qword_t data)
627 uint8_t payload[MAX(MC_CMD_DRIVER_EVENT_IN_LEN,
628 MC_CMD_DRIVER_EVENT_OUT_LEN)];
631 req.emr_cmd = MC_CMD_DRIVER_EVENT;
632 req.emr_in_buf = payload;
633 req.emr_in_length = MC_CMD_DRIVER_EVENT_IN_LEN;
634 req.emr_out_buf = payload;
635 req.emr_out_length = MC_CMD_DRIVER_EVENT_OUT_LEN;
637 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_EVQ, evq);
639 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_LO,
640 EFX_QWORD_FIELD(data, EFX_DWORD_0));
641 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_HI,
642 EFX_QWORD_FIELD(data, EFX_DWORD_1));
644 efx_mcdi_execute(enp, &req);
646 if (req.emr_rc != 0) {
654 EFSYS_PROBE1(fail1, efx_rc_t, rc);
664 efx_nic_t *enp = eep->ee_enp;
667 EFX_POPULATE_QWORD_3(event,
668 ESF_DZ_DRV_CODE, ESE_DZ_EV_CODE_DRV_GEN_EV,
669 ESF_DZ_DRV_SUB_CODE, 0,
670 ESF_DZ_DRV_SUB_DATA_DW0, (uint32_t)data);
672 (void) efx_mcdi_driver_event(enp, eep->ee_index, event);
675 __checkReturn efx_rc_t
678 __in unsigned int us)
680 efx_nic_t *enp = eep->ee_enp;
681 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
686 /* Check that hardware and MCDI use the same timer MODE values */
687 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_DIS ==
688 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS);
689 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_IMMED_START ==
690 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START);
691 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_TRIG_START ==
692 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START);
693 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_INT_HLDOFF ==
694 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF);
696 if (us > encp->enc_evq_timer_max_us) {
701 /* If the value is zero then disable the timer */
703 mode = FFE_CZ_TIMER_MODE_DIS;
705 mode = FFE_CZ_TIMER_MODE_INT_HLDOFF;
708 if (encp->enc_bug61265_workaround) {
709 uint32_t ns = us * 1000;
711 rc = efx_mcdi_set_evq_tmr(enp, eep->ee_index, mode, ns);
717 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
720 if (encp->enc_bug35388_workaround) {
721 EFX_POPULATE_DWORD_3(dword,
722 ERF_DD_EVQ_IND_TIMER_FLAGS,
723 EFE_DD_EVQ_IND_TIMER_FLAGS,
724 ERF_DD_EVQ_IND_TIMER_MODE, mode,
725 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
726 EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT,
727 eep->ee_index, &dword, 0);
729 EFX_POPULATE_DWORD_2(dword,
730 ERF_DZ_TC_TIMER_MODE, mode,
731 ERF_DZ_TC_TIMER_VAL, ticks);
732 EFX_BAR_TBL_WRITED(enp, ER_DZ_EVQ_TMR_REG,
733 eep->ee_index, &dword, 0);
744 EFSYS_PROBE1(fail1, efx_rc_t, rc);
752 ef10_ev_qstats_update(
754 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
758 for (id = 0; id < EV_NQSTATS; id++) {
759 efsys_stat_t *essp = &stat[id];
761 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
762 eep->ee_stat[id] = 0;
765 #endif /* EFSYS_OPT_QSTATS */
767 #if EFSYS_OPT_RX_PACKED_STREAM
769 static __checkReturn boolean_t
770 ef10_ev_rx_packed_stream(
772 __in efx_qword_t *eqp,
773 __in const efx_ev_callbacks_t *eecp,
777 uint32_t pkt_count_lbits;
779 boolean_t should_abort;
780 efx_evq_rxq_state_t *eersp;
781 unsigned int pkt_count;
782 unsigned int current_id;
783 boolean_t new_buffer;
785 pkt_count_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
786 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
787 new_buffer = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_EV_ROTATE);
791 eersp = &eep->ee_rxq_state[label];
794 * RX_DSC_PTR_LBITS has least significant bits of the global
795 * (not per-buffer) packet counter. It is guaranteed that
796 * maximum number of completed packets fits in lbits-mask.
797 * So, modulo lbits-mask arithmetic should be used to calculate
798 * packet counter increment.
800 pkt_count = (pkt_count_lbits - eersp->eers_rx_stream_npackets) &
801 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
802 eersp->eers_rx_stream_npackets += pkt_count;
805 flags |= EFX_PKT_PACKED_STREAM_NEW_BUFFER;
806 eersp->eers_rx_packed_stream_credits++;
807 eersp->eers_rx_read_ptr++;
809 current_id = eersp->eers_rx_read_ptr & eersp->eers_rx_mask;
811 /* Check for errors that invalidate checksum and L3/L4 fields */
812 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECC_ERR) != 0) {
813 /* RX frame truncated (error flag is misnamed) */
814 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
815 flags |= EFX_DISCARD;
818 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
819 /* Bad Ethernet frame CRC */
820 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
821 flags |= EFX_DISCARD;
825 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
826 flags |= EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE;
830 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR))
831 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
833 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR))
834 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
837 /* If we're not discarding the packet then it is ok */
838 if (~flags & EFX_DISCARD)
839 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
841 EFSYS_ASSERT(eecp->eec_rx_ps != NULL);
842 should_abort = eecp->eec_rx_ps(arg, label, current_id, pkt_count,
845 return (should_abort);
848 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
850 static __checkReturn boolean_t
853 __in efx_qword_t *eqp,
854 __in const efx_ev_callbacks_t *eecp,
857 efx_nic_t *enp = eep->ee_enp;
861 uint32_t eth_tag_class;
864 uint32_t next_read_lbits;
867 boolean_t should_abort;
868 efx_evq_rxq_state_t *eersp;
869 unsigned int desc_count;
870 unsigned int last_used_id;
872 EFX_EV_QSTAT_INCR(eep, EV_RX);
874 /* Discard events after RXQ/TXQ errors */
875 if (enp->en_reset_flags & (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR))
878 /* Basic packet information */
879 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
880 eersp = &eep->ee_rxq_state[label];
882 #if EFSYS_OPT_RX_PACKED_STREAM
884 * Packed stream events are very different,
885 * so handle them separately
887 if (eersp->eers_rx_packed_stream)
888 return (ef10_ev_rx_packed_stream(eep, eqp, eecp, arg));
891 size = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_BYTES);
892 next_read_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
893 eth_tag_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ETH_TAG_CLASS);
894 mac_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS);
895 l3_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L3_CLASS);
896 l4_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L4_CLASS);
897 cont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);
899 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DROP_EVENT) != 0) {
900 /* Drop this event */
907 * This may be part of a scattered frame, or it may be a
908 * truncated frame if scatter is disabled on this RXQ.
909 * Overlength frames can be received if e.g. a VF is configured
910 * for 1500 MTU but connected to a port set to 9000 MTU
912 * FIXME: There is not yet any driver that supports scatter on
913 * Huntington. Scatter support is required for OSX.
915 flags |= EFX_PKT_CONT;
918 if (mac_class == ESE_DZ_MAC_CLASS_UCAST)
919 flags |= EFX_PKT_UNICAST;
921 /* Increment the count of descriptors read */
922 desc_count = (next_read_lbits - eersp->eers_rx_read_ptr) &
923 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
924 eersp->eers_rx_read_ptr += desc_count;
927 * FIXME: add error checking to make sure this a batched event.
928 * This could also be an aborted scatter, see Bug36629.
930 if (desc_count > 1) {
931 EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);
932 flags |= EFX_PKT_PREFIX_LEN;
935 /* Calculate the index of the last descriptor consumed */
936 last_used_id = (eersp->eers_rx_read_ptr - 1) & eersp->eers_rx_mask;
938 /* Check for errors that invalidate checksum and L3/L4 fields */
939 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECC_ERR) != 0) {
940 /* RX frame truncated (error flag is misnamed) */
941 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
942 flags |= EFX_DISCARD;
945 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
946 /* Bad Ethernet frame CRC */
947 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
948 flags |= EFX_DISCARD;
951 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
953 * Hardware parse failed, due to malformed headers
954 * or headers that are too long for the parser.
955 * Headers and checksums must be validated by the host.
957 /* TODO: EFX_EV_QSTAT_INCR(eep, EV_RX_PARSE_INCOMPLETE); */
961 if ((eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN1) ||
962 (eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN2)) {
963 flags |= EFX_PKT_VLAN_TAGGED;
967 case ESE_DZ_L3_CLASS_IP4:
968 case ESE_DZ_L3_CLASS_IP4_FRAG:
969 flags |= EFX_PKT_IPV4;
970 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR)) {
971 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
973 flags |= EFX_CKSUM_IPV4;
976 if (l4_class == ESE_DZ_L4_CLASS_TCP) {
977 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
978 flags |= EFX_PKT_TCP;
979 } else if (l4_class == ESE_DZ_L4_CLASS_UDP) {
980 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
981 flags |= EFX_PKT_UDP;
983 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
987 case ESE_DZ_L3_CLASS_IP6:
988 case ESE_DZ_L3_CLASS_IP6_FRAG:
989 flags |= EFX_PKT_IPV6;
991 if (l4_class == ESE_DZ_L4_CLASS_TCP) {
992 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
993 flags |= EFX_PKT_TCP;
994 } else if (l4_class == ESE_DZ_L4_CLASS_UDP) {
995 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
996 flags |= EFX_PKT_UDP;
998 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
1003 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
1007 if (flags & (EFX_PKT_TCP | EFX_PKT_UDP)) {
1008 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
1009 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
1011 flags |= EFX_CKSUM_TCPUDP;
1016 /* If we're not discarding the packet then it is ok */
1017 if (~flags & EFX_DISCARD)
1018 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
1020 EFSYS_ASSERT(eecp->eec_rx != NULL);
1021 should_abort = eecp->eec_rx(arg, label, last_used_id, size, flags);
1023 return (should_abort);
1026 static __checkReturn boolean_t
1028 __in efx_evq_t *eep,
1029 __in efx_qword_t *eqp,
1030 __in const efx_ev_callbacks_t *eecp,
1033 efx_nic_t *enp = eep->ee_enp;
1036 boolean_t should_abort;
1038 EFX_EV_QSTAT_INCR(eep, EV_TX);
1040 /* Discard events after RXQ/TXQ errors */
1041 if (enp->en_reset_flags & (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR))
1044 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DROP_EVENT) != 0) {
1045 /* Drop this event */
1049 /* Per-packet TX completion (was per-descriptor for Falcon/Siena) */
1050 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DESCR_INDX);
1051 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_QLABEL);
1053 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
1055 EFSYS_ASSERT(eecp->eec_tx != NULL);
1056 should_abort = eecp->eec_tx(arg, label, id);
1058 return (should_abort);
1061 static __checkReturn boolean_t
1063 __in efx_evq_t *eep,
1064 __in efx_qword_t *eqp,
1065 __in const efx_ev_callbacks_t *eecp,
1069 boolean_t should_abort;
1071 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
1072 should_abort = B_FALSE;
1074 code = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_CODE);
1076 case ESE_DZ_DRV_TIMER_EV: {
1079 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_TMR_ID);
1081 EFSYS_ASSERT(eecp->eec_timer != NULL);
1082 should_abort = eecp->eec_timer(arg, id);
1086 case ESE_DZ_DRV_WAKE_UP_EV: {
1089 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_EVQ_ID);
1091 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
1092 should_abort = eecp->eec_wake_up(arg, id);
1096 case ESE_DZ_DRV_START_UP_EV:
1097 EFSYS_ASSERT(eecp->eec_initialized != NULL);
1098 should_abort = eecp->eec_initialized(arg);
1102 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1103 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1104 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1108 return (should_abort);
1111 static __checkReturn boolean_t
1113 __in efx_evq_t *eep,
1114 __in efx_qword_t *eqp,
1115 __in const efx_ev_callbacks_t *eecp,
1119 boolean_t should_abort;
1121 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1122 should_abort = B_FALSE;
1124 data = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_DATA_DW0);
1125 if (data >= ((uint32_t)1 << 16)) {
1126 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1127 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1128 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1133 EFSYS_ASSERT(eecp->eec_software != NULL);
1134 should_abort = eecp->eec_software(arg, (uint16_t)data);
1136 return (should_abort);
1139 static __checkReturn boolean_t
1141 __in efx_evq_t *eep,
1142 __in efx_qword_t *eqp,
1143 __in const efx_ev_callbacks_t *eecp,
1146 efx_nic_t *enp = eep->ee_enp;
1148 boolean_t should_abort = B_FALSE;
1150 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1152 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1154 case MCDI_EVENT_CODE_BADSSERT:
1155 efx_mcdi_ev_death(enp, EINTR);
1158 case MCDI_EVENT_CODE_CMDDONE:
1159 efx_mcdi_ev_cpl(enp,
1160 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1161 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1162 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1165 #if EFSYS_OPT_MCDI_PROXY_AUTH
1166 case MCDI_EVENT_CODE_PROXY_RESPONSE:
1168 * This event notifies a function that an authorization request
1169 * has been processed. If the request was authorized then the
1170 * function can now re-send the original MCDI request.
1171 * See SF-113652-SW "SR-IOV Proxied Network Access Control".
1173 efx_mcdi_ev_proxy_response(enp,
1174 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_HANDLE),
1175 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_RC));
1177 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
1179 case MCDI_EVENT_CODE_LINKCHANGE: {
1180 efx_link_mode_t link_mode;
1182 ef10_phy_link_ev(enp, eqp, &link_mode);
1183 should_abort = eecp->eec_link_change(arg, link_mode);
1187 case MCDI_EVENT_CODE_SENSOREVT: {
1188 #if EFSYS_OPT_MON_STATS
1190 efx_mon_stat_value_t value;
1193 /* Decode monitor stat for MCDI sensor (if supported) */
1194 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) {
1195 /* Report monitor stat change */
1196 should_abort = eecp->eec_monitor(arg, id, value);
1197 } else if (rc == ENOTSUP) {
1198 should_abort = eecp->eec_exception(arg,
1199 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1200 MCDI_EV_FIELD(eqp, DATA));
1202 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
1208 case MCDI_EVENT_CODE_SCHEDERR:
1209 /* Informational only */
1212 case MCDI_EVENT_CODE_REBOOT:
1213 /* Falcon/Siena only (should not been seen with Huntington). */
1214 efx_mcdi_ev_death(enp, EIO);
1217 case MCDI_EVENT_CODE_MC_REBOOT:
1218 /* MC_REBOOT event is used for Huntington (EF10) and later. */
1219 efx_mcdi_ev_death(enp, EIO);
1222 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1223 #if EFSYS_OPT_MAC_STATS
1224 if (eecp->eec_mac_stats != NULL) {
1225 eecp->eec_mac_stats(arg,
1226 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1231 case MCDI_EVENT_CODE_FWALERT: {
1232 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1234 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1235 should_abort = eecp->eec_exception(arg,
1236 EFX_EXCEPTION_FWALERT_SRAM,
1237 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1239 should_abort = eecp->eec_exception(arg,
1240 EFX_EXCEPTION_UNKNOWN_FWALERT,
1241 MCDI_EV_FIELD(eqp, DATA));
1245 case MCDI_EVENT_CODE_TX_ERR: {
1247 * After a TXQ error is detected, firmware sends a TX_ERR event.
1248 * This may be followed by TX completions (which we discard),
1249 * and then finally by a TX_FLUSH event. Firmware destroys the
1250 * TXQ automatically after sending the TX_FLUSH event.
1252 enp->en_reset_flags |= EFX_RESET_TXQ_ERR;
1254 EFSYS_PROBE2(tx_descq_err,
1255 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1256 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1258 /* Inform the driver that a reset is required. */
1259 eecp->eec_exception(arg, EFX_EXCEPTION_TX_ERROR,
1260 MCDI_EV_FIELD(eqp, TX_ERR_DATA));
1264 case MCDI_EVENT_CODE_TX_FLUSH: {
1265 uint32_t txq_index = MCDI_EV_FIELD(eqp, TX_FLUSH_TXQ);
1268 * EF10 firmware sends two TX_FLUSH events: one to the txq's
1269 * event queue, and one to evq 0 (with TX_FLUSH_TO_DRIVER set).
1270 * We want to wait for all completions, so ignore the events
1271 * with TX_FLUSH_TO_DRIVER.
1273 if (MCDI_EV_FIELD(eqp, TX_FLUSH_TO_DRIVER) != 0) {
1274 should_abort = B_FALSE;
1278 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
1280 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
1282 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
1283 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
1287 case MCDI_EVENT_CODE_RX_ERR: {
1289 * After an RXQ error is detected, firmware sends an RX_ERR
1290 * event. This may be followed by RX events (which we discard),
1291 * and then finally by an RX_FLUSH event. Firmware destroys the
1292 * RXQ automatically after sending the RX_FLUSH event.
1294 enp->en_reset_flags |= EFX_RESET_RXQ_ERR;
1296 EFSYS_PROBE2(rx_descq_err,
1297 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1298 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1300 /* Inform the driver that a reset is required. */
1301 eecp->eec_exception(arg, EFX_EXCEPTION_RX_ERROR,
1302 MCDI_EV_FIELD(eqp, RX_ERR_DATA));
1306 case MCDI_EVENT_CODE_RX_FLUSH: {
1307 uint32_t rxq_index = MCDI_EV_FIELD(eqp, RX_FLUSH_RXQ);
1310 * EF10 firmware sends two RX_FLUSH events: one to the rxq's
1311 * event queue, and one to evq 0 (with RX_FLUSH_TO_DRIVER set).
1312 * We want to wait for all completions, so ignore the events
1313 * with RX_FLUSH_TO_DRIVER.
1315 if (MCDI_EV_FIELD(eqp, RX_FLUSH_TO_DRIVER) != 0) {
1316 should_abort = B_FALSE;
1320 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
1322 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
1324 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
1325 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
1330 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1331 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1332 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1336 return (should_abort);
1340 ef10_ev_rxlabel_init(
1341 __in efx_evq_t *eep,
1342 __in efx_rxq_t *erp,
1343 __in unsigned int label,
1344 __in efx_rxq_type_t type)
1346 efx_evq_rxq_state_t *eersp;
1347 boolean_t packed_stream = (type >= EFX_RXQ_TYPE_PACKED_STREAM_1M) &&
1348 (type <= EFX_RXQ_TYPE_PACKED_STREAM_64K);
1350 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1351 eersp = &eep->ee_rxq_state[label];
1353 EFSYS_ASSERT3U(eersp->eers_rx_mask, ==, 0);
1355 #if EFSYS_OPT_RX_PACKED_STREAM
1357 * For packed stream modes, the very first event will
1358 * have a new buffer flag set, so it will be incremented,
1359 * yielding the correct pointer. That results in a simpler
1360 * code than trying to detect start-of-the-world condition
1361 * in the event handler.
1363 eersp->eers_rx_read_ptr = packed_stream ? ~0 : 0;
1365 eersp->eers_rx_read_ptr = 0;
1367 eersp->eers_rx_mask = erp->er_mask;
1368 #if EFSYS_OPT_RX_PACKED_STREAM
1369 eersp->eers_rx_stream_npackets = 0;
1370 eersp->eers_rx_packed_stream = packed_stream;
1371 if (packed_stream) {
1372 eersp->eers_rx_packed_stream_credits = (eep->ee_mask + 1) /
1373 (EFX_RX_PACKED_STREAM_MEM_PER_CREDIT /
1374 EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE);
1375 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, !=, 0);
1377 * A single credit is allocated to the queue when it is started.
1378 * It is immediately spent by the first packet which has NEW
1379 * BUFFER flag set, though, but still we shall take into
1380 * account, as to not wrap around the maximum number of credits
1383 eersp->eers_rx_packed_stream_credits--;
1384 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, <=,
1385 EFX_RX_PACKED_STREAM_MAX_CREDITS);
1388 EFSYS_ASSERT(!packed_stream);
1393 ef10_ev_rxlabel_fini(
1394 __in efx_evq_t *eep,
1395 __in unsigned int label)
1397 efx_evq_rxq_state_t *eersp;
1399 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1400 eersp = &eep->ee_rxq_state[label];
1402 EFSYS_ASSERT3U(eersp->eers_rx_mask, !=, 0);
1404 eersp->eers_rx_read_ptr = 0;
1405 eersp->eers_rx_mask = 0;
1406 #if EFSYS_OPT_RX_PACKED_STREAM
1407 eersp->eers_rx_stream_npackets = 0;
1408 eersp->eers_rx_packed_stream = B_FALSE;
1409 eersp->eers_rx_packed_stream_credits = 0;
1413 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */