1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
9 #if EFSYS_OPT_MON_STATS
13 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
16 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
18 (_eep)->ee_stat[_stat]++; \
19 _NOTE(CONSTANTCONDITION) \
22 #define EFX_EV_QSTAT_INCR(_eep, _stat)
26 * Non-interrupting event queue requires interrrupting event queue to
27 * refer to for wake-up events even if wake ups are never used.
28 * It could be even non-allocated event queue.
30 #define EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX (0)
32 static __checkReturn boolean_t
35 __in efx_qword_t *eqp,
36 __in const efx_ev_callbacks_t *eecp,
39 static __checkReturn boolean_t
42 __in efx_qword_t *eqp,
43 __in const efx_ev_callbacks_t *eecp,
46 static __checkReturn boolean_t
49 __in efx_qword_t *eqp,
50 __in const efx_ev_callbacks_t *eecp,
53 static __checkReturn boolean_t
56 __in efx_qword_t *eqp,
57 __in const efx_ev_callbacks_t *eecp,
60 static __checkReturn boolean_t
63 __in efx_qword_t *eqp,
64 __in const efx_ev_callbacks_t *eecp,
68 static __checkReturn efx_rc_t
71 __in uint32_t instance,
73 __in uint32_t timer_ns)
76 uint8_t payload[MAX(MC_CMD_SET_EVQ_TMR_IN_LEN,
77 MC_CMD_SET_EVQ_TMR_OUT_LEN)];
80 (void) memset(payload, 0, sizeof (payload));
81 req.emr_cmd = MC_CMD_SET_EVQ_TMR;
82 req.emr_in_buf = payload;
83 req.emr_in_length = MC_CMD_SET_EVQ_TMR_IN_LEN;
84 req.emr_out_buf = payload;
85 req.emr_out_length = MC_CMD_SET_EVQ_TMR_OUT_LEN;
87 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_INSTANCE, instance);
88 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, timer_ns);
89 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, timer_ns);
90 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_MODE, mode);
92 efx_mcdi_execute(enp, &req);
94 if (req.emr_rc != 0) {
99 if (req.emr_out_length_used < MC_CMD_SET_EVQ_TMR_OUT_LEN) {
109 EFSYS_PROBE1(fail1, efx_rc_t, rc);
114 static __checkReturn efx_rc_t
117 __in unsigned int instance,
118 __in efsys_mem_t *esmp,
123 __in boolean_t low_latency)
127 MAX(MC_CMD_INIT_EVQ_IN_LEN(EFX_EVQ_NBUFS(EFX_EVQ_MAXNEVS)),
128 MC_CMD_INIT_EVQ_OUT_LEN)];
129 efx_qword_t *dma_addr;
133 boolean_t interrupting;
137 npages = EFX_EVQ_NBUFS(nevs);
138 if (MC_CMD_INIT_EVQ_IN_LEN(npages) > MC_CMD_INIT_EVQ_IN_LENMAX) {
143 (void) memset(payload, 0, sizeof (payload));
144 req.emr_cmd = MC_CMD_INIT_EVQ;
145 req.emr_in_buf = payload;
146 req.emr_in_length = MC_CMD_INIT_EVQ_IN_LEN(npages);
147 req.emr_out_buf = payload;
148 req.emr_out_length = MC_CMD_INIT_EVQ_OUT_LEN;
150 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_SIZE, nevs);
151 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_INSTANCE, instance);
152 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_IRQ_NUM, irq);
154 interrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
155 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
158 * On Huntington RX and TX event batching can only be requested together
159 * (even if the datapath firmware doesn't actually support RX
160 * batching). If event cut through is enabled no RX batching will occur.
162 * So always enable RX and TX event batching, and enable event cut
163 * through if we want low latency operation.
165 switch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {
166 case EFX_EVQ_FLAGS_TYPE_AUTO:
167 ev_cut_through = low_latency ? 1 : 0;
169 case EFX_EVQ_FLAGS_TYPE_THROUGHPUT:
172 case EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:
179 MCDI_IN_POPULATE_DWORD_6(req, INIT_EVQ_IN_FLAGS,
180 INIT_EVQ_IN_FLAG_INTERRUPTING, interrupting,
181 INIT_EVQ_IN_FLAG_RPTR_DOS, 0,
182 INIT_EVQ_IN_FLAG_INT_ARMD, 0,
183 INIT_EVQ_IN_FLAG_CUT_THRU, ev_cut_through,
184 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
185 INIT_EVQ_IN_FLAG_TX_MERGE, 1);
187 /* If the value is zero then disable the timer */
189 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
190 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
191 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, 0);
192 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, 0);
196 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
199 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
200 MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF);
201 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, ticks);
202 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, ticks);
205 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_MODE,
206 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
207 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_THRSHLD, 0);
209 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_IN_DMA_ADDR);
210 addr = EFSYS_MEM_ADDR(esmp);
212 for (i = 0; i < npages; i++) {
213 EFX_POPULATE_QWORD_2(*dma_addr,
214 EFX_DWORD_1, (uint32_t)(addr >> 32),
215 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
218 addr += EFX_BUF_SIZE;
221 efx_mcdi_execute(enp, &req);
223 if (req.emr_rc != 0) {
228 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_OUT_LEN) {
233 /* NOTE: ignore the returned IRQ param as firmware does not set it. */
246 EFSYS_PROBE1(fail1, efx_rc_t, rc);
252 static __checkReturn efx_rc_t
253 efx_mcdi_init_evq_v2(
255 __in unsigned int instance,
256 __in efsys_mem_t *esmp,
264 MAX(MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_EVQ_NBUFS(EFX_EVQ_MAXNEVS)),
265 MC_CMD_INIT_EVQ_V2_OUT_LEN)];
266 boolean_t interrupting;
267 unsigned int evq_type;
268 efx_qword_t *dma_addr;
274 npages = EFX_EVQ_NBUFS(nevs);
275 if (MC_CMD_INIT_EVQ_V2_IN_LEN(npages) > MC_CMD_INIT_EVQ_V2_IN_LENMAX) {
280 (void) memset(payload, 0, sizeof (payload));
281 req.emr_cmd = MC_CMD_INIT_EVQ;
282 req.emr_in_buf = payload;
283 req.emr_in_length = MC_CMD_INIT_EVQ_V2_IN_LEN(npages);
284 req.emr_out_buf = payload;
285 req.emr_out_length = MC_CMD_INIT_EVQ_V2_OUT_LEN;
287 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_SIZE, nevs);
288 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_INSTANCE, instance);
289 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_IRQ_NUM, irq);
291 interrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
292 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
294 switch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {
295 case EFX_EVQ_FLAGS_TYPE_AUTO:
296 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO;
298 case EFX_EVQ_FLAGS_TYPE_THROUGHPUT:
299 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT;
301 case EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:
302 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY;
308 MCDI_IN_POPULATE_DWORD_4(req, INIT_EVQ_V2_IN_FLAGS,
309 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, interrupting,
310 INIT_EVQ_V2_IN_FLAG_RPTR_DOS, 0,
311 INIT_EVQ_V2_IN_FLAG_INT_ARMD, 0,
312 INIT_EVQ_V2_IN_FLAG_TYPE, evq_type);
314 /* If the value is zero then disable the timer */
316 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE,
317 MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS);
318 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, 0);
319 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, 0);
323 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
326 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE,
327 MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF);
328 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, ticks);
329 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, ticks);
332 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_MODE,
333 MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS);
334 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_THRSHLD, 0);
336 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_V2_IN_DMA_ADDR);
337 addr = EFSYS_MEM_ADDR(esmp);
339 for (i = 0; i < npages; i++) {
340 EFX_POPULATE_QWORD_2(*dma_addr,
341 EFX_DWORD_1, (uint32_t)(addr >> 32),
342 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
345 addr += EFX_BUF_SIZE;
348 efx_mcdi_execute(enp, &req);
350 if (req.emr_rc != 0) {
355 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_V2_OUT_LEN) {
360 /* NOTE: ignore the returned IRQ param as firmware does not set it. */
362 EFSYS_PROBE1(mcdi_evq_flags, uint32_t,
363 MCDI_OUT_DWORD(req, INIT_EVQ_V2_OUT_FLAGS));
376 EFSYS_PROBE1(fail1, efx_rc_t, rc);
381 static __checkReturn efx_rc_t
384 __in uint32_t instance)
387 uint8_t payload[MAX(MC_CMD_FINI_EVQ_IN_LEN,
388 MC_CMD_FINI_EVQ_OUT_LEN)];
391 (void) memset(payload, 0, sizeof (payload));
392 req.emr_cmd = MC_CMD_FINI_EVQ;
393 req.emr_in_buf = payload;
394 req.emr_in_length = MC_CMD_FINI_EVQ_IN_LEN;
395 req.emr_out_buf = payload;
396 req.emr_out_length = MC_CMD_FINI_EVQ_OUT_LEN;
398 MCDI_IN_SET_DWORD(req, FINI_EVQ_IN_INSTANCE, instance);
400 efx_mcdi_execute_quiet(enp, &req);
402 if (req.emr_rc != 0) {
411 * EALREADY is not an error, but indicates that the MC has rebooted and
412 * that the EVQ has already been destroyed.
415 EFSYS_PROBE1(fail1, efx_rc_t, rc);
422 __checkReturn efx_rc_t
426 _NOTE(ARGUNUSED(enp))
434 _NOTE(ARGUNUSED(enp))
437 __checkReturn efx_rc_t
440 __in unsigned int index,
441 __in efsys_mem_t *esmp,
448 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
452 _NOTE(ARGUNUSED(id)) /* buftbl id managed by MC */
453 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
454 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
457 (ndescs < EFX_EVQ_MINNEVS) || (ndescs > EFX_EVQ_MAXNEVS)) {
462 if (index >= encp->enc_evq_limit) {
467 if (us > encp->enc_evq_timer_max_us) {
472 /* Set up the handler table */
473 eep->ee_rx = ef10_ev_rx;
474 eep->ee_tx = ef10_ev_tx;
475 eep->ee_driver = ef10_ev_driver;
476 eep->ee_drv_gen = ef10_ev_drv_gen;
477 eep->ee_mcdi = ef10_ev_mcdi;
479 /* Set up the event queue */
480 /* INIT_EVQ expects function-relative vector number */
481 if ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
482 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT) {
484 } else if (index == EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX) {
486 flags = (flags & ~EFX_EVQ_FLAGS_NOTIFY_MASK) |
487 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT;
489 irq = EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX;
493 * Interrupts may be raised for events immediately after the queue is
494 * created. See bug58606.
497 if (encp->enc_init_evq_v2_supported) {
499 * On Medford the low latency license is required to enable RX
500 * and event cut through and to disable RX batching. If event
501 * queue type in flags is auto, we let the firmware decide the
502 * settings to use. If the adapter has a low latency license,
503 * it will choose the best settings for low latency, otherwise
504 * it will choose the best settings for throughput.
506 rc = efx_mcdi_init_evq_v2(enp, index, esmp, ndescs, irq, us,
512 * On Huntington we need to specify the settings to use.
513 * If event queue type in flags is auto, we favour throughput
514 * if the adapter is running virtualization supporting firmware
515 * (i.e. the full featured firmware variant)
516 * and latency otherwise. The Ethernet Virtual Bridging
517 * capability is used to make this decision. (Note though that
518 * the low latency firmware variant is also best for
519 * throughput and corresponding type should be specified
522 boolean_t low_latency = encp->enc_datapath_cap_evb ? 0 : 1;
523 rc = efx_mcdi_init_evq(enp, index, esmp, ndescs, irq, us, flags,
540 EFSYS_PROBE1(fail1, efx_rc_t, rc);
549 efx_nic_t *enp = eep->ee_enp;
551 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
552 enp->en_family == EFX_FAMILY_MEDFORD ||
553 enp->en_family == EFX_FAMILY_MEDFORD2);
555 (void) efx_mcdi_fini_evq(enp, eep->ee_index);
558 __checkReturn efx_rc_t
561 __in unsigned int count)
563 efx_nic_t *enp = eep->ee_enp;
567 rptr = count & eep->ee_mask;
569 if (enp->en_nic_cfg.enc_bug35388_workaround) {
570 EFX_STATIC_ASSERT(EFX_EVQ_MINNEVS >
571 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
572 EFX_STATIC_ASSERT(EFX_EVQ_MAXNEVS <
573 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
575 EFX_POPULATE_DWORD_2(dword,
576 ERF_DD_EVQ_IND_RPTR_FLAGS,
577 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
579 (rptr >> ERF_DD_EVQ_IND_RPTR_WIDTH));
580 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
583 EFX_POPULATE_DWORD_2(dword,
584 ERF_DD_EVQ_IND_RPTR_FLAGS,
585 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
587 rptr & ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
588 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
591 EFX_POPULATE_DWORD_1(dword, ERF_DZ_EVQ_RPTR, rptr);
592 EFX_BAR_VI_WRITED(enp, ER_DZ_EVQ_RPTR_REG, eep->ee_index,
599 static __checkReturn efx_rc_t
600 efx_mcdi_driver_event(
603 __in efx_qword_t data)
606 uint8_t payload[MAX(MC_CMD_DRIVER_EVENT_IN_LEN,
607 MC_CMD_DRIVER_EVENT_OUT_LEN)];
610 req.emr_cmd = MC_CMD_DRIVER_EVENT;
611 req.emr_in_buf = payload;
612 req.emr_in_length = MC_CMD_DRIVER_EVENT_IN_LEN;
613 req.emr_out_buf = payload;
614 req.emr_out_length = MC_CMD_DRIVER_EVENT_OUT_LEN;
616 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_EVQ, evq);
618 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_LO,
619 EFX_QWORD_FIELD(data, EFX_DWORD_0));
620 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_HI,
621 EFX_QWORD_FIELD(data, EFX_DWORD_1));
623 efx_mcdi_execute(enp, &req);
625 if (req.emr_rc != 0) {
633 EFSYS_PROBE1(fail1, efx_rc_t, rc);
643 efx_nic_t *enp = eep->ee_enp;
646 EFX_POPULATE_QWORD_3(event,
647 ESF_DZ_DRV_CODE, ESE_DZ_EV_CODE_DRV_GEN_EV,
648 ESF_DZ_DRV_SUB_CODE, 0,
649 ESF_DZ_DRV_SUB_DATA_DW0, (uint32_t)data);
651 (void) efx_mcdi_driver_event(enp, eep->ee_index, event);
654 __checkReturn efx_rc_t
657 __in unsigned int us)
659 efx_nic_t *enp = eep->ee_enp;
660 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
665 /* Check that hardware and MCDI use the same timer MODE values */
666 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_DIS ==
667 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS);
668 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_IMMED_START ==
669 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START);
670 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_TRIG_START ==
671 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START);
672 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_INT_HLDOFF ==
673 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF);
675 if (us > encp->enc_evq_timer_max_us) {
680 /* If the value is zero then disable the timer */
682 mode = FFE_CZ_TIMER_MODE_DIS;
684 mode = FFE_CZ_TIMER_MODE_INT_HLDOFF;
687 if (encp->enc_bug61265_workaround) {
688 uint32_t ns = us * 1000;
690 rc = efx_mcdi_set_evq_tmr(enp, eep->ee_index, mode, ns);
696 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
699 if (encp->enc_bug35388_workaround) {
700 EFX_POPULATE_DWORD_3(dword,
701 ERF_DD_EVQ_IND_TIMER_FLAGS,
702 EFE_DD_EVQ_IND_TIMER_FLAGS,
703 ERF_DD_EVQ_IND_TIMER_MODE, mode,
704 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
705 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT,
706 eep->ee_index, &dword, 0);
708 EFX_POPULATE_DWORD_2(dword,
709 ERF_DZ_TC_TIMER_MODE, mode,
710 ERF_DZ_TC_TIMER_VAL, ticks);
711 EFX_BAR_VI_WRITED(enp, ER_DZ_EVQ_TMR_REG,
712 eep->ee_index, &dword, 0);
723 EFSYS_PROBE1(fail1, efx_rc_t, rc);
731 ef10_ev_qstats_update(
733 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
737 for (id = 0; id < EV_NQSTATS; id++) {
738 efsys_stat_t *essp = &stat[id];
740 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
741 eep->ee_stat[id] = 0;
744 #endif /* EFSYS_OPT_QSTATS */
746 #if EFSYS_OPT_RX_PACKED_STREAM
748 static __checkReturn boolean_t
749 ef10_ev_rx_packed_stream(
751 __in efx_qword_t *eqp,
752 __in const efx_ev_callbacks_t *eecp,
756 uint32_t pkt_count_lbits;
758 boolean_t should_abort;
759 efx_evq_rxq_state_t *eersp;
760 unsigned int pkt_count;
761 unsigned int current_id;
762 boolean_t new_buffer;
764 pkt_count_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
765 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
766 new_buffer = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_EV_ROTATE);
770 eersp = &eep->ee_rxq_state[label];
773 * RX_DSC_PTR_LBITS has least significant bits of the global
774 * (not per-buffer) packet counter. It is guaranteed that
775 * maximum number of completed packets fits in lbits-mask.
776 * So, modulo lbits-mask arithmetic should be used to calculate
777 * packet counter increment.
779 pkt_count = (pkt_count_lbits - eersp->eers_rx_stream_npackets) &
780 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
781 eersp->eers_rx_stream_npackets += pkt_count;
784 flags |= EFX_PKT_PACKED_STREAM_NEW_BUFFER;
785 eersp->eers_rx_packed_stream_credits++;
786 eersp->eers_rx_read_ptr++;
788 current_id = eersp->eers_rx_read_ptr & eersp->eers_rx_mask;
790 /* Check for errors that invalidate checksum and L3/L4 fields */
791 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TRUNC_ERR) != 0) {
792 /* RX frame truncated */
793 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
794 flags |= EFX_DISCARD;
797 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
798 /* Bad Ethernet frame CRC */
799 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
800 flags |= EFX_DISCARD;
804 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
805 flags |= EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE;
809 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR))
810 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
812 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR))
813 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
816 /* If we're not discarding the packet then it is ok */
817 if (~flags & EFX_DISCARD)
818 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
820 EFSYS_ASSERT(eecp->eec_rx_ps != NULL);
821 should_abort = eecp->eec_rx_ps(arg, label, current_id, pkt_count,
824 return (should_abort);
827 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
829 static __checkReturn boolean_t
832 __in efx_qword_t *eqp,
833 __in const efx_ev_callbacks_t *eecp,
836 efx_nic_t *enp = eep->ee_enp;
840 uint32_t eth_tag_class;
843 uint32_t next_read_lbits;
846 boolean_t should_abort;
847 efx_evq_rxq_state_t *eersp;
848 unsigned int desc_count;
849 unsigned int last_used_id;
851 EFX_EV_QSTAT_INCR(eep, EV_RX);
853 /* Discard events after RXQ/TXQ errors */
854 if (enp->en_reset_flags & (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR))
857 /* Basic packet information */
858 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
859 eersp = &eep->ee_rxq_state[label];
861 #if EFSYS_OPT_RX_PACKED_STREAM
863 * Packed stream events are very different,
864 * so handle them separately
866 if (eersp->eers_rx_packed_stream)
867 return (ef10_ev_rx_packed_stream(eep, eqp, eecp, arg));
870 size = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_BYTES);
871 cont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);
872 next_read_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
873 eth_tag_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ETH_TAG_CLASS);
874 mac_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS);
875 l3_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L3_CLASS);
878 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is only
879 * 2 bits wide on Medford2. Check it is safe to use the Medford2 field
880 * and values for all EF10 controllers.
882 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN == ESF_DE_RX_L4_CLASS_LBN);
883 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
884 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
885 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN == ESE_DE_L4_CLASS_UNKNOWN);
887 l4_class = EFX_QWORD_FIELD(*eqp, ESF_FZ_RX_L4_CLASS);
889 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DROP_EVENT) != 0) {
890 /* Drop this event */
897 * This may be part of a scattered frame, or it may be a
898 * truncated frame if scatter is disabled on this RXQ.
899 * Overlength frames can be received if e.g. a VF is configured
900 * for 1500 MTU but connected to a port set to 9000 MTU
902 * FIXME: There is not yet any driver that supports scatter on
903 * Huntington. Scatter support is required for OSX.
905 flags |= EFX_PKT_CONT;
908 if (mac_class == ESE_DZ_MAC_CLASS_UCAST)
909 flags |= EFX_PKT_UNICAST;
911 /* Increment the count of descriptors read */
912 desc_count = (next_read_lbits - eersp->eers_rx_read_ptr) &
913 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
914 eersp->eers_rx_read_ptr += desc_count;
917 * FIXME: add error checking to make sure this a batched event.
918 * This could also be an aborted scatter, see Bug36629.
920 if (desc_count > 1) {
921 EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);
922 flags |= EFX_PKT_PREFIX_LEN;
925 /* Calculate the index of the last descriptor consumed */
926 last_used_id = (eersp->eers_rx_read_ptr - 1) & eersp->eers_rx_mask;
928 /* Check for errors that invalidate checksum and L3/L4 fields */
929 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TRUNC_ERR) != 0) {
930 /* RX frame truncated */
931 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
932 flags |= EFX_DISCARD;
935 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
936 /* Bad Ethernet frame CRC */
937 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
938 flags |= EFX_DISCARD;
941 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
943 * Hardware parse failed, due to malformed headers
944 * or headers that are too long for the parser.
945 * Headers and checksums must be validated by the host.
947 /* TODO: EFX_EV_QSTAT_INCR(eep, EV_RX_PARSE_INCOMPLETE); */
951 if ((eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN1) ||
952 (eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN2)) {
953 flags |= EFX_PKT_VLAN_TAGGED;
957 case ESE_DZ_L3_CLASS_IP4:
958 case ESE_DZ_L3_CLASS_IP4_FRAG:
959 flags |= EFX_PKT_IPV4;
960 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR)) {
961 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
963 flags |= EFX_CKSUM_IPV4;
967 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
968 * only 2 bits wide on Medford2. Check it is safe to use the
969 * Medford2 field and values for all EF10 controllers.
971 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
972 ESF_DE_RX_L4_CLASS_LBN);
973 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
974 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
975 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
976 ESE_DE_L4_CLASS_UNKNOWN);
978 if (l4_class == ESE_FZ_L4_CLASS_TCP) {
979 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
980 flags |= EFX_PKT_TCP;
981 } else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
982 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
983 flags |= EFX_PKT_UDP;
985 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
989 case ESE_DZ_L3_CLASS_IP6:
990 case ESE_DZ_L3_CLASS_IP6_FRAG:
991 flags |= EFX_PKT_IPV6;
994 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
995 * only 2 bits wide on Medford2. Check it is safe to use the
996 * Medford2 field and values for all EF10 controllers.
998 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
999 ESF_DE_RX_L4_CLASS_LBN);
1000 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
1001 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
1002 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
1003 ESE_DE_L4_CLASS_UNKNOWN);
1005 if (l4_class == ESE_FZ_L4_CLASS_TCP) {
1006 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
1007 flags |= EFX_PKT_TCP;
1008 } else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
1009 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
1010 flags |= EFX_PKT_UDP;
1012 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
1017 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
1021 if (flags & (EFX_PKT_TCP | EFX_PKT_UDP)) {
1022 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
1023 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
1025 flags |= EFX_CKSUM_TCPUDP;
1030 /* If we're not discarding the packet then it is ok */
1031 if (~flags & EFX_DISCARD)
1032 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
1034 EFSYS_ASSERT(eecp->eec_rx != NULL);
1035 should_abort = eecp->eec_rx(arg, label, last_used_id, size, flags);
1037 return (should_abort);
1040 static __checkReturn boolean_t
1042 __in efx_evq_t *eep,
1043 __in efx_qword_t *eqp,
1044 __in const efx_ev_callbacks_t *eecp,
1047 efx_nic_t *enp = eep->ee_enp;
1050 boolean_t should_abort;
1052 EFX_EV_QSTAT_INCR(eep, EV_TX);
1054 /* Discard events after RXQ/TXQ errors */
1055 if (enp->en_reset_flags & (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR))
1058 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DROP_EVENT) != 0) {
1059 /* Drop this event */
1063 /* Per-packet TX completion (was per-descriptor for Falcon/Siena) */
1064 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DESCR_INDX);
1065 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_QLABEL);
1067 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
1069 EFSYS_ASSERT(eecp->eec_tx != NULL);
1070 should_abort = eecp->eec_tx(arg, label, id);
1072 return (should_abort);
1075 static __checkReturn boolean_t
1077 __in efx_evq_t *eep,
1078 __in efx_qword_t *eqp,
1079 __in const efx_ev_callbacks_t *eecp,
1083 boolean_t should_abort;
1085 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
1086 should_abort = B_FALSE;
1088 code = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_CODE);
1090 case ESE_DZ_DRV_TIMER_EV: {
1093 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_TMR_ID);
1095 EFSYS_ASSERT(eecp->eec_timer != NULL);
1096 should_abort = eecp->eec_timer(arg, id);
1100 case ESE_DZ_DRV_WAKE_UP_EV: {
1103 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_EVQ_ID);
1105 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
1106 should_abort = eecp->eec_wake_up(arg, id);
1110 case ESE_DZ_DRV_START_UP_EV:
1111 EFSYS_ASSERT(eecp->eec_initialized != NULL);
1112 should_abort = eecp->eec_initialized(arg);
1116 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1117 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1118 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1122 return (should_abort);
1125 static __checkReturn boolean_t
1127 __in efx_evq_t *eep,
1128 __in efx_qword_t *eqp,
1129 __in const efx_ev_callbacks_t *eecp,
1133 boolean_t should_abort;
1135 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1136 should_abort = B_FALSE;
1138 data = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_DATA_DW0);
1139 if (data >= ((uint32_t)1 << 16)) {
1140 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1141 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1142 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1147 EFSYS_ASSERT(eecp->eec_software != NULL);
1148 should_abort = eecp->eec_software(arg, (uint16_t)data);
1150 return (should_abort);
1153 static __checkReturn boolean_t
1155 __in efx_evq_t *eep,
1156 __in efx_qword_t *eqp,
1157 __in const efx_ev_callbacks_t *eecp,
1160 efx_nic_t *enp = eep->ee_enp;
1162 boolean_t should_abort = B_FALSE;
1164 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1166 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1168 case MCDI_EVENT_CODE_BADSSERT:
1169 efx_mcdi_ev_death(enp, EINTR);
1172 case MCDI_EVENT_CODE_CMDDONE:
1173 efx_mcdi_ev_cpl(enp,
1174 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1175 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1176 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1179 #if EFSYS_OPT_MCDI_PROXY_AUTH
1180 case MCDI_EVENT_CODE_PROXY_RESPONSE:
1182 * This event notifies a function that an authorization request
1183 * has been processed. If the request was authorized then the
1184 * function can now re-send the original MCDI request.
1185 * See SF-113652-SW "SR-IOV Proxied Network Access Control".
1187 efx_mcdi_ev_proxy_response(enp,
1188 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_HANDLE),
1189 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_RC));
1191 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
1193 case MCDI_EVENT_CODE_LINKCHANGE: {
1194 efx_link_mode_t link_mode;
1196 ef10_phy_link_ev(enp, eqp, &link_mode);
1197 should_abort = eecp->eec_link_change(arg, link_mode);
1201 case MCDI_EVENT_CODE_SENSOREVT: {
1202 #if EFSYS_OPT_MON_STATS
1204 efx_mon_stat_value_t value;
1207 /* Decode monitor stat for MCDI sensor (if supported) */
1208 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) {
1209 /* Report monitor stat change */
1210 should_abort = eecp->eec_monitor(arg, id, value);
1211 } else if (rc == ENOTSUP) {
1212 should_abort = eecp->eec_exception(arg,
1213 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1214 MCDI_EV_FIELD(eqp, DATA));
1216 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
1222 case MCDI_EVENT_CODE_SCHEDERR:
1223 /* Informational only */
1226 case MCDI_EVENT_CODE_REBOOT:
1227 /* Falcon/Siena only (should not been seen with Huntington). */
1228 efx_mcdi_ev_death(enp, EIO);
1231 case MCDI_EVENT_CODE_MC_REBOOT:
1232 /* MC_REBOOT event is used for Huntington (EF10) and later. */
1233 efx_mcdi_ev_death(enp, EIO);
1236 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1237 #if EFSYS_OPT_MAC_STATS
1238 if (eecp->eec_mac_stats != NULL) {
1239 eecp->eec_mac_stats(arg,
1240 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1245 case MCDI_EVENT_CODE_FWALERT: {
1246 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1248 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1249 should_abort = eecp->eec_exception(arg,
1250 EFX_EXCEPTION_FWALERT_SRAM,
1251 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1253 should_abort = eecp->eec_exception(arg,
1254 EFX_EXCEPTION_UNKNOWN_FWALERT,
1255 MCDI_EV_FIELD(eqp, DATA));
1259 case MCDI_EVENT_CODE_TX_ERR: {
1261 * After a TXQ error is detected, firmware sends a TX_ERR event.
1262 * This may be followed by TX completions (which we discard),
1263 * and then finally by a TX_FLUSH event. Firmware destroys the
1264 * TXQ automatically after sending the TX_FLUSH event.
1266 enp->en_reset_flags |= EFX_RESET_TXQ_ERR;
1268 EFSYS_PROBE2(tx_descq_err,
1269 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1270 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1272 /* Inform the driver that a reset is required. */
1273 eecp->eec_exception(arg, EFX_EXCEPTION_TX_ERROR,
1274 MCDI_EV_FIELD(eqp, TX_ERR_DATA));
1278 case MCDI_EVENT_CODE_TX_FLUSH: {
1279 uint32_t txq_index = MCDI_EV_FIELD(eqp, TX_FLUSH_TXQ);
1282 * EF10 firmware sends two TX_FLUSH events: one to the txq's
1283 * event queue, and one to evq 0 (with TX_FLUSH_TO_DRIVER set).
1284 * We want to wait for all completions, so ignore the events
1285 * with TX_FLUSH_TO_DRIVER.
1287 if (MCDI_EV_FIELD(eqp, TX_FLUSH_TO_DRIVER) != 0) {
1288 should_abort = B_FALSE;
1292 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
1294 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
1296 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
1297 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
1301 case MCDI_EVENT_CODE_RX_ERR: {
1303 * After an RXQ error is detected, firmware sends an RX_ERR
1304 * event. This may be followed by RX events (which we discard),
1305 * and then finally by an RX_FLUSH event. Firmware destroys the
1306 * RXQ automatically after sending the RX_FLUSH event.
1308 enp->en_reset_flags |= EFX_RESET_RXQ_ERR;
1310 EFSYS_PROBE2(rx_descq_err,
1311 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1312 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1314 /* Inform the driver that a reset is required. */
1315 eecp->eec_exception(arg, EFX_EXCEPTION_RX_ERROR,
1316 MCDI_EV_FIELD(eqp, RX_ERR_DATA));
1320 case MCDI_EVENT_CODE_RX_FLUSH: {
1321 uint32_t rxq_index = MCDI_EV_FIELD(eqp, RX_FLUSH_RXQ);
1324 * EF10 firmware sends two RX_FLUSH events: one to the rxq's
1325 * event queue, and one to evq 0 (with RX_FLUSH_TO_DRIVER set).
1326 * We want to wait for all completions, so ignore the events
1327 * with RX_FLUSH_TO_DRIVER.
1329 if (MCDI_EV_FIELD(eqp, RX_FLUSH_TO_DRIVER) != 0) {
1330 should_abort = B_FALSE;
1334 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
1336 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
1338 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
1339 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
1344 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1345 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1346 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1350 return (should_abort);
1354 ef10_ev_rxlabel_init(
1355 __in efx_evq_t *eep,
1356 __in efx_rxq_t *erp,
1357 __in unsigned int label,
1358 __in efx_rxq_type_t type)
1360 efx_evq_rxq_state_t *eersp;
1361 #if EFSYS_OPT_RX_PACKED_STREAM
1362 boolean_t packed_stream = (type == EFX_RXQ_TYPE_PACKED_STREAM);
1365 _NOTE(ARGUNUSED(type))
1366 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1367 eersp = &eep->ee_rxq_state[label];
1369 EFSYS_ASSERT3U(eersp->eers_rx_mask, ==, 0);
1371 #if EFSYS_OPT_RX_PACKED_STREAM
1373 * For packed stream modes, the very first event will
1374 * have a new buffer flag set, so it will be incremented,
1375 * yielding the correct pointer. That results in a simpler
1376 * code than trying to detect start-of-the-world condition
1377 * in the event handler.
1379 eersp->eers_rx_read_ptr = packed_stream ? ~0 : 0;
1381 eersp->eers_rx_read_ptr = 0;
1383 eersp->eers_rx_mask = erp->er_mask;
1384 #if EFSYS_OPT_RX_PACKED_STREAM
1385 eersp->eers_rx_stream_npackets = 0;
1386 eersp->eers_rx_packed_stream = packed_stream;
1387 if (packed_stream) {
1388 eersp->eers_rx_packed_stream_credits = (eep->ee_mask + 1) /
1389 EFX_DIV_ROUND_UP(EFX_RX_PACKED_STREAM_MEM_PER_CREDIT,
1390 EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE);
1391 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, !=, 0);
1393 * A single credit is allocated to the queue when it is started.
1394 * It is immediately spent by the first packet which has NEW
1395 * BUFFER flag set, though, but still we shall take into
1396 * account, as to not wrap around the maximum number of credits
1399 eersp->eers_rx_packed_stream_credits--;
1400 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, <=,
1401 EFX_RX_PACKED_STREAM_MAX_CREDITS);
1407 ef10_ev_rxlabel_fini(
1408 __in efx_evq_t *eep,
1409 __in unsigned int label)
1411 efx_evq_rxq_state_t *eersp;
1413 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1414 eersp = &eep->ee_rxq_state[label];
1416 EFSYS_ASSERT3U(eersp->eers_rx_mask, !=, 0);
1418 eersp->eers_rx_read_ptr = 0;
1419 eersp->eers_rx_mask = 0;
1420 #if EFSYS_OPT_RX_PACKED_STREAM
1421 eersp->eers_rx_stream_npackets = 0;
1422 eersp->eers_rx_packed_stream = B_FALSE;
1423 eersp->eers_rx_packed_stream_credits = 0;
1427 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */