1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
7 #ifndef _SYS_EF10_IMPL_H
8 #define _SYS_EF10_IMPL_H
14 #define EF10_EVQ_MAXNEVS 32768
15 #define EF10_EVQ_MINNEVS 512
17 #define EF10_RXQ_MAXNDESCS 4096
18 #define EF10_RXQ_MINNDESCS 512
20 #define EF10_TXQ_MINNDESCS 512
22 #define EF10_TXQ_DESC_SIZE (sizeof (efx_qword_t))
24 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
25 #define EF10_TXQ_MAXNBUFS 8
27 /* Number of hardware PIO buffers (for compile-time resource dimensions) */
28 #define EF10_MAX_PIOBUF_NBUFS (16)
30 #if EFSYS_OPT_HUNTINGTON
31 # if (EF10_MAX_PIOBUF_NBUFS < HUNT_PIOBUF_NBUFS)
32 # error "EF10_MAX_PIOBUF_NBUFS too small"
34 #endif /* EFSYS_OPT_HUNTINGTON */
36 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD_PIOBUF_NBUFS)
37 # error "EF10_MAX_PIOBUF_NBUFS too small"
39 #endif /* EFSYS_OPT_MEDFORD */
40 #if EFSYS_OPT_MEDFORD2
41 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD2_PIOBUF_NBUFS)
42 # error "EF10_MAX_PIOBUF_NBUFS too small"
44 #endif /* EFSYS_OPT_MEDFORD2 */
49 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
50 * possibly be increased, or the write size reported by newer firmware used
53 #define EF10_NVRAM_CHUNK 0x80
56 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned
57 * to an 8 descriptor boundary.
59 #define EF10_RX_WPTR_ALIGN 8
62 * Max byte offset into the packet the TCP header must start for the hardware
63 * to be able to parse the packet correctly.
65 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
67 /* Invalid RSS context handle */
68 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
73 __checkReturn efx_rc_t
81 __checkReturn efx_rc_t
84 __in unsigned int index,
85 __in efsys_mem_t *esmp,
96 __checkReturn efx_rc_t
99 __in unsigned int count);
106 __checkReturn efx_rc_t
109 __in unsigned int us);
113 ef10_ev_qstats_update(
115 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
116 #endif /* EFSYS_OPT_QSTATS */
119 ef10_ev_rxlabel_init(
122 __in unsigned int label,
123 __in efx_rxq_type_t type);
126 ef10_ev_rxlabel_fini(
128 __in unsigned int label);
132 __checkReturn efx_rc_t
135 __in efx_intr_type_t type,
136 __in efsys_mem_t *esmp);
140 __in efx_nic_t *enp);
144 __in efx_nic_t *enp);
147 ef10_intr_disable_unlocked(
148 __in efx_nic_t *enp);
150 __checkReturn efx_rc_t
153 __in unsigned int level);
156 ef10_intr_status_line(
158 __out boolean_t *fatalp,
159 __out uint32_t *qmaskp);
162 ef10_intr_status_message(
164 __in unsigned int message,
165 __out boolean_t *fatalp);
169 __in efx_nic_t *enp);
172 __in efx_nic_t *enp);
176 extern __checkReturn efx_rc_t
178 __in efx_nic_t *enp);
180 extern __checkReturn efx_rc_t
181 ef10_nic_set_drv_limits(
182 __inout efx_nic_t *enp,
183 __in efx_drv_limits_t *edlp);
185 extern __checkReturn efx_rc_t
186 ef10_nic_get_vi_pool(
188 __out uint32_t *vi_countp);
190 extern __checkReturn efx_rc_t
191 ef10_nic_get_bar_region(
193 __in efx_nic_region_t region,
194 __out uint32_t *offsetp,
195 __out size_t *sizep);
197 extern __checkReturn efx_rc_t
199 __in efx_nic_t *enp);
201 extern __checkReturn efx_rc_t
203 __in efx_nic_t *enp);
205 extern __checkReturn boolean_t
206 ef10_nic_hw_unavailable(
207 __in efx_nic_t *enp);
210 ef10_nic_set_hw_unavailable(
211 __in efx_nic_t *enp);
215 extern __checkReturn efx_rc_t
216 ef10_nic_register_test(
217 __in efx_nic_t *enp);
219 #endif /* EFSYS_OPT_DIAG */
223 __in efx_nic_t *enp);
227 __in efx_nic_t *enp);
232 extern __checkReturn efx_rc_t
235 __out efx_link_mode_t *link_modep);
237 extern __checkReturn efx_rc_t
240 __out boolean_t *mac_upp);
242 extern __checkReturn efx_rc_t
244 __in efx_nic_t *enp);
246 extern __checkReturn efx_rc_t
248 __in efx_nic_t *enp);
250 extern __checkReturn efx_rc_t
255 extern __checkReturn efx_rc_t
256 ef10_mac_reconfigure(
257 __in efx_nic_t *enp);
259 extern __checkReturn efx_rc_t
260 ef10_mac_multicast_list_set(
261 __in efx_nic_t *enp);
263 extern __checkReturn efx_rc_t
264 ef10_mac_filter_default_rxq_set(
267 __in boolean_t using_rss);
270 ef10_mac_filter_default_rxq_clear(
271 __in efx_nic_t *enp);
273 #if EFSYS_OPT_LOOPBACK
275 extern __checkReturn efx_rc_t
276 ef10_mac_loopback_set(
278 __in efx_link_mode_t link_mode,
279 __in efx_loopback_type_t loopback_type);
281 #endif /* EFSYS_OPT_LOOPBACK */
283 #if EFSYS_OPT_MAC_STATS
285 extern __checkReturn efx_rc_t
286 ef10_mac_stats_get_mask(
288 __inout_bcount(mask_size) uint32_t *maskp,
289 __in size_t mask_size);
291 extern __checkReturn efx_rc_t
292 ef10_mac_stats_update(
294 __in efsys_mem_t *esmp,
295 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
296 __inout_opt uint32_t *generationp);
298 #endif /* EFSYS_OPT_MAC_STATS */
305 extern __checkReturn efx_rc_t
308 __in const efx_mcdi_transport_t *mtp);
312 __in efx_nic_t *enp);
315 ef10_mcdi_send_request(
317 __in_bcount(hdr_len) void *hdrp,
319 __in_bcount(sdu_len) void *sdup,
320 __in size_t sdu_len);
322 extern __checkReturn boolean_t
323 ef10_mcdi_poll_response(
324 __in efx_nic_t *enp);
327 ef10_mcdi_read_response(
329 __out_bcount(length) void *bufferp,
334 ef10_mcdi_poll_reboot(
335 __in efx_nic_t *enp);
337 extern __checkReturn efx_rc_t
338 ef10_mcdi_feature_supported(
340 __in efx_mcdi_feature_id_t id,
341 __out boolean_t *supportedp);
344 ef10_mcdi_get_timeout(
346 __in efx_mcdi_req_t *emrp,
347 __out uint32_t *timeoutp);
349 #endif /* EFSYS_OPT_MCDI */
353 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
355 extern __checkReturn efx_rc_t
356 ef10_nvram_buf_read_tlv(
358 __in_bcount(max_seg_size) caddr_t seg_data,
359 __in size_t max_seg_size,
361 __deref_out_bcount_opt(*sizep) caddr_t *datap,
362 __out size_t *sizep);
364 extern __checkReturn efx_rc_t
365 ef10_nvram_buf_write_tlv(
366 __inout_bcount(partn_size) caddr_t partn_data,
367 __in size_t partn_size,
369 __in_bcount(tag_size) caddr_t tag_data,
370 __in size_t tag_size,
371 __out size_t *total_lengthp);
373 extern __checkReturn efx_rc_t
374 ef10_nvram_partn_read_tlv(
378 __deref_out_bcount_opt(*sizep) caddr_t *datap,
379 __out size_t *sizep);
381 extern __checkReturn efx_rc_t
382 ef10_nvram_partn_write_tlv(
386 __in_bcount(size) caddr_t data,
389 extern __checkReturn efx_rc_t
390 ef10_nvram_partn_write_segment_tlv(
394 __in_bcount(size) caddr_t data,
396 __in boolean_t all_segments);
398 extern __checkReturn efx_rc_t
399 ef10_nvram_partn_lock(
401 __in uint32_t partn);
403 extern __checkReturn efx_rc_t
404 ef10_nvram_partn_unlock(
407 __out_opt uint32_t *resultp);
409 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
415 extern __checkReturn efx_rc_t
417 __in efx_nic_t *enp);
419 #endif /* EFSYS_OPT_DIAG */
421 extern __checkReturn efx_rc_t
422 ef10_nvram_type_to_partn(
424 __in efx_nvram_type_t type,
425 __out uint32_t *partnp);
427 extern __checkReturn efx_rc_t
428 ef10_nvram_partn_size(
431 __out size_t *sizep);
433 extern __checkReturn efx_rc_t
434 ef10_nvram_partn_rw_start(
437 __out size_t *chunk_sizep);
439 extern __checkReturn efx_rc_t
440 ef10_nvram_partn_read_mode(
443 __in unsigned int offset,
444 __out_bcount(size) caddr_t data,
448 extern __checkReturn efx_rc_t
449 ef10_nvram_partn_read(
452 __in unsigned int offset,
453 __out_bcount(size) caddr_t data,
456 extern __checkReturn efx_rc_t
457 ef10_nvram_partn_read_backup(
460 __in unsigned int offset,
461 __out_bcount(size) caddr_t data,
464 extern __checkReturn efx_rc_t
465 ef10_nvram_partn_erase(
468 __in unsigned int offset,
471 extern __checkReturn efx_rc_t
472 ef10_nvram_partn_write(
475 __in unsigned int offset,
476 __in_bcount(size) caddr_t data,
479 extern __checkReturn efx_rc_t
480 ef10_nvram_partn_rw_finish(
483 __out_opt uint32_t *verify_resultp);
485 extern __checkReturn efx_rc_t
486 ef10_nvram_partn_get_version(
489 __out uint32_t *subtypep,
490 __out_ecount(4) uint16_t version[4]);
492 extern __checkReturn efx_rc_t
493 ef10_nvram_partn_set_version(
496 __in_ecount(4) uint16_t version[4]);
498 extern __checkReturn efx_rc_t
499 ef10_nvram_buffer_validate(
501 __in_bcount(buffer_size)
503 __in size_t buffer_size);
506 ef10_nvram_buffer_init(
507 __out_bcount(buffer_size)
509 __in size_t buffer_size);
511 extern __checkReturn efx_rc_t
512 ef10_nvram_buffer_create(
513 __in uint32_t partn_type,
514 __out_bcount(buffer_size)
516 __in size_t buffer_size);
518 extern __checkReturn efx_rc_t
519 ef10_nvram_buffer_find_item_start(
520 __in_bcount(buffer_size)
522 __in size_t buffer_size,
523 __out uint32_t *startp);
525 extern __checkReturn efx_rc_t
526 ef10_nvram_buffer_find_end(
527 __in_bcount(buffer_size)
529 __in size_t buffer_size,
530 __in uint32_t offset,
531 __out uint32_t *endp);
533 extern __checkReturn __success(return != B_FALSE) boolean_t
534 ef10_nvram_buffer_find_item(
535 __in_bcount(buffer_size)
537 __in size_t buffer_size,
538 __in uint32_t offset,
539 __out uint32_t *startp,
540 __out uint32_t *lengthp);
542 extern __checkReturn efx_rc_t
543 ef10_nvram_buffer_peek_item(
544 __in_bcount(buffer_size)
546 __in size_t buffer_size,
547 __in uint32_t offset,
548 __out uint32_t *tagp,
549 __out uint32_t *lengthp,
550 __out uint32_t *value_offsetp);
552 extern __checkReturn efx_rc_t
553 ef10_nvram_buffer_get_item(
554 __in_bcount(buffer_size)
556 __in size_t buffer_size,
557 __in uint32_t offset,
558 __in uint32_t length,
559 __out uint32_t *tagp,
560 __out_bcount_part(value_max_size, *lengthp)
562 __in size_t value_max_size,
563 __out uint32_t *lengthp);
565 extern __checkReturn efx_rc_t
566 ef10_nvram_buffer_insert_item(
567 __in_bcount(buffer_size)
569 __in size_t buffer_size,
570 __in uint32_t offset,
572 __in_bcount(length) caddr_t valuep,
573 __in uint32_t length,
574 __out uint32_t *lengthp);
576 extern __checkReturn efx_rc_t
577 ef10_nvram_buffer_modify_item(
578 __in_bcount(buffer_size)
580 __in size_t buffer_size,
581 __in uint32_t offset,
583 __in_bcount(length) caddr_t valuep,
584 __in uint32_t length,
585 __out uint32_t *lengthp);
587 extern __checkReturn efx_rc_t
588 ef10_nvram_buffer_delete_item(
589 __in_bcount(buffer_size)
591 __in size_t buffer_size,
592 __in uint32_t offset,
593 __in uint32_t length,
596 extern __checkReturn efx_rc_t
597 ef10_nvram_buffer_finish(
598 __in_bcount(buffer_size)
600 __in size_t buffer_size);
602 #endif /* EFSYS_OPT_NVRAM */
607 typedef struct ef10_link_state_s {
608 efx_phy_link_state_t epls;
609 #if EFSYS_OPT_LOOPBACK
610 efx_loopback_type_t els_loopback;
612 boolean_t els_mac_up;
618 __in efx_qword_t *eqp,
619 __out efx_link_mode_t *link_modep);
621 extern __checkReturn efx_rc_t
624 __out ef10_link_state_t *elsp);
626 extern __checkReturn efx_rc_t
631 extern __checkReturn efx_rc_t
632 ef10_phy_reconfigure(
633 __in efx_nic_t *enp);
635 extern __checkReturn efx_rc_t
637 __in efx_nic_t *enp);
639 extern __checkReturn efx_rc_t
642 __out uint32_t *ouip);
644 extern __checkReturn efx_rc_t
645 ef10_phy_link_state_get(
647 __out efx_phy_link_state_t *eplsp);
649 #if EFSYS_OPT_PHY_STATS
651 extern __checkReturn efx_rc_t
652 ef10_phy_stats_update(
654 __in efsys_mem_t *esmp,
655 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
657 #endif /* EFSYS_OPT_PHY_STATS */
661 extern __checkReturn efx_rc_t
662 ef10_bist_enable_offline(
663 __in efx_nic_t *enp);
665 extern __checkReturn efx_rc_t
668 __in efx_bist_type_t type);
670 extern __checkReturn efx_rc_t
673 __in efx_bist_type_t type,
674 __out efx_bist_result_t *resultp,
675 __out_opt __drv_when(count > 0, __notnull)
676 uint32_t *value_maskp,
677 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
678 unsigned long *valuesp,
684 __in efx_bist_type_t type);
686 #endif /* EFSYS_OPT_BIST */
690 extern __checkReturn efx_rc_t
692 __in efx_nic_t *enp);
696 __in efx_nic_t *enp);
698 extern __checkReturn efx_rc_t
701 __in unsigned int index,
702 __in unsigned int label,
703 __in efsys_mem_t *esmp,
709 __out unsigned int *addedp);
713 __in efx_txq_t *etp);
715 extern __checkReturn efx_rc_t
718 __in_ecount(ndescs) efx_buffer_t *ebp,
719 __in unsigned int ndescs,
720 __in unsigned int completed,
721 __inout unsigned int *addedp);
726 __in unsigned int added,
727 __in unsigned int pushed);
729 #if EFSYS_OPT_RX_PACKED_STREAM
731 ef10_rx_qpush_ps_credits(
732 __in efx_rxq_t *erp);
734 extern __checkReturn uint8_t *
735 ef10_rx_qps_packet_info(
737 __in uint8_t *buffer,
738 __in uint32_t buffer_length,
739 __in uint32_t current_offset,
740 __out uint16_t *lengthp,
741 __out uint32_t *next_offsetp,
742 __out uint32_t *timestamp);
745 extern __checkReturn efx_rc_t
748 __in unsigned int ns);
750 extern __checkReturn efx_rc_t
752 __in efx_txq_t *etp);
756 __in efx_txq_t *etp);
758 extern __checkReturn efx_rc_t
760 __in efx_txq_t *etp);
763 ef10_tx_qpio_disable(
764 __in efx_txq_t *etp);
766 extern __checkReturn efx_rc_t
769 __in_ecount(buf_length) uint8_t *buffer,
770 __in size_t buf_length,
771 __in size_t pio_buf_offset);
773 extern __checkReturn efx_rc_t
776 __in size_t pkt_length,
777 __in unsigned int completed,
778 __inout unsigned int *addedp);
780 extern __checkReturn efx_rc_t
783 __in_ecount(n) efx_desc_t *ed,
785 __in unsigned int completed,
786 __inout unsigned int *addedp);
789 ef10_tx_qdesc_dma_create(
791 __in efsys_dma_addr_t addr,
794 __out efx_desc_t *edp);
797 ef10_tx_qdesc_tso_create(
799 __in uint16_t ipv4_id,
800 __in uint32_t tcp_seq,
801 __in uint8_t tcp_flags,
802 __out efx_desc_t *edp);
805 ef10_tx_qdesc_tso2_create(
807 __in uint16_t ipv4_id,
808 __in uint16_t outer_ipv4_id,
809 __in uint32_t tcp_seq,
810 __in uint16_t tcp_mss,
811 __out_ecount(count) efx_desc_t *edp,
815 ef10_tx_qdesc_vlantci_create(
817 __in uint16_t vlan_tci,
818 __out efx_desc_t *edp);
821 ef10_tx_qdesc_checksum_create(
824 __out efx_desc_t *edp);
829 ef10_tx_qstats_update(
831 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
833 #endif /* EFSYS_OPT_QSTATS */
835 typedef uint32_t efx_piobuf_handle_t;
837 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1)
839 extern __checkReturn efx_rc_t
841 __inout efx_nic_t *enp,
842 __out uint32_t *bufnump,
843 __out efx_piobuf_handle_t *handlep,
844 __out uint32_t *blknump,
845 __out uint32_t *offsetp,
846 __out size_t *sizep);
848 extern __checkReturn efx_rc_t
850 __inout efx_nic_t *enp,
851 __in uint32_t bufnum,
852 __in uint32_t blknum);
854 extern __checkReturn efx_rc_t
856 __inout efx_nic_t *enp,
857 __in uint32_t vi_index,
858 __in efx_piobuf_handle_t handle);
860 extern __checkReturn efx_rc_t
862 __inout efx_nic_t *enp,
863 __in uint32_t vi_index);
870 extern __checkReturn efx_rc_t
872 __in efx_nic_t *enp);
874 extern __checkReturn efx_rc_t
877 __out size_t *sizep);
879 extern __checkReturn efx_rc_t
882 __out_bcount(size) caddr_t data,
885 extern __checkReturn efx_rc_t
888 __in_bcount(size) caddr_t data,
891 extern __checkReturn efx_rc_t
894 __in_bcount(size) caddr_t data,
897 extern __checkReturn efx_rc_t
900 __in_bcount(size) caddr_t data,
902 __inout efx_vpd_value_t *evvp);
904 extern __checkReturn efx_rc_t
907 __in_bcount(size) caddr_t data,
909 __in efx_vpd_value_t *evvp);
911 extern __checkReturn efx_rc_t
914 __in_bcount(size) caddr_t data,
916 __out efx_vpd_value_t *evvp,
917 __inout unsigned int *contp);
919 extern __checkReturn efx_rc_t
922 __in_bcount(size) caddr_t data,
927 __in efx_nic_t *enp);
929 #endif /* EFSYS_OPT_VPD */
934 extern __checkReturn efx_rc_t
936 __in efx_nic_t *enp);
938 #if EFSYS_OPT_RX_SCATTER
939 extern __checkReturn efx_rc_t
940 ef10_rx_scatter_enable(
942 __in unsigned int buf_size);
943 #endif /* EFSYS_OPT_RX_SCATTER */
946 #if EFSYS_OPT_RX_SCALE
948 extern __checkReturn efx_rc_t
949 ef10_rx_scale_context_alloc(
951 __in efx_rx_scale_context_type_t type,
952 __in uint32_t num_queues,
953 __out uint32_t *rss_contextp);
955 extern __checkReturn efx_rc_t
956 ef10_rx_scale_context_free(
958 __in uint32_t rss_context);
960 extern __checkReturn efx_rc_t
961 ef10_rx_scale_mode_set(
963 __in uint32_t rss_context,
964 __in efx_rx_hash_alg_t alg,
965 __in efx_rx_hash_type_t type,
966 __in boolean_t insert);
968 extern __checkReturn efx_rc_t
969 ef10_rx_scale_key_set(
971 __in uint32_t rss_context,
972 __in_ecount(n) uint8_t *key,
975 extern __checkReturn efx_rc_t
976 ef10_rx_scale_tbl_set(
978 __in uint32_t rss_context,
979 __in_ecount(n) unsigned int *table,
982 extern __checkReturn uint32_t
985 __in efx_rx_hash_alg_t func,
986 __in uint8_t *buffer);
988 #endif /* EFSYS_OPT_RX_SCALE */
990 extern __checkReturn efx_rc_t
991 ef10_rx_prefix_pktlen(
993 __in uint8_t *buffer,
994 __out uint16_t *lengthp);
999 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1001 __in unsigned int ndescs,
1002 __in unsigned int completed,
1003 __in unsigned int added);
1007 __in efx_rxq_t *erp,
1008 __in unsigned int added,
1009 __inout unsigned int *pushedp);
1011 extern __checkReturn efx_rc_t
1013 __in efx_rxq_t *erp);
1017 __in efx_rxq_t *erp);
1019 union efx_rxq_type_data_u;
1021 extern __checkReturn efx_rc_t
1023 __in efx_nic_t *enp,
1024 __in unsigned int index,
1025 __in unsigned int label,
1026 __in efx_rxq_type_t type,
1027 __in_opt const union efx_rxq_type_data_u *type_data,
1028 __in efsys_mem_t *esmp,
1031 __in unsigned int flags,
1032 __in efx_evq_t *eep,
1033 __in efx_rxq_t *erp);
1037 __in efx_rxq_t *erp);
1041 __in efx_nic_t *enp);
1043 #if EFSYS_OPT_FILTER
1045 typedef struct ef10_filter_handle_s {
1048 } ef10_filter_handle_t;
1050 typedef struct ef10_filter_entry_s {
1051 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1052 ef10_filter_handle_t efe_handle;
1053 } ef10_filter_entry_t;
1056 * BUSY flag indicates that an update is in progress.
1057 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1059 #define EFX_EF10_FILTER_FLAG_BUSY 1U
1060 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
1061 #define EFX_EF10_FILTER_FLAGS 3U
1064 * Size of the hash table used by the driver. Doesn't need to be the
1065 * same size as the hardware's table.
1067 #define EFX_EF10_FILTER_TBL_ROWS 8192
1069 /* Only need to allow for one directed and one unknown unicast filter */
1070 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
1072 /* Allow for the broadcast address to be added to the multicast list */
1073 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
1076 * For encapsulated packets, there is one filter each for each combination of
1077 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1078 * multicast inner frames.
1080 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
1082 typedef struct ef10_filter_table_s {
1083 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1084 efx_rxq_t *eft_default_rxq;
1085 boolean_t eft_using_rss;
1086 uint32_t eft_unicst_filter_indexes[
1087 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1088 uint32_t eft_unicst_filter_count;
1089 uint32_t eft_mulcst_filter_indexes[
1090 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1091 uint32_t eft_mulcst_filter_count;
1092 boolean_t eft_using_all_mulcst;
1093 uint32_t eft_encap_filter_indexes[
1094 EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1095 uint32_t eft_encap_filter_count;
1096 } ef10_filter_table_t;
1098 __checkReturn efx_rc_t
1100 __in efx_nic_t *enp);
1104 __in efx_nic_t *enp);
1106 __checkReturn efx_rc_t
1107 ef10_filter_restore(
1108 __in efx_nic_t *enp);
1110 __checkReturn efx_rc_t
1112 __in efx_nic_t *enp,
1113 __inout efx_filter_spec_t *spec,
1114 __in boolean_t may_replace);
1116 __checkReturn efx_rc_t
1118 __in efx_nic_t *enp,
1119 __inout efx_filter_spec_t *spec);
1121 extern __checkReturn efx_rc_t
1122 ef10_filter_supported_filters(
1123 __in efx_nic_t *enp,
1124 __out_ecount(buffer_length) uint32_t *buffer,
1125 __in size_t buffer_length,
1126 __out size_t *list_lengthp);
1128 extern __checkReturn efx_rc_t
1129 ef10_filter_reconfigure(
1130 __in efx_nic_t *enp,
1131 __in_ecount(6) uint8_t const *mac_addr,
1132 __in boolean_t all_unicst,
1133 __in boolean_t mulcst,
1134 __in boolean_t all_mulcst,
1135 __in boolean_t brdcst,
1136 __in_ecount(6*count) uint8_t const *addrs,
1137 __in uint32_t count);
1140 ef10_filter_get_default_rxq(
1141 __in efx_nic_t *enp,
1142 __out efx_rxq_t **erpp,
1143 __out boolean_t *using_rss);
1146 ef10_filter_default_rxq_set(
1147 __in efx_nic_t *enp,
1148 __in efx_rxq_t *erp,
1149 __in boolean_t using_rss);
1152 ef10_filter_default_rxq_clear(
1153 __in efx_nic_t *enp);
1156 #endif /* EFSYS_OPT_FILTER */
1158 extern __checkReturn efx_rc_t
1159 efx_mcdi_get_function_info(
1160 __in efx_nic_t *enp,
1161 __out uint32_t *pfp,
1162 __out_opt uint32_t *vfp);
1164 extern __checkReturn efx_rc_t
1165 efx_mcdi_privilege_mask(
1166 __in efx_nic_t *enp,
1169 __out uint32_t *maskp);
1171 extern __checkReturn efx_rc_t
1172 efx_mcdi_get_port_assignment(
1173 __in efx_nic_t *enp,
1174 __out uint32_t *portp);
1176 extern __checkReturn efx_rc_t
1177 efx_mcdi_get_port_modes(
1178 __in efx_nic_t *enp,
1179 __out uint32_t *modesp,
1180 __out_opt uint32_t *current_modep,
1181 __out_opt uint32_t *default_modep);
1183 extern __checkReturn efx_rc_t
1184 ef10_nic_get_port_mode_bandwidth(
1185 __in efx_nic_t *enp,
1186 __out uint32_t *bandwidth_mbpsp);
1188 extern __checkReturn efx_rc_t
1189 efx_mcdi_get_mac_address_pf(
1190 __in efx_nic_t *enp,
1191 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1193 extern __checkReturn efx_rc_t
1194 efx_mcdi_get_mac_address_vf(
1195 __in efx_nic_t *enp,
1196 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1198 extern __checkReturn efx_rc_t
1200 __in efx_nic_t *enp,
1201 __out uint32_t *sys_freqp,
1202 __out uint32_t *dpcpu_freqp);
1205 extern __checkReturn efx_rc_t
1206 efx_mcdi_get_rxdp_config(
1207 __in efx_nic_t *enp,
1208 __out uint32_t *end_paddingp);
1210 extern __checkReturn efx_rc_t
1211 efx_mcdi_get_vector_cfg(
1212 __in efx_nic_t *enp,
1213 __out_opt uint32_t *vec_basep,
1214 __out_opt uint32_t *pf_nvecp,
1215 __out_opt uint32_t *vf_nvecp);
1217 extern __checkReturn efx_rc_t
1218 ef10_get_privilege_mask(
1219 __in efx_nic_t *enp,
1220 __out uint32_t *maskp);
1222 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1224 extern __checkReturn efx_rc_t
1225 efx_mcdi_get_nic_global(
1226 __in efx_nic_t *enp,
1228 __out uint32_t *valuep);
1230 extern __checkReturn efx_rc_t
1231 efx_mcdi_set_nic_global(
1232 __in efx_nic_t *enp,
1234 __in uint32_t value);
1236 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1239 #if EFSYS_OPT_RX_PACKED_STREAM
1241 /* Data space per credit in packed stream mode */
1242 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1245 * Received packets are always aligned at this boundary. Also there always
1246 * exists a gap of this size between packets.
1247 * (see SF-112241-TC, 4.5)
1249 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64
1252 * Size of a pseudo-header prepended to received packets
1253 * in packed stream mode
1255 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1257 /* Minimum space for packet in packed stream mode */
1258 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
1259 P2ROUNDUP(EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
1261 EFX_RX_PACKED_STREAM_ALIGNMENT, \
1262 EFX_RX_PACKED_STREAM_ALIGNMENT)
1264 /* Maximum number of credits */
1265 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1267 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1269 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1272 * Maximum DMA length and buffer stride alignment.
1273 * (see SF-119419-TC, 3.2)
1275 #define EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT 64
1283 #endif /* _SYS_EF10_IMPL_H */