2 * Copyright (c) 2015-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #ifndef _SYS_EF10_IMPL_H
32 #define _SYS_EF10_IMPL_H
38 #if (EFSYS_OPT_HUNTINGTON && EFSYS_OPT_MEDFORD)
39 #define EF10_MAX_PIOBUF_NBUFS MAX(HUNT_PIOBUF_NBUFS, MEDFORD_PIOBUF_NBUFS)
40 #elif EFSYS_OPT_HUNTINGTON
41 #define EF10_MAX_PIOBUF_NBUFS HUNT_PIOBUF_NBUFS
42 #elif EFSYS_OPT_MEDFORD
43 #define EF10_MAX_PIOBUF_NBUFS MEDFORD_PIOBUF_NBUFS
47 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
48 * possibly be increased, or the write size reported by newer firmware used
51 #define EF10_NVRAM_CHUNK 0x80
53 /* Alignment requirement for value written to RX WPTR:
54 * the WPTR must be aligned to an 8 descriptor boundary
56 #define EF10_RX_WPTR_ALIGN 8
59 * Max byte offset into the packet the TCP header must start for the hardware
60 * to be able to parse the packet correctly.
62 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
64 /* Invalid RSS context handle */
65 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
70 __checkReturn efx_rc_t
78 __checkReturn efx_rc_t
81 __in unsigned int index,
82 __in efsys_mem_t *esmp,
93 __checkReturn efx_rc_t
96 __in unsigned int count);
103 __checkReturn efx_rc_t
106 __in unsigned int us);
110 ef10_ev_qstats_update(
112 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
113 #endif /* EFSYS_OPT_QSTATS */
116 ef10_ev_rxlabel_init(
119 __in unsigned int label,
120 __in boolean_t packed_stream);
123 ef10_ev_rxlabel_fini(
125 __in unsigned int label);
129 __checkReturn efx_rc_t
132 __in efx_intr_type_t type,
133 __in efsys_mem_t *esmp);
137 __in efx_nic_t *enp);
141 __in efx_nic_t *enp);
144 ef10_intr_disable_unlocked(
145 __in efx_nic_t *enp);
147 __checkReturn efx_rc_t
150 __in unsigned int level);
153 ef10_intr_status_line(
155 __out boolean_t *fatalp,
156 __out uint32_t *qmaskp);
159 ef10_intr_status_message(
161 __in unsigned int message,
162 __out boolean_t *fatalp);
166 __in efx_nic_t *enp);
169 __in efx_nic_t *enp);
173 extern __checkReturn efx_rc_t
175 __in efx_nic_t *enp);
177 extern __checkReturn efx_rc_t
178 ef10_nic_set_drv_limits(
179 __inout efx_nic_t *enp,
180 __in efx_drv_limits_t *edlp);
182 extern __checkReturn efx_rc_t
183 ef10_nic_get_vi_pool(
185 __out uint32_t *vi_countp);
187 extern __checkReturn efx_rc_t
188 ef10_nic_get_bar_region(
190 __in efx_nic_region_t region,
191 __out uint32_t *offsetp,
192 __out size_t *sizep);
194 extern __checkReturn efx_rc_t
196 __in efx_nic_t *enp);
198 extern __checkReturn efx_rc_t
200 __in efx_nic_t *enp);
204 extern __checkReturn efx_rc_t
205 ef10_nic_register_test(
206 __in efx_nic_t *enp);
208 #endif /* EFSYS_OPT_DIAG */
212 __in efx_nic_t *enp);
216 __in efx_nic_t *enp);
221 extern __checkReturn efx_rc_t
224 __out efx_link_mode_t *link_modep);
226 extern __checkReturn efx_rc_t
229 __out boolean_t *mac_upp);
231 extern __checkReturn efx_rc_t
233 __in efx_nic_t *enp);
235 extern __checkReturn efx_rc_t
237 __in efx_nic_t *enp);
239 extern __checkReturn efx_rc_t
244 extern __checkReturn efx_rc_t
245 ef10_mac_reconfigure(
246 __in efx_nic_t *enp);
248 extern __checkReturn efx_rc_t
249 ef10_mac_multicast_list_set(
250 __in efx_nic_t *enp);
252 extern __checkReturn efx_rc_t
253 ef10_mac_filter_default_rxq_set(
256 __in boolean_t using_rss);
259 ef10_mac_filter_default_rxq_clear(
260 __in efx_nic_t *enp);
262 #if EFSYS_OPT_LOOPBACK
264 extern __checkReturn efx_rc_t
265 ef10_mac_loopback_set(
267 __in efx_link_mode_t link_mode,
268 __in efx_loopback_type_t loopback_type);
270 #endif /* EFSYS_OPT_LOOPBACK */
272 #if EFSYS_OPT_MAC_STATS
274 extern __checkReturn efx_rc_t
275 ef10_mac_stats_get_mask(
277 __inout_bcount(mask_size) uint32_t *maskp,
278 __in size_t mask_size);
280 extern __checkReturn efx_rc_t
281 ef10_mac_stats_update(
283 __in efsys_mem_t *esmp,
284 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
285 __inout_opt uint32_t *generationp);
287 #endif /* EFSYS_OPT_MAC_STATS */
294 extern __checkReturn efx_rc_t
297 __in const efx_mcdi_transport_t *mtp);
301 __in efx_nic_t *enp);
304 ef10_mcdi_send_request(
306 __in_bcount(hdr_len) void *hdrp,
308 __in_bcount(sdu_len) void *sdup,
309 __in size_t sdu_len);
311 extern __checkReturn boolean_t
312 ef10_mcdi_poll_response(
313 __in efx_nic_t *enp);
316 ef10_mcdi_read_response(
318 __out_bcount(length) void *bufferp,
323 ef10_mcdi_poll_reboot(
324 __in efx_nic_t *enp);
326 extern __checkReturn efx_rc_t
327 ef10_mcdi_feature_supported(
329 __in efx_mcdi_feature_id_t id,
330 __out boolean_t *supportedp);
333 ef10_mcdi_get_timeout(
335 __in efx_mcdi_req_t *emrp,
336 __out uint32_t *timeoutp);
338 #endif /* EFSYS_OPT_MCDI */
345 typedef struct ef10_link_state_s {
346 uint32_t els_adv_cap_mask;
347 uint32_t els_lp_cap_mask;
348 unsigned int els_fcntl;
349 efx_link_mode_t els_link_mode;
350 #if EFSYS_OPT_LOOPBACK
351 efx_loopback_type_t els_loopback;
353 boolean_t els_mac_up;
359 __in efx_qword_t *eqp,
360 __out efx_link_mode_t *link_modep);
362 extern __checkReturn efx_rc_t
365 __out ef10_link_state_t *elsp);
367 extern __checkReturn efx_rc_t
372 extern __checkReturn efx_rc_t
373 ef10_phy_reconfigure(
374 __in efx_nic_t *enp);
376 extern __checkReturn efx_rc_t
378 __in efx_nic_t *enp);
380 extern __checkReturn efx_rc_t
383 __out uint32_t *ouip);
385 #if EFSYS_OPT_PHY_STATS
387 extern __checkReturn efx_rc_t
388 ef10_phy_stats_update(
390 __in efsys_mem_t *esmp,
391 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
393 #endif /* EFSYS_OPT_PHY_STATS */
397 extern __checkReturn efx_rc_t
398 ef10_bist_enable_offline(
399 __in efx_nic_t *enp);
401 extern __checkReturn efx_rc_t
404 __in efx_bist_type_t type);
406 extern __checkReturn efx_rc_t
409 __in efx_bist_type_t type,
410 __out efx_bist_result_t *resultp,
411 __out_opt __drv_when(count > 0, __notnull)
412 uint32_t *value_maskp,
413 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
414 unsigned long *valuesp,
420 __in efx_bist_type_t type);
422 #endif /* EFSYS_OPT_BIST */
426 extern __checkReturn efx_rc_t
428 __in efx_nic_t *enp);
432 __in efx_nic_t *enp);
434 extern __checkReturn efx_rc_t
437 __in unsigned int index,
438 __in unsigned int label,
439 __in efsys_mem_t *esmp,
445 __out unsigned int *addedp);
449 __in efx_txq_t *etp);
451 extern __checkReturn efx_rc_t
454 __in_ecount(n) efx_buffer_t *eb,
456 __in unsigned int completed,
457 __inout unsigned int *addedp);
462 __in unsigned int added,
463 __in unsigned int pushed);
465 extern __checkReturn efx_rc_t
468 __in unsigned int ns);
470 extern __checkReturn efx_rc_t
472 __in efx_txq_t *etp);
476 __in efx_txq_t *etp);
478 extern __checkReturn efx_rc_t
480 __in efx_txq_t *etp);
483 ef10_tx_qpio_disable(
484 __in efx_txq_t *etp);
486 extern __checkReturn efx_rc_t
489 __in_ecount(buf_length) uint8_t *buffer,
490 __in size_t buf_length,
491 __in size_t pio_buf_offset);
493 extern __checkReturn efx_rc_t
496 __in size_t pkt_length,
497 __in unsigned int completed,
498 __inout unsigned int *addedp);
500 extern __checkReturn efx_rc_t
503 __in_ecount(n) efx_desc_t *ed,
505 __in unsigned int completed,
506 __inout unsigned int *addedp);
509 ef10_tx_qdesc_dma_create(
511 __in efsys_dma_addr_t addr,
514 __out efx_desc_t *edp);
517 ef10_tx_qdesc_tso_create(
519 __in uint16_t ipv4_id,
520 __in uint32_t tcp_seq,
521 __in uint8_t tcp_flags,
522 __out efx_desc_t *edp);
525 ef10_tx_qdesc_tso2_create(
527 __in uint16_t ipv4_id,
528 __in uint32_t tcp_seq,
529 __in uint16_t tcp_mss,
530 __out_ecount(count) efx_desc_t *edp,
534 ef10_tx_qdesc_vlantci_create(
536 __in uint16_t vlan_tci,
537 __out efx_desc_t *edp);
543 ef10_tx_qstats_update(
545 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
547 #endif /* EFSYS_OPT_QSTATS */
549 typedef uint32_t efx_piobuf_handle_t;
551 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1)
553 extern __checkReturn efx_rc_t
555 __inout efx_nic_t *enp,
556 __out uint32_t *bufnump,
557 __out efx_piobuf_handle_t *handlep,
558 __out uint32_t *blknump,
559 __out uint32_t *offsetp,
560 __out size_t *sizep);
562 extern __checkReturn efx_rc_t
564 __inout efx_nic_t *enp,
565 __in uint32_t bufnum,
566 __in uint32_t blknum);
568 extern __checkReturn efx_rc_t
570 __inout efx_nic_t *enp,
571 __in uint32_t vi_index,
572 __in efx_piobuf_handle_t handle);
574 extern __checkReturn efx_rc_t
576 __inout efx_nic_t *enp,
577 __in uint32_t vi_index);
585 extern __checkReturn efx_rc_t
587 __in efx_nic_t *enp);
589 #if EFSYS_OPT_RX_SCATTER
590 extern __checkReturn efx_rc_t
591 ef10_rx_scatter_enable(
593 __in unsigned int buf_size);
594 #endif /* EFSYS_OPT_RX_SCATTER */
597 #if EFSYS_OPT_RX_SCALE
599 extern __checkReturn efx_rc_t
600 ef10_rx_scale_mode_set(
602 __in efx_rx_hash_alg_t alg,
603 __in efx_rx_hash_type_t type,
604 __in boolean_t insert);
606 extern __checkReturn efx_rc_t
607 ef10_rx_scale_key_set(
609 __in_ecount(n) uint8_t *key,
612 extern __checkReturn efx_rc_t
613 ef10_rx_scale_tbl_set(
615 __in_ecount(n) unsigned int *table,
618 extern __checkReturn uint32_t
621 __in efx_rx_hash_alg_t func,
622 __in uint8_t *buffer);
624 #endif /* EFSYS_OPT_RX_SCALE */
626 extern __checkReturn efx_rc_t
627 ef10_rx_prefix_pktlen(
629 __in uint8_t *buffer,
630 __out uint16_t *lengthp);
635 __in_ecount(n) efsys_dma_addr_t *addrp,
638 __in unsigned int completed,
639 __in unsigned int added);
644 __in unsigned int added,
645 __inout unsigned int *pushedp);
647 extern __checkReturn efx_rc_t
649 __in efx_rxq_t *erp);
653 __in efx_rxq_t *erp);
655 extern __checkReturn efx_rc_t
658 __in unsigned int index,
659 __in unsigned int label,
660 __in efx_rxq_type_t type,
661 __in efsys_mem_t *esmp,
665 __in efx_rxq_t *erp);
669 __in efx_rxq_t *erp);
673 __in efx_nic_t *enp);
677 typedef struct ef10_filter_handle_s {
680 } ef10_filter_handle_t;
682 typedef struct ef10_filter_entry_s {
683 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
684 ef10_filter_handle_t efe_handle;
685 } ef10_filter_entry_t;
688 * BUSY flag indicates that an update is in progress.
689 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
691 #define EFX_EF10_FILTER_FLAG_BUSY 1U
692 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
693 #define EFX_EF10_FILTER_FLAGS 3U
696 * Size of the hash table used by the driver. Doesn't need to be the
697 * same size as the hardware's table.
699 #define EFX_EF10_FILTER_TBL_ROWS 8192
701 /* Only need to allow for one directed and one unknown unicast filter */
702 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
704 /* Allow for the broadcast address to be added to the multicast list */
705 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
707 typedef struct ef10_filter_table_s {
708 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
709 efx_rxq_t *eft_default_rxq;
710 boolean_t eft_using_rss;
711 uint32_t eft_unicst_filter_indexes[
712 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
713 uint32_t eft_unicst_filter_count;
714 uint32_t eft_mulcst_filter_indexes[
715 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
716 uint32_t eft_mulcst_filter_count;
717 boolean_t eft_using_all_mulcst;
718 } ef10_filter_table_t;
720 __checkReturn efx_rc_t
722 __in efx_nic_t *enp);
726 __in efx_nic_t *enp);
728 __checkReturn efx_rc_t
730 __in efx_nic_t *enp);
732 __checkReturn efx_rc_t
735 __inout efx_filter_spec_t *spec,
736 __in boolean_t may_replace);
738 __checkReturn efx_rc_t
741 __inout efx_filter_spec_t *spec);
743 extern __checkReturn efx_rc_t
744 ef10_filter_supported_filters(
746 __out uint32_t *list,
747 __out size_t *length);
749 extern __checkReturn efx_rc_t
750 ef10_filter_reconfigure(
752 __in_ecount(6) uint8_t const *mac_addr,
753 __in boolean_t all_unicst,
754 __in boolean_t mulcst,
755 __in boolean_t all_mulcst,
756 __in boolean_t brdcst,
757 __in_ecount(6*count) uint8_t const *addrs,
758 __in uint32_t count);
761 ef10_filter_get_default_rxq(
763 __out efx_rxq_t **erpp,
764 __out boolean_t *using_rss);
767 ef10_filter_default_rxq_set(
770 __in boolean_t using_rss);
773 ef10_filter_default_rxq_clear(
774 __in efx_nic_t *enp);
777 #endif /* EFSYS_OPT_FILTER */
779 extern __checkReturn efx_rc_t
780 efx_mcdi_get_function_info(
783 __out_opt uint32_t *vfp);
785 extern __checkReturn efx_rc_t
786 efx_mcdi_privilege_mask(
790 __out uint32_t *maskp);
792 extern __checkReturn efx_rc_t
793 efx_mcdi_get_port_assignment(
795 __out uint32_t *portp);
797 extern __checkReturn efx_rc_t
798 efx_mcdi_get_port_modes(
800 __out uint32_t *modesp,
801 __out_opt uint32_t *current_modep);
803 extern __checkReturn efx_rc_t
804 ef10_nic_get_port_mode_bandwidth(
805 __in uint32_t port_mode,
806 __out uint32_t *bandwidth_mbpsp);
808 extern __checkReturn efx_rc_t
809 efx_mcdi_get_mac_address_pf(
811 __out_ecount_opt(6) uint8_t mac_addrp[6]);
813 extern __checkReturn efx_rc_t
814 efx_mcdi_get_mac_address_vf(
816 __out_ecount_opt(6) uint8_t mac_addrp[6]);
818 extern __checkReturn efx_rc_t
821 __out uint32_t *sys_freqp,
822 __out uint32_t *dpcpu_freqp);
825 extern __checkReturn efx_rc_t
826 efx_mcdi_get_vector_cfg(
828 __out_opt uint32_t *vec_basep,
829 __out_opt uint32_t *pf_nvecp,
830 __out_opt uint32_t *vf_nvecp);
832 extern __checkReturn efx_rc_t
833 ef10_get_datapath_caps(
834 __in efx_nic_t *enp);
836 extern __checkReturn efx_rc_t
837 ef10_get_privilege_mask(
839 __out uint32_t *maskp);
841 extern __checkReturn efx_rc_t
842 ef10_external_port_mapping(
845 __out uint8_t *external_portp);
851 #endif /* _SYS_EF10_IMPL_H */