1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
7 #ifndef _SYS_EF10_IMPL_H
8 #define _SYS_EF10_IMPL_H
15 /* Number of hardware PIO buffers (for compile-time resource dimensions) */
16 #define EF10_MAX_PIOBUF_NBUFS (16)
18 #if EFSYS_OPT_HUNTINGTON
19 # if (EF10_MAX_PIOBUF_NBUFS < HUNT_PIOBUF_NBUFS)
20 # error "EF10_MAX_PIOBUF_NBUFS too small"
22 #endif /* EFSYS_OPT_HUNTINGTON */
24 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD_PIOBUF_NBUFS)
25 # error "EF10_MAX_PIOBUF_NBUFS too small"
27 #endif /* EFSYS_OPT_MEDFORD */
28 #if EFSYS_OPT_MEDFORD2
29 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD2_PIOBUF_NBUFS)
30 # error "EF10_MAX_PIOBUF_NBUFS too small"
32 #endif /* EFSYS_OPT_MEDFORD2 */
37 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
38 * possibly be increased, or the write size reported by newer firmware used
41 #define EF10_NVRAM_CHUNK 0x80
44 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned
45 * to an 8 descriptor boundary.
47 #define EF10_RX_WPTR_ALIGN 8
50 * Max byte offset into the packet the TCP header must start for the hardware
51 * to be able to parse the packet correctly.
53 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
55 /* Invalid RSS context handle */
56 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
61 __checkReturn efx_rc_t
69 __checkReturn efx_rc_t
72 __in unsigned int index,
73 __in efsys_mem_t *esmp,
84 __checkReturn efx_rc_t
87 __in unsigned int count);
94 __checkReturn efx_rc_t
97 __in unsigned int us);
101 ef10_ev_qstats_update(
103 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
104 #endif /* EFSYS_OPT_QSTATS */
107 ef10_ev_rxlabel_init(
110 __in unsigned int label,
111 __in efx_rxq_type_t type);
114 ef10_ev_rxlabel_fini(
116 __in unsigned int label);
120 __checkReturn efx_rc_t
123 __in efx_intr_type_t type,
124 __in efsys_mem_t *esmp);
128 __in efx_nic_t *enp);
132 __in efx_nic_t *enp);
135 ef10_intr_disable_unlocked(
136 __in efx_nic_t *enp);
138 __checkReturn efx_rc_t
141 __in unsigned int level);
144 ef10_intr_status_line(
146 __out boolean_t *fatalp,
147 __out uint32_t *qmaskp);
150 ef10_intr_status_message(
152 __in unsigned int message,
153 __out boolean_t *fatalp);
157 __in efx_nic_t *enp);
160 __in efx_nic_t *enp);
164 extern __checkReturn efx_rc_t
166 __in efx_nic_t *enp);
168 extern __checkReturn efx_rc_t
169 ef10_nic_set_drv_limits(
170 __inout efx_nic_t *enp,
171 __in efx_drv_limits_t *edlp);
173 extern __checkReturn efx_rc_t
174 ef10_nic_get_vi_pool(
176 __out uint32_t *vi_countp);
178 extern __checkReturn efx_rc_t
179 ef10_nic_get_bar_region(
181 __in efx_nic_region_t region,
182 __out uint32_t *offsetp,
183 __out size_t *sizep);
185 extern __checkReturn efx_rc_t
187 __in efx_nic_t *enp);
189 extern __checkReturn efx_rc_t
191 __in efx_nic_t *enp);
193 extern __checkReturn boolean_t
194 ef10_nic_hw_unavailable(
195 __in efx_nic_t *enp);
199 extern __checkReturn efx_rc_t
200 ef10_nic_register_test(
201 __in efx_nic_t *enp);
203 #endif /* EFSYS_OPT_DIAG */
207 __in efx_nic_t *enp);
211 __in efx_nic_t *enp);
216 extern __checkReturn efx_rc_t
219 __out efx_link_mode_t *link_modep);
221 extern __checkReturn efx_rc_t
224 __out boolean_t *mac_upp);
226 extern __checkReturn efx_rc_t
228 __in efx_nic_t *enp);
230 extern __checkReturn efx_rc_t
232 __in efx_nic_t *enp);
234 extern __checkReturn efx_rc_t
239 extern __checkReturn efx_rc_t
240 ef10_mac_reconfigure(
241 __in efx_nic_t *enp);
243 extern __checkReturn efx_rc_t
244 ef10_mac_multicast_list_set(
245 __in efx_nic_t *enp);
247 extern __checkReturn efx_rc_t
248 ef10_mac_filter_default_rxq_set(
251 __in boolean_t using_rss);
254 ef10_mac_filter_default_rxq_clear(
255 __in efx_nic_t *enp);
257 #if EFSYS_OPT_LOOPBACK
259 extern __checkReturn efx_rc_t
260 ef10_mac_loopback_set(
262 __in efx_link_mode_t link_mode,
263 __in efx_loopback_type_t loopback_type);
265 #endif /* EFSYS_OPT_LOOPBACK */
267 #if EFSYS_OPT_MAC_STATS
269 extern __checkReturn efx_rc_t
270 ef10_mac_stats_get_mask(
272 __inout_bcount(mask_size) uint32_t *maskp,
273 __in size_t mask_size);
275 extern __checkReturn efx_rc_t
276 ef10_mac_stats_update(
278 __in efsys_mem_t *esmp,
279 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
280 __inout_opt uint32_t *generationp);
282 #endif /* EFSYS_OPT_MAC_STATS */
289 extern __checkReturn efx_rc_t
292 __in const efx_mcdi_transport_t *mtp);
296 __in efx_nic_t *enp);
299 ef10_mcdi_send_request(
301 __in_bcount(hdr_len) void *hdrp,
303 __in_bcount(sdu_len) void *sdup,
304 __in size_t sdu_len);
306 extern __checkReturn boolean_t
307 ef10_mcdi_poll_response(
308 __in efx_nic_t *enp);
311 ef10_mcdi_read_response(
313 __out_bcount(length) void *bufferp,
318 ef10_mcdi_poll_reboot(
319 __in efx_nic_t *enp);
321 extern __checkReturn efx_rc_t
322 ef10_mcdi_feature_supported(
324 __in efx_mcdi_feature_id_t id,
325 __out boolean_t *supportedp);
328 ef10_mcdi_get_timeout(
330 __in efx_mcdi_req_t *emrp,
331 __out uint32_t *timeoutp);
333 #endif /* EFSYS_OPT_MCDI */
337 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
339 extern __checkReturn efx_rc_t
340 ef10_nvram_buf_read_tlv(
342 __in_bcount(max_seg_size) caddr_t seg_data,
343 __in size_t max_seg_size,
345 __deref_out_bcount_opt(*sizep) caddr_t *datap,
346 __out size_t *sizep);
348 extern __checkReturn efx_rc_t
349 ef10_nvram_buf_write_tlv(
350 __inout_bcount(partn_size) caddr_t partn_data,
351 __in size_t partn_size,
353 __in_bcount(tag_size) caddr_t tag_data,
354 __in size_t tag_size,
355 __out size_t *total_lengthp);
357 extern __checkReturn efx_rc_t
358 ef10_nvram_partn_read_tlv(
362 __deref_out_bcount_opt(*sizep) caddr_t *datap,
363 __out size_t *sizep);
365 extern __checkReturn efx_rc_t
366 ef10_nvram_partn_write_tlv(
370 __in_bcount(size) caddr_t data,
373 extern __checkReturn efx_rc_t
374 ef10_nvram_partn_write_segment_tlv(
378 __in_bcount(size) caddr_t data,
380 __in boolean_t all_segments);
382 extern __checkReturn efx_rc_t
383 ef10_nvram_partn_lock(
385 __in uint32_t partn);
387 extern __checkReturn efx_rc_t
388 ef10_nvram_partn_unlock(
391 __out_opt uint32_t *resultp);
393 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
399 extern __checkReturn efx_rc_t
401 __in efx_nic_t *enp);
403 #endif /* EFSYS_OPT_DIAG */
405 extern __checkReturn efx_rc_t
406 ef10_nvram_type_to_partn(
408 __in efx_nvram_type_t type,
409 __out uint32_t *partnp);
411 extern __checkReturn efx_rc_t
412 ef10_nvram_partn_size(
415 __out size_t *sizep);
417 extern __checkReturn efx_rc_t
418 ef10_nvram_partn_rw_start(
421 __out size_t *chunk_sizep);
423 extern __checkReturn efx_rc_t
424 ef10_nvram_partn_read_mode(
427 __in unsigned int offset,
428 __out_bcount(size) caddr_t data,
432 extern __checkReturn efx_rc_t
433 ef10_nvram_partn_read(
436 __in unsigned int offset,
437 __out_bcount(size) caddr_t data,
440 extern __checkReturn efx_rc_t
441 ef10_nvram_partn_read_backup(
444 __in unsigned int offset,
445 __out_bcount(size) caddr_t data,
448 extern __checkReturn efx_rc_t
449 ef10_nvram_partn_erase(
452 __in unsigned int offset,
455 extern __checkReturn efx_rc_t
456 ef10_nvram_partn_write(
459 __in unsigned int offset,
460 __in_bcount(size) caddr_t data,
463 extern __checkReturn efx_rc_t
464 ef10_nvram_partn_rw_finish(
467 __out_opt uint32_t *verify_resultp);
469 extern __checkReturn efx_rc_t
470 ef10_nvram_partn_get_version(
473 __out uint32_t *subtypep,
474 __out_ecount(4) uint16_t version[4]);
476 extern __checkReturn efx_rc_t
477 ef10_nvram_partn_set_version(
480 __in_ecount(4) uint16_t version[4]);
482 extern __checkReturn efx_rc_t
483 ef10_nvram_buffer_validate(
485 __in_bcount(buffer_size)
487 __in size_t buffer_size);
490 ef10_nvram_buffer_init(
491 __out_bcount(buffer_size)
493 __in size_t buffer_size);
495 extern __checkReturn efx_rc_t
496 ef10_nvram_buffer_create(
497 __in uint32_t partn_type,
498 __out_bcount(buffer_size)
500 __in size_t buffer_size);
502 extern __checkReturn efx_rc_t
503 ef10_nvram_buffer_find_item_start(
504 __in_bcount(buffer_size)
506 __in size_t buffer_size,
507 __out uint32_t *startp);
509 extern __checkReturn efx_rc_t
510 ef10_nvram_buffer_find_end(
511 __in_bcount(buffer_size)
513 __in size_t buffer_size,
514 __in uint32_t offset,
515 __out uint32_t *endp);
517 extern __checkReturn __success(return != B_FALSE) boolean_t
518 ef10_nvram_buffer_find_item(
519 __in_bcount(buffer_size)
521 __in size_t buffer_size,
522 __in uint32_t offset,
523 __out uint32_t *startp,
524 __out uint32_t *lengthp);
526 extern __checkReturn efx_rc_t
527 ef10_nvram_buffer_peek_item(
528 __in_bcount(buffer_size)
530 __in size_t buffer_size,
531 __in uint32_t offset,
532 __out uint32_t *tagp,
533 __out uint32_t *lengthp,
534 __out uint32_t *value_offsetp);
536 extern __checkReturn efx_rc_t
537 ef10_nvram_buffer_get_item(
538 __in_bcount(buffer_size)
540 __in size_t buffer_size,
541 __in uint32_t offset,
542 __in uint32_t length,
543 __out uint32_t *tagp,
544 __out_bcount_part(value_max_size, *lengthp)
546 __in size_t value_max_size,
547 __out uint32_t *lengthp);
549 extern __checkReturn efx_rc_t
550 ef10_nvram_buffer_insert_item(
551 __in_bcount(buffer_size)
553 __in size_t buffer_size,
554 __in uint32_t offset,
556 __in_bcount(length) caddr_t valuep,
557 __in uint32_t length,
558 __out uint32_t *lengthp);
560 extern __checkReturn efx_rc_t
561 ef10_nvram_buffer_modify_item(
562 __in_bcount(buffer_size)
564 __in size_t buffer_size,
565 __in uint32_t offset,
567 __in_bcount(length) caddr_t valuep,
568 __in uint32_t length,
569 __out uint32_t *lengthp);
571 extern __checkReturn efx_rc_t
572 ef10_nvram_buffer_delete_item(
573 __in_bcount(buffer_size)
575 __in size_t buffer_size,
576 __in uint32_t offset,
577 __in uint32_t length,
580 extern __checkReturn efx_rc_t
581 ef10_nvram_buffer_finish(
582 __in_bcount(buffer_size)
584 __in size_t buffer_size);
586 #endif /* EFSYS_OPT_NVRAM */
591 typedef struct ef10_link_state_s {
592 uint32_t els_adv_cap_mask;
593 uint32_t els_lp_cap_mask;
594 unsigned int els_fcntl;
595 efx_link_mode_t els_link_mode;
596 #if EFSYS_OPT_LOOPBACK
597 efx_loopback_type_t els_loopback;
599 boolean_t els_mac_up;
605 __in efx_qword_t *eqp,
606 __out efx_link_mode_t *link_modep);
608 extern __checkReturn efx_rc_t
611 __out ef10_link_state_t *elsp);
613 extern __checkReturn efx_rc_t
618 extern __checkReturn efx_rc_t
619 ef10_phy_reconfigure(
620 __in efx_nic_t *enp);
622 extern __checkReturn efx_rc_t
624 __in efx_nic_t *enp);
626 extern __checkReturn efx_rc_t
629 __out uint32_t *ouip);
631 #if EFSYS_OPT_PHY_STATS
633 extern __checkReturn efx_rc_t
634 ef10_phy_stats_update(
636 __in efsys_mem_t *esmp,
637 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
639 #endif /* EFSYS_OPT_PHY_STATS */
643 extern __checkReturn efx_rc_t
644 ef10_bist_enable_offline(
645 __in efx_nic_t *enp);
647 extern __checkReturn efx_rc_t
650 __in efx_bist_type_t type);
652 extern __checkReturn efx_rc_t
655 __in efx_bist_type_t type,
656 __out efx_bist_result_t *resultp,
657 __out_opt __drv_when(count > 0, __notnull)
658 uint32_t *value_maskp,
659 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
660 unsigned long *valuesp,
666 __in efx_bist_type_t type);
668 #endif /* EFSYS_OPT_BIST */
672 extern __checkReturn efx_rc_t
674 __in efx_nic_t *enp);
678 __in efx_nic_t *enp);
680 extern __checkReturn efx_rc_t
683 __in unsigned int index,
684 __in unsigned int label,
685 __in efsys_mem_t *esmp,
691 __out unsigned int *addedp);
695 __in efx_txq_t *etp);
697 extern __checkReturn efx_rc_t
700 __in_ecount(ndescs) efx_buffer_t *ebp,
701 __in unsigned int ndescs,
702 __in unsigned int completed,
703 __inout unsigned int *addedp);
708 __in unsigned int added,
709 __in unsigned int pushed);
711 #if EFSYS_OPT_RX_PACKED_STREAM
713 ef10_rx_qpush_ps_credits(
714 __in efx_rxq_t *erp);
716 extern __checkReturn uint8_t *
717 ef10_rx_qps_packet_info(
719 __in uint8_t *buffer,
720 __in uint32_t buffer_length,
721 __in uint32_t current_offset,
722 __out uint16_t *lengthp,
723 __out uint32_t *next_offsetp,
724 __out uint32_t *timestamp);
727 extern __checkReturn efx_rc_t
730 __in unsigned int ns);
732 extern __checkReturn efx_rc_t
734 __in efx_txq_t *etp);
738 __in efx_txq_t *etp);
740 extern __checkReturn efx_rc_t
742 __in efx_txq_t *etp);
745 ef10_tx_qpio_disable(
746 __in efx_txq_t *etp);
748 extern __checkReturn efx_rc_t
751 __in_ecount(buf_length) uint8_t *buffer,
752 __in size_t buf_length,
753 __in size_t pio_buf_offset);
755 extern __checkReturn efx_rc_t
758 __in size_t pkt_length,
759 __in unsigned int completed,
760 __inout unsigned int *addedp);
762 extern __checkReturn efx_rc_t
765 __in_ecount(n) efx_desc_t *ed,
767 __in unsigned int completed,
768 __inout unsigned int *addedp);
771 ef10_tx_qdesc_dma_create(
773 __in efsys_dma_addr_t addr,
776 __out efx_desc_t *edp);
779 ef10_tx_qdesc_tso_create(
781 __in uint16_t ipv4_id,
782 __in uint32_t tcp_seq,
783 __in uint8_t tcp_flags,
784 __out efx_desc_t *edp);
787 ef10_tx_qdesc_tso2_create(
789 __in uint16_t ipv4_id,
790 __in uint16_t outer_ipv4_id,
791 __in uint32_t tcp_seq,
792 __in uint16_t tcp_mss,
793 __out_ecount(count) efx_desc_t *edp,
797 ef10_tx_qdesc_vlantci_create(
799 __in uint16_t vlan_tci,
800 __out efx_desc_t *edp);
803 ef10_tx_qdesc_checksum_create(
806 __out efx_desc_t *edp);
811 ef10_tx_qstats_update(
813 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
815 #endif /* EFSYS_OPT_QSTATS */
817 typedef uint32_t efx_piobuf_handle_t;
819 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1)
821 extern __checkReturn efx_rc_t
823 __inout efx_nic_t *enp,
824 __out uint32_t *bufnump,
825 __out efx_piobuf_handle_t *handlep,
826 __out uint32_t *blknump,
827 __out uint32_t *offsetp,
828 __out size_t *sizep);
830 extern __checkReturn efx_rc_t
832 __inout efx_nic_t *enp,
833 __in uint32_t bufnum,
834 __in uint32_t blknum);
836 extern __checkReturn efx_rc_t
838 __inout efx_nic_t *enp,
839 __in uint32_t vi_index,
840 __in efx_piobuf_handle_t handle);
842 extern __checkReturn efx_rc_t
844 __inout efx_nic_t *enp,
845 __in uint32_t vi_index);
852 extern __checkReturn efx_rc_t
854 __in efx_nic_t *enp);
856 extern __checkReturn efx_rc_t
859 __out size_t *sizep);
861 extern __checkReturn efx_rc_t
864 __out_bcount(size) caddr_t data,
867 extern __checkReturn efx_rc_t
870 __in_bcount(size) caddr_t data,
873 extern __checkReturn efx_rc_t
876 __in_bcount(size) caddr_t data,
879 extern __checkReturn efx_rc_t
882 __in_bcount(size) caddr_t data,
884 __inout efx_vpd_value_t *evvp);
886 extern __checkReturn efx_rc_t
889 __in_bcount(size) caddr_t data,
891 __in efx_vpd_value_t *evvp);
893 extern __checkReturn efx_rc_t
896 __in_bcount(size) caddr_t data,
898 __out efx_vpd_value_t *evvp,
899 __inout unsigned int *contp);
901 extern __checkReturn efx_rc_t
904 __in_bcount(size) caddr_t data,
909 __in efx_nic_t *enp);
911 #endif /* EFSYS_OPT_VPD */
916 extern __checkReturn efx_rc_t
918 __in efx_nic_t *enp);
920 #if EFSYS_OPT_RX_SCATTER
921 extern __checkReturn efx_rc_t
922 ef10_rx_scatter_enable(
924 __in unsigned int buf_size);
925 #endif /* EFSYS_OPT_RX_SCATTER */
928 #if EFSYS_OPT_RX_SCALE
930 extern __checkReturn efx_rc_t
931 ef10_rx_scale_context_alloc(
933 __in efx_rx_scale_context_type_t type,
934 __in uint32_t num_queues,
935 __out uint32_t *rss_contextp);
937 extern __checkReturn efx_rc_t
938 ef10_rx_scale_context_free(
940 __in uint32_t rss_context);
942 extern __checkReturn efx_rc_t
943 ef10_rx_scale_mode_set(
945 __in uint32_t rss_context,
946 __in efx_rx_hash_alg_t alg,
947 __in efx_rx_hash_type_t type,
948 __in boolean_t insert);
950 extern __checkReturn efx_rc_t
951 ef10_rx_scale_key_set(
953 __in uint32_t rss_context,
954 __in_ecount(n) uint8_t *key,
957 extern __checkReturn efx_rc_t
958 ef10_rx_scale_tbl_set(
960 __in uint32_t rss_context,
961 __in_ecount(n) unsigned int *table,
964 extern __checkReturn uint32_t
967 __in efx_rx_hash_alg_t func,
968 __in uint8_t *buffer);
970 #endif /* EFSYS_OPT_RX_SCALE */
972 extern __checkReturn efx_rc_t
973 ef10_rx_prefix_pktlen(
975 __in uint8_t *buffer,
976 __out uint16_t *lengthp);
981 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
983 __in unsigned int ndescs,
984 __in unsigned int completed,
985 __in unsigned int added);
990 __in unsigned int added,
991 __inout unsigned int *pushedp);
993 extern __checkReturn efx_rc_t
995 __in efx_rxq_t *erp);
999 __in efx_rxq_t *erp);
1001 union efx_rxq_type_data_u;
1003 extern __checkReturn efx_rc_t
1005 __in efx_nic_t *enp,
1006 __in unsigned int index,
1007 __in unsigned int label,
1008 __in efx_rxq_type_t type,
1009 __in const union efx_rxq_type_data_u *type_data,
1010 __in efsys_mem_t *esmp,
1013 __in unsigned int flags,
1014 __in efx_evq_t *eep,
1015 __in efx_rxq_t *erp);
1019 __in efx_rxq_t *erp);
1023 __in efx_nic_t *enp);
1025 #if EFSYS_OPT_FILTER
1027 typedef struct ef10_filter_handle_s {
1030 } ef10_filter_handle_t;
1032 typedef struct ef10_filter_entry_s {
1033 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1034 ef10_filter_handle_t efe_handle;
1035 } ef10_filter_entry_t;
1038 * BUSY flag indicates that an update is in progress.
1039 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1041 #define EFX_EF10_FILTER_FLAG_BUSY 1U
1042 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
1043 #define EFX_EF10_FILTER_FLAGS 3U
1046 * Size of the hash table used by the driver. Doesn't need to be the
1047 * same size as the hardware's table.
1049 #define EFX_EF10_FILTER_TBL_ROWS 8192
1051 /* Only need to allow for one directed and one unknown unicast filter */
1052 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
1054 /* Allow for the broadcast address to be added to the multicast list */
1055 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
1058 * For encapsulated packets, there is one filter each for each combination of
1059 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1060 * multicast inner frames.
1062 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
1064 typedef struct ef10_filter_table_s {
1065 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1066 efx_rxq_t *eft_default_rxq;
1067 boolean_t eft_using_rss;
1068 uint32_t eft_unicst_filter_indexes[
1069 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1070 uint32_t eft_unicst_filter_count;
1071 uint32_t eft_mulcst_filter_indexes[
1072 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1073 uint32_t eft_mulcst_filter_count;
1074 boolean_t eft_using_all_mulcst;
1075 uint32_t eft_encap_filter_indexes[
1076 EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1077 uint32_t eft_encap_filter_count;
1078 } ef10_filter_table_t;
1080 __checkReturn efx_rc_t
1082 __in efx_nic_t *enp);
1086 __in efx_nic_t *enp);
1088 __checkReturn efx_rc_t
1089 ef10_filter_restore(
1090 __in efx_nic_t *enp);
1092 __checkReturn efx_rc_t
1094 __in efx_nic_t *enp,
1095 __inout efx_filter_spec_t *spec,
1096 __in boolean_t may_replace);
1098 __checkReturn efx_rc_t
1100 __in efx_nic_t *enp,
1101 __inout efx_filter_spec_t *spec);
1103 extern __checkReturn efx_rc_t
1104 ef10_filter_supported_filters(
1105 __in efx_nic_t *enp,
1106 __out_ecount(buffer_length) uint32_t *buffer,
1107 __in size_t buffer_length,
1108 __out size_t *list_lengthp);
1110 extern __checkReturn efx_rc_t
1111 ef10_filter_reconfigure(
1112 __in efx_nic_t *enp,
1113 __in_ecount(6) uint8_t const *mac_addr,
1114 __in boolean_t all_unicst,
1115 __in boolean_t mulcst,
1116 __in boolean_t all_mulcst,
1117 __in boolean_t brdcst,
1118 __in_ecount(6*count) uint8_t const *addrs,
1119 __in uint32_t count);
1122 ef10_filter_get_default_rxq(
1123 __in efx_nic_t *enp,
1124 __out efx_rxq_t **erpp,
1125 __out boolean_t *using_rss);
1128 ef10_filter_default_rxq_set(
1129 __in efx_nic_t *enp,
1130 __in efx_rxq_t *erp,
1131 __in boolean_t using_rss);
1134 ef10_filter_default_rxq_clear(
1135 __in efx_nic_t *enp);
1138 #endif /* EFSYS_OPT_FILTER */
1140 extern __checkReturn efx_rc_t
1141 efx_mcdi_get_function_info(
1142 __in efx_nic_t *enp,
1143 __out uint32_t *pfp,
1144 __out_opt uint32_t *vfp);
1146 extern __checkReturn efx_rc_t
1147 efx_mcdi_privilege_mask(
1148 __in efx_nic_t *enp,
1151 __out uint32_t *maskp);
1153 extern __checkReturn efx_rc_t
1154 efx_mcdi_get_port_assignment(
1155 __in efx_nic_t *enp,
1156 __out uint32_t *portp);
1158 extern __checkReturn efx_rc_t
1159 efx_mcdi_get_port_modes(
1160 __in efx_nic_t *enp,
1161 __out uint32_t *modesp,
1162 __out_opt uint32_t *current_modep,
1163 __out_opt uint32_t *default_modep);
1165 extern __checkReturn efx_rc_t
1166 ef10_nic_get_port_mode_bandwidth(
1167 __in uint32_t port_mode,
1168 __out uint32_t *bandwidth_mbpsp);
1170 extern __checkReturn efx_rc_t
1171 efx_mcdi_get_mac_address_pf(
1172 __in efx_nic_t *enp,
1173 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1175 extern __checkReturn efx_rc_t
1176 efx_mcdi_get_mac_address_vf(
1177 __in efx_nic_t *enp,
1178 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1180 extern __checkReturn efx_rc_t
1182 __in efx_nic_t *enp,
1183 __out uint32_t *sys_freqp,
1184 __out uint32_t *dpcpu_freqp);
1187 extern __checkReturn efx_rc_t
1188 efx_mcdi_get_rxdp_config(
1189 __in efx_nic_t *enp,
1190 __out uint32_t *end_paddingp);
1192 extern __checkReturn efx_rc_t
1193 efx_mcdi_get_vector_cfg(
1194 __in efx_nic_t *enp,
1195 __out_opt uint32_t *vec_basep,
1196 __out_opt uint32_t *pf_nvecp,
1197 __out_opt uint32_t *vf_nvecp);
1199 extern __checkReturn efx_rc_t
1200 ef10_get_privilege_mask(
1201 __in efx_nic_t *enp,
1202 __out uint32_t *maskp);
1204 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1206 extern __checkReturn efx_rc_t
1207 efx_mcdi_get_nic_global(
1208 __in efx_nic_t *enp,
1210 __out uint32_t *valuep);
1212 extern __checkReturn efx_rc_t
1213 efx_mcdi_set_nic_global(
1214 __in efx_nic_t *enp,
1216 __in uint32_t value);
1218 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1221 #if EFSYS_OPT_RX_PACKED_STREAM
1223 /* Data space per credit in packed stream mode */
1224 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1227 * Received packets are always aligned at this boundary. Also there always
1228 * exists a gap of this size between packets.
1229 * (see SF-112241-TC, 4.5)
1231 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64
1234 * Size of a pseudo-header prepended to received packets
1235 * in packed stream mode
1237 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1239 /* Minimum space for packet in packed stream mode */
1240 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
1241 P2ROUNDUP(EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
1243 EFX_RX_PACKED_STREAM_ALIGNMENT, \
1244 EFX_RX_PACKED_STREAM_ALIGNMENT)
1246 /* Maximum number of credits */
1247 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1249 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1251 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1254 * Maximum DMA length and buffer stride alignment.
1255 * (see SF-119419-TC, 3.2)
1257 #define EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT 64
1265 #endif /* _SYS_EF10_IMPL_H */