1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
7 #ifndef _SYS_EF10_IMPL_H
8 #define _SYS_EF10_IMPL_H
14 #define EF10_EVQ_MAXNEVS 32768
15 #define EF10_EVQ_MINNEVS 512
17 #define EF10_RXQ_MAXNDESCS 4096
18 #define EF10_RXQ_MINNDESCS 512
20 #define EF10_TXQ_MINNDESCS 512
22 #define EF10_EVQ_DESC_SIZE (sizeof (efx_qword_t))
23 #define EF10_RXQ_DESC_SIZE (sizeof (efx_qword_t))
24 #define EF10_TXQ_DESC_SIZE (sizeof (efx_qword_t))
26 /* Number of hardware EVQ buffers (for compile-time resource dimensions) */
27 #define EF10_EVQ_MAXNBUFS (64)
29 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
30 #define EF10_TXQ_MAXNBUFS 8
32 #if EFSYS_OPT_HUNTINGTON
33 # if (EF10_EVQ_MAXNBUFS < HUNT_EVQ_MAXNBUFS)
34 # error "EF10_EVQ_MAXNBUFS too small"
36 #endif /* EFSYS_OPT_HUNTINGTON */
38 # if (EF10_EVQ_MAXNBUFS < MEDFORD_EVQ_MAXNBUFS)
39 # error "EF10_EVQ_MAXNBUFS too small"
41 #endif /* EFSYS_OPT_MEDFORD */
42 #if EFSYS_OPT_MEDFORD2
43 # if (EF10_EVQ_MAXNBUFS < MEDFORD2_EVQ_MAXNBUFS)
44 # error "EF10_EVQ_MAXNBUFS too small"
46 #endif /* EFSYS_OPT_MEDFORD2 */
48 /* Number of hardware PIO buffers (for compile-time resource dimensions) */
49 #define EF10_MAX_PIOBUF_NBUFS (16)
51 #if EFSYS_OPT_HUNTINGTON
52 # if (EF10_MAX_PIOBUF_NBUFS < HUNT_PIOBUF_NBUFS)
53 # error "EF10_MAX_PIOBUF_NBUFS too small"
55 #endif /* EFSYS_OPT_HUNTINGTON */
57 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD_PIOBUF_NBUFS)
58 # error "EF10_MAX_PIOBUF_NBUFS too small"
60 #endif /* EFSYS_OPT_MEDFORD */
61 #if EFSYS_OPT_MEDFORD2
62 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD2_PIOBUF_NBUFS)
63 # error "EF10_MAX_PIOBUF_NBUFS too small"
65 #endif /* EFSYS_OPT_MEDFORD2 */
70 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
71 * possibly be increased, or the write size reported by newer firmware used
74 #define EF10_NVRAM_CHUNK 0x80
77 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned
78 * to an 8 descriptor boundary.
80 #define EF10_RX_WPTR_ALIGN 8
83 * Max byte offset into the packet the TCP header must start for the hardware
84 * to be able to parse the packet correctly.
86 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
88 /* Invalid RSS context handle */
89 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
94 __checkReturn efx_rc_t
100 __in efx_nic_t *enp);
102 __checkReturn efx_rc_t
105 __in unsigned int index,
106 __in efsys_mem_t *esmp,
111 __in efx_evq_t *eep);
115 __in efx_evq_t *eep);
117 __checkReturn efx_rc_t
120 __in unsigned int count);
127 __checkReturn efx_rc_t
130 __in unsigned int us);
134 ef10_ev_qstats_update(
136 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
137 #endif /* EFSYS_OPT_QSTATS */
140 ef10_ev_rxlabel_init(
143 __in unsigned int label,
144 __in efx_rxq_type_t type);
147 ef10_ev_rxlabel_fini(
149 __in unsigned int label);
153 __checkReturn efx_rc_t
156 __in efx_intr_type_t type,
157 __in efsys_mem_t *esmp);
161 __in efx_nic_t *enp);
165 __in efx_nic_t *enp);
168 ef10_intr_disable_unlocked(
169 __in efx_nic_t *enp);
171 __checkReturn efx_rc_t
174 __in unsigned int level);
177 ef10_intr_status_line(
179 __out boolean_t *fatalp,
180 __out uint32_t *qmaskp);
183 ef10_intr_status_message(
185 __in unsigned int message,
186 __out boolean_t *fatalp);
190 __in efx_nic_t *enp);
193 __in efx_nic_t *enp);
197 extern __checkReturn efx_rc_t
199 __in efx_nic_t *enp);
201 extern __checkReturn efx_rc_t
202 ef10_nic_set_drv_limits(
203 __inout efx_nic_t *enp,
204 __in efx_drv_limits_t *edlp);
206 extern __checkReturn efx_rc_t
207 ef10_nic_get_vi_pool(
209 __out uint32_t *vi_countp);
211 extern __checkReturn efx_rc_t
212 ef10_nic_get_bar_region(
214 __in efx_nic_region_t region,
215 __out uint32_t *offsetp,
216 __out size_t *sizep);
218 extern __checkReturn efx_rc_t
220 __in efx_nic_t *enp);
222 extern __checkReturn efx_rc_t
224 __in efx_nic_t *enp);
226 extern __checkReturn boolean_t
227 ef10_nic_hw_unavailable(
228 __in efx_nic_t *enp);
231 ef10_nic_set_hw_unavailable(
232 __in efx_nic_t *enp);
236 extern __checkReturn efx_rc_t
237 ef10_nic_register_test(
238 __in efx_nic_t *enp);
240 #endif /* EFSYS_OPT_DIAG */
244 __in efx_nic_t *enp);
248 __in efx_nic_t *enp);
253 extern __checkReturn efx_rc_t
256 __out efx_link_mode_t *link_modep);
258 extern __checkReturn efx_rc_t
261 __out boolean_t *mac_upp);
263 extern __checkReturn efx_rc_t
265 __in efx_nic_t *enp);
267 extern __checkReturn efx_rc_t
269 __in efx_nic_t *enp);
271 extern __checkReturn efx_rc_t
276 extern __checkReturn efx_rc_t
277 ef10_mac_reconfigure(
278 __in efx_nic_t *enp);
280 extern __checkReturn efx_rc_t
281 ef10_mac_multicast_list_set(
282 __in efx_nic_t *enp);
284 extern __checkReturn efx_rc_t
285 ef10_mac_filter_default_rxq_set(
288 __in boolean_t using_rss);
291 ef10_mac_filter_default_rxq_clear(
292 __in efx_nic_t *enp);
294 #if EFSYS_OPT_LOOPBACK
296 extern __checkReturn efx_rc_t
297 ef10_mac_loopback_set(
299 __in efx_link_mode_t link_mode,
300 __in efx_loopback_type_t loopback_type);
302 #endif /* EFSYS_OPT_LOOPBACK */
304 #if EFSYS_OPT_MAC_STATS
306 extern __checkReturn efx_rc_t
307 ef10_mac_stats_get_mask(
309 __inout_bcount(mask_size) uint32_t *maskp,
310 __in size_t mask_size);
312 extern __checkReturn efx_rc_t
313 ef10_mac_stats_update(
315 __in efsys_mem_t *esmp,
316 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
317 __inout_opt uint32_t *generationp);
319 #endif /* EFSYS_OPT_MAC_STATS */
326 extern __checkReturn efx_rc_t
329 __in const efx_mcdi_transport_t *mtp);
333 __in efx_nic_t *enp);
336 ef10_mcdi_send_request(
338 __in_bcount(hdr_len) void *hdrp,
340 __in_bcount(sdu_len) void *sdup,
341 __in size_t sdu_len);
343 extern __checkReturn boolean_t
344 ef10_mcdi_poll_response(
345 __in efx_nic_t *enp);
348 ef10_mcdi_read_response(
350 __out_bcount(length) void *bufferp,
355 ef10_mcdi_poll_reboot(
356 __in efx_nic_t *enp);
358 extern __checkReturn efx_rc_t
359 ef10_mcdi_feature_supported(
361 __in efx_mcdi_feature_id_t id,
362 __out boolean_t *supportedp);
365 ef10_mcdi_get_timeout(
367 __in efx_mcdi_req_t *emrp,
368 __out uint32_t *timeoutp);
370 #endif /* EFSYS_OPT_MCDI */
374 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
376 extern __checkReturn efx_rc_t
377 ef10_nvram_buf_read_tlv(
379 __in_bcount(max_seg_size) caddr_t seg_data,
380 __in size_t max_seg_size,
382 __deref_out_bcount_opt(*sizep) caddr_t *datap,
383 __out size_t *sizep);
385 extern __checkReturn efx_rc_t
386 ef10_nvram_buf_write_tlv(
387 __inout_bcount(partn_size) caddr_t partn_data,
388 __in size_t partn_size,
390 __in_bcount(tag_size) caddr_t tag_data,
391 __in size_t tag_size,
392 __out size_t *total_lengthp);
394 extern __checkReturn efx_rc_t
395 ef10_nvram_partn_read_tlv(
399 __deref_out_bcount_opt(*sizep) caddr_t *datap,
400 __out size_t *sizep);
402 extern __checkReturn efx_rc_t
403 ef10_nvram_partn_write_tlv(
407 __in_bcount(size) caddr_t data,
410 extern __checkReturn efx_rc_t
411 ef10_nvram_partn_write_segment_tlv(
415 __in_bcount(size) caddr_t data,
417 __in boolean_t all_segments);
419 extern __checkReturn efx_rc_t
420 ef10_nvram_partn_lock(
422 __in uint32_t partn);
424 extern __checkReturn efx_rc_t
425 ef10_nvram_partn_unlock(
428 __out_opt uint32_t *resultp);
430 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
436 extern __checkReturn efx_rc_t
438 __in efx_nic_t *enp);
440 #endif /* EFSYS_OPT_DIAG */
442 extern __checkReturn efx_rc_t
443 ef10_nvram_type_to_partn(
445 __in efx_nvram_type_t type,
446 __out uint32_t *partnp);
448 extern __checkReturn efx_rc_t
449 ef10_nvram_partn_size(
452 __out size_t *sizep);
454 extern __checkReturn efx_rc_t
455 ef10_nvram_partn_info(
458 __out efx_nvram_info_t * enip);
460 extern __checkReturn efx_rc_t
461 ef10_nvram_partn_rw_start(
464 __out size_t *chunk_sizep);
466 extern __checkReturn efx_rc_t
467 ef10_nvram_partn_read_mode(
470 __in unsigned int offset,
471 __out_bcount(size) caddr_t data,
475 extern __checkReturn efx_rc_t
476 ef10_nvram_partn_read(
479 __in unsigned int offset,
480 __out_bcount(size) caddr_t data,
483 extern __checkReturn efx_rc_t
484 ef10_nvram_partn_read_backup(
487 __in unsigned int offset,
488 __out_bcount(size) caddr_t data,
491 extern __checkReturn efx_rc_t
492 ef10_nvram_partn_erase(
495 __in unsigned int offset,
498 extern __checkReturn efx_rc_t
499 ef10_nvram_partn_write(
502 __in unsigned int offset,
503 __in_bcount(size) caddr_t data,
506 extern __checkReturn efx_rc_t
507 ef10_nvram_partn_rw_finish(
510 __out_opt uint32_t *verify_resultp);
512 extern __checkReturn efx_rc_t
513 ef10_nvram_partn_get_version(
516 __out uint32_t *subtypep,
517 __out_ecount(4) uint16_t version[4]);
519 extern __checkReturn efx_rc_t
520 ef10_nvram_partn_set_version(
523 __in_ecount(4) uint16_t version[4]);
525 extern __checkReturn efx_rc_t
526 ef10_nvram_buffer_validate(
528 __in_bcount(buffer_size)
530 __in size_t buffer_size);
533 ef10_nvram_buffer_init(
534 __out_bcount(buffer_size)
536 __in size_t buffer_size);
538 extern __checkReturn efx_rc_t
539 ef10_nvram_buffer_create(
540 __in uint32_t partn_type,
541 __out_bcount(buffer_size)
543 __in size_t buffer_size);
545 extern __checkReturn efx_rc_t
546 ef10_nvram_buffer_find_item_start(
547 __in_bcount(buffer_size)
549 __in size_t buffer_size,
550 __out uint32_t *startp);
552 extern __checkReturn efx_rc_t
553 ef10_nvram_buffer_find_end(
554 __in_bcount(buffer_size)
556 __in size_t buffer_size,
557 __in uint32_t offset,
558 __out uint32_t *endp);
560 extern __checkReturn __success(return != B_FALSE) boolean_t
561 ef10_nvram_buffer_find_item(
562 __in_bcount(buffer_size)
564 __in size_t buffer_size,
565 __in uint32_t offset,
566 __out uint32_t *startp,
567 __out uint32_t *lengthp);
569 extern __checkReturn efx_rc_t
570 ef10_nvram_buffer_peek_item(
571 __in_bcount(buffer_size)
573 __in size_t buffer_size,
574 __in uint32_t offset,
575 __out uint32_t *tagp,
576 __out uint32_t *lengthp,
577 __out uint32_t *value_offsetp);
579 extern __checkReturn efx_rc_t
580 ef10_nvram_buffer_get_item(
581 __in_bcount(buffer_size)
583 __in size_t buffer_size,
584 __in uint32_t offset,
585 __in uint32_t length,
586 __out uint32_t *tagp,
587 __out_bcount_part(value_max_size, *lengthp)
589 __in size_t value_max_size,
590 __out uint32_t *lengthp);
592 extern __checkReturn efx_rc_t
593 ef10_nvram_buffer_insert_item(
594 __in_bcount(buffer_size)
596 __in size_t buffer_size,
597 __in uint32_t offset,
599 __in_bcount(length) caddr_t valuep,
600 __in uint32_t length,
601 __out uint32_t *lengthp);
603 extern __checkReturn efx_rc_t
604 ef10_nvram_buffer_modify_item(
605 __in_bcount(buffer_size)
607 __in size_t buffer_size,
608 __in uint32_t offset,
610 __in_bcount(length) caddr_t valuep,
611 __in uint32_t length,
612 __out uint32_t *lengthp);
614 extern __checkReturn efx_rc_t
615 ef10_nvram_buffer_delete_item(
616 __in_bcount(buffer_size)
618 __in size_t buffer_size,
619 __in uint32_t offset,
620 __in uint32_t length,
623 extern __checkReturn efx_rc_t
624 ef10_nvram_buffer_finish(
625 __in_bcount(buffer_size)
627 __in size_t buffer_size);
629 #endif /* EFSYS_OPT_NVRAM */
634 typedef struct ef10_link_state_s {
635 efx_phy_link_state_t epls;
636 #if EFSYS_OPT_LOOPBACK
637 efx_loopback_type_t els_loopback;
639 boolean_t els_mac_up;
645 __in efx_qword_t *eqp,
646 __out efx_link_mode_t *link_modep);
648 extern __checkReturn efx_rc_t
651 __out ef10_link_state_t *elsp);
653 extern __checkReturn efx_rc_t
658 extern __checkReturn efx_rc_t
659 ef10_phy_reconfigure(
660 __in efx_nic_t *enp);
662 extern __checkReturn efx_rc_t
664 __in efx_nic_t *enp);
666 extern __checkReturn efx_rc_t
669 __out uint32_t *ouip);
671 extern __checkReturn efx_rc_t
672 ef10_phy_link_state_get(
674 __out efx_phy_link_state_t *eplsp);
676 #if EFSYS_OPT_PHY_STATS
678 extern __checkReturn efx_rc_t
679 ef10_phy_stats_update(
681 __in efsys_mem_t *esmp,
682 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
684 #endif /* EFSYS_OPT_PHY_STATS */
688 extern __checkReturn efx_rc_t
689 ef10_bist_enable_offline(
690 __in efx_nic_t *enp);
692 extern __checkReturn efx_rc_t
695 __in efx_bist_type_t type);
697 extern __checkReturn efx_rc_t
700 __in efx_bist_type_t type,
701 __out efx_bist_result_t *resultp,
702 __out_opt __drv_when(count > 0, __notnull)
703 uint32_t *value_maskp,
704 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
705 unsigned long *valuesp,
711 __in efx_bist_type_t type);
713 #endif /* EFSYS_OPT_BIST */
717 extern __checkReturn efx_rc_t
719 __in efx_nic_t *enp);
723 __in efx_nic_t *enp);
725 extern __checkReturn efx_rc_t
728 __in unsigned int index,
729 __in unsigned int label,
730 __in efsys_mem_t *esmp,
736 __out unsigned int *addedp);
740 __in efx_txq_t *etp);
742 extern __checkReturn efx_rc_t
745 __in_ecount(ndescs) efx_buffer_t *ebp,
746 __in unsigned int ndescs,
747 __in unsigned int completed,
748 __inout unsigned int *addedp);
753 __in unsigned int added,
754 __in unsigned int pushed);
756 #if EFSYS_OPT_RX_PACKED_STREAM
758 ef10_rx_qpush_ps_credits(
759 __in efx_rxq_t *erp);
761 extern __checkReturn uint8_t *
762 ef10_rx_qps_packet_info(
764 __in uint8_t *buffer,
765 __in uint32_t buffer_length,
766 __in uint32_t current_offset,
767 __out uint16_t *lengthp,
768 __out uint32_t *next_offsetp,
769 __out uint32_t *timestamp);
772 extern __checkReturn efx_rc_t
775 __in unsigned int ns);
777 extern __checkReturn efx_rc_t
779 __in efx_txq_t *etp);
783 __in efx_txq_t *etp);
785 extern __checkReturn efx_rc_t
787 __in efx_txq_t *etp);
790 ef10_tx_qpio_disable(
791 __in efx_txq_t *etp);
793 extern __checkReturn efx_rc_t
796 __in_ecount(buf_length) uint8_t *buffer,
797 __in size_t buf_length,
798 __in size_t pio_buf_offset);
800 extern __checkReturn efx_rc_t
803 __in size_t pkt_length,
804 __in unsigned int completed,
805 __inout unsigned int *addedp);
807 extern __checkReturn efx_rc_t
810 __in_ecount(n) efx_desc_t *ed,
812 __in unsigned int completed,
813 __inout unsigned int *addedp);
816 ef10_tx_qdesc_dma_create(
818 __in efsys_dma_addr_t addr,
821 __out efx_desc_t *edp);
824 ef10_tx_qdesc_tso_create(
826 __in uint16_t ipv4_id,
827 __in uint32_t tcp_seq,
828 __in uint8_t tcp_flags,
829 __out efx_desc_t *edp);
832 ef10_tx_qdesc_tso2_create(
834 __in uint16_t ipv4_id,
835 __in uint16_t outer_ipv4_id,
836 __in uint32_t tcp_seq,
837 __in uint16_t tcp_mss,
838 __out_ecount(count) efx_desc_t *edp,
842 ef10_tx_qdesc_vlantci_create(
844 __in uint16_t vlan_tci,
845 __out efx_desc_t *edp);
848 ef10_tx_qdesc_checksum_create(
851 __out efx_desc_t *edp);
856 ef10_tx_qstats_update(
858 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
860 #endif /* EFSYS_OPT_QSTATS */
862 typedef uint32_t efx_piobuf_handle_t;
864 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1)
866 extern __checkReturn efx_rc_t
868 __inout efx_nic_t *enp,
869 __out uint32_t *bufnump,
870 __out efx_piobuf_handle_t *handlep,
871 __out uint32_t *blknump,
872 __out uint32_t *offsetp,
873 __out size_t *sizep);
875 extern __checkReturn efx_rc_t
877 __inout efx_nic_t *enp,
878 __in uint32_t bufnum,
879 __in uint32_t blknum);
881 extern __checkReturn efx_rc_t
883 __inout efx_nic_t *enp,
884 __in uint32_t vi_index,
885 __in efx_piobuf_handle_t handle);
887 extern __checkReturn efx_rc_t
889 __inout efx_nic_t *enp,
890 __in uint32_t vi_index);
897 extern __checkReturn efx_rc_t
899 __in efx_nic_t *enp);
901 extern __checkReturn efx_rc_t
904 __out size_t *sizep);
906 extern __checkReturn efx_rc_t
909 __out_bcount(size) caddr_t data,
912 extern __checkReturn efx_rc_t
915 __in_bcount(size) caddr_t data,
918 extern __checkReturn efx_rc_t
921 __in_bcount(size) caddr_t data,
924 extern __checkReturn efx_rc_t
927 __in_bcount(size) caddr_t data,
929 __inout efx_vpd_value_t *evvp);
931 extern __checkReturn efx_rc_t
934 __in_bcount(size) caddr_t data,
936 __in efx_vpd_value_t *evvp);
938 extern __checkReturn efx_rc_t
941 __in_bcount(size) caddr_t data,
943 __out efx_vpd_value_t *evvp,
944 __inout unsigned int *contp);
946 extern __checkReturn efx_rc_t
949 __in_bcount(size) caddr_t data,
954 __in efx_nic_t *enp);
956 #endif /* EFSYS_OPT_VPD */
961 extern __checkReturn efx_rc_t
963 __in efx_nic_t *enp);
965 #if EFSYS_OPT_RX_SCATTER
966 extern __checkReturn efx_rc_t
967 ef10_rx_scatter_enable(
969 __in unsigned int buf_size);
970 #endif /* EFSYS_OPT_RX_SCATTER */
973 #if EFSYS_OPT_RX_SCALE
975 extern __checkReturn efx_rc_t
976 ef10_rx_scale_context_alloc(
978 __in efx_rx_scale_context_type_t type,
979 __in uint32_t num_queues,
980 __out uint32_t *rss_contextp);
982 extern __checkReturn efx_rc_t
983 ef10_rx_scale_context_free(
985 __in uint32_t rss_context);
987 extern __checkReturn efx_rc_t
988 ef10_rx_scale_mode_set(
990 __in uint32_t rss_context,
991 __in efx_rx_hash_alg_t alg,
992 __in efx_rx_hash_type_t type,
993 __in boolean_t insert);
995 extern __checkReturn efx_rc_t
996 ef10_rx_scale_key_set(
998 __in uint32_t rss_context,
999 __in_ecount(n) uint8_t *key,
1002 extern __checkReturn efx_rc_t
1003 ef10_rx_scale_tbl_set(
1004 __in efx_nic_t *enp,
1005 __in uint32_t rss_context,
1006 __in_ecount(n) unsigned int *table,
1009 extern __checkReturn uint32_t
1010 ef10_rx_prefix_hash(
1011 __in efx_nic_t *enp,
1012 __in efx_rx_hash_alg_t func,
1013 __in uint8_t *buffer);
1015 #endif /* EFSYS_OPT_RX_SCALE */
1017 extern __checkReturn efx_rc_t
1018 ef10_rx_prefix_pktlen(
1019 __in efx_nic_t *enp,
1020 __in uint8_t *buffer,
1021 __out uint16_t *lengthp);
1025 __in efx_rxq_t *erp,
1026 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1028 __in unsigned int ndescs,
1029 __in unsigned int completed,
1030 __in unsigned int added);
1034 __in efx_rxq_t *erp,
1035 __in unsigned int added,
1036 __inout unsigned int *pushedp);
1038 extern __checkReturn efx_rc_t
1040 __in efx_rxq_t *erp);
1044 __in efx_rxq_t *erp);
1046 union efx_rxq_type_data_u;
1048 extern __checkReturn efx_rc_t
1050 __in efx_nic_t *enp,
1051 __in unsigned int index,
1052 __in unsigned int label,
1053 __in efx_rxq_type_t type,
1054 __in_opt const union efx_rxq_type_data_u *type_data,
1055 __in efsys_mem_t *esmp,
1058 __in unsigned int flags,
1059 __in efx_evq_t *eep,
1060 __in efx_rxq_t *erp);
1064 __in efx_rxq_t *erp);
1068 __in efx_nic_t *enp);
1070 #if EFSYS_OPT_FILTER
1072 typedef struct ef10_filter_handle_s {
1075 } ef10_filter_handle_t;
1077 typedef struct ef10_filter_entry_s {
1078 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1079 ef10_filter_handle_t efe_handle;
1080 } ef10_filter_entry_t;
1083 * BUSY flag indicates that an update is in progress.
1084 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1086 #define EFX_EF10_FILTER_FLAG_BUSY 1U
1087 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
1088 #define EFX_EF10_FILTER_FLAGS 3U
1091 * Size of the hash table used by the driver. Doesn't need to be the
1092 * same size as the hardware's table.
1094 #define EFX_EF10_FILTER_TBL_ROWS 8192
1096 /* Only need to allow for one directed and one unknown unicast filter */
1097 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
1099 /* Allow for the broadcast address to be added to the multicast list */
1100 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
1103 * For encapsulated packets, there is one filter each for each combination of
1104 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1105 * multicast inner frames.
1107 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
1109 typedef struct ef10_filter_table_s {
1110 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1111 efx_rxq_t *eft_default_rxq;
1112 boolean_t eft_using_rss;
1113 uint32_t eft_unicst_filter_indexes[
1114 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1115 uint32_t eft_unicst_filter_count;
1116 uint32_t eft_mulcst_filter_indexes[
1117 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1118 uint32_t eft_mulcst_filter_count;
1119 boolean_t eft_using_all_mulcst;
1120 uint32_t eft_encap_filter_indexes[
1121 EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1122 uint32_t eft_encap_filter_count;
1123 } ef10_filter_table_t;
1125 __checkReturn efx_rc_t
1127 __in efx_nic_t *enp);
1131 __in efx_nic_t *enp);
1133 __checkReturn efx_rc_t
1134 ef10_filter_restore(
1135 __in efx_nic_t *enp);
1137 __checkReturn efx_rc_t
1139 __in efx_nic_t *enp,
1140 __inout efx_filter_spec_t *spec,
1141 __in boolean_t may_replace);
1143 __checkReturn efx_rc_t
1145 __in efx_nic_t *enp,
1146 __inout efx_filter_spec_t *spec);
1148 extern __checkReturn efx_rc_t
1149 ef10_filter_supported_filters(
1150 __in efx_nic_t *enp,
1151 __out_ecount(buffer_length) uint32_t *buffer,
1152 __in size_t buffer_length,
1153 __out size_t *list_lengthp);
1155 extern __checkReturn efx_rc_t
1156 ef10_filter_reconfigure(
1157 __in efx_nic_t *enp,
1158 __in_ecount(6) uint8_t const *mac_addr,
1159 __in boolean_t all_unicst,
1160 __in boolean_t mulcst,
1161 __in boolean_t all_mulcst,
1162 __in boolean_t brdcst,
1163 __in_ecount(6*count) uint8_t const *addrs,
1164 __in uint32_t count);
1167 ef10_filter_get_default_rxq(
1168 __in efx_nic_t *enp,
1169 __out efx_rxq_t **erpp,
1170 __out boolean_t *using_rss);
1173 ef10_filter_default_rxq_set(
1174 __in efx_nic_t *enp,
1175 __in efx_rxq_t *erp,
1176 __in boolean_t using_rss);
1179 ef10_filter_default_rxq_clear(
1180 __in efx_nic_t *enp);
1183 #endif /* EFSYS_OPT_FILTER */
1185 extern __checkReturn efx_rc_t
1186 efx_mcdi_get_function_info(
1187 __in efx_nic_t *enp,
1188 __out uint32_t *pfp,
1189 __out_opt uint32_t *vfp);
1191 extern __checkReturn efx_rc_t
1192 efx_mcdi_privilege_mask(
1193 __in efx_nic_t *enp,
1196 __out uint32_t *maskp);
1198 extern __checkReturn efx_rc_t
1199 efx_mcdi_get_port_assignment(
1200 __in efx_nic_t *enp,
1201 __out uint32_t *portp);
1203 extern __checkReturn efx_rc_t
1204 efx_mcdi_get_port_modes(
1205 __in efx_nic_t *enp,
1206 __out uint32_t *modesp,
1207 __out_opt uint32_t *current_modep,
1208 __out_opt uint32_t *default_modep);
1210 extern __checkReturn efx_rc_t
1211 ef10_nic_get_port_mode_bandwidth(
1212 __in efx_nic_t *enp,
1213 __out uint32_t *bandwidth_mbpsp);
1215 extern __checkReturn efx_rc_t
1216 efx_mcdi_get_mac_address_pf(
1217 __in efx_nic_t *enp,
1218 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1220 extern __checkReturn efx_rc_t
1221 efx_mcdi_get_mac_address_vf(
1222 __in efx_nic_t *enp,
1223 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1225 extern __checkReturn efx_rc_t
1227 __in efx_nic_t *enp,
1228 __out uint32_t *sys_freqp,
1229 __out uint32_t *dpcpu_freqp);
1232 extern __checkReturn efx_rc_t
1233 efx_mcdi_get_rxdp_config(
1234 __in efx_nic_t *enp,
1235 __out uint32_t *end_paddingp);
1237 extern __checkReturn efx_rc_t
1238 efx_mcdi_get_vector_cfg(
1239 __in efx_nic_t *enp,
1240 __out_opt uint32_t *vec_basep,
1241 __out_opt uint32_t *pf_nvecp,
1242 __out_opt uint32_t *vf_nvecp);
1244 extern __checkReturn efx_rc_t
1245 ef10_get_privilege_mask(
1246 __in efx_nic_t *enp,
1247 __out uint32_t *maskp);
1249 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1251 extern __checkReturn efx_rc_t
1252 efx_mcdi_get_nic_global(
1253 __in efx_nic_t *enp,
1255 __out uint32_t *valuep);
1257 extern __checkReturn efx_rc_t
1258 efx_mcdi_set_nic_global(
1259 __in efx_nic_t *enp,
1261 __in uint32_t value);
1263 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1266 #if EFSYS_OPT_RX_PACKED_STREAM
1268 /* Data space per credit in packed stream mode */
1269 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1272 * Received packets are always aligned at this boundary. Also there always
1273 * exists a gap of this size between packets.
1274 * (see SF-112241-TC, 4.5)
1276 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64
1279 * Size of a pseudo-header prepended to received packets
1280 * in packed stream mode
1282 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1284 /* Minimum space for packet in packed stream mode */
1285 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
1286 P2ROUNDUP(EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
1288 EFX_RX_PACKED_STREAM_ALIGNMENT, \
1289 EFX_RX_PACKED_STREAM_ALIGNMENT)
1291 /* Maximum number of credits */
1292 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1294 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1296 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1299 * Maximum DMA length and buffer stride alignment.
1300 * (see SF-119419-TC, 3.2)
1302 #define EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT 64
1310 #endif /* _SYS_EF10_IMPL_H */