1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
7 #ifndef _SYS_EF10_IMPL_H
8 #define _SYS_EF10_IMPL_H
14 #define EF10_EVQ_MAXNEVS 32768
15 #define EF10_EVQ_MINNEVS 512
17 #define EF10_RXQ_MAXNDESCS 4096
18 #define EF10_RXQ_MINNDESCS 512
20 #define EF10_TXQ_MINNDESCS 512
22 #define EF10_RXQ_DESC_SIZE (sizeof (efx_qword_t))
23 #define EF10_TXQ_DESC_SIZE (sizeof (efx_qword_t))
25 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
26 #define EF10_TXQ_MAXNBUFS 8
28 /* Number of hardware PIO buffers (for compile-time resource dimensions) */
29 #define EF10_MAX_PIOBUF_NBUFS (16)
31 #if EFSYS_OPT_HUNTINGTON
32 # if (EF10_MAX_PIOBUF_NBUFS < HUNT_PIOBUF_NBUFS)
33 # error "EF10_MAX_PIOBUF_NBUFS too small"
35 #endif /* EFSYS_OPT_HUNTINGTON */
37 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD_PIOBUF_NBUFS)
38 # error "EF10_MAX_PIOBUF_NBUFS too small"
40 #endif /* EFSYS_OPT_MEDFORD */
41 #if EFSYS_OPT_MEDFORD2
42 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD2_PIOBUF_NBUFS)
43 # error "EF10_MAX_PIOBUF_NBUFS too small"
45 #endif /* EFSYS_OPT_MEDFORD2 */
50 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
51 * possibly be increased, or the write size reported by newer firmware used
54 #define EF10_NVRAM_CHUNK 0x80
57 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned
58 * to an 8 descriptor boundary.
60 #define EF10_RX_WPTR_ALIGN 8
63 * Max byte offset into the packet the TCP header must start for the hardware
64 * to be able to parse the packet correctly.
66 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
68 /* Invalid RSS context handle */
69 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
74 __checkReturn efx_rc_t
82 __checkReturn efx_rc_t
85 __in unsigned int index,
86 __in efsys_mem_t *esmp,
97 __checkReturn efx_rc_t
100 __in unsigned int count);
107 __checkReturn efx_rc_t
110 __in unsigned int us);
114 ef10_ev_qstats_update(
116 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
117 #endif /* EFSYS_OPT_QSTATS */
120 ef10_ev_rxlabel_init(
123 __in unsigned int label,
124 __in efx_rxq_type_t type);
127 ef10_ev_rxlabel_fini(
129 __in unsigned int label);
133 __checkReturn efx_rc_t
136 __in efx_intr_type_t type,
137 __in efsys_mem_t *esmp);
141 __in efx_nic_t *enp);
145 __in efx_nic_t *enp);
148 ef10_intr_disable_unlocked(
149 __in efx_nic_t *enp);
151 __checkReturn efx_rc_t
154 __in unsigned int level);
157 ef10_intr_status_line(
159 __out boolean_t *fatalp,
160 __out uint32_t *qmaskp);
163 ef10_intr_status_message(
165 __in unsigned int message,
166 __out boolean_t *fatalp);
170 __in efx_nic_t *enp);
173 __in efx_nic_t *enp);
177 extern __checkReturn efx_rc_t
179 __in efx_nic_t *enp);
181 extern __checkReturn efx_rc_t
182 ef10_nic_set_drv_limits(
183 __inout efx_nic_t *enp,
184 __in efx_drv_limits_t *edlp);
186 extern __checkReturn efx_rc_t
187 ef10_nic_get_vi_pool(
189 __out uint32_t *vi_countp);
191 extern __checkReturn efx_rc_t
192 ef10_nic_get_bar_region(
194 __in efx_nic_region_t region,
195 __out uint32_t *offsetp,
196 __out size_t *sizep);
198 extern __checkReturn efx_rc_t
200 __in efx_nic_t *enp);
202 extern __checkReturn efx_rc_t
204 __in efx_nic_t *enp);
206 extern __checkReturn boolean_t
207 ef10_nic_hw_unavailable(
208 __in efx_nic_t *enp);
211 ef10_nic_set_hw_unavailable(
212 __in efx_nic_t *enp);
216 extern __checkReturn efx_rc_t
217 ef10_nic_register_test(
218 __in efx_nic_t *enp);
220 #endif /* EFSYS_OPT_DIAG */
224 __in efx_nic_t *enp);
228 __in efx_nic_t *enp);
233 extern __checkReturn efx_rc_t
236 __out efx_link_mode_t *link_modep);
238 extern __checkReturn efx_rc_t
241 __out boolean_t *mac_upp);
243 extern __checkReturn efx_rc_t
245 __in efx_nic_t *enp);
247 extern __checkReturn efx_rc_t
249 __in efx_nic_t *enp);
251 extern __checkReturn efx_rc_t
256 extern __checkReturn efx_rc_t
257 ef10_mac_reconfigure(
258 __in efx_nic_t *enp);
260 extern __checkReturn efx_rc_t
261 ef10_mac_multicast_list_set(
262 __in efx_nic_t *enp);
264 extern __checkReturn efx_rc_t
265 ef10_mac_filter_default_rxq_set(
268 __in boolean_t using_rss);
271 ef10_mac_filter_default_rxq_clear(
272 __in efx_nic_t *enp);
274 #if EFSYS_OPT_LOOPBACK
276 extern __checkReturn efx_rc_t
277 ef10_mac_loopback_set(
279 __in efx_link_mode_t link_mode,
280 __in efx_loopback_type_t loopback_type);
282 #endif /* EFSYS_OPT_LOOPBACK */
284 #if EFSYS_OPT_MAC_STATS
286 extern __checkReturn efx_rc_t
287 ef10_mac_stats_get_mask(
289 __inout_bcount(mask_size) uint32_t *maskp,
290 __in size_t mask_size);
292 extern __checkReturn efx_rc_t
293 ef10_mac_stats_update(
295 __in efsys_mem_t *esmp,
296 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
297 __inout_opt uint32_t *generationp);
299 #endif /* EFSYS_OPT_MAC_STATS */
306 extern __checkReturn efx_rc_t
309 __in const efx_mcdi_transport_t *mtp);
313 __in efx_nic_t *enp);
316 ef10_mcdi_send_request(
318 __in_bcount(hdr_len) void *hdrp,
320 __in_bcount(sdu_len) void *sdup,
321 __in size_t sdu_len);
323 extern __checkReturn boolean_t
324 ef10_mcdi_poll_response(
325 __in efx_nic_t *enp);
328 ef10_mcdi_read_response(
330 __out_bcount(length) void *bufferp,
335 ef10_mcdi_poll_reboot(
336 __in efx_nic_t *enp);
338 extern __checkReturn efx_rc_t
339 ef10_mcdi_feature_supported(
341 __in efx_mcdi_feature_id_t id,
342 __out boolean_t *supportedp);
345 ef10_mcdi_get_timeout(
347 __in efx_mcdi_req_t *emrp,
348 __out uint32_t *timeoutp);
350 #endif /* EFSYS_OPT_MCDI */
354 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
356 extern __checkReturn efx_rc_t
357 ef10_nvram_buf_read_tlv(
359 __in_bcount(max_seg_size) caddr_t seg_data,
360 __in size_t max_seg_size,
362 __deref_out_bcount_opt(*sizep) caddr_t *datap,
363 __out size_t *sizep);
365 extern __checkReturn efx_rc_t
366 ef10_nvram_buf_write_tlv(
367 __inout_bcount(partn_size) caddr_t partn_data,
368 __in size_t partn_size,
370 __in_bcount(tag_size) caddr_t tag_data,
371 __in size_t tag_size,
372 __out size_t *total_lengthp);
374 extern __checkReturn efx_rc_t
375 ef10_nvram_partn_read_tlv(
379 __deref_out_bcount_opt(*sizep) caddr_t *datap,
380 __out size_t *sizep);
382 extern __checkReturn efx_rc_t
383 ef10_nvram_partn_write_tlv(
387 __in_bcount(size) caddr_t data,
390 extern __checkReturn efx_rc_t
391 ef10_nvram_partn_write_segment_tlv(
395 __in_bcount(size) caddr_t data,
397 __in boolean_t all_segments);
399 extern __checkReturn efx_rc_t
400 ef10_nvram_partn_lock(
402 __in uint32_t partn);
404 extern __checkReturn efx_rc_t
405 ef10_nvram_partn_unlock(
408 __out_opt uint32_t *resultp);
410 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
416 extern __checkReturn efx_rc_t
418 __in efx_nic_t *enp);
420 #endif /* EFSYS_OPT_DIAG */
422 extern __checkReturn efx_rc_t
423 ef10_nvram_type_to_partn(
425 __in efx_nvram_type_t type,
426 __out uint32_t *partnp);
428 extern __checkReturn efx_rc_t
429 ef10_nvram_partn_size(
432 __out size_t *sizep);
434 extern __checkReturn efx_rc_t
435 ef10_nvram_partn_rw_start(
438 __out size_t *chunk_sizep);
440 extern __checkReturn efx_rc_t
441 ef10_nvram_partn_read_mode(
444 __in unsigned int offset,
445 __out_bcount(size) caddr_t data,
449 extern __checkReturn efx_rc_t
450 ef10_nvram_partn_read(
453 __in unsigned int offset,
454 __out_bcount(size) caddr_t data,
457 extern __checkReturn efx_rc_t
458 ef10_nvram_partn_read_backup(
461 __in unsigned int offset,
462 __out_bcount(size) caddr_t data,
465 extern __checkReturn efx_rc_t
466 ef10_nvram_partn_erase(
469 __in unsigned int offset,
472 extern __checkReturn efx_rc_t
473 ef10_nvram_partn_write(
476 __in unsigned int offset,
477 __in_bcount(size) caddr_t data,
480 extern __checkReturn efx_rc_t
481 ef10_nvram_partn_rw_finish(
484 __out_opt uint32_t *verify_resultp);
486 extern __checkReturn efx_rc_t
487 ef10_nvram_partn_get_version(
490 __out uint32_t *subtypep,
491 __out_ecount(4) uint16_t version[4]);
493 extern __checkReturn efx_rc_t
494 ef10_nvram_partn_set_version(
497 __in_ecount(4) uint16_t version[4]);
499 extern __checkReturn efx_rc_t
500 ef10_nvram_buffer_validate(
502 __in_bcount(buffer_size)
504 __in size_t buffer_size);
507 ef10_nvram_buffer_init(
508 __out_bcount(buffer_size)
510 __in size_t buffer_size);
512 extern __checkReturn efx_rc_t
513 ef10_nvram_buffer_create(
514 __in uint32_t partn_type,
515 __out_bcount(buffer_size)
517 __in size_t buffer_size);
519 extern __checkReturn efx_rc_t
520 ef10_nvram_buffer_find_item_start(
521 __in_bcount(buffer_size)
523 __in size_t buffer_size,
524 __out uint32_t *startp);
526 extern __checkReturn efx_rc_t
527 ef10_nvram_buffer_find_end(
528 __in_bcount(buffer_size)
530 __in size_t buffer_size,
531 __in uint32_t offset,
532 __out uint32_t *endp);
534 extern __checkReturn __success(return != B_FALSE) boolean_t
535 ef10_nvram_buffer_find_item(
536 __in_bcount(buffer_size)
538 __in size_t buffer_size,
539 __in uint32_t offset,
540 __out uint32_t *startp,
541 __out uint32_t *lengthp);
543 extern __checkReturn efx_rc_t
544 ef10_nvram_buffer_peek_item(
545 __in_bcount(buffer_size)
547 __in size_t buffer_size,
548 __in uint32_t offset,
549 __out uint32_t *tagp,
550 __out uint32_t *lengthp,
551 __out uint32_t *value_offsetp);
553 extern __checkReturn efx_rc_t
554 ef10_nvram_buffer_get_item(
555 __in_bcount(buffer_size)
557 __in size_t buffer_size,
558 __in uint32_t offset,
559 __in uint32_t length,
560 __out uint32_t *tagp,
561 __out_bcount_part(value_max_size, *lengthp)
563 __in size_t value_max_size,
564 __out uint32_t *lengthp);
566 extern __checkReturn efx_rc_t
567 ef10_nvram_buffer_insert_item(
568 __in_bcount(buffer_size)
570 __in size_t buffer_size,
571 __in uint32_t offset,
573 __in_bcount(length) caddr_t valuep,
574 __in uint32_t length,
575 __out uint32_t *lengthp);
577 extern __checkReturn efx_rc_t
578 ef10_nvram_buffer_modify_item(
579 __in_bcount(buffer_size)
581 __in size_t buffer_size,
582 __in uint32_t offset,
584 __in_bcount(length) caddr_t valuep,
585 __in uint32_t length,
586 __out uint32_t *lengthp);
588 extern __checkReturn efx_rc_t
589 ef10_nvram_buffer_delete_item(
590 __in_bcount(buffer_size)
592 __in size_t buffer_size,
593 __in uint32_t offset,
594 __in uint32_t length,
597 extern __checkReturn efx_rc_t
598 ef10_nvram_buffer_finish(
599 __in_bcount(buffer_size)
601 __in size_t buffer_size);
603 #endif /* EFSYS_OPT_NVRAM */
608 typedef struct ef10_link_state_s {
609 efx_phy_link_state_t epls;
610 #if EFSYS_OPT_LOOPBACK
611 efx_loopback_type_t els_loopback;
613 boolean_t els_mac_up;
619 __in efx_qword_t *eqp,
620 __out efx_link_mode_t *link_modep);
622 extern __checkReturn efx_rc_t
625 __out ef10_link_state_t *elsp);
627 extern __checkReturn efx_rc_t
632 extern __checkReturn efx_rc_t
633 ef10_phy_reconfigure(
634 __in efx_nic_t *enp);
636 extern __checkReturn efx_rc_t
638 __in efx_nic_t *enp);
640 extern __checkReturn efx_rc_t
643 __out uint32_t *ouip);
645 extern __checkReturn efx_rc_t
646 ef10_phy_link_state_get(
648 __out efx_phy_link_state_t *eplsp);
650 #if EFSYS_OPT_PHY_STATS
652 extern __checkReturn efx_rc_t
653 ef10_phy_stats_update(
655 __in efsys_mem_t *esmp,
656 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
658 #endif /* EFSYS_OPT_PHY_STATS */
662 extern __checkReturn efx_rc_t
663 ef10_bist_enable_offline(
664 __in efx_nic_t *enp);
666 extern __checkReturn efx_rc_t
669 __in efx_bist_type_t type);
671 extern __checkReturn efx_rc_t
674 __in efx_bist_type_t type,
675 __out efx_bist_result_t *resultp,
676 __out_opt __drv_when(count > 0, __notnull)
677 uint32_t *value_maskp,
678 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
679 unsigned long *valuesp,
685 __in efx_bist_type_t type);
687 #endif /* EFSYS_OPT_BIST */
691 extern __checkReturn efx_rc_t
693 __in efx_nic_t *enp);
697 __in efx_nic_t *enp);
699 extern __checkReturn efx_rc_t
702 __in unsigned int index,
703 __in unsigned int label,
704 __in efsys_mem_t *esmp,
710 __out unsigned int *addedp);
714 __in efx_txq_t *etp);
716 extern __checkReturn efx_rc_t
719 __in_ecount(ndescs) efx_buffer_t *ebp,
720 __in unsigned int ndescs,
721 __in unsigned int completed,
722 __inout unsigned int *addedp);
727 __in unsigned int added,
728 __in unsigned int pushed);
730 #if EFSYS_OPT_RX_PACKED_STREAM
732 ef10_rx_qpush_ps_credits(
733 __in efx_rxq_t *erp);
735 extern __checkReturn uint8_t *
736 ef10_rx_qps_packet_info(
738 __in uint8_t *buffer,
739 __in uint32_t buffer_length,
740 __in uint32_t current_offset,
741 __out uint16_t *lengthp,
742 __out uint32_t *next_offsetp,
743 __out uint32_t *timestamp);
746 extern __checkReturn efx_rc_t
749 __in unsigned int ns);
751 extern __checkReturn efx_rc_t
753 __in efx_txq_t *etp);
757 __in efx_txq_t *etp);
759 extern __checkReturn efx_rc_t
761 __in efx_txq_t *etp);
764 ef10_tx_qpio_disable(
765 __in efx_txq_t *etp);
767 extern __checkReturn efx_rc_t
770 __in_ecount(buf_length) uint8_t *buffer,
771 __in size_t buf_length,
772 __in size_t pio_buf_offset);
774 extern __checkReturn efx_rc_t
777 __in size_t pkt_length,
778 __in unsigned int completed,
779 __inout unsigned int *addedp);
781 extern __checkReturn efx_rc_t
784 __in_ecount(n) efx_desc_t *ed,
786 __in unsigned int completed,
787 __inout unsigned int *addedp);
790 ef10_tx_qdesc_dma_create(
792 __in efsys_dma_addr_t addr,
795 __out efx_desc_t *edp);
798 ef10_tx_qdesc_tso_create(
800 __in uint16_t ipv4_id,
801 __in uint32_t tcp_seq,
802 __in uint8_t tcp_flags,
803 __out efx_desc_t *edp);
806 ef10_tx_qdesc_tso2_create(
808 __in uint16_t ipv4_id,
809 __in uint16_t outer_ipv4_id,
810 __in uint32_t tcp_seq,
811 __in uint16_t tcp_mss,
812 __out_ecount(count) efx_desc_t *edp,
816 ef10_tx_qdesc_vlantci_create(
818 __in uint16_t vlan_tci,
819 __out efx_desc_t *edp);
822 ef10_tx_qdesc_checksum_create(
825 __out efx_desc_t *edp);
830 ef10_tx_qstats_update(
832 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
834 #endif /* EFSYS_OPT_QSTATS */
836 typedef uint32_t efx_piobuf_handle_t;
838 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1)
840 extern __checkReturn efx_rc_t
842 __inout efx_nic_t *enp,
843 __out uint32_t *bufnump,
844 __out efx_piobuf_handle_t *handlep,
845 __out uint32_t *blknump,
846 __out uint32_t *offsetp,
847 __out size_t *sizep);
849 extern __checkReturn efx_rc_t
851 __inout efx_nic_t *enp,
852 __in uint32_t bufnum,
853 __in uint32_t blknum);
855 extern __checkReturn efx_rc_t
857 __inout efx_nic_t *enp,
858 __in uint32_t vi_index,
859 __in efx_piobuf_handle_t handle);
861 extern __checkReturn efx_rc_t
863 __inout efx_nic_t *enp,
864 __in uint32_t vi_index);
871 extern __checkReturn efx_rc_t
873 __in efx_nic_t *enp);
875 extern __checkReturn efx_rc_t
878 __out size_t *sizep);
880 extern __checkReturn efx_rc_t
883 __out_bcount(size) caddr_t data,
886 extern __checkReturn efx_rc_t
889 __in_bcount(size) caddr_t data,
892 extern __checkReturn efx_rc_t
895 __in_bcount(size) caddr_t data,
898 extern __checkReturn efx_rc_t
901 __in_bcount(size) caddr_t data,
903 __inout efx_vpd_value_t *evvp);
905 extern __checkReturn efx_rc_t
908 __in_bcount(size) caddr_t data,
910 __in efx_vpd_value_t *evvp);
912 extern __checkReturn efx_rc_t
915 __in_bcount(size) caddr_t data,
917 __out efx_vpd_value_t *evvp,
918 __inout unsigned int *contp);
920 extern __checkReturn efx_rc_t
923 __in_bcount(size) caddr_t data,
928 __in efx_nic_t *enp);
930 #endif /* EFSYS_OPT_VPD */
935 extern __checkReturn efx_rc_t
937 __in efx_nic_t *enp);
939 #if EFSYS_OPT_RX_SCATTER
940 extern __checkReturn efx_rc_t
941 ef10_rx_scatter_enable(
943 __in unsigned int buf_size);
944 #endif /* EFSYS_OPT_RX_SCATTER */
947 #if EFSYS_OPT_RX_SCALE
949 extern __checkReturn efx_rc_t
950 ef10_rx_scale_context_alloc(
952 __in efx_rx_scale_context_type_t type,
953 __in uint32_t num_queues,
954 __out uint32_t *rss_contextp);
956 extern __checkReturn efx_rc_t
957 ef10_rx_scale_context_free(
959 __in uint32_t rss_context);
961 extern __checkReturn efx_rc_t
962 ef10_rx_scale_mode_set(
964 __in uint32_t rss_context,
965 __in efx_rx_hash_alg_t alg,
966 __in efx_rx_hash_type_t type,
967 __in boolean_t insert);
969 extern __checkReturn efx_rc_t
970 ef10_rx_scale_key_set(
972 __in uint32_t rss_context,
973 __in_ecount(n) uint8_t *key,
976 extern __checkReturn efx_rc_t
977 ef10_rx_scale_tbl_set(
979 __in uint32_t rss_context,
980 __in_ecount(n) unsigned int *table,
983 extern __checkReturn uint32_t
986 __in efx_rx_hash_alg_t func,
987 __in uint8_t *buffer);
989 #endif /* EFSYS_OPT_RX_SCALE */
991 extern __checkReturn efx_rc_t
992 ef10_rx_prefix_pktlen(
994 __in uint8_t *buffer,
995 __out uint16_t *lengthp);
1000 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1002 __in unsigned int ndescs,
1003 __in unsigned int completed,
1004 __in unsigned int added);
1008 __in efx_rxq_t *erp,
1009 __in unsigned int added,
1010 __inout unsigned int *pushedp);
1012 extern __checkReturn efx_rc_t
1014 __in efx_rxq_t *erp);
1018 __in efx_rxq_t *erp);
1020 union efx_rxq_type_data_u;
1022 extern __checkReturn efx_rc_t
1024 __in efx_nic_t *enp,
1025 __in unsigned int index,
1026 __in unsigned int label,
1027 __in efx_rxq_type_t type,
1028 __in_opt const union efx_rxq_type_data_u *type_data,
1029 __in efsys_mem_t *esmp,
1032 __in unsigned int flags,
1033 __in efx_evq_t *eep,
1034 __in efx_rxq_t *erp);
1038 __in efx_rxq_t *erp);
1042 __in efx_nic_t *enp);
1044 #if EFSYS_OPT_FILTER
1046 typedef struct ef10_filter_handle_s {
1049 } ef10_filter_handle_t;
1051 typedef struct ef10_filter_entry_s {
1052 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1053 ef10_filter_handle_t efe_handle;
1054 } ef10_filter_entry_t;
1057 * BUSY flag indicates that an update is in progress.
1058 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1060 #define EFX_EF10_FILTER_FLAG_BUSY 1U
1061 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
1062 #define EFX_EF10_FILTER_FLAGS 3U
1065 * Size of the hash table used by the driver. Doesn't need to be the
1066 * same size as the hardware's table.
1068 #define EFX_EF10_FILTER_TBL_ROWS 8192
1070 /* Only need to allow for one directed and one unknown unicast filter */
1071 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
1073 /* Allow for the broadcast address to be added to the multicast list */
1074 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
1077 * For encapsulated packets, there is one filter each for each combination of
1078 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1079 * multicast inner frames.
1081 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
1083 typedef struct ef10_filter_table_s {
1084 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1085 efx_rxq_t *eft_default_rxq;
1086 boolean_t eft_using_rss;
1087 uint32_t eft_unicst_filter_indexes[
1088 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1089 uint32_t eft_unicst_filter_count;
1090 uint32_t eft_mulcst_filter_indexes[
1091 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1092 uint32_t eft_mulcst_filter_count;
1093 boolean_t eft_using_all_mulcst;
1094 uint32_t eft_encap_filter_indexes[
1095 EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1096 uint32_t eft_encap_filter_count;
1097 } ef10_filter_table_t;
1099 __checkReturn efx_rc_t
1101 __in efx_nic_t *enp);
1105 __in efx_nic_t *enp);
1107 __checkReturn efx_rc_t
1108 ef10_filter_restore(
1109 __in efx_nic_t *enp);
1111 __checkReturn efx_rc_t
1113 __in efx_nic_t *enp,
1114 __inout efx_filter_spec_t *spec,
1115 __in boolean_t may_replace);
1117 __checkReturn efx_rc_t
1119 __in efx_nic_t *enp,
1120 __inout efx_filter_spec_t *spec);
1122 extern __checkReturn efx_rc_t
1123 ef10_filter_supported_filters(
1124 __in efx_nic_t *enp,
1125 __out_ecount(buffer_length) uint32_t *buffer,
1126 __in size_t buffer_length,
1127 __out size_t *list_lengthp);
1129 extern __checkReturn efx_rc_t
1130 ef10_filter_reconfigure(
1131 __in efx_nic_t *enp,
1132 __in_ecount(6) uint8_t const *mac_addr,
1133 __in boolean_t all_unicst,
1134 __in boolean_t mulcst,
1135 __in boolean_t all_mulcst,
1136 __in boolean_t brdcst,
1137 __in_ecount(6*count) uint8_t const *addrs,
1138 __in uint32_t count);
1141 ef10_filter_get_default_rxq(
1142 __in efx_nic_t *enp,
1143 __out efx_rxq_t **erpp,
1144 __out boolean_t *using_rss);
1147 ef10_filter_default_rxq_set(
1148 __in efx_nic_t *enp,
1149 __in efx_rxq_t *erp,
1150 __in boolean_t using_rss);
1153 ef10_filter_default_rxq_clear(
1154 __in efx_nic_t *enp);
1157 #endif /* EFSYS_OPT_FILTER */
1159 extern __checkReturn efx_rc_t
1160 efx_mcdi_get_function_info(
1161 __in efx_nic_t *enp,
1162 __out uint32_t *pfp,
1163 __out_opt uint32_t *vfp);
1165 extern __checkReturn efx_rc_t
1166 efx_mcdi_privilege_mask(
1167 __in efx_nic_t *enp,
1170 __out uint32_t *maskp);
1172 extern __checkReturn efx_rc_t
1173 efx_mcdi_get_port_assignment(
1174 __in efx_nic_t *enp,
1175 __out uint32_t *portp);
1177 extern __checkReturn efx_rc_t
1178 efx_mcdi_get_port_modes(
1179 __in efx_nic_t *enp,
1180 __out uint32_t *modesp,
1181 __out_opt uint32_t *current_modep,
1182 __out_opt uint32_t *default_modep);
1184 extern __checkReturn efx_rc_t
1185 ef10_nic_get_port_mode_bandwidth(
1186 __in efx_nic_t *enp,
1187 __out uint32_t *bandwidth_mbpsp);
1189 extern __checkReturn efx_rc_t
1190 efx_mcdi_get_mac_address_pf(
1191 __in efx_nic_t *enp,
1192 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1194 extern __checkReturn efx_rc_t
1195 efx_mcdi_get_mac_address_vf(
1196 __in efx_nic_t *enp,
1197 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1199 extern __checkReturn efx_rc_t
1201 __in efx_nic_t *enp,
1202 __out uint32_t *sys_freqp,
1203 __out uint32_t *dpcpu_freqp);
1206 extern __checkReturn efx_rc_t
1207 efx_mcdi_get_rxdp_config(
1208 __in efx_nic_t *enp,
1209 __out uint32_t *end_paddingp);
1211 extern __checkReturn efx_rc_t
1212 efx_mcdi_get_vector_cfg(
1213 __in efx_nic_t *enp,
1214 __out_opt uint32_t *vec_basep,
1215 __out_opt uint32_t *pf_nvecp,
1216 __out_opt uint32_t *vf_nvecp);
1218 extern __checkReturn efx_rc_t
1219 ef10_get_privilege_mask(
1220 __in efx_nic_t *enp,
1221 __out uint32_t *maskp);
1223 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1225 extern __checkReturn efx_rc_t
1226 efx_mcdi_get_nic_global(
1227 __in efx_nic_t *enp,
1229 __out uint32_t *valuep);
1231 extern __checkReturn efx_rc_t
1232 efx_mcdi_set_nic_global(
1233 __in efx_nic_t *enp,
1235 __in uint32_t value);
1237 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1240 #if EFSYS_OPT_RX_PACKED_STREAM
1242 /* Data space per credit in packed stream mode */
1243 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1246 * Received packets are always aligned at this boundary. Also there always
1247 * exists a gap of this size between packets.
1248 * (see SF-112241-TC, 4.5)
1250 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64
1253 * Size of a pseudo-header prepended to received packets
1254 * in packed stream mode
1256 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1258 /* Minimum space for packet in packed stream mode */
1259 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
1260 P2ROUNDUP(EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
1262 EFX_RX_PACKED_STREAM_ALIGNMENT, \
1263 EFX_RX_PACKED_STREAM_ALIGNMENT)
1265 /* Maximum number of credits */
1266 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1268 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1270 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1273 * Maximum DMA length and buffer stride alignment.
1274 * (see SF-119419-TC, 3.2)
1276 #define EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT 64
1284 #endif /* _SYS_EF10_IMPL_H */