1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
7 #ifndef _SYS_EF10_IMPL_H
8 #define _SYS_EF10_IMPL_H
15 /* Number of hardware PIO buffers (for compile-time resource dimensions) */
16 #define EF10_MAX_PIOBUF_NBUFS (16)
18 #if EFSYS_OPT_HUNTINGTON
19 # if (EF10_MAX_PIOBUF_NBUFS < HUNT_PIOBUF_NBUFS)
20 # error "EF10_MAX_PIOBUF_NBUFS too small"
22 #endif /* EFSYS_OPT_HUNTINGTON */
24 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD_PIOBUF_NBUFS)
25 # error "EF10_MAX_PIOBUF_NBUFS too small"
27 #endif /* EFSYS_OPT_MEDFORD */
28 #if EFSYS_OPT_MEDFORD2
29 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD2_PIOBUF_NBUFS)
30 # error "EF10_MAX_PIOBUF_NBUFS too small"
32 #endif /* EFSYS_OPT_MEDFORD2 */
37 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
38 * possibly be increased, or the write size reported by newer firmware used
41 #define EF10_NVRAM_CHUNK 0x80
44 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned
45 * to an 8 descriptor boundary.
47 #define EF10_RX_WPTR_ALIGN 8
50 * Max byte offset into the packet the TCP header must start for the hardware
51 * to be able to parse the packet correctly.
53 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
55 /* Invalid RSS context handle */
56 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
61 __checkReturn efx_rc_t
69 __checkReturn efx_rc_t
72 __in unsigned int index,
73 __in efsys_mem_t *esmp,
84 __checkReturn efx_rc_t
87 __in unsigned int count);
94 __checkReturn efx_rc_t
97 __in unsigned int us);
101 ef10_ev_qstats_update(
103 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
104 #endif /* EFSYS_OPT_QSTATS */
107 ef10_ev_rxlabel_init(
110 __in unsigned int label,
111 __in efx_rxq_type_t type);
114 ef10_ev_rxlabel_fini(
116 __in unsigned int label);
120 __checkReturn efx_rc_t
123 __in efx_intr_type_t type,
124 __in efsys_mem_t *esmp);
128 __in efx_nic_t *enp);
132 __in efx_nic_t *enp);
135 ef10_intr_disable_unlocked(
136 __in efx_nic_t *enp);
138 __checkReturn efx_rc_t
141 __in unsigned int level);
144 ef10_intr_status_line(
146 __out boolean_t *fatalp,
147 __out uint32_t *qmaskp);
150 ef10_intr_status_message(
152 __in unsigned int message,
153 __out boolean_t *fatalp);
157 __in efx_nic_t *enp);
160 __in efx_nic_t *enp);
164 extern __checkReturn efx_rc_t
166 __in efx_nic_t *enp);
168 extern __checkReturn efx_rc_t
169 ef10_nic_set_drv_limits(
170 __inout efx_nic_t *enp,
171 __in efx_drv_limits_t *edlp);
173 extern __checkReturn efx_rc_t
174 ef10_nic_get_vi_pool(
176 __out uint32_t *vi_countp);
178 extern __checkReturn efx_rc_t
179 ef10_nic_get_bar_region(
181 __in efx_nic_region_t region,
182 __out uint32_t *offsetp,
183 __out size_t *sizep);
185 extern __checkReturn efx_rc_t
187 __in efx_nic_t *enp);
189 extern __checkReturn efx_rc_t
191 __in efx_nic_t *enp);
195 extern __checkReturn efx_rc_t
196 ef10_nic_register_test(
197 __in efx_nic_t *enp);
199 #endif /* EFSYS_OPT_DIAG */
203 __in efx_nic_t *enp);
207 __in efx_nic_t *enp);
212 extern __checkReturn efx_rc_t
215 __out efx_link_mode_t *link_modep);
217 extern __checkReturn efx_rc_t
220 __out boolean_t *mac_upp);
222 extern __checkReturn efx_rc_t
224 __in efx_nic_t *enp);
226 extern __checkReturn efx_rc_t
228 __in efx_nic_t *enp);
230 extern __checkReturn efx_rc_t
235 extern __checkReturn efx_rc_t
236 ef10_mac_reconfigure(
237 __in efx_nic_t *enp);
239 extern __checkReturn efx_rc_t
240 ef10_mac_multicast_list_set(
241 __in efx_nic_t *enp);
243 extern __checkReturn efx_rc_t
244 ef10_mac_filter_default_rxq_set(
247 __in boolean_t using_rss);
250 ef10_mac_filter_default_rxq_clear(
251 __in efx_nic_t *enp);
253 #if EFSYS_OPT_LOOPBACK
255 extern __checkReturn efx_rc_t
256 ef10_mac_loopback_set(
258 __in efx_link_mode_t link_mode,
259 __in efx_loopback_type_t loopback_type);
261 #endif /* EFSYS_OPT_LOOPBACK */
263 #if EFSYS_OPT_MAC_STATS
265 extern __checkReturn efx_rc_t
266 ef10_mac_stats_get_mask(
268 __inout_bcount(mask_size) uint32_t *maskp,
269 __in size_t mask_size);
271 extern __checkReturn efx_rc_t
272 ef10_mac_stats_update(
274 __in efsys_mem_t *esmp,
275 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
276 __inout_opt uint32_t *generationp);
278 #endif /* EFSYS_OPT_MAC_STATS */
285 extern __checkReturn efx_rc_t
288 __in const efx_mcdi_transport_t *mtp);
292 __in efx_nic_t *enp);
295 ef10_mcdi_send_request(
297 __in_bcount(hdr_len) void *hdrp,
299 __in_bcount(sdu_len) void *sdup,
300 __in size_t sdu_len);
302 extern __checkReturn boolean_t
303 ef10_mcdi_poll_response(
304 __in efx_nic_t *enp);
307 ef10_mcdi_read_response(
309 __out_bcount(length) void *bufferp,
314 ef10_mcdi_poll_reboot(
315 __in efx_nic_t *enp);
317 extern __checkReturn efx_rc_t
318 ef10_mcdi_feature_supported(
320 __in efx_mcdi_feature_id_t id,
321 __out boolean_t *supportedp);
324 ef10_mcdi_get_timeout(
326 __in efx_mcdi_req_t *emrp,
327 __out uint32_t *timeoutp);
329 #endif /* EFSYS_OPT_MCDI */
333 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
335 extern __checkReturn efx_rc_t
336 ef10_nvram_buf_read_tlv(
338 __in_bcount(max_seg_size) caddr_t seg_data,
339 __in size_t max_seg_size,
341 __deref_out_bcount_opt(*sizep) caddr_t *datap,
342 __out size_t *sizep);
344 extern __checkReturn efx_rc_t
345 ef10_nvram_buf_write_tlv(
346 __inout_bcount(partn_size) caddr_t partn_data,
347 __in size_t partn_size,
349 __in_bcount(tag_size) caddr_t tag_data,
350 __in size_t tag_size,
351 __out size_t *total_lengthp);
353 extern __checkReturn efx_rc_t
354 ef10_nvram_partn_read_tlv(
358 __deref_out_bcount_opt(*sizep) caddr_t *datap,
359 __out size_t *sizep);
361 extern __checkReturn efx_rc_t
362 ef10_nvram_partn_write_tlv(
366 __in_bcount(size) caddr_t data,
369 extern __checkReturn efx_rc_t
370 ef10_nvram_partn_write_segment_tlv(
374 __in_bcount(size) caddr_t data,
376 __in boolean_t all_segments);
378 extern __checkReturn efx_rc_t
379 ef10_nvram_partn_lock(
381 __in uint32_t partn);
383 extern __checkReturn efx_rc_t
384 ef10_nvram_partn_unlock(
387 __out_opt uint32_t *resultp);
389 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
395 extern __checkReturn efx_rc_t
397 __in efx_nic_t *enp);
399 #endif /* EFSYS_OPT_DIAG */
401 extern __checkReturn efx_rc_t
402 ef10_nvram_type_to_partn(
404 __in efx_nvram_type_t type,
405 __out uint32_t *partnp);
407 extern __checkReturn efx_rc_t
408 ef10_nvram_partn_size(
411 __out size_t *sizep);
413 extern __checkReturn efx_rc_t
414 ef10_nvram_partn_rw_start(
417 __out size_t *chunk_sizep);
419 extern __checkReturn efx_rc_t
420 ef10_nvram_partn_read_mode(
423 __in unsigned int offset,
424 __out_bcount(size) caddr_t data,
428 extern __checkReturn efx_rc_t
429 ef10_nvram_partn_read(
432 __in unsigned int offset,
433 __out_bcount(size) caddr_t data,
436 extern __checkReturn efx_rc_t
437 ef10_nvram_partn_read_backup(
440 __in unsigned int offset,
441 __out_bcount(size) caddr_t data,
444 extern __checkReturn efx_rc_t
445 ef10_nvram_partn_erase(
448 __in unsigned int offset,
451 extern __checkReturn efx_rc_t
452 ef10_nvram_partn_write(
455 __in unsigned int offset,
456 __out_bcount(size) caddr_t data,
459 extern __checkReturn efx_rc_t
460 ef10_nvram_partn_rw_finish(
463 __out_opt uint32_t *verify_resultp);
465 extern __checkReturn efx_rc_t
466 ef10_nvram_partn_get_version(
469 __out uint32_t *subtypep,
470 __out_ecount(4) uint16_t version[4]);
472 extern __checkReturn efx_rc_t
473 ef10_nvram_partn_set_version(
476 __in_ecount(4) uint16_t version[4]);
478 extern __checkReturn efx_rc_t
479 ef10_nvram_buffer_validate(
482 __in_bcount(buffer_size)
484 __in size_t buffer_size);
486 extern __checkReturn efx_rc_t
487 ef10_nvram_buffer_create(
489 __in uint16_t partn_type,
490 __in_bcount(buffer_size)
492 __in size_t buffer_size);
494 extern __checkReturn efx_rc_t
495 ef10_nvram_buffer_find_item_start(
496 __in_bcount(buffer_size)
498 __in size_t buffer_size,
499 __out uint32_t *startp);
501 extern __checkReturn efx_rc_t
502 ef10_nvram_buffer_find_end(
503 __in_bcount(buffer_size)
505 __in size_t buffer_size,
506 __in uint32_t offset,
507 __out uint32_t *endp);
509 extern __checkReturn __success(return != B_FALSE) boolean_t
510 ef10_nvram_buffer_find_item(
511 __in_bcount(buffer_size)
513 __in size_t buffer_size,
514 __in uint32_t offset,
515 __out uint32_t *startp,
516 __out uint32_t *lengthp);
518 extern __checkReturn efx_rc_t
519 ef10_nvram_buffer_get_item(
520 __in_bcount(buffer_size)
522 __in size_t buffer_size,
523 __in uint32_t offset,
524 __in uint32_t length,
525 __out_bcount_part(item_max_size, *lengthp)
527 __in size_t item_max_size,
528 __out uint32_t *lengthp);
530 extern __checkReturn efx_rc_t
531 ef10_nvram_buffer_insert_item(
532 __in_bcount(buffer_size)
534 __in size_t buffer_size,
535 __in uint32_t offset,
536 __in_bcount(length) caddr_t keyp,
537 __in uint32_t length,
538 __out uint32_t *lengthp);
540 extern __checkReturn efx_rc_t
541 ef10_nvram_buffer_delete_item(
542 __in_bcount(buffer_size)
544 __in size_t buffer_size,
545 __in uint32_t offset,
546 __in uint32_t length,
549 extern __checkReturn efx_rc_t
550 ef10_nvram_buffer_finish(
551 __in_bcount(buffer_size)
553 __in size_t buffer_size);
555 #endif /* EFSYS_OPT_NVRAM */
560 typedef struct ef10_link_state_s {
561 uint32_t els_adv_cap_mask;
562 uint32_t els_lp_cap_mask;
563 unsigned int els_fcntl;
564 efx_link_mode_t els_link_mode;
565 #if EFSYS_OPT_LOOPBACK
566 efx_loopback_type_t els_loopback;
568 boolean_t els_mac_up;
574 __in efx_qword_t *eqp,
575 __out efx_link_mode_t *link_modep);
577 extern __checkReturn efx_rc_t
580 __out ef10_link_state_t *elsp);
582 extern __checkReturn efx_rc_t
587 extern __checkReturn efx_rc_t
588 ef10_phy_reconfigure(
589 __in efx_nic_t *enp);
591 extern __checkReturn efx_rc_t
593 __in efx_nic_t *enp);
595 extern __checkReturn efx_rc_t
598 __out uint32_t *ouip);
600 #if EFSYS_OPT_PHY_STATS
602 extern __checkReturn efx_rc_t
603 ef10_phy_stats_update(
605 __in efsys_mem_t *esmp,
606 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
608 #endif /* EFSYS_OPT_PHY_STATS */
612 extern __checkReturn efx_rc_t
613 ef10_bist_enable_offline(
614 __in efx_nic_t *enp);
616 extern __checkReturn efx_rc_t
619 __in efx_bist_type_t type);
621 extern __checkReturn efx_rc_t
624 __in efx_bist_type_t type,
625 __out efx_bist_result_t *resultp,
626 __out_opt __drv_when(count > 0, __notnull)
627 uint32_t *value_maskp,
628 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
629 unsigned long *valuesp,
635 __in efx_bist_type_t type);
637 #endif /* EFSYS_OPT_BIST */
641 extern __checkReturn efx_rc_t
643 __in efx_nic_t *enp);
647 __in efx_nic_t *enp);
649 extern __checkReturn efx_rc_t
652 __in unsigned int index,
653 __in unsigned int label,
654 __in efsys_mem_t *esmp,
660 __out unsigned int *addedp);
664 __in efx_txq_t *etp);
666 extern __checkReturn efx_rc_t
669 __in_ecount(ndescs) efx_buffer_t *ebp,
670 __in unsigned int ndescs,
671 __in unsigned int completed,
672 __inout unsigned int *addedp);
677 __in unsigned int added,
678 __in unsigned int pushed);
680 #if EFSYS_OPT_RX_PACKED_STREAM
682 ef10_rx_qpush_ps_credits(
683 __in efx_rxq_t *erp);
685 extern __checkReturn uint8_t *
686 ef10_rx_qps_packet_info(
688 __in uint8_t *buffer,
689 __in uint32_t buffer_length,
690 __in uint32_t current_offset,
691 __out uint16_t *lengthp,
692 __out uint32_t *next_offsetp,
693 __out uint32_t *timestamp);
696 extern __checkReturn efx_rc_t
699 __in unsigned int ns);
701 extern __checkReturn efx_rc_t
703 __in efx_txq_t *etp);
707 __in efx_txq_t *etp);
709 extern __checkReturn efx_rc_t
711 __in efx_txq_t *etp);
714 ef10_tx_qpio_disable(
715 __in efx_txq_t *etp);
717 extern __checkReturn efx_rc_t
720 __in_ecount(buf_length) uint8_t *buffer,
721 __in size_t buf_length,
722 __in size_t pio_buf_offset);
724 extern __checkReturn efx_rc_t
727 __in size_t pkt_length,
728 __in unsigned int completed,
729 __inout unsigned int *addedp);
731 extern __checkReturn efx_rc_t
734 __in_ecount(n) efx_desc_t *ed,
736 __in unsigned int completed,
737 __inout unsigned int *addedp);
740 ef10_tx_qdesc_dma_create(
742 __in efsys_dma_addr_t addr,
745 __out efx_desc_t *edp);
748 ef10_tx_qdesc_tso_create(
750 __in uint16_t ipv4_id,
751 __in uint32_t tcp_seq,
752 __in uint8_t tcp_flags,
753 __out efx_desc_t *edp);
756 ef10_tx_qdesc_tso2_create(
758 __in uint16_t ipv4_id,
759 __in uint32_t tcp_seq,
760 __in uint16_t tcp_mss,
761 __out_ecount(count) efx_desc_t *edp,
765 ef10_tx_qdesc_vlantci_create(
767 __in uint16_t vlan_tci,
768 __out efx_desc_t *edp);
771 ef10_tx_qdesc_checksum_create(
774 __out efx_desc_t *edp);
779 ef10_tx_qstats_update(
781 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
783 #endif /* EFSYS_OPT_QSTATS */
785 typedef uint32_t efx_piobuf_handle_t;
787 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1)
789 extern __checkReturn efx_rc_t
791 __inout efx_nic_t *enp,
792 __out uint32_t *bufnump,
793 __out efx_piobuf_handle_t *handlep,
794 __out uint32_t *blknump,
795 __out uint32_t *offsetp,
796 __out size_t *sizep);
798 extern __checkReturn efx_rc_t
800 __inout efx_nic_t *enp,
801 __in uint32_t bufnum,
802 __in uint32_t blknum);
804 extern __checkReturn efx_rc_t
806 __inout efx_nic_t *enp,
807 __in uint32_t vi_index,
808 __in efx_piobuf_handle_t handle);
810 extern __checkReturn efx_rc_t
812 __inout efx_nic_t *enp,
813 __in uint32_t vi_index);
820 extern __checkReturn efx_rc_t
822 __in efx_nic_t *enp);
824 extern __checkReturn efx_rc_t
827 __out size_t *sizep);
829 extern __checkReturn efx_rc_t
832 __out_bcount(size) caddr_t data,
835 extern __checkReturn efx_rc_t
838 __in_bcount(size) caddr_t data,
841 extern __checkReturn efx_rc_t
844 __in_bcount(size) caddr_t data,
847 extern __checkReturn efx_rc_t
850 __in_bcount(size) caddr_t data,
852 __inout efx_vpd_value_t *evvp);
854 extern __checkReturn efx_rc_t
857 __in_bcount(size) caddr_t data,
859 __in efx_vpd_value_t *evvp);
861 extern __checkReturn efx_rc_t
864 __in_bcount(size) caddr_t data,
866 __out efx_vpd_value_t *evvp,
867 __inout unsigned int *contp);
869 extern __checkReturn efx_rc_t
872 __in_bcount(size) caddr_t data,
877 __in efx_nic_t *enp);
879 #endif /* EFSYS_OPT_VPD */
884 extern __checkReturn efx_rc_t
886 __in efx_nic_t *enp);
888 #if EFSYS_OPT_RX_SCATTER
889 extern __checkReturn efx_rc_t
890 ef10_rx_scatter_enable(
892 __in unsigned int buf_size);
893 #endif /* EFSYS_OPT_RX_SCATTER */
896 #if EFSYS_OPT_RX_SCALE
898 extern __checkReturn efx_rc_t
899 ef10_rx_scale_context_alloc(
901 __in efx_rx_scale_context_type_t type,
902 __in uint32_t num_queues,
903 __out uint32_t *rss_contextp);
905 extern __checkReturn efx_rc_t
906 ef10_rx_scale_context_free(
908 __in uint32_t rss_context);
910 extern __checkReturn efx_rc_t
911 ef10_rx_scale_mode_set(
913 __in uint32_t rss_context,
914 __in efx_rx_hash_alg_t alg,
915 __in efx_rx_hash_type_t type,
916 __in boolean_t insert);
918 extern __checkReturn efx_rc_t
919 ef10_rx_scale_key_set(
921 __in uint32_t rss_context,
922 __in_ecount(n) uint8_t *key,
925 extern __checkReturn efx_rc_t
926 ef10_rx_scale_tbl_set(
928 __in uint32_t rss_context,
929 __in_ecount(n) unsigned int *table,
932 extern __checkReturn uint32_t
935 __in efx_rx_hash_alg_t func,
936 __in uint8_t *buffer);
938 #endif /* EFSYS_OPT_RX_SCALE */
940 extern __checkReturn efx_rc_t
941 ef10_rx_prefix_pktlen(
943 __in uint8_t *buffer,
944 __out uint16_t *lengthp);
949 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
951 __in unsigned int ndescs,
952 __in unsigned int completed,
953 __in unsigned int added);
958 __in unsigned int added,
959 __inout unsigned int *pushedp);
961 extern __checkReturn efx_rc_t
963 __in efx_rxq_t *erp);
967 __in efx_rxq_t *erp);
969 extern __checkReturn efx_rc_t
972 __in unsigned int index,
973 __in unsigned int label,
974 __in efx_rxq_type_t type,
975 __in uint32_t type_data,
976 __in efsys_mem_t *esmp,
979 __in unsigned int flags,
981 __in efx_rxq_t *erp);
985 __in efx_rxq_t *erp);
989 __in efx_nic_t *enp);
993 typedef struct ef10_filter_handle_s {
996 } ef10_filter_handle_t;
998 typedef struct ef10_filter_entry_s {
999 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1000 ef10_filter_handle_t efe_handle;
1001 } ef10_filter_entry_t;
1004 * BUSY flag indicates that an update is in progress.
1005 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1007 #define EFX_EF10_FILTER_FLAG_BUSY 1U
1008 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
1009 #define EFX_EF10_FILTER_FLAGS 3U
1012 * Size of the hash table used by the driver. Doesn't need to be the
1013 * same size as the hardware's table.
1015 #define EFX_EF10_FILTER_TBL_ROWS 8192
1017 /* Only need to allow for one directed and one unknown unicast filter */
1018 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
1020 /* Allow for the broadcast address to be added to the multicast list */
1021 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
1024 * For encapsulated packets, there is one filter each for each combination of
1025 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1026 * multicast inner frames.
1028 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
1030 typedef struct ef10_filter_table_s {
1031 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1032 efx_rxq_t *eft_default_rxq;
1033 boolean_t eft_using_rss;
1034 uint32_t eft_unicst_filter_indexes[
1035 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1036 uint32_t eft_unicst_filter_count;
1037 uint32_t eft_mulcst_filter_indexes[
1038 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1039 uint32_t eft_mulcst_filter_count;
1040 boolean_t eft_using_all_mulcst;
1041 uint32_t eft_encap_filter_indexes[
1042 EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1043 uint32_t eft_encap_filter_count;
1044 } ef10_filter_table_t;
1046 __checkReturn efx_rc_t
1048 __in efx_nic_t *enp);
1052 __in efx_nic_t *enp);
1054 __checkReturn efx_rc_t
1055 ef10_filter_restore(
1056 __in efx_nic_t *enp);
1058 __checkReturn efx_rc_t
1060 __in efx_nic_t *enp,
1061 __inout efx_filter_spec_t *spec,
1062 __in boolean_t may_replace);
1064 __checkReturn efx_rc_t
1066 __in efx_nic_t *enp,
1067 __inout efx_filter_spec_t *spec);
1069 extern __checkReturn efx_rc_t
1070 ef10_filter_supported_filters(
1071 __in efx_nic_t *enp,
1072 __out_ecount(buffer_length) uint32_t *buffer,
1073 __in size_t buffer_length,
1074 __out size_t *list_lengthp);
1076 extern __checkReturn efx_rc_t
1077 ef10_filter_reconfigure(
1078 __in efx_nic_t *enp,
1079 __in_ecount(6) uint8_t const *mac_addr,
1080 __in boolean_t all_unicst,
1081 __in boolean_t mulcst,
1082 __in boolean_t all_mulcst,
1083 __in boolean_t brdcst,
1084 __in_ecount(6*count) uint8_t const *addrs,
1085 __in uint32_t count);
1088 ef10_filter_get_default_rxq(
1089 __in efx_nic_t *enp,
1090 __out efx_rxq_t **erpp,
1091 __out boolean_t *using_rss);
1094 ef10_filter_default_rxq_set(
1095 __in efx_nic_t *enp,
1096 __in efx_rxq_t *erp,
1097 __in boolean_t using_rss);
1100 ef10_filter_default_rxq_clear(
1101 __in efx_nic_t *enp);
1104 #endif /* EFSYS_OPT_FILTER */
1106 extern __checkReturn efx_rc_t
1107 efx_mcdi_get_function_info(
1108 __in efx_nic_t *enp,
1109 __out uint32_t *pfp,
1110 __out_opt uint32_t *vfp);
1112 extern __checkReturn efx_rc_t
1113 efx_mcdi_privilege_mask(
1114 __in efx_nic_t *enp,
1117 __out uint32_t *maskp);
1119 extern __checkReturn efx_rc_t
1120 efx_mcdi_get_port_assignment(
1121 __in efx_nic_t *enp,
1122 __out uint32_t *portp);
1124 extern __checkReturn efx_rc_t
1125 efx_mcdi_get_port_modes(
1126 __in efx_nic_t *enp,
1127 __out uint32_t *modesp,
1128 __out_opt uint32_t *current_modep);
1130 extern __checkReturn efx_rc_t
1131 ef10_nic_get_port_mode_bandwidth(
1132 __in uint32_t port_mode,
1133 __out uint32_t *bandwidth_mbpsp);
1135 extern __checkReturn efx_rc_t
1136 efx_mcdi_get_mac_address_pf(
1137 __in efx_nic_t *enp,
1138 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1140 extern __checkReturn efx_rc_t
1141 efx_mcdi_get_mac_address_vf(
1142 __in efx_nic_t *enp,
1143 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1145 extern __checkReturn efx_rc_t
1147 __in efx_nic_t *enp,
1148 __out uint32_t *sys_freqp,
1149 __out uint32_t *dpcpu_freqp);
1152 extern __checkReturn efx_rc_t
1153 efx_mcdi_get_rxdp_config(
1154 __in efx_nic_t *enp,
1155 __out uint32_t *end_paddingp);
1157 extern __checkReturn efx_rc_t
1158 efx_mcdi_get_vector_cfg(
1159 __in efx_nic_t *enp,
1160 __out_opt uint32_t *vec_basep,
1161 __out_opt uint32_t *pf_nvecp,
1162 __out_opt uint32_t *vf_nvecp);
1164 extern __checkReturn efx_rc_t
1165 ef10_get_datapath_caps(
1166 __in efx_nic_t *enp);
1168 extern __checkReturn efx_rc_t
1169 ef10_get_vi_window_shift(
1170 __in efx_nic_t *enp,
1171 __out uint32_t *vi_window_shiftp);
1173 extern __checkReturn efx_rc_t
1174 ef10_get_privilege_mask(
1175 __in efx_nic_t *enp,
1176 __out uint32_t *maskp);
1179 #if EFSYS_OPT_RX_PACKED_STREAM
1181 /* Data space per credit in packed stream mode */
1182 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1185 * Received packets are always aligned at this boundary. Also there always
1186 * exists a gap of this size between packets.
1187 * (see SF-112241-TC, 4.5)
1189 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64
1192 * Size of a pseudo-header prepended to received packets
1193 * in packed stream mode
1195 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1197 /* Minimum space for packet in packed stream mode */
1198 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
1199 P2ROUNDUP(EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
1201 EFX_RX_PACKED_STREAM_ALIGNMENT, \
1202 EFX_RX_PACKED_STREAM_ALIGNMENT)
1204 /* Maximum number of credits */
1205 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1207 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1213 #endif /* _SYS_EF10_IMPL_H */