2 * Copyright (c) 2015-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
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28 * policies, either expressed or implied, of the FreeBSD Project.
31 #ifndef _SYS_EF10_IMPL_H
32 #define _SYS_EF10_IMPL_H
38 #if (EFSYS_OPT_HUNTINGTON && EFSYS_OPT_MEDFORD)
39 #define EF10_MAX_PIOBUF_NBUFS MAX(HUNT_PIOBUF_NBUFS, MEDFORD_PIOBUF_NBUFS)
40 #elif EFSYS_OPT_HUNTINGTON
41 #define EF10_MAX_PIOBUF_NBUFS HUNT_PIOBUF_NBUFS
42 #elif EFSYS_OPT_MEDFORD
43 #define EF10_MAX_PIOBUF_NBUFS MEDFORD_PIOBUF_NBUFS
47 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
48 * possibly be increased, or the write size reported by newer firmware used
51 #define EF10_NVRAM_CHUNK 0x80
53 /* Alignment requirement for value written to RX WPTR:
54 * the WPTR must be aligned to an 8 descriptor boundary
56 #define EF10_RX_WPTR_ALIGN 8
59 * Max byte offset into the packet the TCP header must start for the hardware
60 * to be able to parse the packet correctly.
62 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
64 /* Invalid RSS context handle */
65 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
70 __checkReturn efx_rc_t
78 __checkReturn efx_rc_t
81 __in unsigned int index,
82 __in efsys_mem_t *esmp,
93 __checkReturn efx_rc_t
96 __in unsigned int count);
103 __checkReturn efx_rc_t
106 __in unsigned int us);
109 ef10_ev_rxlabel_init(
112 __in unsigned int label,
113 __in boolean_t packed_stream);
116 ef10_ev_rxlabel_fini(
118 __in unsigned int label);
122 __checkReturn efx_rc_t
125 __in efx_intr_type_t type,
126 __in efsys_mem_t *esmp);
130 __in efx_nic_t *enp);
134 __in efx_nic_t *enp);
137 ef10_intr_disable_unlocked(
138 __in efx_nic_t *enp);
140 __checkReturn efx_rc_t
143 __in unsigned int level);
146 ef10_intr_status_line(
148 __out boolean_t *fatalp,
149 __out uint32_t *qmaskp);
152 ef10_intr_status_message(
154 __in unsigned int message,
155 __out boolean_t *fatalp);
159 __in efx_nic_t *enp);
162 __in efx_nic_t *enp);
166 extern __checkReturn efx_rc_t
168 __in efx_nic_t *enp);
170 extern __checkReturn efx_rc_t
171 ef10_nic_set_drv_limits(
172 __inout efx_nic_t *enp,
173 __in efx_drv_limits_t *edlp);
175 extern __checkReturn efx_rc_t
176 ef10_nic_get_vi_pool(
178 __out uint32_t *vi_countp);
180 extern __checkReturn efx_rc_t
181 ef10_nic_get_bar_region(
183 __in efx_nic_region_t region,
184 __out uint32_t *offsetp,
185 __out size_t *sizep);
187 extern __checkReturn efx_rc_t
189 __in efx_nic_t *enp);
191 extern __checkReturn efx_rc_t
193 __in efx_nic_t *enp);
197 __in efx_nic_t *enp);
201 __in efx_nic_t *enp);
206 extern __checkReturn efx_rc_t
209 __out efx_link_mode_t *link_modep);
211 extern __checkReturn efx_rc_t
214 __out boolean_t *mac_upp);
216 extern __checkReturn efx_rc_t
218 __in efx_nic_t *enp);
220 extern __checkReturn efx_rc_t
222 __in efx_nic_t *enp);
224 extern __checkReturn efx_rc_t
229 extern __checkReturn efx_rc_t
230 ef10_mac_reconfigure(
231 __in efx_nic_t *enp);
233 extern __checkReturn efx_rc_t
234 ef10_mac_multicast_list_set(
235 __in efx_nic_t *enp);
237 extern __checkReturn efx_rc_t
238 ef10_mac_filter_default_rxq_set(
241 __in boolean_t using_rss);
244 ef10_mac_filter_default_rxq_clear(
245 __in efx_nic_t *enp);
252 extern __checkReturn efx_rc_t
255 __in const efx_mcdi_transport_t *mtp);
259 __in efx_nic_t *enp);
262 ef10_mcdi_send_request(
264 __in_bcount(hdr_len) void *hdrp,
266 __in_bcount(sdu_len) void *sdup,
267 __in size_t sdu_len);
269 extern __checkReturn boolean_t
270 ef10_mcdi_poll_response(
271 __in efx_nic_t *enp);
274 ef10_mcdi_read_response(
276 __out_bcount(length) void *bufferp,
281 ef10_mcdi_poll_reboot(
282 __in efx_nic_t *enp);
284 extern __checkReturn efx_rc_t
285 ef10_mcdi_feature_supported(
287 __in efx_mcdi_feature_id_t id,
288 __out boolean_t *supportedp);
291 ef10_mcdi_get_timeout(
293 __in efx_mcdi_req_t *emrp,
294 __out uint32_t *timeoutp);
296 #endif /* EFSYS_OPT_MCDI */
303 typedef struct ef10_link_state_s {
304 uint32_t els_adv_cap_mask;
305 uint32_t els_lp_cap_mask;
306 unsigned int els_fcntl;
307 efx_link_mode_t els_link_mode;
308 boolean_t els_mac_up;
314 __in efx_qword_t *eqp,
315 __out efx_link_mode_t *link_modep);
317 extern __checkReturn efx_rc_t
320 __out ef10_link_state_t *elsp);
322 extern __checkReturn efx_rc_t
327 extern __checkReturn efx_rc_t
328 ef10_phy_reconfigure(
329 __in efx_nic_t *enp);
331 extern __checkReturn efx_rc_t
333 __in efx_nic_t *enp);
335 extern __checkReturn efx_rc_t
338 __out uint32_t *ouip);
342 extern __checkReturn efx_rc_t
344 __in efx_nic_t *enp);
348 __in efx_nic_t *enp);
350 extern __checkReturn efx_rc_t
353 __in unsigned int index,
354 __in unsigned int label,
355 __in efsys_mem_t *esmp,
361 __out unsigned int *addedp);
365 __in efx_txq_t *etp);
367 extern __checkReturn efx_rc_t
370 __in_ecount(n) efx_buffer_t *eb,
372 __in unsigned int completed,
373 __inout unsigned int *addedp);
378 __in unsigned int added,
379 __in unsigned int pushed);
381 extern __checkReturn efx_rc_t
384 __in unsigned int ns);
386 extern __checkReturn efx_rc_t
388 __in efx_txq_t *etp);
392 __in efx_txq_t *etp);
394 extern __checkReturn efx_rc_t
396 __in efx_txq_t *etp);
399 ef10_tx_qpio_disable(
400 __in efx_txq_t *etp);
402 extern __checkReturn efx_rc_t
405 __in_ecount(buf_length) uint8_t *buffer,
406 __in size_t buf_length,
407 __in size_t pio_buf_offset);
409 extern __checkReturn efx_rc_t
412 __in size_t pkt_length,
413 __in unsigned int completed,
414 __inout unsigned int *addedp);
416 extern __checkReturn efx_rc_t
419 __in_ecount(n) efx_desc_t *ed,
421 __in unsigned int completed,
422 __inout unsigned int *addedp);
425 ef10_tx_qdesc_dma_create(
427 __in efsys_dma_addr_t addr,
430 __out efx_desc_t *edp);
433 ef10_tx_qdesc_tso_create(
435 __in uint16_t ipv4_id,
436 __in uint32_t tcp_seq,
437 __in uint8_t tcp_flags,
438 __out efx_desc_t *edp);
441 ef10_tx_qdesc_tso2_create(
443 __in uint16_t ipv4_id,
444 __in uint32_t tcp_seq,
445 __in uint16_t tcp_mss,
446 __out_ecount(count) efx_desc_t *edp,
450 ef10_tx_qdesc_vlantci_create(
452 __in uint16_t vlan_tci,
453 __out efx_desc_t *edp);
456 typedef uint32_t efx_piobuf_handle_t;
458 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1)
460 extern __checkReturn efx_rc_t
462 __inout efx_nic_t *enp,
463 __out uint32_t *bufnump,
464 __out efx_piobuf_handle_t *handlep,
465 __out uint32_t *blknump,
466 __out uint32_t *offsetp,
467 __out size_t *sizep);
469 extern __checkReturn efx_rc_t
471 __inout efx_nic_t *enp,
472 __in uint32_t bufnum,
473 __in uint32_t blknum);
475 extern __checkReturn efx_rc_t
477 __inout efx_nic_t *enp,
478 __in uint32_t vi_index,
479 __in efx_piobuf_handle_t handle);
481 extern __checkReturn efx_rc_t
483 __inout efx_nic_t *enp,
484 __in uint32_t vi_index);
492 extern __checkReturn efx_rc_t
494 __in efx_nic_t *enp);
497 extern __checkReturn efx_rc_t
498 ef10_rx_prefix_pktlen(
500 __in uint8_t *buffer,
501 __out uint16_t *lengthp);
506 __in_ecount(n) efsys_dma_addr_t *addrp,
509 __in unsigned int completed,
510 __in unsigned int added);
515 __in unsigned int added,
516 __inout unsigned int *pushedp);
518 extern __checkReturn efx_rc_t
520 __in efx_rxq_t *erp);
524 __in efx_rxq_t *erp);
526 extern __checkReturn efx_rc_t
529 __in unsigned int index,
530 __in unsigned int label,
531 __in efx_rxq_type_t type,
532 __in efsys_mem_t *esmp,
536 __in efx_rxq_t *erp);
540 __in efx_rxq_t *erp);
544 __in efx_nic_t *enp);
548 typedef struct ef10_filter_handle_s {
551 } ef10_filter_handle_t;
553 typedef struct ef10_filter_entry_s {
554 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
555 ef10_filter_handle_t efe_handle;
556 } ef10_filter_entry_t;
559 * BUSY flag indicates that an update is in progress.
560 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
562 #define EFX_EF10_FILTER_FLAG_BUSY 1U
563 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
564 #define EFX_EF10_FILTER_FLAGS 3U
567 * Size of the hash table used by the driver. Doesn't need to be the
568 * same size as the hardware's table.
570 #define EFX_EF10_FILTER_TBL_ROWS 8192
572 /* Only need to allow for one directed and one unknown unicast filter */
573 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
575 /* Allow for the broadcast address to be added to the multicast list */
576 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
578 typedef struct ef10_filter_table_s {
579 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
580 efx_rxq_t *eft_default_rxq;
581 boolean_t eft_using_rss;
582 uint32_t eft_unicst_filter_indexes[
583 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
584 uint32_t eft_unicst_filter_count;
585 uint32_t eft_mulcst_filter_indexes[
586 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
587 uint32_t eft_mulcst_filter_count;
588 boolean_t eft_using_all_mulcst;
589 } ef10_filter_table_t;
591 __checkReturn efx_rc_t
593 __in efx_nic_t *enp);
597 __in efx_nic_t *enp);
599 __checkReturn efx_rc_t
601 __in efx_nic_t *enp);
603 __checkReturn efx_rc_t
606 __inout efx_filter_spec_t *spec,
607 __in boolean_t may_replace);
609 __checkReturn efx_rc_t
612 __inout efx_filter_spec_t *spec);
614 extern __checkReturn efx_rc_t
615 ef10_filter_supported_filters(
617 __out uint32_t *list,
618 __out size_t *length);
620 extern __checkReturn efx_rc_t
621 ef10_filter_reconfigure(
623 __in_ecount(6) uint8_t const *mac_addr,
624 __in boolean_t all_unicst,
625 __in boolean_t mulcst,
626 __in boolean_t all_mulcst,
627 __in boolean_t brdcst,
628 __in_ecount(6*count) uint8_t const *addrs,
629 __in uint32_t count);
632 ef10_filter_get_default_rxq(
634 __out efx_rxq_t **erpp,
635 __out boolean_t *using_rss);
638 ef10_filter_default_rxq_set(
641 __in boolean_t using_rss);
644 ef10_filter_default_rxq_clear(
645 __in efx_nic_t *enp);
648 #endif /* EFSYS_OPT_FILTER */
650 extern __checkReturn efx_rc_t
651 efx_mcdi_get_function_info(
654 __out_opt uint32_t *vfp);
656 extern __checkReturn efx_rc_t
657 efx_mcdi_privilege_mask(
661 __out uint32_t *maskp);
663 extern __checkReturn efx_rc_t
664 efx_mcdi_get_port_assignment(
666 __out uint32_t *portp);
668 extern __checkReturn efx_rc_t
669 efx_mcdi_get_port_modes(
671 __out uint32_t *modesp,
672 __out_opt uint32_t *current_modep);
674 extern __checkReturn efx_rc_t
675 ef10_nic_get_port_mode_bandwidth(
676 __in uint32_t port_mode,
677 __out uint32_t *bandwidth_mbpsp);
679 extern __checkReturn efx_rc_t
680 efx_mcdi_get_mac_address_pf(
682 __out_ecount_opt(6) uint8_t mac_addrp[6]);
684 extern __checkReturn efx_rc_t
685 efx_mcdi_get_mac_address_vf(
687 __out_ecount_opt(6) uint8_t mac_addrp[6]);
689 extern __checkReturn efx_rc_t
692 __out uint32_t *sys_freqp,
693 __out uint32_t *dpcpu_freqp);
696 extern __checkReturn efx_rc_t
697 efx_mcdi_get_vector_cfg(
699 __out_opt uint32_t *vec_basep,
700 __out_opt uint32_t *pf_nvecp,
701 __out_opt uint32_t *vf_nvecp);
703 extern __checkReturn efx_rc_t
704 ef10_get_datapath_caps(
705 __in efx_nic_t *enp);
707 extern __checkReturn efx_rc_t
708 ef10_get_privilege_mask(
710 __out uint32_t *maskp);
712 extern __checkReturn efx_rc_t
713 ef10_external_port_mapping(
716 __out uint8_t *external_portp);
722 #endif /* _SYS_EF10_IMPL_H */