2 * Copyright (c) 2015-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #ifndef _SYS_EF10_IMPL_H
32 #define _SYS_EF10_IMPL_H
38 #if (EFSYS_OPT_HUNTINGTON && EFSYS_OPT_MEDFORD)
39 #define EF10_MAX_PIOBUF_NBUFS MAX(HUNT_PIOBUF_NBUFS, MEDFORD_PIOBUF_NBUFS)
40 #elif EFSYS_OPT_HUNTINGTON
41 #define EF10_MAX_PIOBUF_NBUFS HUNT_PIOBUF_NBUFS
42 #elif EFSYS_OPT_MEDFORD
43 #define EF10_MAX_PIOBUF_NBUFS MEDFORD_PIOBUF_NBUFS
47 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
48 * possibly be increased, or the write size reported by newer firmware used
51 #define EF10_NVRAM_CHUNK 0x80
53 /* Alignment requirement for value written to RX WPTR:
54 * the WPTR must be aligned to an 8 descriptor boundary
56 #define EF10_RX_WPTR_ALIGN 8
59 * Max byte offset into the packet the TCP header must start for the hardware
60 * to be able to parse the packet correctly.
62 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
64 /* Invalid RSS context handle */
65 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
70 __checkReturn efx_rc_t
78 __checkReturn efx_rc_t
81 __in unsigned int index,
82 __in efsys_mem_t *esmp,
93 __checkReturn efx_rc_t
96 __in unsigned int count);
103 __checkReturn efx_rc_t
106 __in unsigned int us);
110 ef10_ev_qstats_update(
112 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
113 #endif /* EFSYS_OPT_QSTATS */
116 ef10_ev_rxlabel_init(
119 __in unsigned int label,
120 __in boolean_t packed_stream);
123 ef10_ev_rxlabel_fini(
125 __in unsigned int label);
129 __checkReturn efx_rc_t
132 __in efx_intr_type_t type,
133 __in efsys_mem_t *esmp);
137 __in efx_nic_t *enp);
141 __in efx_nic_t *enp);
144 ef10_intr_disable_unlocked(
145 __in efx_nic_t *enp);
147 __checkReturn efx_rc_t
150 __in unsigned int level);
153 ef10_intr_status_line(
155 __out boolean_t *fatalp,
156 __out uint32_t *qmaskp);
159 ef10_intr_status_message(
161 __in unsigned int message,
162 __out boolean_t *fatalp);
166 __in efx_nic_t *enp);
169 __in efx_nic_t *enp);
173 extern __checkReturn efx_rc_t
175 __in efx_nic_t *enp);
177 extern __checkReturn efx_rc_t
178 ef10_nic_set_drv_limits(
179 __inout efx_nic_t *enp,
180 __in efx_drv_limits_t *edlp);
182 extern __checkReturn efx_rc_t
183 ef10_nic_get_vi_pool(
185 __out uint32_t *vi_countp);
187 extern __checkReturn efx_rc_t
188 ef10_nic_get_bar_region(
190 __in efx_nic_region_t region,
191 __out uint32_t *offsetp,
192 __out size_t *sizep);
194 extern __checkReturn efx_rc_t
196 __in efx_nic_t *enp);
198 extern __checkReturn efx_rc_t
200 __in efx_nic_t *enp);
204 extern __checkReturn efx_rc_t
205 ef10_nic_register_test(
206 __in efx_nic_t *enp);
208 #endif /* EFSYS_OPT_DIAG */
212 __in efx_nic_t *enp);
216 __in efx_nic_t *enp);
221 extern __checkReturn efx_rc_t
224 __out efx_link_mode_t *link_modep);
226 extern __checkReturn efx_rc_t
229 __out boolean_t *mac_upp);
231 extern __checkReturn efx_rc_t
233 __in efx_nic_t *enp);
235 extern __checkReturn efx_rc_t
237 __in efx_nic_t *enp);
239 extern __checkReturn efx_rc_t
244 extern __checkReturn efx_rc_t
245 ef10_mac_reconfigure(
246 __in efx_nic_t *enp);
248 extern __checkReturn efx_rc_t
249 ef10_mac_multicast_list_set(
250 __in efx_nic_t *enp);
252 extern __checkReturn efx_rc_t
253 ef10_mac_filter_default_rxq_set(
256 __in boolean_t using_rss);
259 ef10_mac_filter_default_rxq_clear(
260 __in efx_nic_t *enp);
262 #if EFSYS_OPT_MAC_STATS
264 extern __checkReturn efx_rc_t
265 ef10_mac_stats_get_mask(
267 __inout_bcount(mask_size) uint32_t *maskp,
268 __in size_t mask_size);
270 extern __checkReturn efx_rc_t
271 ef10_mac_stats_update(
273 __in efsys_mem_t *esmp,
274 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
275 __inout_opt uint32_t *generationp);
277 #endif /* EFSYS_OPT_MAC_STATS */
284 extern __checkReturn efx_rc_t
287 __in const efx_mcdi_transport_t *mtp);
291 __in efx_nic_t *enp);
294 ef10_mcdi_send_request(
296 __in_bcount(hdr_len) void *hdrp,
298 __in_bcount(sdu_len) void *sdup,
299 __in size_t sdu_len);
301 extern __checkReturn boolean_t
302 ef10_mcdi_poll_response(
303 __in efx_nic_t *enp);
306 ef10_mcdi_read_response(
308 __out_bcount(length) void *bufferp,
313 ef10_mcdi_poll_reboot(
314 __in efx_nic_t *enp);
316 extern __checkReturn efx_rc_t
317 ef10_mcdi_feature_supported(
319 __in efx_mcdi_feature_id_t id,
320 __out boolean_t *supportedp);
323 ef10_mcdi_get_timeout(
325 __in efx_mcdi_req_t *emrp,
326 __out uint32_t *timeoutp);
328 #endif /* EFSYS_OPT_MCDI */
335 typedef struct ef10_link_state_s {
336 uint32_t els_adv_cap_mask;
337 uint32_t els_lp_cap_mask;
338 unsigned int els_fcntl;
339 efx_link_mode_t els_link_mode;
340 boolean_t els_mac_up;
346 __in efx_qword_t *eqp,
347 __out efx_link_mode_t *link_modep);
349 extern __checkReturn efx_rc_t
352 __out ef10_link_state_t *elsp);
354 extern __checkReturn efx_rc_t
359 extern __checkReturn efx_rc_t
360 ef10_phy_reconfigure(
361 __in efx_nic_t *enp);
363 extern __checkReturn efx_rc_t
365 __in efx_nic_t *enp);
367 extern __checkReturn efx_rc_t
370 __out uint32_t *ouip);
372 #if EFSYS_OPT_PHY_STATS
374 extern __checkReturn efx_rc_t
375 ef10_phy_stats_update(
377 __in efsys_mem_t *esmp,
378 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
380 #endif /* EFSYS_OPT_PHY_STATS */
384 extern __checkReturn efx_rc_t
385 ef10_bist_enable_offline(
386 __in efx_nic_t *enp);
388 extern __checkReturn efx_rc_t
391 __in efx_bist_type_t type);
393 extern __checkReturn efx_rc_t
396 __in efx_bist_type_t type,
397 __out efx_bist_result_t *resultp,
398 __out_opt __drv_when(count > 0, __notnull)
399 uint32_t *value_maskp,
400 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
401 unsigned long *valuesp,
407 __in efx_bist_type_t type);
409 #endif /* EFSYS_OPT_BIST */
413 extern __checkReturn efx_rc_t
415 __in efx_nic_t *enp);
419 __in efx_nic_t *enp);
421 extern __checkReturn efx_rc_t
424 __in unsigned int index,
425 __in unsigned int label,
426 __in efsys_mem_t *esmp,
432 __out unsigned int *addedp);
436 __in efx_txq_t *etp);
438 extern __checkReturn efx_rc_t
441 __in_ecount(n) efx_buffer_t *eb,
443 __in unsigned int completed,
444 __inout unsigned int *addedp);
449 __in unsigned int added,
450 __in unsigned int pushed);
452 extern __checkReturn efx_rc_t
455 __in unsigned int ns);
457 extern __checkReturn efx_rc_t
459 __in efx_txq_t *etp);
463 __in efx_txq_t *etp);
465 extern __checkReturn efx_rc_t
467 __in efx_txq_t *etp);
470 ef10_tx_qpio_disable(
471 __in efx_txq_t *etp);
473 extern __checkReturn efx_rc_t
476 __in_ecount(buf_length) uint8_t *buffer,
477 __in size_t buf_length,
478 __in size_t pio_buf_offset);
480 extern __checkReturn efx_rc_t
483 __in size_t pkt_length,
484 __in unsigned int completed,
485 __inout unsigned int *addedp);
487 extern __checkReturn efx_rc_t
490 __in_ecount(n) efx_desc_t *ed,
492 __in unsigned int completed,
493 __inout unsigned int *addedp);
496 ef10_tx_qdesc_dma_create(
498 __in efsys_dma_addr_t addr,
501 __out efx_desc_t *edp);
504 ef10_tx_qdesc_tso_create(
506 __in uint16_t ipv4_id,
507 __in uint32_t tcp_seq,
508 __in uint8_t tcp_flags,
509 __out efx_desc_t *edp);
512 ef10_tx_qdesc_tso2_create(
514 __in uint16_t ipv4_id,
515 __in uint32_t tcp_seq,
516 __in uint16_t tcp_mss,
517 __out_ecount(count) efx_desc_t *edp,
521 ef10_tx_qdesc_vlantci_create(
523 __in uint16_t vlan_tci,
524 __out efx_desc_t *edp);
530 ef10_tx_qstats_update(
532 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
534 #endif /* EFSYS_OPT_QSTATS */
536 typedef uint32_t efx_piobuf_handle_t;
538 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1)
540 extern __checkReturn efx_rc_t
542 __inout efx_nic_t *enp,
543 __out uint32_t *bufnump,
544 __out efx_piobuf_handle_t *handlep,
545 __out uint32_t *blknump,
546 __out uint32_t *offsetp,
547 __out size_t *sizep);
549 extern __checkReturn efx_rc_t
551 __inout efx_nic_t *enp,
552 __in uint32_t bufnum,
553 __in uint32_t blknum);
555 extern __checkReturn efx_rc_t
557 __inout efx_nic_t *enp,
558 __in uint32_t vi_index,
559 __in efx_piobuf_handle_t handle);
561 extern __checkReturn efx_rc_t
563 __inout efx_nic_t *enp,
564 __in uint32_t vi_index);
572 extern __checkReturn efx_rc_t
574 __in efx_nic_t *enp);
577 extern __checkReturn efx_rc_t
578 ef10_rx_prefix_pktlen(
580 __in uint8_t *buffer,
581 __out uint16_t *lengthp);
586 __in_ecount(n) efsys_dma_addr_t *addrp,
589 __in unsigned int completed,
590 __in unsigned int added);
595 __in unsigned int added,
596 __inout unsigned int *pushedp);
598 extern __checkReturn efx_rc_t
600 __in efx_rxq_t *erp);
604 __in efx_rxq_t *erp);
606 extern __checkReturn efx_rc_t
609 __in unsigned int index,
610 __in unsigned int label,
611 __in efx_rxq_type_t type,
612 __in efsys_mem_t *esmp,
616 __in efx_rxq_t *erp);
620 __in efx_rxq_t *erp);
624 __in efx_nic_t *enp);
628 typedef struct ef10_filter_handle_s {
631 } ef10_filter_handle_t;
633 typedef struct ef10_filter_entry_s {
634 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
635 ef10_filter_handle_t efe_handle;
636 } ef10_filter_entry_t;
639 * BUSY flag indicates that an update is in progress.
640 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
642 #define EFX_EF10_FILTER_FLAG_BUSY 1U
643 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
644 #define EFX_EF10_FILTER_FLAGS 3U
647 * Size of the hash table used by the driver. Doesn't need to be the
648 * same size as the hardware's table.
650 #define EFX_EF10_FILTER_TBL_ROWS 8192
652 /* Only need to allow for one directed and one unknown unicast filter */
653 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
655 /* Allow for the broadcast address to be added to the multicast list */
656 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
658 typedef struct ef10_filter_table_s {
659 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
660 efx_rxq_t *eft_default_rxq;
661 boolean_t eft_using_rss;
662 uint32_t eft_unicst_filter_indexes[
663 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
664 uint32_t eft_unicst_filter_count;
665 uint32_t eft_mulcst_filter_indexes[
666 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
667 uint32_t eft_mulcst_filter_count;
668 boolean_t eft_using_all_mulcst;
669 } ef10_filter_table_t;
671 __checkReturn efx_rc_t
673 __in efx_nic_t *enp);
677 __in efx_nic_t *enp);
679 __checkReturn efx_rc_t
681 __in efx_nic_t *enp);
683 __checkReturn efx_rc_t
686 __inout efx_filter_spec_t *spec,
687 __in boolean_t may_replace);
689 __checkReturn efx_rc_t
692 __inout efx_filter_spec_t *spec);
694 extern __checkReturn efx_rc_t
695 ef10_filter_supported_filters(
697 __out uint32_t *list,
698 __out size_t *length);
700 extern __checkReturn efx_rc_t
701 ef10_filter_reconfigure(
703 __in_ecount(6) uint8_t const *mac_addr,
704 __in boolean_t all_unicst,
705 __in boolean_t mulcst,
706 __in boolean_t all_mulcst,
707 __in boolean_t brdcst,
708 __in_ecount(6*count) uint8_t const *addrs,
709 __in uint32_t count);
712 ef10_filter_get_default_rxq(
714 __out efx_rxq_t **erpp,
715 __out boolean_t *using_rss);
718 ef10_filter_default_rxq_set(
721 __in boolean_t using_rss);
724 ef10_filter_default_rxq_clear(
725 __in efx_nic_t *enp);
728 #endif /* EFSYS_OPT_FILTER */
730 extern __checkReturn efx_rc_t
731 efx_mcdi_get_function_info(
734 __out_opt uint32_t *vfp);
736 extern __checkReturn efx_rc_t
737 efx_mcdi_privilege_mask(
741 __out uint32_t *maskp);
743 extern __checkReturn efx_rc_t
744 efx_mcdi_get_port_assignment(
746 __out uint32_t *portp);
748 extern __checkReturn efx_rc_t
749 efx_mcdi_get_port_modes(
751 __out uint32_t *modesp,
752 __out_opt uint32_t *current_modep);
754 extern __checkReturn efx_rc_t
755 ef10_nic_get_port_mode_bandwidth(
756 __in uint32_t port_mode,
757 __out uint32_t *bandwidth_mbpsp);
759 extern __checkReturn efx_rc_t
760 efx_mcdi_get_mac_address_pf(
762 __out_ecount_opt(6) uint8_t mac_addrp[6]);
764 extern __checkReturn efx_rc_t
765 efx_mcdi_get_mac_address_vf(
767 __out_ecount_opt(6) uint8_t mac_addrp[6]);
769 extern __checkReturn efx_rc_t
772 __out uint32_t *sys_freqp,
773 __out uint32_t *dpcpu_freqp);
776 extern __checkReturn efx_rc_t
777 efx_mcdi_get_vector_cfg(
779 __out_opt uint32_t *vec_basep,
780 __out_opt uint32_t *pf_nvecp,
781 __out_opt uint32_t *vf_nvecp);
783 extern __checkReturn efx_rc_t
784 ef10_get_datapath_caps(
785 __in efx_nic_t *enp);
787 extern __checkReturn efx_rc_t
788 ef10_get_privilege_mask(
790 __out uint32_t *maskp);
792 extern __checkReturn efx_rc_t
793 ef10_external_port_mapping(
796 __out uint8_t *external_portp);
802 #endif /* _SYS_EF10_IMPL_H */