2 * Copyright (c) 2015-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #ifndef _SYS_EF10_IMPL_H
32 #define _SYS_EF10_IMPL_H
38 #if (EFSYS_OPT_HUNTINGTON && EFSYS_OPT_MEDFORD)
39 #define EF10_MAX_PIOBUF_NBUFS MAX(HUNT_PIOBUF_NBUFS, MEDFORD_PIOBUF_NBUFS)
40 #elif EFSYS_OPT_HUNTINGTON
41 #define EF10_MAX_PIOBUF_NBUFS HUNT_PIOBUF_NBUFS
42 #elif EFSYS_OPT_MEDFORD
43 #define EF10_MAX_PIOBUF_NBUFS MEDFORD_PIOBUF_NBUFS
47 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
48 * possibly be increased, or the write size reported by newer firmware used
51 #define EF10_NVRAM_CHUNK 0x80
53 /* Alignment requirement for value written to RX WPTR:
54 * the WPTR must be aligned to an 8 descriptor boundary
56 #define EF10_RX_WPTR_ALIGN 8
59 * Max byte offset into the packet the TCP header must start for the hardware
60 * to be able to parse the packet correctly.
62 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
64 /* Invalid RSS context handle */
65 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
70 __checkReturn efx_rc_t
78 __checkReturn efx_rc_t
81 __in unsigned int index,
82 __in efsys_mem_t *esmp,
93 __checkReturn efx_rc_t
96 __in unsigned int count);
103 __checkReturn efx_rc_t
106 __in unsigned int us);
110 ef10_ev_qstats_update(
112 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
113 #endif /* EFSYS_OPT_QSTATS */
116 ef10_ev_rxlabel_init(
119 __in unsigned int label,
120 __in efx_rxq_type_t type);
123 ef10_ev_rxlabel_fini(
125 __in unsigned int label);
129 __checkReturn efx_rc_t
132 __in efx_intr_type_t type,
133 __in efsys_mem_t *esmp);
137 __in efx_nic_t *enp);
141 __in efx_nic_t *enp);
144 ef10_intr_disable_unlocked(
145 __in efx_nic_t *enp);
147 __checkReturn efx_rc_t
150 __in unsigned int level);
153 ef10_intr_status_line(
155 __out boolean_t *fatalp,
156 __out uint32_t *qmaskp);
159 ef10_intr_status_message(
161 __in unsigned int message,
162 __out boolean_t *fatalp);
166 __in efx_nic_t *enp);
169 __in efx_nic_t *enp);
173 extern __checkReturn efx_rc_t
175 __in efx_nic_t *enp);
177 extern __checkReturn efx_rc_t
178 ef10_nic_set_drv_limits(
179 __inout efx_nic_t *enp,
180 __in efx_drv_limits_t *edlp);
182 extern __checkReturn efx_rc_t
183 ef10_nic_get_vi_pool(
185 __out uint32_t *vi_countp);
187 extern __checkReturn efx_rc_t
188 ef10_nic_get_bar_region(
190 __in efx_nic_region_t region,
191 __out uint32_t *offsetp,
192 __out size_t *sizep);
194 extern __checkReturn efx_rc_t
196 __in efx_nic_t *enp);
198 extern __checkReturn efx_rc_t
200 __in efx_nic_t *enp);
204 extern __checkReturn efx_rc_t
205 ef10_nic_register_test(
206 __in efx_nic_t *enp);
208 #endif /* EFSYS_OPT_DIAG */
212 __in efx_nic_t *enp);
216 __in efx_nic_t *enp);
221 extern __checkReturn efx_rc_t
224 __out efx_link_mode_t *link_modep);
226 extern __checkReturn efx_rc_t
229 __out boolean_t *mac_upp);
231 extern __checkReturn efx_rc_t
233 __in efx_nic_t *enp);
235 extern __checkReturn efx_rc_t
237 __in efx_nic_t *enp);
239 extern __checkReturn efx_rc_t
244 extern __checkReturn efx_rc_t
245 ef10_mac_reconfigure(
246 __in efx_nic_t *enp);
248 extern __checkReturn efx_rc_t
249 ef10_mac_multicast_list_set(
250 __in efx_nic_t *enp);
252 extern __checkReturn efx_rc_t
253 ef10_mac_filter_default_rxq_set(
256 __in boolean_t using_rss);
259 ef10_mac_filter_default_rxq_clear(
260 __in efx_nic_t *enp);
262 #if EFSYS_OPT_LOOPBACK
264 extern __checkReturn efx_rc_t
265 ef10_mac_loopback_set(
267 __in efx_link_mode_t link_mode,
268 __in efx_loopback_type_t loopback_type);
270 #endif /* EFSYS_OPT_LOOPBACK */
272 #if EFSYS_OPT_MAC_STATS
274 extern __checkReturn efx_rc_t
275 ef10_mac_stats_get_mask(
277 __inout_bcount(mask_size) uint32_t *maskp,
278 __in size_t mask_size);
280 extern __checkReturn efx_rc_t
281 ef10_mac_stats_update(
283 __in efsys_mem_t *esmp,
284 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
285 __inout_opt uint32_t *generationp);
287 #endif /* EFSYS_OPT_MAC_STATS */
294 extern __checkReturn efx_rc_t
297 __in const efx_mcdi_transport_t *mtp);
301 __in efx_nic_t *enp);
304 ef10_mcdi_send_request(
306 __in_bcount(hdr_len) void *hdrp,
308 __in_bcount(sdu_len) void *sdup,
309 __in size_t sdu_len);
311 extern __checkReturn boolean_t
312 ef10_mcdi_poll_response(
313 __in efx_nic_t *enp);
316 ef10_mcdi_read_response(
318 __out_bcount(length) void *bufferp,
323 ef10_mcdi_poll_reboot(
324 __in efx_nic_t *enp);
326 extern __checkReturn efx_rc_t
327 ef10_mcdi_feature_supported(
329 __in efx_mcdi_feature_id_t id,
330 __out boolean_t *supportedp);
333 ef10_mcdi_get_timeout(
335 __in efx_mcdi_req_t *emrp,
336 __out uint32_t *timeoutp);
338 #endif /* EFSYS_OPT_MCDI */
342 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
344 extern __checkReturn efx_rc_t
345 ef10_nvram_buf_read_tlv(
347 __in_bcount(max_seg_size) caddr_t seg_data,
348 __in size_t max_seg_size,
350 __deref_out_bcount_opt(*sizep) caddr_t *datap,
351 __out size_t *sizep);
353 extern __checkReturn efx_rc_t
354 ef10_nvram_buf_write_tlv(
355 __inout_bcount(partn_size) caddr_t partn_data,
356 __in size_t partn_size,
358 __in_bcount(tag_size) caddr_t tag_data,
359 __in size_t tag_size,
360 __out size_t *total_lengthp);
362 extern __checkReturn efx_rc_t
363 ef10_nvram_partn_read_tlv(
367 __deref_out_bcount_opt(*sizep) caddr_t *datap,
368 __out size_t *sizep);
370 extern __checkReturn efx_rc_t
371 ef10_nvram_partn_write_tlv(
375 __in_bcount(size) caddr_t data,
378 extern __checkReturn efx_rc_t
379 ef10_nvram_partn_write_segment_tlv(
383 __in_bcount(size) caddr_t data,
385 __in boolean_t all_segments);
387 extern __checkReturn efx_rc_t
388 ef10_nvram_partn_lock(
390 __in uint32_t partn);
392 extern __checkReturn efx_rc_t
393 ef10_nvram_partn_unlock(
396 __out_opt uint32_t *resultp);
398 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
404 extern __checkReturn efx_rc_t
406 __in efx_nic_t *enp);
408 #endif /* EFSYS_OPT_DIAG */
410 extern __checkReturn efx_rc_t
411 ef10_nvram_type_to_partn(
413 __in efx_nvram_type_t type,
414 __out uint32_t *partnp);
416 extern __checkReturn efx_rc_t
417 ef10_nvram_partn_size(
420 __out size_t *sizep);
422 extern __checkReturn efx_rc_t
423 ef10_nvram_partn_rw_start(
426 __out size_t *chunk_sizep);
428 extern __checkReturn efx_rc_t
429 ef10_nvram_partn_read_mode(
432 __in unsigned int offset,
433 __out_bcount(size) caddr_t data,
437 extern __checkReturn efx_rc_t
438 ef10_nvram_partn_read(
441 __in unsigned int offset,
442 __out_bcount(size) caddr_t data,
445 extern __checkReturn efx_rc_t
446 ef10_nvram_partn_read_backup(
449 __in unsigned int offset,
450 __out_bcount(size) caddr_t data,
453 extern __checkReturn efx_rc_t
454 ef10_nvram_partn_erase(
457 __in unsigned int offset,
460 extern __checkReturn efx_rc_t
461 ef10_nvram_partn_write(
464 __in unsigned int offset,
465 __out_bcount(size) caddr_t data,
468 extern __checkReturn efx_rc_t
469 ef10_nvram_partn_rw_finish(
472 __out_opt uint32_t *verify_resultp);
474 extern __checkReturn efx_rc_t
475 ef10_nvram_partn_get_version(
478 __out uint32_t *subtypep,
479 __out_ecount(4) uint16_t version[4]);
481 extern __checkReturn efx_rc_t
482 ef10_nvram_partn_set_version(
485 __in_ecount(4) uint16_t version[4]);
487 extern __checkReturn efx_rc_t
488 ef10_nvram_buffer_validate(
491 __in_bcount(buffer_size)
493 __in size_t buffer_size);
495 extern __checkReturn efx_rc_t
496 ef10_nvram_buffer_create(
498 __in uint16_t partn_type,
499 __in_bcount(buffer_size)
501 __in size_t buffer_size);
503 extern __checkReturn efx_rc_t
504 ef10_nvram_buffer_find_item_start(
505 __in_bcount(buffer_size)
507 __in size_t buffer_size,
508 __out uint32_t *startp
511 extern __checkReturn efx_rc_t
512 ef10_nvram_buffer_find_end(
513 __in_bcount(buffer_size)
515 __in size_t buffer_size,
516 __in uint32_t offset,
520 extern __checkReturn __success(return != B_FALSE) boolean_t
521 ef10_nvram_buffer_find_item(
522 __in_bcount(buffer_size)
524 __in size_t buffer_size,
525 __in uint32_t offset,
526 __out uint32_t *startp,
527 __out uint32_t *lengthp
530 extern __checkReturn efx_rc_t
531 ef10_nvram_buffer_get_item(
532 __in_bcount(buffer_size)
534 __in size_t buffer_size,
535 __in uint32_t offset,
536 __in uint32_t length,
537 __out_bcount_part(item_max_size, *lengthp)
539 __in size_t item_max_size,
540 __out uint32_t *lengthp
543 extern __checkReturn efx_rc_t
544 ef10_nvram_buffer_insert_item(
545 __in_bcount(buffer_size)
547 __in size_t buffer_size,
548 __in uint32_t offset,
549 __in_bcount(length) caddr_t keyp,
550 __in uint32_t length,
551 __out uint32_t *lengthp
554 extern __checkReturn efx_rc_t
555 ef10_nvram_buffer_delete_item(
556 __in_bcount(buffer_size)
558 __in size_t buffer_size,
559 __in uint32_t offset,
560 __in uint32_t length,
564 extern __checkReturn efx_rc_t
565 ef10_nvram_buffer_finish(
566 __in_bcount(buffer_size)
568 __in size_t buffer_size
571 #endif /* EFSYS_OPT_NVRAM */
576 typedef struct ef10_link_state_s {
577 uint32_t els_adv_cap_mask;
578 uint32_t els_lp_cap_mask;
579 unsigned int els_fcntl;
580 efx_link_mode_t els_link_mode;
581 #if EFSYS_OPT_LOOPBACK
582 efx_loopback_type_t els_loopback;
584 boolean_t els_mac_up;
590 __in efx_qword_t *eqp,
591 __out efx_link_mode_t *link_modep);
593 extern __checkReturn efx_rc_t
596 __out ef10_link_state_t *elsp);
598 extern __checkReturn efx_rc_t
603 extern __checkReturn efx_rc_t
604 ef10_phy_reconfigure(
605 __in efx_nic_t *enp);
607 extern __checkReturn efx_rc_t
609 __in efx_nic_t *enp);
611 extern __checkReturn efx_rc_t
614 __out uint32_t *ouip);
616 #if EFSYS_OPT_PHY_STATS
618 extern __checkReturn efx_rc_t
619 ef10_phy_stats_update(
621 __in efsys_mem_t *esmp,
622 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
624 #endif /* EFSYS_OPT_PHY_STATS */
628 extern __checkReturn efx_rc_t
629 ef10_bist_enable_offline(
630 __in efx_nic_t *enp);
632 extern __checkReturn efx_rc_t
635 __in efx_bist_type_t type);
637 extern __checkReturn efx_rc_t
640 __in efx_bist_type_t type,
641 __out efx_bist_result_t *resultp,
642 __out_opt __drv_when(count > 0, __notnull)
643 uint32_t *value_maskp,
644 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
645 unsigned long *valuesp,
651 __in efx_bist_type_t type);
653 #endif /* EFSYS_OPT_BIST */
657 extern __checkReturn efx_rc_t
659 __in efx_nic_t *enp);
663 __in efx_nic_t *enp);
665 extern __checkReturn efx_rc_t
668 __in unsigned int index,
669 __in unsigned int label,
670 __in efsys_mem_t *esmp,
676 __out unsigned int *addedp);
680 __in efx_txq_t *etp);
682 extern __checkReturn efx_rc_t
685 __in_ecount(n) efx_buffer_t *eb,
687 __in unsigned int completed,
688 __inout unsigned int *addedp);
693 __in unsigned int added,
694 __in unsigned int pushed);
696 #if EFSYS_OPT_RX_PACKED_STREAM
698 ef10_rx_qpush_ps_credits(
699 __in efx_rxq_t *erp);
701 extern __checkReturn uint8_t *
702 ef10_rx_qps_packet_info(
704 __in uint8_t *buffer,
705 __in uint32_t buffer_length,
706 __in uint32_t current_offset,
707 __out uint16_t *lengthp,
708 __out uint32_t *next_offsetp,
709 __out uint32_t *timestamp);
712 extern __checkReturn efx_rc_t
715 __in unsigned int ns);
717 extern __checkReturn efx_rc_t
719 __in efx_txq_t *etp);
723 __in efx_txq_t *etp);
725 extern __checkReturn efx_rc_t
727 __in efx_txq_t *etp);
730 ef10_tx_qpio_disable(
731 __in efx_txq_t *etp);
733 extern __checkReturn efx_rc_t
736 __in_ecount(buf_length) uint8_t *buffer,
737 __in size_t buf_length,
738 __in size_t pio_buf_offset);
740 extern __checkReturn efx_rc_t
743 __in size_t pkt_length,
744 __in unsigned int completed,
745 __inout unsigned int *addedp);
747 extern __checkReturn efx_rc_t
750 __in_ecount(n) efx_desc_t *ed,
752 __in unsigned int completed,
753 __inout unsigned int *addedp);
756 ef10_tx_qdesc_dma_create(
758 __in efsys_dma_addr_t addr,
761 __out efx_desc_t *edp);
764 ef10_tx_qdesc_tso_create(
766 __in uint16_t ipv4_id,
767 __in uint32_t tcp_seq,
768 __in uint8_t tcp_flags,
769 __out efx_desc_t *edp);
772 ef10_tx_qdesc_tso2_create(
774 __in uint16_t ipv4_id,
775 __in uint32_t tcp_seq,
776 __in uint16_t tcp_mss,
777 __out_ecount(count) efx_desc_t *edp,
781 ef10_tx_qdesc_vlantci_create(
783 __in uint16_t vlan_tci,
784 __out efx_desc_t *edp);
790 ef10_tx_qstats_update(
792 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
794 #endif /* EFSYS_OPT_QSTATS */
796 typedef uint32_t efx_piobuf_handle_t;
798 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1)
800 extern __checkReturn efx_rc_t
802 __inout efx_nic_t *enp,
803 __out uint32_t *bufnump,
804 __out efx_piobuf_handle_t *handlep,
805 __out uint32_t *blknump,
806 __out uint32_t *offsetp,
807 __out size_t *sizep);
809 extern __checkReturn efx_rc_t
811 __inout efx_nic_t *enp,
812 __in uint32_t bufnum,
813 __in uint32_t blknum);
815 extern __checkReturn efx_rc_t
817 __inout efx_nic_t *enp,
818 __in uint32_t vi_index,
819 __in efx_piobuf_handle_t handle);
821 extern __checkReturn efx_rc_t
823 __inout efx_nic_t *enp,
824 __in uint32_t vi_index);
831 extern __checkReturn efx_rc_t
833 __in efx_nic_t *enp);
835 extern __checkReturn efx_rc_t
838 __out size_t *sizep);
840 extern __checkReturn efx_rc_t
843 __out_bcount(size) caddr_t data,
846 extern __checkReturn efx_rc_t
849 __in_bcount(size) caddr_t data,
852 extern __checkReturn efx_rc_t
855 __in_bcount(size) caddr_t data,
858 extern __checkReturn efx_rc_t
861 __in_bcount(size) caddr_t data,
863 __inout efx_vpd_value_t *evvp);
865 extern __checkReturn efx_rc_t
868 __in_bcount(size) caddr_t data,
870 __in efx_vpd_value_t *evvp);
872 extern __checkReturn efx_rc_t
875 __in_bcount(size) caddr_t data,
877 __out efx_vpd_value_t *evvp,
878 __inout unsigned int *contp);
880 extern __checkReturn efx_rc_t
883 __in_bcount(size) caddr_t data,
888 __in efx_nic_t *enp);
890 #endif /* EFSYS_OPT_VPD */
895 extern __checkReturn efx_rc_t
897 __in efx_nic_t *enp);
899 #if EFSYS_OPT_RX_SCATTER
900 extern __checkReturn efx_rc_t
901 ef10_rx_scatter_enable(
903 __in unsigned int buf_size);
904 #endif /* EFSYS_OPT_RX_SCATTER */
907 #if EFSYS_OPT_RX_SCALE
909 extern __checkReturn efx_rc_t
910 ef10_rx_scale_context_alloc(
912 __in efx_rx_scale_context_type_t type,
913 __in uint32_t num_queues,
914 __out uint32_t *rss_contextp);
916 extern __checkReturn efx_rc_t
917 ef10_rx_scale_context_free(
919 __in uint32_t rss_context);
921 extern __checkReturn efx_rc_t
922 ef10_rx_scale_mode_set(
924 __in uint32_t rss_context,
925 __in efx_rx_hash_alg_t alg,
926 __in efx_rx_hash_type_t type,
927 __in boolean_t insert);
929 extern __checkReturn efx_rc_t
930 ef10_rx_scale_key_set(
932 __in uint32_t rss_context,
933 __in_ecount(n) uint8_t *key,
936 extern __checkReturn efx_rc_t
937 ef10_rx_scale_tbl_set(
939 __in uint32_t rss_context,
940 __in_ecount(n) unsigned int *table,
943 extern __checkReturn uint32_t
946 __in efx_rx_hash_alg_t func,
947 __in uint8_t *buffer);
949 #endif /* EFSYS_OPT_RX_SCALE */
951 extern __checkReturn efx_rc_t
952 ef10_rx_prefix_pktlen(
954 __in uint8_t *buffer,
955 __out uint16_t *lengthp);
960 __in_ecount(n) efsys_dma_addr_t *addrp,
963 __in unsigned int completed,
964 __in unsigned int added);
969 __in unsigned int added,
970 __inout unsigned int *pushedp);
972 extern __checkReturn efx_rc_t
974 __in efx_rxq_t *erp);
978 __in efx_rxq_t *erp);
980 extern __checkReturn efx_rc_t
983 __in unsigned int index,
984 __in unsigned int label,
985 __in efx_rxq_type_t type,
986 __in efsys_mem_t *esmp,
990 __in efx_rxq_t *erp);
994 __in efx_rxq_t *erp);
998 __in efx_nic_t *enp);
1000 #if EFSYS_OPT_FILTER
1002 typedef struct ef10_filter_handle_s {
1005 } ef10_filter_handle_t;
1007 typedef struct ef10_filter_entry_s {
1008 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1009 ef10_filter_handle_t efe_handle;
1010 } ef10_filter_entry_t;
1013 * BUSY flag indicates that an update is in progress.
1014 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1016 #define EFX_EF10_FILTER_FLAG_BUSY 1U
1017 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
1018 #define EFX_EF10_FILTER_FLAGS 3U
1021 * Size of the hash table used by the driver. Doesn't need to be the
1022 * same size as the hardware's table.
1024 #define EFX_EF10_FILTER_TBL_ROWS 8192
1026 /* Only need to allow for one directed and one unknown unicast filter */
1027 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
1029 /* Allow for the broadcast address to be added to the multicast list */
1030 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
1033 * For encapsulated packets, there is one filter each for each combination of
1034 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1035 * multicast inner frames.
1037 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
1039 typedef struct ef10_filter_table_s {
1040 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1041 efx_rxq_t *eft_default_rxq;
1042 boolean_t eft_using_rss;
1043 uint32_t eft_unicst_filter_indexes[
1044 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1045 uint32_t eft_unicst_filter_count;
1046 uint32_t eft_mulcst_filter_indexes[
1047 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1048 uint32_t eft_mulcst_filter_count;
1049 boolean_t eft_using_all_mulcst;
1050 uint32_t eft_encap_filter_indexes[
1051 EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1052 uint32_t eft_encap_filter_count;
1053 } ef10_filter_table_t;
1055 __checkReturn efx_rc_t
1057 __in efx_nic_t *enp);
1061 __in efx_nic_t *enp);
1063 __checkReturn efx_rc_t
1064 ef10_filter_restore(
1065 __in efx_nic_t *enp);
1067 __checkReturn efx_rc_t
1069 __in efx_nic_t *enp,
1070 __inout efx_filter_spec_t *spec,
1071 __in boolean_t may_replace);
1073 __checkReturn efx_rc_t
1075 __in efx_nic_t *enp,
1076 __inout efx_filter_spec_t *spec);
1078 extern __checkReturn efx_rc_t
1079 ef10_filter_supported_filters(
1080 __in efx_nic_t *enp,
1081 __out_ecount(buffer_length) uint32_t *buffer,
1082 __in size_t buffer_length,
1083 __out size_t *list_lengthp);
1085 extern __checkReturn efx_rc_t
1086 ef10_filter_reconfigure(
1087 __in efx_nic_t *enp,
1088 __in_ecount(6) uint8_t const *mac_addr,
1089 __in boolean_t all_unicst,
1090 __in boolean_t mulcst,
1091 __in boolean_t all_mulcst,
1092 __in boolean_t brdcst,
1093 __in_ecount(6*count) uint8_t const *addrs,
1094 __in uint32_t count);
1097 ef10_filter_get_default_rxq(
1098 __in efx_nic_t *enp,
1099 __out efx_rxq_t **erpp,
1100 __out boolean_t *using_rss);
1103 ef10_filter_default_rxq_set(
1104 __in efx_nic_t *enp,
1105 __in efx_rxq_t *erp,
1106 __in boolean_t using_rss);
1109 ef10_filter_default_rxq_clear(
1110 __in efx_nic_t *enp);
1113 #endif /* EFSYS_OPT_FILTER */
1115 extern __checkReturn efx_rc_t
1116 efx_mcdi_get_function_info(
1117 __in efx_nic_t *enp,
1118 __out uint32_t *pfp,
1119 __out_opt uint32_t *vfp);
1121 extern __checkReturn efx_rc_t
1122 efx_mcdi_privilege_mask(
1123 __in efx_nic_t *enp,
1126 __out uint32_t *maskp);
1128 extern __checkReturn efx_rc_t
1129 efx_mcdi_get_port_assignment(
1130 __in efx_nic_t *enp,
1131 __out uint32_t *portp);
1133 extern __checkReturn efx_rc_t
1134 efx_mcdi_get_port_modes(
1135 __in efx_nic_t *enp,
1136 __out uint32_t *modesp,
1137 __out_opt uint32_t *current_modep);
1139 extern __checkReturn efx_rc_t
1140 ef10_nic_get_port_mode_bandwidth(
1141 __in uint32_t port_mode,
1142 __out uint32_t *bandwidth_mbpsp);
1144 extern __checkReturn efx_rc_t
1145 efx_mcdi_get_mac_address_pf(
1146 __in efx_nic_t *enp,
1147 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1149 extern __checkReturn efx_rc_t
1150 efx_mcdi_get_mac_address_vf(
1151 __in efx_nic_t *enp,
1152 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1154 extern __checkReturn efx_rc_t
1156 __in efx_nic_t *enp,
1157 __out uint32_t *sys_freqp,
1158 __out uint32_t *dpcpu_freqp);
1161 extern __checkReturn efx_rc_t
1162 efx_mcdi_get_vector_cfg(
1163 __in efx_nic_t *enp,
1164 __out_opt uint32_t *vec_basep,
1165 __out_opt uint32_t *pf_nvecp,
1166 __out_opt uint32_t *vf_nvecp);
1168 extern __checkReturn efx_rc_t
1169 ef10_get_datapath_caps(
1170 __in efx_nic_t *enp);
1172 extern __checkReturn efx_rc_t
1173 ef10_get_privilege_mask(
1174 __in efx_nic_t *enp,
1175 __out uint32_t *maskp);
1177 extern __checkReturn efx_rc_t
1178 ef10_external_port_mapping(
1179 __in efx_nic_t *enp,
1181 __out uint8_t *external_portp);
1183 #if EFSYS_OPT_RX_PACKED_STREAM
1185 /* Data space per credit in packed stream mode */
1186 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1189 * Received packets are always aligned at this boundary. Also there always
1190 * exists a gap of this size between packets.
1191 * (see SF-112241-TC, 4.5)
1193 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64
1196 * Size of a pseudo-header prepended to received packets
1197 * in packed stream mode
1199 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1201 /* Minimum space for packet in packed stream mode */
1202 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
1203 P2ROUNDUP(EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
1205 EFX_RX_PACKED_STREAM_ALIGNMENT, \
1206 EFX_RX_PACKED_STREAM_ALIGNMENT)
1208 /* Maximum number of credits */
1209 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1211 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1217 #endif /* _SYS_EF10_IMPL_H */