1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
7 #ifndef _SYS_EF10_IMPL_H
8 #define _SYS_EF10_IMPL_H
15 /* Number of hardware PIO buffers (for compile-time resource dimensions) */
16 #define EF10_MAX_PIOBUF_NBUFS (16)
18 #if EFSYS_OPT_HUNTINGTON
19 # if (EF10_MAX_PIOBUF_NBUFS < HUNT_PIOBUF_NBUFS)
20 # error "EF10_MAX_PIOBUF_NBUFS too small"
22 #endif /* EFSYS_OPT_HUNTINGTON */
24 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD_PIOBUF_NBUFS)
25 # error "EF10_MAX_PIOBUF_NBUFS too small"
27 #endif /* EFSYS_OPT_MEDFORD */
28 #if EFSYS_OPT_MEDFORD2
29 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD2_PIOBUF_NBUFS)
30 # error "EF10_MAX_PIOBUF_NBUFS too small"
32 #endif /* EFSYS_OPT_MEDFORD2 */
37 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
38 * possibly be increased, or the write size reported by newer firmware used
41 #define EF10_NVRAM_CHUNK 0x80
44 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned
45 * to an 8 descriptor boundary.
47 #define EF10_RX_WPTR_ALIGN 8
50 * Max byte offset into the packet the TCP header must start for the hardware
51 * to be able to parse the packet correctly.
53 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
55 /* Invalid RSS context handle */
56 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
61 __checkReturn efx_rc_t
69 __checkReturn efx_rc_t
72 __in unsigned int index,
73 __in efsys_mem_t *esmp,
84 __checkReturn efx_rc_t
87 __in unsigned int count);
94 __checkReturn efx_rc_t
97 __in unsigned int us);
101 ef10_ev_qstats_update(
103 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
104 #endif /* EFSYS_OPT_QSTATS */
107 ef10_ev_rxlabel_init(
110 __in unsigned int label,
111 __in efx_rxq_type_t type);
114 ef10_ev_rxlabel_fini(
116 __in unsigned int label);
120 __checkReturn efx_rc_t
123 __in efx_intr_type_t type,
124 __in efsys_mem_t *esmp);
128 __in efx_nic_t *enp);
132 __in efx_nic_t *enp);
135 ef10_intr_disable_unlocked(
136 __in efx_nic_t *enp);
138 __checkReturn efx_rc_t
141 __in unsigned int level);
144 ef10_intr_status_line(
146 __out boolean_t *fatalp,
147 __out uint32_t *qmaskp);
150 ef10_intr_status_message(
152 __in unsigned int message,
153 __out boolean_t *fatalp);
157 __in efx_nic_t *enp);
160 __in efx_nic_t *enp);
164 extern __checkReturn efx_rc_t
166 __in efx_nic_t *enp);
168 extern __checkReturn efx_rc_t
169 ef10_nic_set_drv_limits(
170 __inout efx_nic_t *enp,
171 __in efx_drv_limits_t *edlp);
173 extern __checkReturn efx_rc_t
174 ef10_nic_get_vi_pool(
176 __out uint32_t *vi_countp);
178 extern __checkReturn efx_rc_t
179 ef10_nic_get_bar_region(
181 __in efx_nic_region_t region,
182 __out uint32_t *offsetp,
183 __out size_t *sizep);
185 extern __checkReturn efx_rc_t
187 __in efx_nic_t *enp);
189 extern __checkReturn efx_rc_t
191 __in efx_nic_t *enp);
193 extern __checkReturn boolean_t
194 ef10_nic_hw_unavailable(
195 __in efx_nic_t *enp);
198 ef10_nic_set_hw_unavailable(
199 __in efx_nic_t *enp);
203 extern __checkReturn efx_rc_t
204 ef10_nic_register_test(
205 __in efx_nic_t *enp);
207 #endif /* EFSYS_OPT_DIAG */
211 __in efx_nic_t *enp);
215 __in efx_nic_t *enp);
220 extern __checkReturn efx_rc_t
223 __out efx_link_mode_t *link_modep);
225 extern __checkReturn efx_rc_t
228 __out boolean_t *mac_upp);
230 extern __checkReturn efx_rc_t
232 __in efx_nic_t *enp);
234 extern __checkReturn efx_rc_t
236 __in efx_nic_t *enp);
238 extern __checkReturn efx_rc_t
243 extern __checkReturn efx_rc_t
244 ef10_mac_reconfigure(
245 __in efx_nic_t *enp);
247 extern __checkReturn efx_rc_t
248 ef10_mac_multicast_list_set(
249 __in efx_nic_t *enp);
251 extern __checkReturn efx_rc_t
252 ef10_mac_filter_default_rxq_set(
255 __in boolean_t using_rss);
258 ef10_mac_filter_default_rxq_clear(
259 __in efx_nic_t *enp);
261 #if EFSYS_OPT_LOOPBACK
263 extern __checkReturn efx_rc_t
264 ef10_mac_loopback_set(
266 __in efx_link_mode_t link_mode,
267 __in efx_loopback_type_t loopback_type);
269 #endif /* EFSYS_OPT_LOOPBACK */
271 #if EFSYS_OPT_MAC_STATS
273 extern __checkReturn efx_rc_t
274 ef10_mac_stats_get_mask(
276 __inout_bcount(mask_size) uint32_t *maskp,
277 __in size_t mask_size);
279 extern __checkReturn efx_rc_t
280 ef10_mac_stats_update(
282 __in efsys_mem_t *esmp,
283 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
284 __inout_opt uint32_t *generationp);
286 #endif /* EFSYS_OPT_MAC_STATS */
293 extern __checkReturn efx_rc_t
296 __in const efx_mcdi_transport_t *mtp);
300 __in efx_nic_t *enp);
303 ef10_mcdi_send_request(
305 __in_bcount(hdr_len) void *hdrp,
307 __in_bcount(sdu_len) void *sdup,
308 __in size_t sdu_len);
310 extern __checkReturn boolean_t
311 ef10_mcdi_poll_response(
312 __in efx_nic_t *enp);
315 ef10_mcdi_read_response(
317 __out_bcount(length) void *bufferp,
322 ef10_mcdi_poll_reboot(
323 __in efx_nic_t *enp);
325 extern __checkReturn efx_rc_t
326 ef10_mcdi_feature_supported(
328 __in efx_mcdi_feature_id_t id,
329 __out boolean_t *supportedp);
332 ef10_mcdi_get_timeout(
334 __in efx_mcdi_req_t *emrp,
335 __out uint32_t *timeoutp);
337 #endif /* EFSYS_OPT_MCDI */
341 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
343 extern __checkReturn efx_rc_t
344 ef10_nvram_buf_read_tlv(
346 __in_bcount(max_seg_size) caddr_t seg_data,
347 __in size_t max_seg_size,
349 __deref_out_bcount_opt(*sizep) caddr_t *datap,
350 __out size_t *sizep);
352 extern __checkReturn efx_rc_t
353 ef10_nvram_buf_write_tlv(
354 __inout_bcount(partn_size) caddr_t partn_data,
355 __in size_t partn_size,
357 __in_bcount(tag_size) caddr_t tag_data,
358 __in size_t tag_size,
359 __out size_t *total_lengthp);
361 extern __checkReturn efx_rc_t
362 ef10_nvram_partn_read_tlv(
366 __deref_out_bcount_opt(*sizep) caddr_t *datap,
367 __out size_t *sizep);
369 extern __checkReturn efx_rc_t
370 ef10_nvram_partn_write_tlv(
374 __in_bcount(size) caddr_t data,
377 extern __checkReturn efx_rc_t
378 ef10_nvram_partn_write_segment_tlv(
382 __in_bcount(size) caddr_t data,
384 __in boolean_t all_segments);
386 extern __checkReturn efx_rc_t
387 ef10_nvram_partn_lock(
389 __in uint32_t partn);
391 extern __checkReturn efx_rc_t
392 ef10_nvram_partn_unlock(
395 __out_opt uint32_t *resultp);
397 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
403 extern __checkReturn efx_rc_t
405 __in efx_nic_t *enp);
407 #endif /* EFSYS_OPT_DIAG */
409 extern __checkReturn efx_rc_t
410 ef10_nvram_type_to_partn(
412 __in efx_nvram_type_t type,
413 __out uint32_t *partnp);
415 extern __checkReturn efx_rc_t
416 ef10_nvram_partn_size(
419 __out size_t *sizep);
421 extern __checkReturn efx_rc_t
422 ef10_nvram_partn_rw_start(
425 __out size_t *chunk_sizep);
427 extern __checkReturn efx_rc_t
428 ef10_nvram_partn_read_mode(
431 __in unsigned int offset,
432 __out_bcount(size) caddr_t data,
436 extern __checkReturn efx_rc_t
437 ef10_nvram_partn_read(
440 __in unsigned int offset,
441 __out_bcount(size) caddr_t data,
444 extern __checkReturn efx_rc_t
445 ef10_nvram_partn_read_backup(
448 __in unsigned int offset,
449 __out_bcount(size) caddr_t data,
452 extern __checkReturn efx_rc_t
453 ef10_nvram_partn_erase(
456 __in unsigned int offset,
459 extern __checkReturn efx_rc_t
460 ef10_nvram_partn_write(
463 __in unsigned int offset,
464 __in_bcount(size) caddr_t data,
467 extern __checkReturn efx_rc_t
468 ef10_nvram_partn_rw_finish(
471 __out_opt uint32_t *verify_resultp);
473 extern __checkReturn efx_rc_t
474 ef10_nvram_partn_get_version(
477 __out uint32_t *subtypep,
478 __out_ecount(4) uint16_t version[4]);
480 extern __checkReturn efx_rc_t
481 ef10_nvram_partn_set_version(
484 __in_ecount(4) uint16_t version[4]);
486 extern __checkReturn efx_rc_t
487 ef10_nvram_buffer_validate(
489 __in_bcount(buffer_size)
491 __in size_t buffer_size);
494 ef10_nvram_buffer_init(
495 __out_bcount(buffer_size)
497 __in size_t buffer_size);
499 extern __checkReturn efx_rc_t
500 ef10_nvram_buffer_create(
501 __in uint32_t partn_type,
502 __out_bcount(buffer_size)
504 __in size_t buffer_size);
506 extern __checkReturn efx_rc_t
507 ef10_nvram_buffer_find_item_start(
508 __in_bcount(buffer_size)
510 __in size_t buffer_size,
511 __out uint32_t *startp);
513 extern __checkReturn efx_rc_t
514 ef10_nvram_buffer_find_end(
515 __in_bcount(buffer_size)
517 __in size_t buffer_size,
518 __in uint32_t offset,
519 __out uint32_t *endp);
521 extern __checkReturn __success(return != B_FALSE) boolean_t
522 ef10_nvram_buffer_find_item(
523 __in_bcount(buffer_size)
525 __in size_t buffer_size,
526 __in uint32_t offset,
527 __out uint32_t *startp,
528 __out uint32_t *lengthp);
530 extern __checkReturn efx_rc_t
531 ef10_nvram_buffer_peek_item(
532 __in_bcount(buffer_size)
534 __in size_t buffer_size,
535 __in uint32_t offset,
536 __out uint32_t *tagp,
537 __out uint32_t *lengthp,
538 __out uint32_t *value_offsetp);
540 extern __checkReturn efx_rc_t
541 ef10_nvram_buffer_get_item(
542 __in_bcount(buffer_size)
544 __in size_t buffer_size,
545 __in uint32_t offset,
546 __in uint32_t length,
547 __out uint32_t *tagp,
548 __out_bcount_part(value_max_size, *lengthp)
550 __in size_t value_max_size,
551 __out uint32_t *lengthp);
553 extern __checkReturn efx_rc_t
554 ef10_nvram_buffer_insert_item(
555 __in_bcount(buffer_size)
557 __in size_t buffer_size,
558 __in uint32_t offset,
560 __in_bcount(length) caddr_t valuep,
561 __in uint32_t length,
562 __out uint32_t *lengthp);
564 extern __checkReturn efx_rc_t
565 ef10_nvram_buffer_modify_item(
566 __in_bcount(buffer_size)
568 __in size_t buffer_size,
569 __in uint32_t offset,
571 __in_bcount(length) caddr_t valuep,
572 __in uint32_t length,
573 __out uint32_t *lengthp);
575 extern __checkReturn efx_rc_t
576 ef10_nvram_buffer_delete_item(
577 __in_bcount(buffer_size)
579 __in size_t buffer_size,
580 __in uint32_t offset,
581 __in uint32_t length,
584 extern __checkReturn efx_rc_t
585 ef10_nvram_buffer_finish(
586 __in_bcount(buffer_size)
588 __in size_t buffer_size);
590 #endif /* EFSYS_OPT_NVRAM */
595 typedef struct ef10_link_state_s {
596 uint32_t els_adv_cap_mask;
597 uint32_t els_lp_cap_mask;
598 unsigned int els_fcntl;
599 efx_phy_fec_type_t els_fec;
600 efx_link_mode_t els_link_mode;
601 #if EFSYS_OPT_LOOPBACK
602 efx_loopback_type_t els_loopback;
604 boolean_t els_mac_up;
610 __in efx_qword_t *eqp,
611 __out efx_link_mode_t *link_modep);
613 extern __checkReturn efx_rc_t
616 __out ef10_link_state_t *elsp);
618 extern __checkReturn efx_rc_t
623 extern __checkReturn efx_rc_t
624 ef10_phy_reconfigure(
625 __in efx_nic_t *enp);
627 extern __checkReturn efx_rc_t
629 __in efx_nic_t *enp);
631 extern __checkReturn efx_rc_t
634 __out uint32_t *ouip);
636 extern __checkReturn efx_rc_t
637 ef10_phy_fec_type_get(
639 __out efx_phy_fec_type_t *fecp);
641 #if EFSYS_OPT_PHY_STATS
643 extern __checkReturn efx_rc_t
644 ef10_phy_stats_update(
646 __in efsys_mem_t *esmp,
647 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
649 #endif /* EFSYS_OPT_PHY_STATS */
653 extern __checkReturn efx_rc_t
654 ef10_bist_enable_offline(
655 __in efx_nic_t *enp);
657 extern __checkReturn efx_rc_t
660 __in efx_bist_type_t type);
662 extern __checkReturn efx_rc_t
665 __in efx_bist_type_t type,
666 __out efx_bist_result_t *resultp,
667 __out_opt __drv_when(count > 0, __notnull)
668 uint32_t *value_maskp,
669 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
670 unsigned long *valuesp,
676 __in efx_bist_type_t type);
678 #endif /* EFSYS_OPT_BIST */
682 extern __checkReturn efx_rc_t
684 __in efx_nic_t *enp);
688 __in efx_nic_t *enp);
690 extern __checkReturn efx_rc_t
693 __in unsigned int index,
694 __in unsigned int label,
695 __in efsys_mem_t *esmp,
701 __out unsigned int *addedp);
705 __in efx_txq_t *etp);
707 extern __checkReturn efx_rc_t
710 __in_ecount(ndescs) efx_buffer_t *ebp,
711 __in unsigned int ndescs,
712 __in unsigned int completed,
713 __inout unsigned int *addedp);
718 __in unsigned int added,
719 __in unsigned int pushed);
721 #if EFSYS_OPT_RX_PACKED_STREAM
723 ef10_rx_qpush_ps_credits(
724 __in efx_rxq_t *erp);
726 extern __checkReturn uint8_t *
727 ef10_rx_qps_packet_info(
729 __in uint8_t *buffer,
730 __in uint32_t buffer_length,
731 __in uint32_t current_offset,
732 __out uint16_t *lengthp,
733 __out uint32_t *next_offsetp,
734 __out uint32_t *timestamp);
737 extern __checkReturn efx_rc_t
740 __in unsigned int ns);
742 extern __checkReturn efx_rc_t
744 __in efx_txq_t *etp);
748 __in efx_txq_t *etp);
750 extern __checkReturn efx_rc_t
752 __in efx_txq_t *etp);
755 ef10_tx_qpio_disable(
756 __in efx_txq_t *etp);
758 extern __checkReturn efx_rc_t
761 __in_ecount(buf_length) uint8_t *buffer,
762 __in size_t buf_length,
763 __in size_t pio_buf_offset);
765 extern __checkReturn efx_rc_t
768 __in size_t pkt_length,
769 __in unsigned int completed,
770 __inout unsigned int *addedp);
772 extern __checkReturn efx_rc_t
775 __in_ecount(n) efx_desc_t *ed,
777 __in unsigned int completed,
778 __inout unsigned int *addedp);
781 ef10_tx_qdesc_dma_create(
783 __in efsys_dma_addr_t addr,
786 __out efx_desc_t *edp);
789 ef10_tx_qdesc_tso_create(
791 __in uint16_t ipv4_id,
792 __in uint32_t tcp_seq,
793 __in uint8_t tcp_flags,
794 __out efx_desc_t *edp);
797 ef10_tx_qdesc_tso2_create(
799 __in uint16_t ipv4_id,
800 __in uint16_t outer_ipv4_id,
801 __in uint32_t tcp_seq,
802 __in uint16_t tcp_mss,
803 __out_ecount(count) efx_desc_t *edp,
807 ef10_tx_qdesc_vlantci_create(
809 __in uint16_t vlan_tci,
810 __out efx_desc_t *edp);
813 ef10_tx_qdesc_checksum_create(
816 __out efx_desc_t *edp);
821 ef10_tx_qstats_update(
823 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
825 #endif /* EFSYS_OPT_QSTATS */
827 typedef uint32_t efx_piobuf_handle_t;
829 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1)
831 extern __checkReturn efx_rc_t
833 __inout efx_nic_t *enp,
834 __out uint32_t *bufnump,
835 __out efx_piobuf_handle_t *handlep,
836 __out uint32_t *blknump,
837 __out uint32_t *offsetp,
838 __out size_t *sizep);
840 extern __checkReturn efx_rc_t
842 __inout efx_nic_t *enp,
843 __in uint32_t bufnum,
844 __in uint32_t blknum);
846 extern __checkReturn efx_rc_t
848 __inout efx_nic_t *enp,
849 __in uint32_t vi_index,
850 __in efx_piobuf_handle_t handle);
852 extern __checkReturn efx_rc_t
854 __inout efx_nic_t *enp,
855 __in uint32_t vi_index);
862 extern __checkReturn efx_rc_t
864 __in efx_nic_t *enp);
866 extern __checkReturn efx_rc_t
869 __out size_t *sizep);
871 extern __checkReturn efx_rc_t
874 __out_bcount(size) caddr_t data,
877 extern __checkReturn efx_rc_t
880 __in_bcount(size) caddr_t data,
883 extern __checkReturn efx_rc_t
886 __in_bcount(size) caddr_t data,
889 extern __checkReturn efx_rc_t
892 __in_bcount(size) caddr_t data,
894 __inout efx_vpd_value_t *evvp);
896 extern __checkReturn efx_rc_t
899 __in_bcount(size) caddr_t data,
901 __in efx_vpd_value_t *evvp);
903 extern __checkReturn efx_rc_t
906 __in_bcount(size) caddr_t data,
908 __out efx_vpd_value_t *evvp,
909 __inout unsigned int *contp);
911 extern __checkReturn efx_rc_t
914 __in_bcount(size) caddr_t data,
919 __in efx_nic_t *enp);
921 #endif /* EFSYS_OPT_VPD */
926 extern __checkReturn efx_rc_t
928 __in efx_nic_t *enp);
930 #if EFSYS_OPT_RX_SCATTER
931 extern __checkReturn efx_rc_t
932 ef10_rx_scatter_enable(
934 __in unsigned int buf_size);
935 #endif /* EFSYS_OPT_RX_SCATTER */
938 #if EFSYS_OPT_RX_SCALE
940 extern __checkReturn efx_rc_t
941 ef10_rx_scale_context_alloc(
943 __in efx_rx_scale_context_type_t type,
944 __in uint32_t num_queues,
945 __out uint32_t *rss_contextp);
947 extern __checkReturn efx_rc_t
948 ef10_rx_scale_context_free(
950 __in uint32_t rss_context);
952 extern __checkReturn efx_rc_t
953 ef10_rx_scale_mode_set(
955 __in uint32_t rss_context,
956 __in efx_rx_hash_alg_t alg,
957 __in efx_rx_hash_type_t type,
958 __in boolean_t insert);
960 extern __checkReturn efx_rc_t
961 ef10_rx_scale_key_set(
963 __in uint32_t rss_context,
964 __in_ecount(n) uint8_t *key,
967 extern __checkReturn efx_rc_t
968 ef10_rx_scale_tbl_set(
970 __in uint32_t rss_context,
971 __in_ecount(n) unsigned int *table,
974 extern __checkReturn uint32_t
977 __in efx_rx_hash_alg_t func,
978 __in uint8_t *buffer);
980 #endif /* EFSYS_OPT_RX_SCALE */
982 extern __checkReturn efx_rc_t
983 ef10_rx_prefix_pktlen(
985 __in uint8_t *buffer,
986 __out uint16_t *lengthp);
991 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
993 __in unsigned int ndescs,
994 __in unsigned int completed,
995 __in unsigned int added);
1000 __in unsigned int added,
1001 __inout unsigned int *pushedp);
1003 extern __checkReturn efx_rc_t
1005 __in efx_rxq_t *erp);
1009 __in efx_rxq_t *erp);
1011 union efx_rxq_type_data_u;
1013 extern __checkReturn efx_rc_t
1015 __in efx_nic_t *enp,
1016 __in unsigned int index,
1017 __in unsigned int label,
1018 __in efx_rxq_type_t type,
1019 __in const union efx_rxq_type_data_u *type_data,
1020 __in efsys_mem_t *esmp,
1023 __in unsigned int flags,
1024 __in efx_evq_t *eep,
1025 __in efx_rxq_t *erp);
1029 __in efx_rxq_t *erp);
1033 __in efx_nic_t *enp);
1035 #if EFSYS_OPT_FILTER
1037 typedef struct ef10_filter_handle_s {
1040 } ef10_filter_handle_t;
1042 typedef struct ef10_filter_entry_s {
1043 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1044 ef10_filter_handle_t efe_handle;
1045 } ef10_filter_entry_t;
1048 * BUSY flag indicates that an update is in progress.
1049 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1051 #define EFX_EF10_FILTER_FLAG_BUSY 1U
1052 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
1053 #define EFX_EF10_FILTER_FLAGS 3U
1056 * Size of the hash table used by the driver. Doesn't need to be the
1057 * same size as the hardware's table.
1059 #define EFX_EF10_FILTER_TBL_ROWS 8192
1061 /* Only need to allow for one directed and one unknown unicast filter */
1062 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
1064 /* Allow for the broadcast address to be added to the multicast list */
1065 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
1068 * For encapsulated packets, there is one filter each for each combination of
1069 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1070 * multicast inner frames.
1072 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
1074 typedef struct ef10_filter_table_s {
1075 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1076 efx_rxq_t *eft_default_rxq;
1077 boolean_t eft_using_rss;
1078 uint32_t eft_unicst_filter_indexes[
1079 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1080 uint32_t eft_unicst_filter_count;
1081 uint32_t eft_mulcst_filter_indexes[
1082 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1083 uint32_t eft_mulcst_filter_count;
1084 boolean_t eft_using_all_mulcst;
1085 uint32_t eft_encap_filter_indexes[
1086 EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1087 uint32_t eft_encap_filter_count;
1088 } ef10_filter_table_t;
1090 __checkReturn efx_rc_t
1092 __in efx_nic_t *enp);
1096 __in efx_nic_t *enp);
1098 __checkReturn efx_rc_t
1099 ef10_filter_restore(
1100 __in efx_nic_t *enp);
1102 __checkReturn efx_rc_t
1104 __in efx_nic_t *enp,
1105 __inout efx_filter_spec_t *spec,
1106 __in boolean_t may_replace);
1108 __checkReturn efx_rc_t
1110 __in efx_nic_t *enp,
1111 __inout efx_filter_spec_t *spec);
1113 extern __checkReturn efx_rc_t
1114 ef10_filter_supported_filters(
1115 __in efx_nic_t *enp,
1116 __out_ecount(buffer_length) uint32_t *buffer,
1117 __in size_t buffer_length,
1118 __out size_t *list_lengthp);
1120 extern __checkReturn efx_rc_t
1121 ef10_filter_reconfigure(
1122 __in efx_nic_t *enp,
1123 __in_ecount(6) uint8_t const *mac_addr,
1124 __in boolean_t all_unicst,
1125 __in boolean_t mulcst,
1126 __in boolean_t all_mulcst,
1127 __in boolean_t brdcst,
1128 __in_ecount(6*count) uint8_t const *addrs,
1129 __in uint32_t count);
1132 ef10_filter_get_default_rxq(
1133 __in efx_nic_t *enp,
1134 __out efx_rxq_t **erpp,
1135 __out boolean_t *using_rss);
1138 ef10_filter_default_rxq_set(
1139 __in efx_nic_t *enp,
1140 __in efx_rxq_t *erp,
1141 __in boolean_t using_rss);
1144 ef10_filter_default_rxq_clear(
1145 __in efx_nic_t *enp);
1148 #endif /* EFSYS_OPT_FILTER */
1150 extern __checkReturn efx_rc_t
1151 efx_mcdi_get_function_info(
1152 __in efx_nic_t *enp,
1153 __out uint32_t *pfp,
1154 __out_opt uint32_t *vfp);
1156 extern __checkReturn efx_rc_t
1157 efx_mcdi_privilege_mask(
1158 __in efx_nic_t *enp,
1161 __out uint32_t *maskp);
1163 extern __checkReturn efx_rc_t
1164 efx_mcdi_get_port_assignment(
1165 __in efx_nic_t *enp,
1166 __out uint32_t *portp);
1168 extern __checkReturn efx_rc_t
1169 efx_mcdi_get_port_modes(
1170 __in efx_nic_t *enp,
1171 __out uint32_t *modesp,
1172 __out_opt uint32_t *current_modep,
1173 __out_opt uint32_t *default_modep);
1175 extern __checkReturn efx_rc_t
1176 ef10_nic_get_port_mode_bandwidth(
1177 __in uint32_t port_mode,
1178 __out uint32_t *bandwidth_mbpsp);
1180 extern __checkReturn efx_rc_t
1181 efx_mcdi_get_mac_address_pf(
1182 __in efx_nic_t *enp,
1183 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1185 extern __checkReturn efx_rc_t
1186 efx_mcdi_get_mac_address_vf(
1187 __in efx_nic_t *enp,
1188 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1190 extern __checkReturn efx_rc_t
1192 __in efx_nic_t *enp,
1193 __out uint32_t *sys_freqp,
1194 __out uint32_t *dpcpu_freqp);
1197 extern __checkReturn efx_rc_t
1198 efx_mcdi_get_rxdp_config(
1199 __in efx_nic_t *enp,
1200 __out uint32_t *end_paddingp);
1202 extern __checkReturn efx_rc_t
1203 efx_mcdi_get_vector_cfg(
1204 __in efx_nic_t *enp,
1205 __out_opt uint32_t *vec_basep,
1206 __out_opt uint32_t *pf_nvecp,
1207 __out_opt uint32_t *vf_nvecp);
1209 extern __checkReturn efx_rc_t
1210 ef10_get_privilege_mask(
1211 __in efx_nic_t *enp,
1212 __out uint32_t *maskp);
1214 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1216 extern __checkReturn efx_rc_t
1217 efx_mcdi_get_nic_global(
1218 __in efx_nic_t *enp,
1220 __out uint32_t *valuep);
1222 extern __checkReturn efx_rc_t
1223 efx_mcdi_set_nic_global(
1224 __in efx_nic_t *enp,
1226 __in uint32_t value);
1228 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1231 #if EFSYS_OPT_RX_PACKED_STREAM
1233 /* Data space per credit in packed stream mode */
1234 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1237 * Received packets are always aligned at this boundary. Also there always
1238 * exists a gap of this size between packets.
1239 * (see SF-112241-TC, 4.5)
1241 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64
1244 * Size of a pseudo-header prepended to received packets
1245 * in packed stream mode
1247 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1249 /* Minimum space for packet in packed stream mode */
1250 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
1251 P2ROUNDUP(EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
1253 EFX_RX_PACKED_STREAM_ALIGNMENT, \
1254 EFX_RX_PACKED_STREAM_ALIGNMENT)
1256 /* Maximum number of credits */
1257 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1259 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1261 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1264 * Maximum DMA length and buffer stride alignment.
1265 * (see SF-119419-TC, 3.2)
1267 #define EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT 64
1275 #endif /* _SYS_EF10_IMPL_H */