1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
7 #ifndef _SYS_EF10_IMPL_H
8 #define _SYS_EF10_IMPL_H
14 #if (EFSYS_OPT_HUNTINGTON && EFSYS_OPT_MEDFORD)
15 #define EF10_MAX_PIOBUF_NBUFS MAX(HUNT_PIOBUF_NBUFS, MEDFORD_PIOBUF_NBUFS)
16 #elif EFSYS_OPT_HUNTINGTON
17 #define EF10_MAX_PIOBUF_NBUFS HUNT_PIOBUF_NBUFS
18 #elif EFSYS_OPT_MEDFORD
19 #define EF10_MAX_PIOBUF_NBUFS MEDFORD_PIOBUF_NBUFS
23 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
24 * possibly be increased, or the write size reported by newer firmware used
27 #define EF10_NVRAM_CHUNK 0x80
30 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned
31 * to an 8 descriptor boundary.
33 #define EF10_RX_WPTR_ALIGN 8
36 * Max byte offset into the packet the TCP header must start for the hardware
37 * to be able to parse the packet correctly.
39 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
41 /* Invalid RSS context handle */
42 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
47 __checkReturn efx_rc_t
55 __checkReturn efx_rc_t
58 __in unsigned int index,
59 __in efsys_mem_t *esmp,
70 __checkReturn efx_rc_t
73 __in unsigned int count);
80 __checkReturn efx_rc_t
83 __in unsigned int us);
87 ef10_ev_qstats_update(
89 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
90 #endif /* EFSYS_OPT_QSTATS */
96 __in unsigned int label,
97 __in efx_rxq_type_t type);
100 ef10_ev_rxlabel_fini(
102 __in unsigned int label);
106 __checkReturn efx_rc_t
109 __in efx_intr_type_t type,
110 __in efsys_mem_t *esmp);
114 __in efx_nic_t *enp);
118 __in efx_nic_t *enp);
121 ef10_intr_disable_unlocked(
122 __in efx_nic_t *enp);
124 __checkReturn efx_rc_t
127 __in unsigned int level);
130 ef10_intr_status_line(
132 __out boolean_t *fatalp,
133 __out uint32_t *qmaskp);
136 ef10_intr_status_message(
138 __in unsigned int message,
139 __out boolean_t *fatalp);
143 __in efx_nic_t *enp);
146 __in efx_nic_t *enp);
150 extern __checkReturn efx_rc_t
152 __in efx_nic_t *enp);
154 extern __checkReturn efx_rc_t
155 ef10_nic_set_drv_limits(
156 __inout efx_nic_t *enp,
157 __in efx_drv_limits_t *edlp);
159 extern __checkReturn efx_rc_t
160 ef10_nic_get_vi_pool(
162 __out uint32_t *vi_countp);
164 extern __checkReturn efx_rc_t
165 ef10_nic_get_bar_region(
167 __in efx_nic_region_t region,
168 __out uint32_t *offsetp,
169 __out size_t *sizep);
171 extern __checkReturn efx_rc_t
173 __in efx_nic_t *enp);
175 extern __checkReturn efx_rc_t
177 __in efx_nic_t *enp);
181 extern __checkReturn efx_rc_t
182 ef10_nic_register_test(
183 __in efx_nic_t *enp);
185 #endif /* EFSYS_OPT_DIAG */
189 __in efx_nic_t *enp);
193 __in efx_nic_t *enp);
198 extern __checkReturn efx_rc_t
201 __out efx_link_mode_t *link_modep);
203 extern __checkReturn efx_rc_t
206 __out boolean_t *mac_upp);
208 extern __checkReturn efx_rc_t
210 __in efx_nic_t *enp);
212 extern __checkReturn efx_rc_t
214 __in efx_nic_t *enp);
216 extern __checkReturn efx_rc_t
221 extern __checkReturn efx_rc_t
222 ef10_mac_reconfigure(
223 __in efx_nic_t *enp);
225 extern __checkReturn efx_rc_t
226 ef10_mac_multicast_list_set(
227 __in efx_nic_t *enp);
229 extern __checkReturn efx_rc_t
230 ef10_mac_filter_default_rxq_set(
233 __in boolean_t using_rss);
236 ef10_mac_filter_default_rxq_clear(
237 __in efx_nic_t *enp);
239 #if EFSYS_OPT_LOOPBACK
241 extern __checkReturn efx_rc_t
242 ef10_mac_loopback_set(
244 __in efx_link_mode_t link_mode,
245 __in efx_loopback_type_t loopback_type);
247 #endif /* EFSYS_OPT_LOOPBACK */
249 #if EFSYS_OPT_MAC_STATS
251 extern __checkReturn efx_rc_t
252 ef10_mac_stats_get_mask(
254 __inout_bcount(mask_size) uint32_t *maskp,
255 __in size_t mask_size);
257 extern __checkReturn efx_rc_t
258 ef10_mac_stats_update(
260 __in efsys_mem_t *esmp,
261 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
262 __inout_opt uint32_t *generationp);
264 #endif /* EFSYS_OPT_MAC_STATS */
271 extern __checkReturn efx_rc_t
274 __in const efx_mcdi_transport_t *mtp);
278 __in efx_nic_t *enp);
281 ef10_mcdi_send_request(
283 __in_bcount(hdr_len) void *hdrp,
285 __in_bcount(sdu_len) void *sdup,
286 __in size_t sdu_len);
288 extern __checkReturn boolean_t
289 ef10_mcdi_poll_response(
290 __in efx_nic_t *enp);
293 ef10_mcdi_read_response(
295 __out_bcount(length) void *bufferp,
300 ef10_mcdi_poll_reboot(
301 __in efx_nic_t *enp);
303 extern __checkReturn efx_rc_t
304 ef10_mcdi_feature_supported(
306 __in efx_mcdi_feature_id_t id,
307 __out boolean_t *supportedp);
310 ef10_mcdi_get_timeout(
312 __in efx_mcdi_req_t *emrp,
313 __out uint32_t *timeoutp);
315 #endif /* EFSYS_OPT_MCDI */
319 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
321 extern __checkReturn efx_rc_t
322 ef10_nvram_buf_read_tlv(
324 __in_bcount(max_seg_size) caddr_t seg_data,
325 __in size_t max_seg_size,
327 __deref_out_bcount_opt(*sizep) caddr_t *datap,
328 __out size_t *sizep);
330 extern __checkReturn efx_rc_t
331 ef10_nvram_buf_write_tlv(
332 __inout_bcount(partn_size) caddr_t partn_data,
333 __in size_t partn_size,
335 __in_bcount(tag_size) caddr_t tag_data,
336 __in size_t tag_size,
337 __out size_t *total_lengthp);
339 extern __checkReturn efx_rc_t
340 ef10_nvram_partn_read_tlv(
344 __deref_out_bcount_opt(*sizep) caddr_t *datap,
345 __out size_t *sizep);
347 extern __checkReturn efx_rc_t
348 ef10_nvram_partn_write_tlv(
352 __in_bcount(size) caddr_t data,
355 extern __checkReturn efx_rc_t
356 ef10_nvram_partn_write_segment_tlv(
360 __in_bcount(size) caddr_t data,
362 __in boolean_t all_segments);
364 extern __checkReturn efx_rc_t
365 ef10_nvram_partn_lock(
367 __in uint32_t partn);
369 extern __checkReturn efx_rc_t
370 ef10_nvram_partn_unlock(
373 __out_opt uint32_t *resultp);
375 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
381 extern __checkReturn efx_rc_t
383 __in efx_nic_t *enp);
385 #endif /* EFSYS_OPT_DIAG */
387 extern __checkReturn efx_rc_t
388 ef10_nvram_type_to_partn(
390 __in efx_nvram_type_t type,
391 __out uint32_t *partnp);
393 extern __checkReturn efx_rc_t
394 ef10_nvram_partn_size(
397 __out size_t *sizep);
399 extern __checkReturn efx_rc_t
400 ef10_nvram_partn_rw_start(
403 __out size_t *chunk_sizep);
405 extern __checkReturn efx_rc_t
406 ef10_nvram_partn_read_mode(
409 __in unsigned int offset,
410 __out_bcount(size) caddr_t data,
414 extern __checkReturn efx_rc_t
415 ef10_nvram_partn_read(
418 __in unsigned int offset,
419 __out_bcount(size) caddr_t data,
422 extern __checkReturn efx_rc_t
423 ef10_nvram_partn_read_backup(
426 __in unsigned int offset,
427 __out_bcount(size) caddr_t data,
430 extern __checkReturn efx_rc_t
431 ef10_nvram_partn_erase(
434 __in unsigned int offset,
437 extern __checkReturn efx_rc_t
438 ef10_nvram_partn_write(
441 __in unsigned int offset,
442 __out_bcount(size) caddr_t data,
445 extern __checkReturn efx_rc_t
446 ef10_nvram_partn_rw_finish(
449 __out_opt uint32_t *verify_resultp);
451 extern __checkReturn efx_rc_t
452 ef10_nvram_partn_get_version(
455 __out uint32_t *subtypep,
456 __out_ecount(4) uint16_t version[4]);
458 extern __checkReturn efx_rc_t
459 ef10_nvram_partn_set_version(
462 __in_ecount(4) uint16_t version[4]);
464 extern __checkReturn efx_rc_t
465 ef10_nvram_buffer_validate(
468 __in_bcount(buffer_size)
470 __in size_t buffer_size);
472 extern __checkReturn efx_rc_t
473 ef10_nvram_buffer_create(
475 __in uint16_t partn_type,
476 __in_bcount(buffer_size)
478 __in size_t buffer_size);
480 extern __checkReturn efx_rc_t
481 ef10_nvram_buffer_find_item_start(
482 __in_bcount(buffer_size)
484 __in size_t buffer_size,
485 __out uint32_t *startp);
487 extern __checkReturn efx_rc_t
488 ef10_nvram_buffer_find_end(
489 __in_bcount(buffer_size)
491 __in size_t buffer_size,
492 __in uint32_t offset,
493 __out uint32_t *endp);
495 extern __checkReturn __success(return != B_FALSE) boolean_t
496 ef10_nvram_buffer_find_item(
497 __in_bcount(buffer_size)
499 __in size_t buffer_size,
500 __in uint32_t offset,
501 __out uint32_t *startp,
502 __out uint32_t *lengthp);
504 extern __checkReturn efx_rc_t
505 ef10_nvram_buffer_get_item(
506 __in_bcount(buffer_size)
508 __in size_t buffer_size,
509 __in uint32_t offset,
510 __in uint32_t length,
511 __out_bcount_part(item_max_size, *lengthp)
513 __in size_t item_max_size,
514 __out uint32_t *lengthp);
516 extern __checkReturn efx_rc_t
517 ef10_nvram_buffer_insert_item(
518 __in_bcount(buffer_size)
520 __in size_t buffer_size,
521 __in uint32_t offset,
522 __in_bcount(length) caddr_t keyp,
523 __in uint32_t length,
524 __out uint32_t *lengthp);
526 extern __checkReturn efx_rc_t
527 ef10_nvram_buffer_delete_item(
528 __in_bcount(buffer_size)
530 __in size_t buffer_size,
531 __in uint32_t offset,
532 __in uint32_t length,
535 extern __checkReturn efx_rc_t
536 ef10_nvram_buffer_finish(
537 __in_bcount(buffer_size)
539 __in size_t buffer_size);
541 #endif /* EFSYS_OPT_NVRAM */
546 typedef struct ef10_link_state_s {
547 uint32_t els_adv_cap_mask;
548 uint32_t els_lp_cap_mask;
549 unsigned int els_fcntl;
550 efx_link_mode_t els_link_mode;
551 #if EFSYS_OPT_LOOPBACK
552 efx_loopback_type_t els_loopback;
554 boolean_t els_mac_up;
560 __in efx_qword_t *eqp,
561 __out efx_link_mode_t *link_modep);
563 extern __checkReturn efx_rc_t
566 __out ef10_link_state_t *elsp);
568 extern __checkReturn efx_rc_t
573 extern __checkReturn efx_rc_t
574 ef10_phy_reconfigure(
575 __in efx_nic_t *enp);
577 extern __checkReturn efx_rc_t
579 __in efx_nic_t *enp);
581 extern __checkReturn efx_rc_t
584 __out uint32_t *ouip);
586 #if EFSYS_OPT_PHY_STATS
588 extern __checkReturn efx_rc_t
589 ef10_phy_stats_update(
591 __in efsys_mem_t *esmp,
592 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
594 #endif /* EFSYS_OPT_PHY_STATS */
598 extern __checkReturn efx_rc_t
599 ef10_bist_enable_offline(
600 __in efx_nic_t *enp);
602 extern __checkReturn efx_rc_t
605 __in efx_bist_type_t type);
607 extern __checkReturn efx_rc_t
610 __in efx_bist_type_t type,
611 __out efx_bist_result_t *resultp,
612 __out_opt __drv_when(count > 0, __notnull)
613 uint32_t *value_maskp,
614 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
615 unsigned long *valuesp,
621 __in efx_bist_type_t type);
623 #endif /* EFSYS_OPT_BIST */
627 extern __checkReturn efx_rc_t
629 __in efx_nic_t *enp);
633 __in efx_nic_t *enp);
635 extern __checkReturn efx_rc_t
638 __in unsigned int index,
639 __in unsigned int label,
640 __in efsys_mem_t *esmp,
646 __out unsigned int *addedp);
650 __in efx_txq_t *etp);
652 extern __checkReturn efx_rc_t
655 __in_ecount(ndescs) efx_buffer_t *ebp,
656 __in unsigned int ndescs,
657 __in unsigned int completed,
658 __inout unsigned int *addedp);
663 __in unsigned int added,
664 __in unsigned int pushed);
666 #if EFSYS_OPT_RX_PACKED_STREAM
668 ef10_rx_qpush_ps_credits(
669 __in efx_rxq_t *erp);
671 extern __checkReturn uint8_t *
672 ef10_rx_qps_packet_info(
674 __in uint8_t *buffer,
675 __in uint32_t buffer_length,
676 __in uint32_t current_offset,
677 __out uint16_t *lengthp,
678 __out uint32_t *next_offsetp,
679 __out uint32_t *timestamp);
682 extern __checkReturn efx_rc_t
685 __in unsigned int ns);
687 extern __checkReturn efx_rc_t
689 __in efx_txq_t *etp);
693 __in efx_txq_t *etp);
695 extern __checkReturn efx_rc_t
697 __in efx_txq_t *etp);
700 ef10_tx_qpio_disable(
701 __in efx_txq_t *etp);
703 extern __checkReturn efx_rc_t
706 __in_ecount(buf_length) uint8_t *buffer,
707 __in size_t buf_length,
708 __in size_t pio_buf_offset);
710 extern __checkReturn efx_rc_t
713 __in size_t pkt_length,
714 __in unsigned int completed,
715 __inout unsigned int *addedp);
717 extern __checkReturn efx_rc_t
720 __in_ecount(n) efx_desc_t *ed,
722 __in unsigned int completed,
723 __inout unsigned int *addedp);
726 ef10_tx_qdesc_dma_create(
728 __in efsys_dma_addr_t addr,
731 __out efx_desc_t *edp);
734 ef10_tx_qdesc_tso_create(
736 __in uint16_t ipv4_id,
737 __in uint32_t tcp_seq,
738 __in uint8_t tcp_flags,
739 __out efx_desc_t *edp);
742 ef10_tx_qdesc_tso2_create(
744 __in uint16_t ipv4_id,
745 __in uint32_t tcp_seq,
746 __in uint16_t tcp_mss,
747 __out_ecount(count) efx_desc_t *edp,
751 ef10_tx_qdesc_vlantci_create(
753 __in uint16_t vlan_tci,
754 __out efx_desc_t *edp);
760 ef10_tx_qstats_update(
762 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
764 #endif /* EFSYS_OPT_QSTATS */
766 typedef uint32_t efx_piobuf_handle_t;
768 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1)
770 extern __checkReturn efx_rc_t
772 __inout efx_nic_t *enp,
773 __out uint32_t *bufnump,
774 __out efx_piobuf_handle_t *handlep,
775 __out uint32_t *blknump,
776 __out uint32_t *offsetp,
777 __out size_t *sizep);
779 extern __checkReturn efx_rc_t
781 __inout efx_nic_t *enp,
782 __in uint32_t bufnum,
783 __in uint32_t blknum);
785 extern __checkReturn efx_rc_t
787 __inout efx_nic_t *enp,
788 __in uint32_t vi_index,
789 __in efx_piobuf_handle_t handle);
791 extern __checkReturn efx_rc_t
793 __inout efx_nic_t *enp,
794 __in uint32_t vi_index);
801 extern __checkReturn efx_rc_t
803 __in efx_nic_t *enp);
805 extern __checkReturn efx_rc_t
808 __out size_t *sizep);
810 extern __checkReturn efx_rc_t
813 __out_bcount(size) caddr_t data,
816 extern __checkReturn efx_rc_t
819 __in_bcount(size) caddr_t data,
822 extern __checkReturn efx_rc_t
825 __in_bcount(size) caddr_t data,
828 extern __checkReturn efx_rc_t
831 __in_bcount(size) caddr_t data,
833 __inout efx_vpd_value_t *evvp);
835 extern __checkReturn efx_rc_t
838 __in_bcount(size) caddr_t data,
840 __in efx_vpd_value_t *evvp);
842 extern __checkReturn efx_rc_t
845 __in_bcount(size) caddr_t data,
847 __out efx_vpd_value_t *evvp,
848 __inout unsigned int *contp);
850 extern __checkReturn efx_rc_t
853 __in_bcount(size) caddr_t data,
858 __in efx_nic_t *enp);
860 #endif /* EFSYS_OPT_VPD */
865 extern __checkReturn efx_rc_t
867 __in efx_nic_t *enp);
869 #if EFSYS_OPT_RX_SCATTER
870 extern __checkReturn efx_rc_t
871 ef10_rx_scatter_enable(
873 __in unsigned int buf_size);
874 #endif /* EFSYS_OPT_RX_SCATTER */
877 #if EFSYS_OPT_RX_SCALE
879 extern __checkReturn efx_rc_t
880 ef10_rx_scale_context_alloc(
882 __in efx_rx_scale_context_type_t type,
883 __in uint32_t num_queues,
884 __out uint32_t *rss_contextp);
886 extern __checkReturn efx_rc_t
887 ef10_rx_scale_context_free(
889 __in uint32_t rss_context);
891 extern __checkReturn efx_rc_t
892 ef10_rx_scale_mode_set(
894 __in uint32_t rss_context,
895 __in efx_rx_hash_alg_t alg,
896 __in efx_rx_hash_type_t type,
897 __in boolean_t insert);
899 extern __checkReturn efx_rc_t
900 ef10_rx_scale_key_set(
902 __in uint32_t rss_context,
903 __in_ecount(n) uint8_t *key,
906 extern __checkReturn efx_rc_t
907 ef10_rx_scale_tbl_set(
909 __in uint32_t rss_context,
910 __in_ecount(n) unsigned int *table,
913 extern __checkReturn uint32_t
916 __in efx_rx_hash_alg_t func,
917 __in uint8_t *buffer);
919 #endif /* EFSYS_OPT_RX_SCALE */
921 extern __checkReturn efx_rc_t
922 ef10_rx_prefix_pktlen(
924 __in uint8_t *buffer,
925 __out uint16_t *lengthp);
930 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
932 __in unsigned int ndescs,
933 __in unsigned int completed,
934 __in unsigned int added);
939 __in unsigned int added,
940 __inout unsigned int *pushedp);
942 extern __checkReturn efx_rc_t
944 __in efx_rxq_t *erp);
948 __in efx_rxq_t *erp);
950 extern __checkReturn efx_rc_t
953 __in unsigned int index,
954 __in unsigned int label,
955 __in efx_rxq_type_t type,
956 __in uint32_t type_data,
957 __in efsys_mem_t *esmp,
960 __in unsigned int flags,
962 __in efx_rxq_t *erp);
966 __in efx_rxq_t *erp);
970 __in efx_nic_t *enp);
974 typedef struct ef10_filter_handle_s {
977 } ef10_filter_handle_t;
979 typedef struct ef10_filter_entry_s {
980 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
981 ef10_filter_handle_t efe_handle;
982 } ef10_filter_entry_t;
985 * BUSY flag indicates that an update is in progress.
986 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
988 #define EFX_EF10_FILTER_FLAG_BUSY 1U
989 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
990 #define EFX_EF10_FILTER_FLAGS 3U
993 * Size of the hash table used by the driver. Doesn't need to be the
994 * same size as the hardware's table.
996 #define EFX_EF10_FILTER_TBL_ROWS 8192
998 /* Only need to allow for one directed and one unknown unicast filter */
999 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
1001 /* Allow for the broadcast address to be added to the multicast list */
1002 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
1005 * For encapsulated packets, there is one filter each for each combination of
1006 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1007 * multicast inner frames.
1009 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
1011 typedef struct ef10_filter_table_s {
1012 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1013 efx_rxq_t *eft_default_rxq;
1014 boolean_t eft_using_rss;
1015 uint32_t eft_unicst_filter_indexes[
1016 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1017 uint32_t eft_unicst_filter_count;
1018 uint32_t eft_mulcst_filter_indexes[
1019 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1020 uint32_t eft_mulcst_filter_count;
1021 boolean_t eft_using_all_mulcst;
1022 uint32_t eft_encap_filter_indexes[
1023 EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1024 uint32_t eft_encap_filter_count;
1025 } ef10_filter_table_t;
1027 __checkReturn efx_rc_t
1029 __in efx_nic_t *enp);
1033 __in efx_nic_t *enp);
1035 __checkReturn efx_rc_t
1036 ef10_filter_restore(
1037 __in efx_nic_t *enp);
1039 __checkReturn efx_rc_t
1041 __in efx_nic_t *enp,
1042 __inout efx_filter_spec_t *spec,
1043 __in boolean_t may_replace);
1045 __checkReturn efx_rc_t
1047 __in efx_nic_t *enp,
1048 __inout efx_filter_spec_t *spec);
1050 extern __checkReturn efx_rc_t
1051 ef10_filter_supported_filters(
1052 __in efx_nic_t *enp,
1053 __out_ecount(buffer_length) uint32_t *buffer,
1054 __in size_t buffer_length,
1055 __out size_t *list_lengthp);
1057 extern __checkReturn efx_rc_t
1058 ef10_filter_reconfigure(
1059 __in efx_nic_t *enp,
1060 __in_ecount(6) uint8_t const *mac_addr,
1061 __in boolean_t all_unicst,
1062 __in boolean_t mulcst,
1063 __in boolean_t all_mulcst,
1064 __in boolean_t brdcst,
1065 __in_ecount(6*count) uint8_t const *addrs,
1066 __in uint32_t count);
1069 ef10_filter_get_default_rxq(
1070 __in efx_nic_t *enp,
1071 __out efx_rxq_t **erpp,
1072 __out boolean_t *using_rss);
1075 ef10_filter_default_rxq_set(
1076 __in efx_nic_t *enp,
1077 __in efx_rxq_t *erp,
1078 __in boolean_t using_rss);
1081 ef10_filter_default_rxq_clear(
1082 __in efx_nic_t *enp);
1085 #endif /* EFSYS_OPT_FILTER */
1087 extern __checkReturn efx_rc_t
1088 efx_mcdi_get_function_info(
1089 __in efx_nic_t *enp,
1090 __out uint32_t *pfp,
1091 __out_opt uint32_t *vfp);
1093 extern __checkReturn efx_rc_t
1094 efx_mcdi_privilege_mask(
1095 __in efx_nic_t *enp,
1098 __out uint32_t *maskp);
1100 extern __checkReturn efx_rc_t
1101 efx_mcdi_get_port_assignment(
1102 __in efx_nic_t *enp,
1103 __out uint32_t *portp);
1105 extern __checkReturn efx_rc_t
1106 efx_mcdi_get_port_modes(
1107 __in efx_nic_t *enp,
1108 __out uint32_t *modesp,
1109 __out_opt uint32_t *current_modep);
1111 extern __checkReturn efx_rc_t
1112 ef10_nic_get_port_mode_bandwidth(
1113 __in uint32_t port_mode,
1114 __out uint32_t *bandwidth_mbpsp);
1116 extern __checkReturn efx_rc_t
1117 efx_mcdi_get_mac_address_pf(
1118 __in efx_nic_t *enp,
1119 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1121 extern __checkReturn efx_rc_t
1122 efx_mcdi_get_mac_address_vf(
1123 __in efx_nic_t *enp,
1124 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1126 extern __checkReturn efx_rc_t
1128 __in efx_nic_t *enp,
1129 __out uint32_t *sys_freqp,
1130 __out uint32_t *dpcpu_freqp);
1133 extern __checkReturn efx_rc_t
1134 efx_mcdi_get_vector_cfg(
1135 __in efx_nic_t *enp,
1136 __out_opt uint32_t *vec_basep,
1137 __out_opt uint32_t *pf_nvecp,
1138 __out_opt uint32_t *vf_nvecp);
1140 extern __checkReturn efx_rc_t
1141 ef10_get_datapath_caps(
1142 __in efx_nic_t *enp);
1144 extern __checkReturn efx_rc_t
1145 ef10_get_privilege_mask(
1146 __in efx_nic_t *enp,
1147 __out uint32_t *maskp);
1149 extern __checkReturn efx_rc_t
1150 ef10_external_port_mapping(
1151 __in efx_nic_t *enp,
1153 __out uint8_t *external_portp);
1155 #if EFSYS_OPT_RX_PACKED_STREAM
1157 /* Data space per credit in packed stream mode */
1158 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1161 * Received packets are always aligned at this boundary. Also there always
1162 * exists a gap of this size between packets.
1163 * (see SF-112241-TC, 4.5)
1165 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64
1168 * Size of a pseudo-header prepended to received packets
1169 * in packed stream mode
1171 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1173 /* Minimum space for packet in packed stream mode */
1174 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
1175 P2ROUNDUP(EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
1177 EFX_RX_PACKED_STREAM_ALIGNMENT, \
1178 EFX_RX_PACKED_STREAM_ALIGNMENT)
1180 /* Maximum number of credits */
1181 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1183 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1189 #endif /* _SYS_EF10_IMPL_H */