1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
7 #ifndef _SYS_EF10_IMPL_H
8 #define _SYS_EF10_IMPL_H
14 #define EF10_EVQ_MAXNEVS 32768
15 #define EF10_EVQ_MINNEVS 512
17 #define EF10_RXQ_MAXNDESCS 4096
18 #define EF10_RXQ_MINNDESCS 512
20 #define EF10_TXQ_MINNDESCS 512
22 #define EF10_EVQ_DESC_SIZE (sizeof (efx_qword_t))
23 #define EF10_RXQ_DESC_SIZE (sizeof (efx_qword_t))
24 #define EF10_TXQ_DESC_SIZE (sizeof (efx_qword_t))
26 /* Number of hardware EVQ buffers (for compile-time resource dimensions) */
27 #define EF10_EVQ_MAXNBUFS (64)
29 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
30 #define EF10_TXQ_MAXNBUFS 8
32 #if EFSYS_OPT_HUNTINGTON
33 # if (EF10_EVQ_MAXNBUFS < HUNT_EVQ_MAXNBUFS)
34 # error "EF10_EVQ_MAXNBUFS too small"
36 #endif /* EFSYS_OPT_HUNTINGTON */
38 # if (EF10_EVQ_MAXNBUFS < MEDFORD_EVQ_MAXNBUFS)
39 # error "EF10_EVQ_MAXNBUFS too small"
41 #endif /* EFSYS_OPT_MEDFORD */
42 #if EFSYS_OPT_MEDFORD2
43 # if (EF10_EVQ_MAXNBUFS < MEDFORD2_EVQ_MAXNBUFS)
44 # error "EF10_EVQ_MAXNBUFS too small"
46 #endif /* EFSYS_OPT_MEDFORD2 */
48 /* Number of hardware PIO buffers (for compile-time resource dimensions) */
49 #define EF10_MAX_PIOBUF_NBUFS (16)
51 #if EFSYS_OPT_HUNTINGTON
52 # if (EF10_MAX_PIOBUF_NBUFS < HUNT_PIOBUF_NBUFS)
53 # error "EF10_MAX_PIOBUF_NBUFS too small"
55 #endif /* EFSYS_OPT_HUNTINGTON */
57 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD_PIOBUF_NBUFS)
58 # error "EF10_MAX_PIOBUF_NBUFS too small"
60 #endif /* EFSYS_OPT_MEDFORD */
61 #if EFSYS_OPT_MEDFORD2
62 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD2_PIOBUF_NBUFS)
63 # error "EF10_MAX_PIOBUF_NBUFS too small"
65 #endif /* EFSYS_OPT_MEDFORD2 */
70 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
71 * possibly be increased, or the write size reported by newer firmware used
74 #define EF10_NVRAM_CHUNK 0x80
77 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned
78 * to an 8 descriptor boundary.
80 #define EF10_RX_WPTR_ALIGN 8
83 * Max byte offset into the packet the TCP header must start for the hardware
84 * to be able to parse the packet correctly.
86 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
88 /* Invalid RSS context handle */
89 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
94 __checkReturn efx_rc_t
100 __in efx_nic_t *enp);
102 __checkReturn efx_rc_t
105 __in unsigned int index,
106 __in efsys_mem_t *esmp,
111 __in efx_evq_t *eep);
115 __in efx_evq_t *eep);
117 __checkReturn efx_rc_t
120 __in unsigned int count);
127 __checkReturn efx_rc_t
130 __in unsigned int us);
134 ef10_ev_qstats_update(
136 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
137 #endif /* EFSYS_OPT_QSTATS */
140 ef10_ev_rxlabel_init(
143 __in unsigned int label,
144 __in efx_rxq_type_t type);
147 ef10_ev_rxlabel_fini(
149 __in unsigned int label);
153 __checkReturn efx_rc_t
156 __in efx_intr_type_t type,
157 __in efsys_mem_t *esmp);
161 __in efx_nic_t *enp);
165 __in efx_nic_t *enp);
168 ef10_intr_disable_unlocked(
169 __in efx_nic_t *enp);
171 __checkReturn efx_rc_t
174 __in unsigned int level);
177 ef10_intr_status_line(
179 __out boolean_t *fatalp,
180 __out uint32_t *qmaskp);
183 ef10_intr_status_message(
185 __in unsigned int message,
186 __out boolean_t *fatalp);
190 __in efx_nic_t *enp);
193 __in efx_nic_t *enp);
197 extern __checkReturn efx_rc_t
199 __in efx_nic_t *enp);
201 extern __checkReturn efx_rc_t
202 ef10_nic_set_drv_limits(
203 __inout efx_nic_t *enp,
204 __in efx_drv_limits_t *edlp);
206 extern __checkReturn efx_rc_t
207 ef10_nic_get_vi_pool(
209 __out uint32_t *vi_countp);
211 extern __checkReturn efx_rc_t
212 ef10_nic_get_bar_region(
214 __in efx_nic_region_t region,
215 __out uint32_t *offsetp,
216 __out size_t *sizep);
218 extern __checkReturn efx_rc_t
220 __in efx_nic_t *enp);
222 extern __checkReturn efx_rc_t
224 __in efx_nic_t *enp);
226 extern __checkReturn boolean_t
227 ef10_nic_hw_unavailable(
228 __in efx_nic_t *enp);
231 ef10_nic_set_hw_unavailable(
232 __in efx_nic_t *enp);
236 extern __checkReturn efx_rc_t
237 ef10_nic_register_test(
238 __in efx_nic_t *enp);
240 #endif /* EFSYS_OPT_DIAG */
244 __in efx_nic_t *enp);
248 __in efx_nic_t *enp);
253 extern __checkReturn efx_rc_t
256 __out efx_link_mode_t *link_modep);
258 extern __checkReturn efx_rc_t
261 __out boolean_t *mac_upp);
263 extern __checkReturn efx_rc_t
265 __in efx_nic_t *enp);
267 extern __checkReturn efx_rc_t
269 __in efx_nic_t *enp);
271 extern __checkReturn efx_rc_t
276 extern __checkReturn efx_rc_t
277 ef10_mac_reconfigure(
278 __in efx_nic_t *enp);
280 extern __checkReturn efx_rc_t
281 ef10_mac_multicast_list_set(
282 __in efx_nic_t *enp);
284 extern __checkReturn efx_rc_t
285 ef10_mac_filter_default_rxq_set(
288 __in boolean_t using_rss);
291 ef10_mac_filter_default_rxq_clear(
292 __in efx_nic_t *enp);
294 #if EFSYS_OPT_LOOPBACK
296 extern __checkReturn efx_rc_t
297 ef10_mac_loopback_set(
299 __in efx_link_mode_t link_mode,
300 __in efx_loopback_type_t loopback_type);
302 #endif /* EFSYS_OPT_LOOPBACK */
304 #if EFSYS_OPT_MAC_STATS
306 extern __checkReturn efx_rc_t
307 ef10_mac_stats_get_mask(
309 __inout_bcount(mask_size) uint32_t *maskp,
310 __in size_t mask_size);
312 extern __checkReturn efx_rc_t
313 ef10_mac_stats_update(
315 __in efsys_mem_t *esmp,
316 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
317 __inout_opt uint32_t *generationp);
319 #endif /* EFSYS_OPT_MAC_STATS */
326 extern __checkReturn efx_rc_t
329 __in const efx_mcdi_transport_t *mtp);
333 __in efx_nic_t *enp);
336 ef10_mcdi_send_request(
338 __in_bcount(hdr_len) void *hdrp,
340 __in_bcount(sdu_len) void *sdup,
341 __in size_t sdu_len);
343 extern __checkReturn boolean_t
344 ef10_mcdi_poll_response(
345 __in efx_nic_t *enp);
348 ef10_mcdi_read_response(
350 __out_bcount(length) void *bufferp,
355 ef10_mcdi_poll_reboot(
356 __in efx_nic_t *enp);
358 extern __checkReturn efx_rc_t
359 ef10_mcdi_feature_supported(
361 __in efx_mcdi_feature_id_t id,
362 __out boolean_t *supportedp);
365 ef10_mcdi_get_timeout(
367 __in efx_mcdi_req_t *emrp,
368 __out uint32_t *timeoutp);
370 #endif /* EFSYS_OPT_MCDI */
374 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
376 extern __checkReturn efx_rc_t
377 ef10_nvram_buf_read_tlv(
379 __in_bcount(max_seg_size) caddr_t seg_data,
380 __in size_t max_seg_size,
382 __deref_out_bcount_opt(*sizep) caddr_t *datap,
383 __out size_t *sizep);
385 extern __checkReturn efx_rc_t
386 ef10_nvram_buf_write_tlv(
387 __inout_bcount(partn_size) caddr_t partn_data,
388 __in size_t partn_size,
390 __in_bcount(tag_size) caddr_t tag_data,
391 __in size_t tag_size,
392 __out size_t *total_lengthp);
394 extern __checkReturn efx_rc_t
395 ef10_nvram_partn_read_tlv(
399 __deref_out_bcount_opt(*sizep) caddr_t *datap,
400 __out size_t *sizep);
402 extern __checkReturn efx_rc_t
403 ef10_nvram_partn_write_tlv(
407 __in_bcount(size) caddr_t data,
410 extern __checkReturn efx_rc_t
411 ef10_nvram_partn_write_segment_tlv(
415 __in_bcount(size) caddr_t data,
417 __in boolean_t all_segments);
419 extern __checkReturn efx_rc_t
420 ef10_nvram_partn_lock(
422 __in uint32_t partn);
424 extern __checkReturn efx_rc_t
425 ef10_nvram_partn_unlock(
428 __out_opt uint32_t *resultp);
430 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
436 extern __checkReturn efx_rc_t
438 __in efx_nic_t *enp);
440 #endif /* EFSYS_OPT_DIAG */
442 extern __checkReturn efx_rc_t
443 ef10_nvram_type_to_partn(
445 __in efx_nvram_type_t type,
446 __out uint32_t *partnp);
448 extern __checkReturn efx_rc_t
449 ef10_nvram_partn_size(
452 __out size_t *sizep);
454 extern __checkReturn efx_rc_t
455 ef10_nvram_partn_rw_start(
458 __out size_t *chunk_sizep);
460 extern __checkReturn efx_rc_t
461 ef10_nvram_partn_read_mode(
464 __in unsigned int offset,
465 __out_bcount(size) caddr_t data,
469 extern __checkReturn efx_rc_t
470 ef10_nvram_partn_read(
473 __in unsigned int offset,
474 __out_bcount(size) caddr_t data,
477 extern __checkReturn efx_rc_t
478 ef10_nvram_partn_read_backup(
481 __in unsigned int offset,
482 __out_bcount(size) caddr_t data,
485 extern __checkReturn efx_rc_t
486 ef10_nvram_partn_erase(
489 __in unsigned int offset,
492 extern __checkReturn efx_rc_t
493 ef10_nvram_partn_write(
496 __in unsigned int offset,
497 __in_bcount(size) caddr_t data,
500 extern __checkReturn efx_rc_t
501 ef10_nvram_partn_rw_finish(
504 __out_opt uint32_t *verify_resultp);
506 extern __checkReturn efx_rc_t
507 ef10_nvram_partn_get_version(
510 __out uint32_t *subtypep,
511 __out_ecount(4) uint16_t version[4]);
513 extern __checkReturn efx_rc_t
514 ef10_nvram_partn_set_version(
517 __in_ecount(4) uint16_t version[4]);
519 extern __checkReturn efx_rc_t
520 ef10_nvram_buffer_validate(
522 __in_bcount(buffer_size)
524 __in size_t buffer_size);
527 ef10_nvram_buffer_init(
528 __out_bcount(buffer_size)
530 __in size_t buffer_size);
532 extern __checkReturn efx_rc_t
533 ef10_nvram_buffer_create(
534 __in uint32_t partn_type,
535 __out_bcount(buffer_size)
537 __in size_t buffer_size);
539 extern __checkReturn efx_rc_t
540 ef10_nvram_buffer_find_item_start(
541 __in_bcount(buffer_size)
543 __in size_t buffer_size,
544 __out uint32_t *startp);
546 extern __checkReturn efx_rc_t
547 ef10_nvram_buffer_find_end(
548 __in_bcount(buffer_size)
550 __in size_t buffer_size,
551 __in uint32_t offset,
552 __out uint32_t *endp);
554 extern __checkReturn __success(return != B_FALSE) boolean_t
555 ef10_nvram_buffer_find_item(
556 __in_bcount(buffer_size)
558 __in size_t buffer_size,
559 __in uint32_t offset,
560 __out uint32_t *startp,
561 __out uint32_t *lengthp);
563 extern __checkReturn efx_rc_t
564 ef10_nvram_buffer_peek_item(
565 __in_bcount(buffer_size)
567 __in size_t buffer_size,
568 __in uint32_t offset,
569 __out uint32_t *tagp,
570 __out uint32_t *lengthp,
571 __out uint32_t *value_offsetp);
573 extern __checkReturn efx_rc_t
574 ef10_nvram_buffer_get_item(
575 __in_bcount(buffer_size)
577 __in size_t buffer_size,
578 __in uint32_t offset,
579 __in uint32_t length,
580 __out uint32_t *tagp,
581 __out_bcount_part(value_max_size, *lengthp)
583 __in size_t value_max_size,
584 __out uint32_t *lengthp);
586 extern __checkReturn efx_rc_t
587 ef10_nvram_buffer_insert_item(
588 __in_bcount(buffer_size)
590 __in size_t buffer_size,
591 __in uint32_t offset,
593 __in_bcount(length) caddr_t valuep,
594 __in uint32_t length,
595 __out uint32_t *lengthp);
597 extern __checkReturn efx_rc_t
598 ef10_nvram_buffer_modify_item(
599 __in_bcount(buffer_size)
601 __in size_t buffer_size,
602 __in uint32_t offset,
604 __in_bcount(length) caddr_t valuep,
605 __in uint32_t length,
606 __out uint32_t *lengthp);
608 extern __checkReturn efx_rc_t
609 ef10_nvram_buffer_delete_item(
610 __in_bcount(buffer_size)
612 __in size_t buffer_size,
613 __in uint32_t offset,
614 __in uint32_t length,
617 extern __checkReturn efx_rc_t
618 ef10_nvram_buffer_finish(
619 __in_bcount(buffer_size)
621 __in size_t buffer_size);
623 #endif /* EFSYS_OPT_NVRAM */
628 typedef struct ef10_link_state_s {
629 efx_phy_link_state_t epls;
630 #if EFSYS_OPT_LOOPBACK
631 efx_loopback_type_t els_loopback;
633 boolean_t els_mac_up;
639 __in efx_qword_t *eqp,
640 __out efx_link_mode_t *link_modep);
642 extern __checkReturn efx_rc_t
645 __out ef10_link_state_t *elsp);
647 extern __checkReturn efx_rc_t
652 extern __checkReturn efx_rc_t
653 ef10_phy_reconfigure(
654 __in efx_nic_t *enp);
656 extern __checkReturn efx_rc_t
658 __in efx_nic_t *enp);
660 extern __checkReturn efx_rc_t
663 __out uint32_t *ouip);
665 extern __checkReturn efx_rc_t
666 ef10_phy_link_state_get(
668 __out efx_phy_link_state_t *eplsp);
670 #if EFSYS_OPT_PHY_STATS
672 extern __checkReturn efx_rc_t
673 ef10_phy_stats_update(
675 __in efsys_mem_t *esmp,
676 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
678 #endif /* EFSYS_OPT_PHY_STATS */
682 extern __checkReturn efx_rc_t
683 ef10_bist_enable_offline(
684 __in efx_nic_t *enp);
686 extern __checkReturn efx_rc_t
689 __in efx_bist_type_t type);
691 extern __checkReturn efx_rc_t
694 __in efx_bist_type_t type,
695 __out efx_bist_result_t *resultp,
696 __out_opt __drv_when(count > 0, __notnull)
697 uint32_t *value_maskp,
698 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
699 unsigned long *valuesp,
705 __in efx_bist_type_t type);
707 #endif /* EFSYS_OPT_BIST */
711 extern __checkReturn efx_rc_t
713 __in efx_nic_t *enp);
717 __in efx_nic_t *enp);
719 extern __checkReturn efx_rc_t
722 __in unsigned int index,
723 __in unsigned int label,
724 __in efsys_mem_t *esmp,
730 __out unsigned int *addedp);
734 __in efx_txq_t *etp);
736 extern __checkReturn efx_rc_t
739 __in_ecount(ndescs) efx_buffer_t *ebp,
740 __in unsigned int ndescs,
741 __in unsigned int completed,
742 __inout unsigned int *addedp);
747 __in unsigned int added,
748 __in unsigned int pushed);
750 #if EFSYS_OPT_RX_PACKED_STREAM
752 ef10_rx_qpush_ps_credits(
753 __in efx_rxq_t *erp);
755 extern __checkReturn uint8_t *
756 ef10_rx_qps_packet_info(
758 __in uint8_t *buffer,
759 __in uint32_t buffer_length,
760 __in uint32_t current_offset,
761 __out uint16_t *lengthp,
762 __out uint32_t *next_offsetp,
763 __out uint32_t *timestamp);
766 extern __checkReturn efx_rc_t
769 __in unsigned int ns);
771 extern __checkReturn efx_rc_t
773 __in efx_txq_t *etp);
777 __in efx_txq_t *etp);
779 extern __checkReturn efx_rc_t
781 __in efx_txq_t *etp);
784 ef10_tx_qpio_disable(
785 __in efx_txq_t *etp);
787 extern __checkReturn efx_rc_t
790 __in_ecount(buf_length) uint8_t *buffer,
791 __in size_t buf_length,
792 __in size_t pio_buf_offset);
794 extern __checkReturn efx_rc_t
797 __in size_t pkt_length,
798 __in unsigned int completed,
799 __inout unsigned int *addedp);
801 extern __checkReturn efx_rc_t
804 __in_ecount(n) efx_desc_t *ed,
806 __in unsigned int completed,
807 __inout unsigned int *addedp);
810 ef10_tx_qdesc_dma_create(
812 __in efsys_dma_addr_t addr,
815 __out efx_desc_t *edp);
818 ef10_tx_qdesc_tso_create(
820 __in uint16_t ipv4_id,
821 __in uint32_t tcp_seq,
822 __in uint8_t tcp_flags,
823 __out efx_desc_t *edp);
826 ef10_tx_qdesc_tso2_create(
828 __in uint16_t ipv4_id,
829 __in uint16_t outer_ipv4_id,
830 __in uint32_t tcp_seq,
831 __in uint16_t tcp_mss,
832 __out_ecount(count) efx_desc_t *edp,
836 ef10_tx_qdesc_vlantci_create(
838 __in uint16_t vlan_tci,
839 __out efx_desc_t *edp);
842 ef10_tx_qdesc_checksum_create(
845 __out efx_desc_t *edp);
850 ef10_tx_qstats_update(
852 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
854 #endif /* EFSYS_OPT_QSTATS */
856 typedef uint32_t efx_piobuf_handle_t;
858 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1)
860 extern __checkReturn efx_rc_t
862 __inout efx_nic_t *enp,
863 __out uint32_t *bufnump,
864 __out efx_piobuf_handle_t *handlep,
865 __out uint32_t *blknump,
866 __out uint32_t *offsetp,
867 __out size_t *sizep);
869 extern __checkReturn efx_rc_t
871 __inout efx_nic_t *enp,
872 __in uint32_t bufnum,
873 __in uint32_t blknum);
875 extern __checkReturn efx_rc_t
877 __inout efx_nic_t *enp,
878 __in uint32_t vi_index,
879 __in efx_piobuf_handle_t handle);
881 extern __checkReturn efx_rc_t
883 __inout efx_nic_t *enp,
884 __in uint32_t vi_index);
891 extern __checkReturn efx_rc_t
893 __in efx_nic_t *enp);
895 extern __checkReturn efx_rc_t
898 __out size_t *sizep);
900 extern __checkReturn efx_rc_t
903 __out_bcount(size) caddr_t data,
906 extern __checkReturn efx_rc_t
909 __in_bcount(size) caddr_t data,
912 extern __checkReturn efx_rc_t
915 __in_bcount(size) caddr_t data,
918 extern __checkReturn efx_rc_t
921 __in_bcount(size) caddr_t data,
923 __inout efx_vpd_value_t *evvp);
925 extern __checkReturn efx_rc_t
928 __in_bcount(size) caddr_t data,
930 __in efx_vpd_value_t *evvp);
932 extern __checkReturn efx_rc_t
935 __in_bcount(size) caddr_t data,
937 __out efx_vpd_value_t *evvp,
938 __inout unsigned int *contp);
940 extern __checkReturn efx_rc_t
943 __in_bcount(size) caddr_t data,
948 __in efx_nic_t *enp);
950 #endif /* EFSYS_OPT_VPD */
955 extern __checkReturn efx_rc_t
957 __in efx_nic_t *enp);
959 #if EFSYS_OPT_RX_SCATTER
960 extern __checkReturn efx_rc_t
961 ef10_rx_scatter_enable(
963 __in unsigned int buf_size);
964 #endif /* EFSYS_OPT_RX_SCATTER */
967 #if EFSYS_OPT_RX_SCALE
969 extern __checkReturn efx_rc_t
970 ef10_rx_scale_context_alloc(
972 __in efx_rx_scale_context_type_t type,
973 __in uint32_t num_queues,
974 __out uint32_t *rss_contextp);
976 extern __checkReturn efx_rc_t
977 ef10_rx_scale_context_free(
979 __in uint32_t rss_context);
981 extern __checkReturn efx_rc_t
982 ef10_rx_scale_mode_set(
984 __in uint32_t rss_context,
985 __in efx_rx_hash_alg_t alg,
986 __in efx_rx_hash_type_t type,
987 __in boolean_t insert);
989 extern __checkReturn efx_rc_t
990 ef10_rx_scale_key_set(
992 __in uint32_t rss_context,
993 __in_ecount(n) uint8_t *key,
996 extern __checkReturn efx_rc_t
997 ef10_rx_scale_tbl_set(
999 __in uint32_t rss_context,
1000 __in_ecount(n) unsigned int *table,
1003 extern __checkReturn uint32_t
1004 ef10_rx_prefix_hash(
1005 __in efx_nic_t *enp,
1006 __in efx_rx_hash_alg_t func,
1007 __in uint8_t *buffer);
1009 #endif /* EFSYS_OPT_RX_SCALE */
1011 extern __checkReturn efx_rc_t
1012 ef10_rx_prefix_pktlen(
1013 __in efx_nic_t *enp,
1014 __in uint8_t *buffer,
1015 __out uint16_t *lengthp);
1019 __in efx_rxq_t *erp,
1020 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1022 __in unsigned int ndescs,
1023 __in unsigned int completed,
1024 __in unsigned int added);
1028 __in efx_rxq_t *erp,
1029 __in unsigned int added,
1030 __inout unsigned int *pushedp);
1032 extern __checkReturn efx_rc_t
1034 __in efx_rxq_t *erp);
1038 __in efx_rxq_t *erp);
1040 union efx_rxq_type_data_u;
1042 extern __checkReturn efx_rc_t
1044 __in efx_nic_t *enp,
1045 __in unsigned int index,
1046 __in unsigned int label,
1047 __in efx_rxq_type_t type,
1048 __in_opt const union efx_rxq_type_data_u *type_data,
1049 __in efsys_mem_t *esmp,
1052 __in unsigned int flags,
1053 __in efx_evq_t *eep,
1054 __in efx_rxq_t *erp);
1058 __in efx_rxq_t *erp);
1062 __in efx_nic_t *enp);
1064 #if EFSYS_OPT_FILTER
1066 typedef struct ef10_filter_handle_s {
1069 } ef10_filter_handle_t;
1071 typedef struct ef10_filter_entry_s {
1072 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1073 ef10_filter_handle_t efe_handle;
1074 } ef10_filter_entry_t;
1077 * BUSY flag indicates that an update is in progress.
1078 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1080 #define EFX_EF10_FILTER_FLAG_BUSY 1U
1081 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
1082 #define EFX_EF10_FILTER_FLAGS 3U
1085 * Size of the hash table used by the driver. Doesn't need to be the
1086 * same size as the hardware's table.
1088 #define EFX_EF10_FILTER_TBL_ROWS 8192
1090 /* Only need to allow for one directed and one unknown unicast filter */
1091 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
1093 /* Allow for the broadcast address to be added to the multicast list */
1094 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
1097 * For encapsulated packets, there is one filter each for each combination of
1098 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1099 * multicast inner frames.
1101 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
1103 typedef struct ef10_filter_table_s {
1104 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1105 efx_rxq_t *eft_default_rxq;
1106 boolean_t eft_using_rss;
1107 uint32_t eft_unicst_filter_indexes[
1108 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1109 uint32_t eft_unicst_filter_count;
1110 uint32_t eft_mulcst_filter_indexes[
1111 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1112 uint32_t eft_mulcst_filter_count;
1113 boolean_t eft_using_all_mulcst;
1114 uint32_t eft_encap_filter_indexes[
1115 EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1116 uint32_t eft_encap_filter_count;
1117 } ef10_filter_table_t;
1119 __checkReturn efx_rc_t
1121 __in efx_nic_t *enp);
1125 __in efx_nic_t *enp);
1127 __checkReturn efx_rc_t
1128 ef10_filter_restore(
1129 __in efx_nic_t *enp);
1131 __checkReturn efx_rc_t
1133 __in efx_nic_t *enp,
1134 __inout efx_filter_spec_t *spec,
1135 __in boolean_t may_replace);
1137 __checkReturn efx_rc_t
1139 __in efx_nic_t *enp,
1140 __inout efx_filter_spec_t *spec);
1142 extern __checkReturn efx_rc_t
1143 ef10_filter_supported_filters(
1144 __in efx_nic_t *enp,
1145 __out_ecount(buffer_length) uint32_t *buffer,
1146 __in size_t buffer_length,
1147 __out size_t *list_lengthp);
1149 extern __checkReturn efx_rc_t
1150 ef10_filter_reconfigure(
1151 __in efx_nic_t *enp,
1152 __in_ecount(6) uint8_t const *mac_addr,
1153 __in boolean_t all_unicst,
1154 __in boolean_t mulcst,
1155 __in boolean_t all_mulcst,
1156 __in boolean_t brdcst,
1157 __in_ecount(6*count) uint8_t const *addrs,
1158 __in uint32_t count);
1161 ef10_filter_get_default_rxq(
1162 __in efx_nic_t *enp,
1163 __out efx_rxq_t **erpp,
1164 __out boolean_t *using_rss);
1167 ef10_filter_default_rxq_set(
1168 __in efx_nic_t *enp,
1169 __in efx_rxq_t *erp,
1170 __in boolean_t using_rss);
1173 ef10_filter_default_rxq_clear(
1174 __in efx_nic_t *enp);
1177 #endif /* EFSYS_OPT_FILTER */
1179 extern __checkReturn efx_rc_t
1180 efx_mcdi_get_function_info(
1181 __in efx_nic_t *enp,
1182 __out uint32_t *pfp,
1183 __out_opt uint32_t *vfp);
1185 extern __checkReturn efx_rc_t
1186 efx_mcdi_privilege_mask(
1187 __in efx_nic_t *enp,
1190 __out uint32_t *maskp);
1192 extern __checkReturn efx_rc_t
1193 efx_mcdi_get_port_assignment(
1194 __in efx_nic_t *enp,
1195 __out uint32_t *portp);
1197 extern __checkReturn efx_rc_t
1198 efx_mcdi_get_port_modes(
1199 __in efx_nic_t *enp,
1200 __out uint32_t *modesp,
1201 __out_opt uint32_t *current_modep,
1202 __out_opt uint32_t *default_modep);
1204 extern __checkReturn efx_rc_t
1205 ef10_nic_get_port_mode_bandwidth(
1206 __in efx_nic_t *enp,
1207 __out uint32_t *bandwidth_mbpsp);
1209 extern __checkReturn efx_rc_t
1210 efx_mcdi_get_mac_address_pf(
1211 __in efx_nic_t *enp,
1212 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1214 extern __checkReturn efx_rc_t
1215 efx_mcdi_get_mac_address_vf(
1216 __in efx_nic_t *enp,
1217 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1219 extern __checkReturn efx_rc_t
1221 __in efx_nic_t *enp,
1222 __out uint32_t *sys_freqp,
1223 __out uint32_t *dpcpu_freqp);
1226 extern __checkReturn efx_rc_t
1227 efx_mcdi_get_rxdp_config(
1228 __in efx_nic_t *enp,
1229 __out uint32_t *end_paddingp);
1231 extern __checkReturn efx_rc_t
1232 efx_mcdi_get_vector_cfg(
1233 __in efx_nic_t *enp,
1234 __out_opt uint32_t *vec_basep,
1235 __out_opt uint32_t *pf_nvecp,
1236 __out_opt uint32_t *vf_nvecp);
1238 extern __checkReturn efx_rc_t
1239 ef10_get_privilege_mask(
1240 __in efx_nic_t *enp,
1241 __out uint32_t *maskp);
1243 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1245 extern __checkReturn efx_rc_t
1246 efx_mcdi_get_nic_global(
1247 __in efx_nic_t *enp,
1249 __out uint32_t *valuep);
1251 extern __checkReturn efx_rc_t
1252 efx_mcdi_set_nic_global(
1253 __in efx_nic_t *enp,
1255 __in uint32_t value);
1257 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1260 #if EFSYS_OPT_RX_PACKED_STREAM
1262 /* Data space per credit in packed stream mode */
1263 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1266 * Received packets are always aligned at this boundary. Also there always
1267 * exists a gap of this size between packets.
1268 * (see SF-112241-TC, 4.5)
1270 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64
1273 * Size of a pseudo-header prepended to received packets
1274 * in packed stream mode
1276 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1278 /* Minimum space for packet in packed stream mode */
1279 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
1280 P2ROUNDUP(EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
1282 EFX_RX_PACKED_STREAM_ALIGNMENT, \
1283 EFX_RX_PACKED_STREAM_ALIGNMENT)
1285 /* Maximum number of credits */
1286 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1288 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1290 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1293 * Maximum DMA length and buffer stride alignment.
1294 * (see SF-119419-TC, 3.2)
1296 #define EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT 64
1304 #endif /* _SYS_EF10_IMPL_H */