1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
11 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
13 __checkReturn efx_rc_t
16 __out efx_link_mode_t *link_modep)
18 efx_port_t *epp = &(enp->en_port);
19 ef10_link_state_t els;
22 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
25 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
26 epp->ep_fcntl = els.els_fcntl;
28 *link_modep = els.els_link_mode;
33 EFSYS_PROBE1(fail1, efx_rc_t, rc);
35 *link_modep = EFX_LINK_UNKNOWN;
40 __checkReturn efx_rc_t
43 __out boolean_t *mac_upp)
45 ef10_link_state_t els;
49 * Because EF10 doesn't *require* polling, we can't rely on
50 * ef10_mac_poll() being executed to populate epp->ep_mac_up.
52 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
55 *mac_upp = els.els_mac_up;
60 EFSYS_PROBE1(fail1, efx_rc_t, rc);
66 * EF10 adapters use MC_CMD_VADAPTOR_SET_MAC to set the
67 * MAC address; the address field in MC_CMD_SET_MAC has no
69 * MC_CMD_VADAPTOR_SET_MAC requires mac-spoofing privilege and
70 * the port to have no filters or queues active.
72 static __checkReturn efx_rc_t
73 efx_mcdi_vadapter_set_mac(
76 efx_port_t *epp = &(enp->en_port);
78 uint8_t payload[MAX(MC_CMD_VADAPTOR_SET_MAC_IN_LEN,
79 MC_CMD_VADAPTOR_SET_MAC_OUT_LEN)];
82 (void) memset(payload, 0, sizeof (payload));
83 req.emr_cmd = MC_CMD_VADAPTOR_SET_MAC;
84 req.emr_in_buf = payload;
85 req.emr_in_length = MC_CMD_VADAPTOR_SET_MAC_IN_LEN;
86 req.emr_out_buf = payload;
87 req.emr_out_length = MC_CMD_VADAPTOR_SET_MAC_OUT_LEN;
89 MCDI_IN_SET_DWORD(req, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
91 EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, VADAPTOR_SET_MAC_IN_MACADDR),
94 efx_mcdi_execute(enp, &req);
96 if (req.emr_rc != 0) {
104 EFSYS_PROBE1(fail1, efx_rc_t, rc);
109 __checkReturn efx_rc_t
115 if ((rc = efx_mcdi_vadapter_set_mac(enp)) != 0) {
120 * Fallback for older Huntington firmware without Vadapter
123 if ((rc = ef10_mac_reconfigure(enp)) != 0)
133 EFSYS_PROBE1(fail1, efx_rc_t, rc);
138 static __checkReturn efx_rc_t
144 uint8_t payload[MAX(MC_CMD_SET_MAC_EXT_IN_LEN,
145 MC_CMD_SET_MAC_OUT_LEN)];
148 (void) memset(payload, 0, sizeof (payload));
149 req.emr_cmd = MC_CMD_SET_MAC;
150 req.emr_in_buf = payload;
151 req.emr_in_length = MC_CMD_SET_MAC_EXT_IN_LEN;
152 req.emr_out_buf = payload;
153 req.emr_out_length = MC_CMD_SET_MAC_OUT_LEN;
155 /* Only configure the MTU in this call to MC_CMD_SET_MAC */
156 MCDI_IN_SET_DWORD(req, SET_MAC_EXT_IN_MTU, mtu);
157 MCDI_IN_POPULATE_DWORD_1(req, SET_MAC_EXT_IN_CONTROL,
158 SET_MAC_EXT_IN_CFG_MTU, 1);
160 efx_mcdi_execute(enp, &req);
162 if (req.emr_rc != 0) {
170 EFSYS_PROBE1(fail1, efx_rc_t, rc);
175 static __checkReturn efx_rc_t
181 uint8_t payload[MAX(MC_CMD_SET_MAC_EXT_IN_LEN,
182 MC_CMD_SET_MAC_V2_OUT_LEN)];
185 (void) memset(payload, 0, sizeof (payload));
186 req.emr_cmd = MC_CMD_SET_MAC;
187 req.emr_in_buf = payload;
188 req.emr_in_length = MC_CMD_SET_MAC_EXT_IN_LEN;
189 req.emr_out_buf = payload;
190 req.emr_out_length = MC_CMD_SET_MAC_V2_OUT_LEN;
193 * With MC_CMD_SET_MAC_EXT_IN_CONTROL set to 0, this just queries the
194 * MTU. This should always be supported on Medford, but it is not
195 * supported on older Huntington firmware.
197 MCDI_IN_SET_DWORD(req, SET_MAC_EXT_IN_CONTROL, 0);
199 efx_mcdi_execute(enp, &req);
201 if (req.emr_rc != 0) {
205 if (req.emr_out_length_used < MC_CMD_SET_MAC_V2_OUT_MTU_OFST + 4) {
210 *mtu = MCDI_OUT_DWORD(req, SET_MAC_V2_OUT_MTU);
217 EFSYS_PROBE1(fail1, efx_rc_t, rc);
222 __checkReturn efx_rc_t
226 efx_port_t *epp = &(enp->en_port);
227 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
230 if (encp->enc_enhanced_set_mac_supported) {
231 if ((rc = efx_mcdi_mtu_set(enp, epp->ep_mac_pdu)) != 0)
235 * Fallback for older Huntington firmware, which always
236 * configure all of the parameters to MC_CMD_SET_MAC. This isn't
237 * suitable for setting the MTU on unpriviliged functions.
239 if ((rc = ef10_mac_reconfigure(enp)) != 0)
248 EFSYS_PROBE1(fail1, efx_rc_t, rc);
253 __checkReturn efx_rc_t
260 if ((rc = efx_mcdi_mtu_get(enp, pdu)) != 0)
266 EFSYS_PROBE1(fail1, efx_rc_t, rc);
271 __checkReturn efx_rc_t
272 ef10_mac_reconfigure(
275 efx_port_t *epp = &(enp->en_port);
277 uint8_t payload[MAX(MC_CMD_SET_MAC_IN_LEN,
278 MC_CMD_SET_MAC_OUT_LEN)];
281 (void) memset(payload, 0, sizeof (payload));
282 req.emr_cmd = MC_CMD_SET_MAC;
283 req.emr_in_buf = payload;
284 req.emr_in_length = MC_CMD_SET_MAC_IN_LEN;
285 req.emr_out_buf = payload;
286 req.emr_out_length = MC_CMD_SET_MAC_OUT_LEN;
288 MCDI_IN_SET_DWORD(req, SET_MAC_IN_MTU, epp->ep_mac_pdu);
289 MCDI_IN_SET_DWORD(req, SET_MAC_IN_DRAIN, epp->ep_mac_drain ? 1 : 0);
290 EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, SET_MAC_IN_ADDR),
294 * Note: The Huntington MAC does not support REJECT_BRDCST.
295 * The REJECT_UNCST flag will also prevent multicast traffic
296 * from reaching the filters. As Huntington filters drop any
297 * traffic that does not match a filter it is ok to leave the
298 * MAC running in promiscuous mode. See bug41141.
300 * FIXME: Does REJECT_UNCST behave the same way on Medford?
302 MCDI_IN_POPULATE_DWORD_2(req, SET_MAC_IN_REJECT,
303 SET_MAC_IN_REJECT_UNCST, 0,
304 SET_MAC_IN_REJECT_BRDCST, 0);
307 * Flow control, whether it is auto-negotiated or not,
308 * is set via the PHY advertised capabilities. When set to
309 * automatic the MAC will use the PHY settings to determine
310 * the flow control settings.
312 MCDI_IN_SET_DWORD(req, SET_MAC_IN_FCNTL, MC_CMD_FCNTL_AUTO);
314 /* Do not include the Ethernet frame checksum in RX packets */
315 MCDI_IN_POPULATE_DWORD_1(req, SET_MAC_IN_FLAGS,
316 SET_MAC_IN_FLAG_INCLUDE_FCS, 0);
318 efx_mcdi_execute_quiet(enp, &req);
320 if (req.emr_rc != 0) {
322 * Unprivileged functions cannot control link state,
323 * but still need to configure filters.
325 if (req.emr_rc != EACCES) {
332 * Apply the filters for the MAC configuration.
333 * If the NIC isn't ready to accept filters this may
334 * return success without setting anything.
336 rc = efx_filter_reconfigure(enp, epp->ep_mac_addr,
337 epp->ep_all_unicst, epp->ep_mulcst,
338 epp->ep_all_mulcst, epp->ep_brdcst,
339 epp->ep_mulcst_addr_list,
340 epp->ep_mulcst_addr_count);
345 EFSYS_PROBE1(fail1, efx_rc_t, rc);
350 __checkReturn efx_rc_t
351 ef10_mac_multicast_list_set(
354 efx_port_t *epp = &(enp->en_port);
355 const efx_mac_ops_t *emop = epp->ep_emop;
358 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
359 enp->en_family == EFX_FAMILY_MEDFORD ||
360 enp->en_family == EFX_FAMILY_MEDFORD2);
362 if ((rc = emop->emo_reconfigure(enp)) != 0)
368 EFSYS_PROBE1(fail1, efx_rc_t, rc);
373 __checkReturn efx_rc_t
374 ef10_mac_filter_default_rxq_set(
377 __in boolean_t using_rss)
379 efx_port_t *epp = &(enp->en_port);
381 boolean_t old_using_rss;
384 ef10_filter_get_default_rxq(enp, &old_rxq, &old_using_rss);
386 ef10_filter_default_rxq_set(enp, erp, using_rss);
388 rc = efx_filter_reconfigure(enp, epp->ep_mac_addr,
389 epp->ep_all_unicst, epp->ep_mulcst,
390 epp->ep_all_mulcst, epp->ep_brdcst,
391 epp->ep_mulcst_addr_list,
392 epp->ep_mulcst_addr_count);
400 EFSYS_PROBE1(fail1, efx_rc_t, rc);
402 ef10_filter_default_rxq_set(enp, old_rxq, old_using_rss);
408 ef10_mac_filter_default_rxq_clear(
411 efx_port_t *epp = &(enp->en_port);
413 ef10_filter_default_rxq_clear(enp);
415 efx_filter_reconfigure(enp, epp->ep_mac_addr,
416 epp->ep_all_unicst, epp->ep_mulcst,
417 epp->ep_all_mulcst, epp->ep_brdcst,
418 epp->ep_mulcst_addr_list,
419 epp->ep_mulcst_addr_count);
423 #if EFSYS_OPT_LOOPBACK
425 __checkReturn efx_rc_t
426 ef10_mac_loopback_set(
428 __in efx_link_mode_t link_mode,
429 __in efx_loopback_type_t loopback_type)
431 efx_port_t *epp = &(enp->en_port);
432 const efx_phy_ops_t *epop = epp->ep_epop;
433 efx_loopback_type_t old_loopback_type;
434 efx_link_mode_t old_loopback_link_mode;
437 /* The PHY object handles this on EF10 */
438 old_loopback_type = epp->ep_loopback_type;
439 old_loopback_link_mode = epp->ep_loopback_link_mode;
440 epp->ep_loopback_type = loopback_type;
441 epp->ep_loopback_link_mode = link_mode;
443 if ((rc = epop->epo_reconfigure(enp)) != 0)
449 EFSYS_PROBE1(fail1, efx_rc_t, rc);
451 epp->ep_loopback_type = old_loopback_type;
452 epp->ep_loopback_link_mode = old_loopback_link_mode;
457 #endif /* EFSYS_OPT_LOOPBACK */
459 #if EFSYS_OPT_MAC_STATS
461 __checkReturn efx_rc_t
462 ef10_mac_stats_get_mask(
464 __inout_bcount(mask_size) uint32_t *maskp,
465 __in size_t mask_size)
467 const struct efx_mac_stats_range ef10_common[] = {
468 { EFX_MAC_RX_OCTETS, EFX_MAC_RX_GE_15XX_PKTS },
469 { EFX_MAC_RX_FCS_ERRORS, EFX_MAC_RX_DROP_EVENTS },
470 { EFX_MAC_RX_JABBER_PKTS, EFX_MAC_RX_JABBER_PKTS },
471 { EFX_MAC_RX_NODESC_DROP_CNT, EFX_MAC_TX_PAUSE_PKTS },
473 const struct efx_mac_stats_range ef10_tx_size_bins[] = {
474 { EFX_MAC_TX_LE_64_PKTS, EFX_MAC_TX_GE_15XX_PKTS },
476 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
477 efx_port_t *epp = &(enp->en_port);
480 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
481 ef10_common, EFX_ARRAY_SIZE(ef10_common))) != 0)
484 if (epp->ep_phy_cap_mask & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
485 const struct efx_mac_stats_range ef10_40g_extra[] = {
486 { EFX_MAC_RX_ALIGN_ERRORS, EFX_MAC_RX_ALIGN_ERRORS },
489 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
490 ef10_40g_extra, EFX_ARRAY_SIZE(ef10_40g_extra))) != 0)
493 if (encp->enc_mac_stats_40g_tx_size_bins) {
494 if ((rc = efx_mac_stats_mask_add_ranges(maskp,
495 mask_size, ef10_tx_size_bins,
496 EFX_ARRAY_SIZE(ef10_tx_size_bins))) != 0)
500 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
501 ef10_tx_size_bins, EFX_ARRAY_SIZE(ef10_tx_size_bins))) != 0)
505 if (encp->enc_pm_and_rxdp_counters) {
506 const struct efx_mac_stats_range ef10_pm_and_rxdp[] = {
507 { EFX_MAC_PM_TRUNC_BB_OVERFLOW, EFX_MAC_RXDP_HLB_WAIT },
510 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
511 ef10_pm_and_rxdp, EFX_ARRAY_SIZE(ef10_pm_and_rxdp))) != 0)
515 if (encp->enc_datapath_cap_evb) {
516 const struct efx_mac_stats_range ef10_vadaptor[] = {
517 { EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
518 EFX_MAC_VADAPTER_TX_OVERFLOW },
521 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
522 ef10_vadaptor, EFX_ARRAY_SIZE(ef10_vadaptor))) != 0)
526 if (encp->enc_fec_counters) {
527 const struct efx_mac_stats_range ef10_fec[] = {
528 { EFX_MAC_FEC_UNCORRECTED_ERRORS,
529 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3 },
531 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
532 ef10_fec, EFX_ARRAY_SIZE(ef10_fec))) != 0)
536 if (encp->enc_mac_stats_nstats >= MC_CMD_MAC_NSTATS_V4) {
537 const struct efx_mac_stats_range ef10_rxdp_sdt[] = {
538 { EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
539 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC },
542 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
543 ef10_rxdp_sdt, EFX_ARRAY_SIZE(ef10_rxdp_sdt))) != 0)
547 if (encp->enc_hlb_counters) {
548 const struct efx_mac_stats_range ef10_hlb[] = {
549 { EFX_MAC_RXDP_HLB_IDLE, EFX_MAC_RXDP_HLB_TIMEOUT },
551 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
552 ef10_hlb, EFX_ARRAY_SIZE(ef10_hlb))) != 0)
575 EFSYS_PROBE1(fail1, efx_rc_t, rc);
580 #define EF10_MAC_STAT_READ(_esmp, _field, _eqp) \
581 EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp)
584 __checkReturn efx_rc_t
585 ef10_mac_stats_update(
587 __in efsys_mem_t *esmp,
588 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
589 __inout_opt uint32_t *generationp)
591 const efx_nic_cfg_t *encp = &enp->en_nic_cfg;
592 efx_qword_t generation_start;
593 efx_qword_t generation_end;
598 * The MAC_STATS contain start and end generation counters used to
599 * detect when the DMA buffer has been updated during stats decode.
600 * All stats counters are 64bit unsigned values.
602 * Siena-compatible MAC stats contain MC_CMD_MAC_NSTATS 64bit counters.
603 * The generation end counter is at index MC_CMD_MAC_GENERATION_END
604 * (same as MC_CMD_MAC_NSTATS-1).
606 * Medford2 and later use a larger DMA buffer: MAC_STATS_NUM_STATS from
607 * MC_CMD_GET_CAPABILITIES_V4_OUT reports the number of 64bit counters.
609 * Firmware writes the generation end counter as the last counter in the
610 * DMA buffer. Do not use MC_CMD_MAC_GENERATION_END, as that is only
611 * correct for legacy Siena-compatible MAC stats.
614 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS) {
615 /* MAC stats count too small for legacy MAC stats */
619 if (EFSYS_MEM_SIZE(esmp) <
620 (encp->enc_mac_stats_nstats * sizeof (efx_qword_t))) {
621 /* DMA buffer too small */
626 /* Read END first so we don't race with the MC */
627 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp));
628 EF10_MAC_STAT_READ(esmp, (encp->enc_mac_stats_nstats - 1),
630 EFSYS_MEM_READ_BARRIER();
633 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PKTS, &value);
634 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value);
636 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_CONTROL_PKTS, &value);
637 EFSYS_STAT_SUBR_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value);
639 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PAUSE_PKTS, &value);
640 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PAUSE_PKTS]), &value);
642 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_UNICAST_PKTS, &value);
643 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_UNICST_PKTS]), &value);
645 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTICAST_PKTS, &value);
646 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULTICST_PKTS]), &value);
648 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BROADCAST_PKTS, &value);
649 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_BRDCST_PKTS]), &value);
651 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BYTES, &value);
652 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_OCTETS]), &value);
654 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LT64_PKTS, &value);
655 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value);
656 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_64_PKTS, &value);
657 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value);
659 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_65_TO_127_PKTS, &value);
660 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_65_TO_127_PKTS]), &value);
662 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_128_TO_255_PKTS, &value);
663 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_128_TO_255_PKTS]), &value);
665 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_256_TO_511_PKTS, &value);
666 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_256_TO_511_PKTS]), &value);
668 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_512_TO_1023_PKTS, &value);
669 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_512_TO_1023_PKTS]), &value);
671 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_1024_TO_15XX_PKTS, &value);
672 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_1024_TO_15XX_PKTS]), &value);
674 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS, &value);
675 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value);
676 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_GTJUMBO_PKTS, &value);
677 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value);
679 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BAD_FCS_PKTS, &value);
680 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_ERRORS]), &value);
682 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS, &value);
683 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_SGL_COL_PKTS]), &value);
685 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS,
687 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULT_COL_PKTS]), &value);
689 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS,
691 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_COL_PKTS]), &value);
693 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LATE_COLLISION_PKTS, &value);
694 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LATE_COL_PKTS]), &value);
696 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_DEFERRED_PKTS, &value);
697 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_DEF_PKTS]), &value);
699 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS,
701 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_DEF_PKTS]), &value);
704 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BYTES, &value);
705 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_OCTETS]), &value);
707 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PKTS, &value);
708 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PKTS]), &value);
710 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNICAST_PKTS, &value);
711 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_UNICST_PKTS]), &value);
713 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MULTICAST_PKTS, &value);
714 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MULTICST_PKTS]), &value);
716 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BROADCAST_PKTS, &value);
717 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_BRDCST_PKTS]), &value);
719 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PAUSE_PKTS, &value);
720 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PAUSE_PKTS]), &value);
722 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNDERSIZE_PKTS, &value);
723 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value);
724 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_64_PKTS, &value);
725 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value);
727 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_65_TO_127_PKTS, &value);
728 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_65_TO_127_PKTS]), &value);
730 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_128_TO_255_PKTS, &value);
731 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_128_TO_255_PKTS]), &value);
733 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_256_TO_511_PKTS, &value);
734 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_256_TO_511_PKTS]), &value);
736 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_512_TO_1023_PKTS, &value);
737 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_512_TO_1023_PKTS]), &value);
739 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_1024_TO_15XX_PKTS, &value);
740 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_1024_TO_15XX_PKTS]), &value);
742 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS, &value);
743 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value);
744 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_GTJUMBO_PKTS, &value);
745 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value);
747 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BAD_FCS_PKTS, &value);
748 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FCS_ERRORS]), &value);
750 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_OVERFLOW_PKTS, &value);
751 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_DROP_EVENTS]), &value);
753 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_FALSE_CARRIER_PKTS, &value);
754 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FALSE_CARRIER_ERRORS]), &value);
756 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS, &value);
757 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_SYMBOL_ERRORS]), &value);
759 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_ALIGN_ERROR_PKTS, &value);
760 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_ALIGN_ERRORS]), &value);
762 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS, &value);
763 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_INTERNAL_ERRORS]), &value);
765 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_JABBER_PKTS, &value);
766 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_JABBER_PKTS]), &value);
768 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_CHAR_ERR, &value);
769 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_CHAR_ERR]),
770 &(value.eq_dword[0]));
771 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_CHAR_ERR]),
772 &(value.eq_dword[1]));
774 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_CHAR_ERR, &value);
775 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_CHAR_ERR]),
776 &(value.eq_dword[0]));
777 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_CHAR_ERR]),
778 &(value.eq_dword[1]));
780 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_DISP_ERR, &value);
781 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_DISP_ERR]),
782 &(value.eq_dword[0]));
783 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_DISP_ERR]),
784 &(value.eq_dword[1]));
786 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_DISP_ERR, &value);
787 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_DISP_ERR]),
788 &(value.eq_dword[0]));
789 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_DISP_ERR]),
790 &(value.eq_dword[1]));
792 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MATCH_FAULT, &value);
793 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MATCH_FAULT]), &value);
795 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_NODESC_DROPS, &value);
796 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_NODESC_DROP_CNT]), &value);
798 /* Packet memory (EF10 only) */
799 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW, &value);
800 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_TRUNC_BB_OVERFLOW]), &value);
802 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW, &value);
803 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_BB_OVERFLOW]), &value);
805 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_TRUNC_VFIFO_FULL, &value);
806 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_TRUNC_VFIFO_FULL]), &value);
808 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_VFIFO_FULL, &value);
809 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_VFIFO_FULL]), &value);
811 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_TRUNC_QBB, &value);
812 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_TRUNC_QBB]), &value);
814 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_QBB, &value);
815 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_QBB]), &value);
817 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_MAPPING, &value);
818 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_MAPPING]), &value);
821 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_Q_DISABLED_PKTS, &value);
822 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_Q_DISABLED_PKTS]), &value);
824 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_DI_DROPPED_PKTS, &value);
825 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_DI_DROPPED_PKTS]), &value);
827 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_STREAMING_PKTS, &value);
828 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_STREAMING_PKTS]), &value);
830 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS, &value);
831 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_FETCH]), &value);
833 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS, &value);
834 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_WAIT]), &value);
838 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS,
840 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_UNICAST_PACKETS]),
843 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES,
845 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_UNICAST_BYTES]),
848 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS,
850 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS]),
853 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES,
855 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_MULTICAST_BYTES]),
858 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS,
860 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS]),
863 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES,
865 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BROADCAST_BYTES]),
868 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS,
870 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BAD_PACKETS]),
873 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BAD_BYTES, &value);
874 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BAD_BYTES]), &value);
876 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_OVERFLOW, &value);
877 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_OVERFLOW]), &value);
880 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS,
882 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_UNICAST_PACKETS]),
885 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES,
887 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_UNICAST_BYTES]),
890 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS,
892 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS]),
895 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES,
897 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_MULTICAST_BYTES]),
900 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS,
902 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS]),
905 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES,
907 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BROADCAST_BYTES]),
910 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS, &value);
911 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BAD_PACKETS]), &value);
913 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BAD_BYTES, &value);
914 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BAD_BYTES]), &value);
916 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_OVERFLOW, &value);
917 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_OVERFLOW]), &value);
920 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS_V2)
924 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_UNCORRECTED_ERRORS, &value);
925 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_UNCORRECTED_ERRORS]), &value);
927 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_CORRECTED_ERRORS, &value);
928 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_CORRECTED_ERRORS]), &value);
930 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
932 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0]),
935 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
937 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1]),
940 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
942 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2]),
945 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
947 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3]),
950 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS_V3)
953 /* CTPIO exceptions */
954 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK, &value);
955 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_VI_BUSY_FALLBACK]), &value);
957 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS, &value);
958 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_LONG_WRITE_SUCCESS]), &value);
960 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL, &value);
961 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_MISSING_DBELL_FAIL]), &value);
963 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_OVERFLOW_FAIL, &value);
964 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_OVERFLOW_FAIL]), &value);
966 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL, &value);
967 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_UNDERFLOW_FAIL]), &value);
969 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_TIMEOUT_FAIL, &value);
970 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_TIMEOUT_FAIL]), &value);
972 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL, &value);
973 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_NONCONTIG_WR_FAIL]), &value);
975 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL, &value);
976 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_FRM_CLOBBER_FAIL]), &value);
978 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_INVALID_WR_FAIL, &value);
979 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_INVALID_WR_FAIL]), &value);
981 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK, &value);
982 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK]),
985 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK, &value);
986 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK]),
989 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_RUNT_FALLBACK, &value);
990 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_RUNT_FALLBACK]), &value);
992 /* CTPIO per-port stats */
993 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_SUCCESS, &value);
994 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_SUCCESS]), &value);
996 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_FALLBACK, &value);
997 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_FALLBACK]), &value);
999 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_POISON, &value);
1000 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_POISON]), &value);
1002 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_ERASE, &value);
1003 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_ERASE]), &value);
1005 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS_V4)
1008 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_SCATTER_DISABLED_TRUNC,
1010 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC]),
1013 /* Head-of-line blocking */
1014 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_IDLE, &value);
1015 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_IDLE]), &value);
1017 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_TIMEOUT, &value);
1018 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_TIMEOUT]), &value);
1021 /* Read START generation counter */
1022 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp));
1023 EFSYS_MEM_READ_BARRIER();
1024 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_START,
1027 /* Check that we didn't read the stats in the middle of a DMA */
1028 /* Not a good enough check ? */
1029 if (memcmp(&generation_start, &generation_end,
1030 sizeof (generation_start)))
1034 *generationp = EFX_QWORD_FIELD(generation_start, EFX_DWORD_0);
1041 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1046 #endif /* EFSYS_OPT_MAC_STATS */
1048 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */