drivers/net/sfc/base/ef10_mac.c

   1 /*
   2  * Copyright (c) 2012-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #include "efx.h"
  32 #include "efx_impl.h"
  33
  34
  35 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
  36
  37         __checkReturn   efx_rc_t
  38 ef10_mac_poll(
  39         __in            efx_nic_t *enp,
  40         __out           efx_link_mode_t *link_modep)
  41 {
  42         efx_port_t *epp = &(enp->en_port);
  43         ef10_link_state_t els;
  44         efx_rc_t rc;
  45
  46         if ((rc = ef10_phy_get_link(enp, &els)) != 0)
  47                 goto fail1;
  48
  49         epp->ep_adv_cap_mask = els.els_adv_cap_mask;
  50         epp->ep_fcntl = els.els_fcntl;
  51
  52         *link_modep = els.els_link_mode;
  53
  54         return (0);
  55
  56 fail1:
  57         EFSYS_PROBE1(fail1, efx_rc_t, rc);
  58
  59         *link_modep = EFX_LINK_UNKNOWN;
  60
  61         return (rc);
  62 }
  63
  64         __checkReturn   efx_rc_t
  65 ef10_mac_up(
  66         __in            efx_nic_t *enp,
  67         __out           boolean_t *mac_upp)
  68 {
  69         ef10_link_state_t els;
  70         efx_rc_t rc;
  71
  72         /*
  73          * Because EF10 doesn't *require* polling, we can't rely on
  74          * ef10_mac_poll() being executed to populate epp->ep_mac_up.
  75          */
  76         if ((rc = ef10_phy_get_link(enp, &els)) != 0)
  77                 goto fail1;
  78
  79         *mac_upp = els.els_mac_up;
  80
  81         return (0);
  82
  83 fail1:
  84         EFSYS_PROBE1(fail1, efx_rc_t, rc);
  85
  86         return (rc);
  87 }
  88
  89 /*
  90  * EF10 adapters use MC_CMD_VADAPTOR_SET_MAC to set the
  91  * MAC address; the address field in MC_CMD_SET_MAC has no
  92  * effect.
  93  * MC_CMD_VADAPTOR_SET_MAC requires mac-spoofing privilege and
  94  * the port to have no filters or queues active.
  95  */
  96 static  __checkReturn   efx_rc_t
  97 efx_mcdi_vadapter_set_mac(
  98         __in            efx_nic_t *enp)
  99 {
 100         efx_port_t *epp = &(enp->en_port);
 101         efx_mcdi_req_t req;
 102         uint8_t payload[MAX(MC_CMD_VADAPTOR_SET_MAC_IN_LEN,
 103                             MC_CMD_VADAPTOR_SET_MAC_OUT_LEN)];
 104         efx_rc_t rc;
 105
 106         (void) memset(payload, 0, sizeof (payload));
 107         req.emr_cmd = MC_CMD_VADAPTOR_SET_MAC;
 108         req.emr_in_buf = payload;
 109         req.emr_in_length = MC_CMD_VADAPTOR_SET_MAC_IN_LEN;
 110         req.emr_out_buf = payload;
 111         req.emr_out_length = MC_CMD_VADAPTOR_SET_MAC_OUT_LEN;
 112
 113         MCDI_IN_SET_DWORD(req, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
 114             enp->en_vport_id);
 115         EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, VADAPTOR_SET_MAC_IN_MACADDR),
 116             epp->ep_mac_addr);
 117
 118         efx_mcdi_execute(enp, &req);
 119
 120         if (req.emr_rc != 0) {
 121                 rc = req.emr_rc;
 122                 goto fail1;
 123         }
 124
 125         return (0);
 126
 127 fail1:
 128         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 129
 130         return (rc);
 131 }
 132
 133         __checkReturn   efx_rc_t
 134 ef10_mac_addr_set(
 135         __in            efx_nic_t *enp)
 136 {
 137         efx_rc_t rc;
 138
 139         if ((rc = efx_mcdi_vadapter_set_mac(enp)) != 0) {
 140                 if (rc != ENOTSUP)
 141                         goto fail1;
 142
 143                 /*
 144                  * Fallback for older Huntington firmware without Vadapter
 145                  * support.
 146                  */
 147                 if ((rc = ef10_mac_reconfigure(enp)) != 0)
 148                         goto fail2;
 149         }
 150
 151         return (0);
 152
 153 fail2:
 154         EFSYS_PROBE(fail2);
 155
 156 fail1:
 157         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 158
 159         return (rc);
 160 }
 161
 162 static  __checkReturn   efx_rc_t
 163 efx_mcdi_mtu_set(
 164         __in            efx_nic_t *enp,
 165         __in            uint32_t mtu)
 166 {
 167         efx_mcdi_req_t req;
 168         uint8_t payload[MAX(MC_CMD_SET_MAC_EXT_IN_LEN,
 169                             MC_CMD_SET_MAC_OUT_LEN)];
 170         efx_rc_t rc;
 171
 172         (void) memset(payload, 0, sizeof (payload));
 173         req.emr_cmd = MC_CMD_SET_MAC;
 174         req.emr_in_buf = payload;
 175         req.emr_in_length = MC_CMD_SET_MAC_EXT_IN_LEN;
 176         req.emr_out_buf = payload;
 177         req.emr_out_length = MC_CMD_SET_MAC_OUT_LEN;
 178
 179         /* Only configure the MTU in this call to MC_CMD_SET_MAC */
 180         MCDI_IN_SET_DWORD(req, SET_MAC_EXT_IN_MTU, mtu);
 181         MCDI_IN_POPULATE_DWORD_1(req, SET_MAC_EXT_IN_CONTROL,
 182                             SET_MAC_EXT_IN_CFG_MTU, 1);
 183
 184         efx_mcdi_execute(enp, &req);
 185
 186         if (req.emr_rc != 0) {
 187                 rc = req.emr_rc;
 188                 goto fail1;
 189         }
 190
 191         return (0);
 192
 193 fail1:
 194         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 195
 196         return (rc);
 197 }
 198
 199 static  __checkReturn           efx_rc_t
 200 efx_mcdi_mtu_get(
 201         __in            efx_nic_t *enp,
 202         __out           size_t *mtu)
 203 {
 204         efx_mcdi_req_t req;
 205         uint8_t payload[MAX(MC_CMD_SET_MAC_EXT_IN_LEN,
 206                             MC_CMD_SET_MAC_V2_OUT_LEN)];
 207         efx_rc_t rc;
 208
 209         (void) memset(payload, 0, sizeof (payload));
 210         req.emr_cmd = MC_CMD_SET_MAC;
 211         req.emr_in_buf = payload;
 212         req.emr_in_length = MC_CMD_SET_MAC_EXT_IN_LEN;
 213         req.emr_out_buf = payload;
 214         req.emr_out_length = MC_CMD_SET_MAC_V2_OUT_LEN;
 215
 216         /*
 217          * With MC_CMD_SET_MAC_EXT_IN_CONTROL set to 0, this just queries the
 218          * MTU.  This should always be supported on Medford, but it is not
 219          * supported on older Huntington firmware.
 220          */
 221         MCDI_IN_SET_DWORD(req, SET_MAC_EXT_IN_CONTROL, 0);
 222
 223         efx_mcdi_execute(enp, &req);
 224
 225         if (req.emr_rc != 0) {
 226                 rc = req.emr_rc;
 227                 goto fail1;
 228         }
 229         if (req.emr_out_length_used < MC_CMD_SET_MAC_V2_OUT_MTU_OFST + 4) {
 230                 rc = EMSGSIZE;
 231                 goto fail2;
 232         }
 233
 234         *mtu = MCDI_OUT_DWORD(req, SET_MAC_V2_OUT_MTU);
 235
 236         return (0);
 237
 238 fail2:
 239         EFSYS_PROBE(fail2);
 240 fail1:
 241         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 242
 243         return (rc);
 244 }
 245
 246         __checkReturn   efx_rc_t
 247 ef10_mac_pdu_set(
 248         __in            efx_nic_t *enp)
 249 {
 250         efx_port_t *epp = &(enp->en_port);
 251         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 252         efx_rc_t rc;
 253
 254         if (encp->enc_enhanced_set_mac_supported) {
 255                 if ((rc = efx_mcdi_mtu_set(enp, epp->ep_mac_pdu)) != 0)
 256                         goto fail1;
 257         } else {
 258                 /*
 259                  * Fallback for older Huntington firmware, which always
 260                  * configure all of the parameters to MC_CMD_SET_MAC. This isn't
 261                  * suitable for setting the MTU on unpriviliged functions.
 262                  */
 263                 if ((rc = ef10_mac_reconfigure(enp)) != 0)
 264                         goto fail2;
 265         }
 266
 267         return (0);
 268
 269 fail2:
 270         EFSYS_PROBE(fail2);
 271 fail1:
 272         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 273
 274         return (rc);
 275 }
 276
 277         __checkReturn           efx_rc_t
 278 ef10_mac_pdu_get(
 279         __in            efx_nic_t *enp,
 280         __out           size_t *pdu)
 281 {
 282         efx_rc_t rc;
 283
 284         if ((rc = efx_mcdi_mtu_get(enp, pdu)) != 0)
 285                 goto fail1;
 286
 287         return (0);
 288
 289 fail1:
 290         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 291
 292         return (rc);
 293 }
 294
 295 __checkReturn   efx_rc_t
 296 ef10_mac_reconfigure(
 297         __in            efx_nic_t *enp)
 298 {
 299         efx_port_t *epp = &(enp->en_port);
 300         efx_mcdi_req_t req;
 301         uint8_t payload[MAX(MC_CMD_SET_MAC_IN_LEN,
 302                             MC_CMD_SET_MAC_OUT_LEN)];
 303         efx_rc_t rc;
 304
 305         (void) memset(payload, 0, sizeof (payload));
 306         req.emr_cmd = MC_CMD_SET_MAC;
 307         req.emr_in_buf = payload;
 308         req.emr_in_length = MC_CMD_SET_MAC_IN_LEN;
 309         req.emr_out_buf = payload;
 310         req.emr_out_length = MC_CMD_SET_MAC_OUT_LEN;
 311
 312         MCDI_IN_SET_DWORD(req, SET_MAC_IN_MTU, epp->ep_mac_pdu);
 313         MCDI_IN_SET_DWORD(req, SET_MAC_IN_DRAIN, epp->ep_mac_drain ? 1 : 0);
 314         EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, SET_MAC_IN_ADDR),
 315                             epp->ep_mac_addr);
 316
 317         /*
 318          * Note: The Huntington MAC does not support REJECT_BRDCST.
 319          * The REJECT_UNCST flag will also prevent multicast traffic
 320          * from reaching the filters. As Huntington filters drop any
 321          * traffic that does not match a filter it is ok to leave the
 322          * MAC running in promiscuous mode. See bug41141.
 323          *
 324          * FIXME: Does REJECT_UNCST behave the same way on Medford?
 325          */
 326         MCDI_IN_POPULATE_DWORD_2(req, SET_MAC_IN_REJECT,
 327                                     SET_MAC_IN_REJECT_UNCST, 0,
 328                                     SET_MAC_IN_REJECT_BRDCST, 0);
 329
 330         /*
 331          * Flow control, whether it is auto-negotiated or not,
 332          * is set via the PHY advertised capabilities.  When set to
 333          * automatic the MAC will use the PHY settings to determine
 334          * the flow control settings.
 335          */
 336         MCDI_IN_SET_DWORD(req, SET_MAC_IN_FCNTL, MC_CMD_FCNTL_AUTO);
 337
 338         /* Do not include the Ethernet frame checksum in RX packets */
 339         MCDI_IN_POPULATE_DWORD_1(req, SET_MAC_IN_FLAGS,
 340                                     SET_MAC_IN_FLAG_INCLUDE_FCS, 0);
 341
 342         efx_mcdi_execute_quiet(enp, &req);
 343
 344         if (req.emr_rc != 0) {
 345                 /*
 346                  * Unprivileged functions cannot control link state,
 347                  * but still need to configure filters.
 348                  */
 349                 if (req.emr_rc != EACCES) {
 350                         rc = req.emr_rc;
 351                         goto fail1;
 352                 }
 353         }
 354
 355         /*
 356          * Apply the filters for the MAC configuration.
 357          * If the NIC isn't ready to accept filters this may
 358          * return success without setting anything.
 359          */
 360         rc = efx_filter_reconfigure(enp, epp->ep_mac_addr,
 361                                     epp->ep_all_unicst, epp->ep_mulcst,
 362                                     epp->ep_all_mulcst, epp->ep_brdcst,
 363                                     epp->ep_mulcst_addr_list,
 364                                     epp->ep_mulcst_addr_count);
 365
 366         return (0);
 367
 368 fail1:
 369         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 370
 371         return (rc);
 372 }
 373
 374         __checkReturn                   efx_rc_t
 375 ef10_mac_multicast_list_set(
 376         __in                            efx_nic_t *enp)
 377 {
 378         efx_port_t *epp = &(enp->en_port);
 379         const efx_mac_ops_t *emop = epp->ep_emop;
 380         efx_rc_t rc;
 381
 382         EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
 383                     enp->en_family == EFX_FAMILY_MEDFORD);
 384
 385         if ((rc = emop->emo_reconfigure(enp)) != 0)
 386                 goto fail1;
 387
 388         return (0);
 389
 390 fail1:
 391         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 392
 393         return (rc);
 394 }
 395
 396         __checkReturn   efx_rc_t
 397 ef10_mac_filter_default_rxq_set(
 398         __in            efx_nic_t *enp,
 399         __in            efx_rxq_t *erp,
 400         __in            boolean_t using_rss)
 401 {
 402         efx_port_t *epp = &(enp->en_port);
 403         efx_rxq_t *old_rxq;
 404         boolean_t old_using_rss;
 405         efx_rc_t rc;
 406
 407         ef10_filter_get_default_rxq(enp, &old_rxq, &old_using_rss);
 408
 409         ef10_filter_default_rxq_set(enp, erp, using_rss);
 410
 411         rc = efx_filter_reconfigure(enp, epp->ep_mac_addr,
 412                                     epp->ep_all_unicst, epp->ep_mulcst,
 413                                     epp->ep_all_mulcst, epp->ep_brdcst,
 414                                     epp->ep_mulcst_addr_list,
 415                                     epp->ep_mulcst_addr_count);
 416
 417         if (rc != 0)
 418                 goto fail1;
 419
 420         return (0);
 421
 422 fail1:
 423         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 424
 425         ef10_filter_default_rxq_set(enp, old_rxq, old_using_rss);
 426
 427         return (rc);
 428 }
 429
 430                         void
 431 ef10_mac_filter_default_rxq_clear(
 432         __in            efx_nic_t *enp)
 433 {
 434         efx_port_t *epp = &(enp->en_port);
 435
 436         ef10_filter_default_rxq_clear(enp);
 437
 438         efx_filter_reconfigure(enp, epp->ep_mac_addr,
 439                                     epp->ep_all_unicst, epp->ep_mulcst,
 440                                     epp->ep_all_mulcst, epp->ep_brdcst,
 441                                     epp->ep_mulcst_addr_list,
 442                                     epp->ep_mulcst_addr_count);
 443 }
 444
 445
 446 #if EFSYS_OPT_MAC_STATS
 447
 448         __checkReturn                   efx_rc_t
 449 ef10_mac_stats_get_mask(
 450         __in                            efx_nic_t *enp,
 451         __inout_bcount(mask_size)       uint32_t *maskp,
 452         __in                            size_t mask_size)
 453 {
 454         const struct efx_mac_stats_range ef10_common[] = {
 455                 { EFX_MAC_RX_OCTETS, EFX_MAC_RX_GE_15XX_PKTS },
 456                 { EFX_MAC_RX_FCS_ERRORS, EFX_MAC_RX_DROP_EVENTS },
 457                 { EFX_MAC_RX_JABBER_PKTS, EFX_MAC_RX_JABBER_PKTS },
 458                 { EFX_MAC_RX_NODESC_DROP_CNT, EFX_MAC_TX_PAUSE_PKTS },
 459         };
 460         const struct efx_mac_stats_range ef10_tx_size_bins[] = {
 461                 { EFX_MAC_TX_LE_64_PKTS, EFX_MAC_TX_GE_15XX_PKTS },
 462         };
 463         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 464         efx_port_t *epp = &(enp->en_port);
 465         efx_rc_t rc;
 466
 467         if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
 468             ef10_common, EFX_ARRAY_SIZE(ef10_common))) != 0)
 469                 goto fail1;
 470
 471         if (epp->ep_phy_cap_mask & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
 472                 const struct efx_mac_stats_range ef10_40g_extra[] = {
 473                         { EFX_MAC_RX_ALIGN_ERRORS, EFX_MAC_RX_ALIGN_ERRORS },
 474                 };
 475
 476                 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
 477                     ef10_40g_extra, EFX_ARRAY_SIZE(ef10_40g_extra))) != 0)
 478                         goto fail2;
 479
 480                 if (encp->enc_mac_stats_40g_tx_size_bins) {
 481                         if ((rc = efx_mac_stats_mask_add_ranges(maskp,
 482                             mask_size, ef10_tx_size_bins,
 483                             EFX_ARRAY_SIZE(ef10_tx_size_bins))) != 0)
 484                                 goto fail3;
 485                 }
 486         } else {
 487                 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
 488                     ef10_tx_size_bins, EFX_ARRAY_SIZE(ef10_tx_size_bins))) != 0)
 489                         goto fail4;
 490         }
 491
 492         if (encp->enc_pm_and_rxdp_counters) {
 493                 const struct efx_mac_stats_range ef10_pm_and_rxdp[] = {
 494                         { EFX_MAC_PM_TRUNC_BB_OVERFLOW, EFX_MAC_RXDP_HLB_WAIT },
 495                 };
 496
 497                 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
 498                     ef10_pm_and_rxdp, EFX_ARRAY_SIZE(ef10_pm_and_rxdp))) != 0)
 499                         goto fail5;
 500         }
 501
 502         if (encp->enc_datapath_cap_evb) {
 503                 const struct efx_mac_stats_range ef10_vadaptor[] = {
 504                         { EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
 505                             EFX_MAC_VADAPTER_TX_OVERFLOW },
 506                 };
 507
 508                 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
 509                     ef10_vadaptor, EFX_ARRAY_SIZE(ef10_vadaptor))) != 0)
 510                         goto fail6;
 511         }
 512
 513         return (0);
 514
 515 fail6:
 516         EFSYS_PROBE(fail6);
 517 fail5:
 518         EFSYS_PROBE(fail5);
 519 fail4:
 520         EFSYS_PROBE(fail4);
 521 fail3:
 522         EFSYS_PROBE(fail3);
 523 fail2:
 524         EFSYS_PROBE(fail2);
 525 fail1:
 526         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 527
 528         return (rc);
 529 }
 530
 531 #define EF10_MAC_STAT_READ(_esmp, _field, _eqp)                 \
 532         EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp)
 533
 534
 535         __checkReturn                   efx_rc_t
 536 ef10_mac_stats_update(
 537         __in                            efx_nic_t *enp,
 538         __in                            efsys_mem_t *esmp,
 539         __inout_ecount(EFX_MAC_NSTATS)  efsys_stat_t *stat,
 540         __inout_opt                     uint32_t *generationp)
 541 {
 542         efx_qword_t value;
 543         efx_qword_t generation_start;
 544         efx_qword_t generation_end;
 545
 546         _NOTE(ARGUNUSED(enp))
 547
 548         /* Read END first so we don't race with the MC */
 549         EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFX_MAC_STATS_SIZE);
 550         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_END,
 551                             &generation_end);
 552         EFSYS_MEM_READ_BARRIER();
 553
 554         /* TX */
 555         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PKTS, &value);
 556         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value);
 557
 558         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_CONTROL_PKTS, &value);
 559         EFSYS_STAT_SUBR_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value);
 560
 561         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PAUSE_PKTS, &value);
 562         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PAUSE_PKTS]), &value);
 563
 564         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_UNICAST_PKTS, &value);
 565         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_UNICST_PKTS]), &value);
 566
 567         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTICAST_PKTS, &value);
 568         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULTICST_PKTS]), &value);
 569
 570         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BROADCAST_PKTS, &value);
 571         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_BRDCST_PKTS]), &value);
 572
 573         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BYTES, &value);
 574         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_OCTETS]), &value);
 575
 576         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LT64_PKTS, &value);
 577         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value);
 578         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_64_PKTS, &value);
 579         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value);
 580
 581         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_65_TO_127_PKTS, &value);
 582         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_65_TO_127_PKTS]), &value);
 583
 584         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_128_TO_255_PKTS, &value);
 585         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_128_TO_255_PKTS]), &value);
 586
 587         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_256_TO_511_PKTS, &value);
 588         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_256_TO_511_PKTS]), &value);
 589
 590         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_512_TO_1023_PKTS, &value);
 591         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_512_TO_1023_PKTS]), &value);
 592
 593         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_1024_TO_15XX_PKTS, &value);
 594         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_1024_TO_15XX_PKTS]), &value);
 595
 596         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS, &value);
 597         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value);
 598         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_GTJUMBO_PKTS, &value);
 599         EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value);
 600
 601         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BAD_FCS_PKTS, &value);
 602         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_ERRORS]), &value);
 603
 604         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS, &value);
 605         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_SGL_COL_PKTS]), &value);
 606
 607         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS,
 608                             &value);
 609         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULT_COL_PKTS]), &value);
 610
 611         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS,
 612                             &value);
 613         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_COL_PKTS]), &value);
 614
 615         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LATE_COLLISION_PKTS, &value);
 616         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LATE_COL_PKTS]), &value);
 617
 618         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_DEFERRED_PKTS, &value);
 619         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_DEF_PKTS]), &value);
 620
 621         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS,
 622             &value);
 623         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_DEF_PKTS]), &value);
 624
 625         /* RX */
 626         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BYTES, &value);
 627         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_OCTETS]), &value);
 628
 629         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PKTS, &value);
 630         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PKTS]), &value);
 631
 632         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNICAST_PKTS, &value);
 633         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_UNICST_PKTS]), &value);
 634
 635         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MULTICAST_PKTS, &value);
 636         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MULTICST_PKTS]), &value);
 637
 638         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BROADCAST_PKTS, &value);
 639         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_BRDCST_PKTS]), &value);
 640
 641         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PAUSE_PKTS, &value);
 642         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PAUSE_PKTS]), &value);
 643
 644         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNDERSIZE_PKTS, &value);
 645         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value);
 646         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_64_PKTS, &value);
 647         EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value);
 648
 649         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_65_TO_127_PKTS, &value);
 650         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_65_TO_127_PKTS]), &value);
 651
 652         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_128_TO_255_PKTS, &value);
 653         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_128_TO_255_PKTS]), &value);
 654
 655         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_256_TO_511_PKTS, &value);
 656         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_256_TO_511_PKTS]), &value);
 657
 658         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_512_TO_1023_PKTS, &value);
 659         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_512_TO_1023_PKTS]), &value);
 660
 661         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_1024_TO_15XX_PKTS, &value);
 662         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_1024_TO_15XX_PKTS]), &value);
 663
 664         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS, &value);
 665         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value);
 666         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_GTJUMBO_PKTS, &value);
 667         EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value);
 668
 669         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BAD_FCS_PKTS, &value);
 670         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FCS_ERRORS]), &value);
 671
 672         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_OVERFLOW_PKTS, &value);
 673         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_DROP_EVENTS]), &value);
 674
 675         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_FALSE_CARRIER_PKTS, &value);
 676         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FALSE_CARRIER_ERRORS]), &value);
 677
 678         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS, &value);
 679         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_SYMBOL_ERRORS]), &value);
 680
 681         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_ALIGN_ERROR_PKTS, &value);
 682         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_ALIGN_ERRORS]), &value);
 683
 684         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS, &value);
 685         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_INTERNAL_ERRORS]), &value);
 686
 687         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_JABBER_PKTS, &value);
 688         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_JABBER_PKTS]), &value);
 689
 690         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_CHAR_ERR, &value);
 691         EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_CHAR_ERR]),
 692                             &(value.eq_dword[0]));
 693         EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_CHAR_ERR]),
 694                             &(value.eq_dword[1]));
 695
 696         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_CHAR_ERR, &value);
 697         EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_CHAR_ERR]),
 698                             &(value.eq_dword[0]));
 699         EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_CHAR_ERR]),
 700                             &(value.eq_dword[1]));
 701
 702         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_DISP_ERR, &value);
 703         EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_DISP_ERR]),
 704                             &(value.eq_dword[0]));
 705         EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_DISP_ERR]),
 706                             &(value.eq_dword[1]));
 707
 708         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_DISP_ERR, &value);
 709         EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_DISP_ERR]),
 710                             &(value.eq_dword[0]));
 711         EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_DISP_ERR]),
 712                             &(value.eq_dword[1]));
 713
 714         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MATCH_FAULT, &value);
 715         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MATCH_FAULT]), &value);
 716
 717         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_NODESC_DROPS, &value);
 718         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_NODESC_DROP_CNT]), &value);
 719
 720         /* Packet memory (EF10 only) */
 721         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW, &value);
 722         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_TRUNC_BB_OVERFLOW]), &value);
 723
 724         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW, &value);
 725         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_BB_OVERFLOW]), &value);
 726
 727         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_TRUNC_VFIFO_FULL, &value);
 728         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_TRUNC_VFIFO_FULL]), &value);
 729
 730         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_VFIFO_FULL, &value);
 731         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_VFIFO_FULL]), &value);
 732
 733         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_TRUNC_QBB, &value);
 734         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_TRUNC_QBB]), &value);
 735
 736         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_QBB, &value);
 737         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_QBB]), &value);
 738
 739         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_MAPPING, &value);
 740         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_MAPPING]), &value);
 741
 742         /* RX datapath */
 743         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_Q_DISABLED_PKTS, &value);
 744         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_Q_DISABLED_PKTS]), &value);
 745
 746         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_DI_DROPPED_PKTS, &value);
 747         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_DI_DROPPED_PKTS]), &value);
 748
 749         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_STREAMING_PKTS, &value);
 750         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_STREAMING_PKTS]), &value);
 751
 752         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS, &value);
 753         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_FETCH]), &value);
 754
 755         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS, &value);
 756         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_WAIT]), &value);
 757
 758
 759         /* VADAPTER RX */
 760         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS,
 761             &value);
 762         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_UNICAST_PACKETS]),
 763             &value);
 764
 765         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES,
 766             &value);
 767         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_UNICAST_BYTES]),
 768             &value);
 769
 770         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS,
 771             &value);
 772         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS]),
 773             &value);
 774
 775         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES,
 776             &value);
 777         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_MULTICAST_BYTES]),
 778             &value);
 779
 780         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS,
 781             &value);
 782         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS]),
 783             &value);
 784
 785         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES,
 786             &value);
 787         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BROADCAST_BYTES]),
 788             &value);
 789
 790         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS,
 791             &value);
 792         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BAD_PACKETS]),
 793             &value);
 794
 795         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BAD_BYTES, &value);
 796         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BAD_BYTES]), &value);
 797
 798         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_OVERFLOW, &value);
 799         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_OVERFLOW]), &value);
 800
 801         /* VADAPTER TX */
 802         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS,
 803             &value);
 804         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_UNICAST_PACKETS]),
 805             &value);
 806
 807         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES,
 808             &value);
 809         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_UNICAST_BYTES]),
 810             &value);
 811
 812         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS,
 813             &value);
 814         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS]),
 815             &value);
 816
 817         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES,
 818             &value);
 819         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_MULTICAST_BYTES]),
 820             &value);
 821
 822         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS,
 823             &value);
 824         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS]),
 825             &value);
 826
 827         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES,
 828             &value);
 829         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BROADCAST_BYTES]),
 830             &value);
 831
 832         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS, &value);
 833         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BAD_PACKETS]), &value);
 834
 835         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BAD_BYTES, &value);
 836         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BAD_BYTES]), &value);
 837
 838         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_OVERFLOW, &value);
 839         EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_OVERFLOW]), &value);
 840
 841
 842         EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFX_MAC_STATS_SIZE);
 843         EFSYS_MEM_READ_BARRIER();
 844         EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_START,
 845                             &generation_start);
 846
 847         /* Check that we didn't read the stats in the middle of a DMA */
 848         /* Not a good enough check ? */
 849         if (memcmp(&generation_start, &generation_end,
 850             sizeof (generation_start)))
 851                 return (EAGAIN);
 852
 853         if (generationp)
 854                 *generationp = EFX_QWORD_FIELD(generation_start, EFX_DWORD_0);
 855
 856         return (0);
 857 }
 858
 859 #endif  /* EFSYS_OPT_MAC_STATS */
 860
 861 #endif  /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */