1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
15 #include "ef10_tlv_layout.h"
17 __checkReturn efx_rc_t
18 efx_mcdi_get_port_assignment(
20 __out uint32_t *portp)
23 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
24 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN);
27 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
29 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
30 req.emr_in_buf = payload;
31 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
32 req.emr_out_buf = payload;
33 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
35 efx_mcdi_execute(enp, &req);
37 if (req.emr_rc != 0) {
42 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
47 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
54 EFSYS_PROBE1(fail1, efx_rc_t, rc);
59 __checkReturn efx_rc_t
60 efx_mcdi_get_port_modes(
62 __out uint32_t *modesp,
63 __out_opt uint32_t *current_modep,
64 __out_opt uint32_t *default_modep)
67 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_MODES_IN_LEN,
68 MC_CMD_GET_PORT_MODES_OUT_LEN);
71 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
73 req.emr_cmd = MC_CMD_GET_PORT_MODES;
74 req.emr_in_buf = payload;
75 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
76 req.emr_out_buf = payload;
77 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
79 efx_mcdi_execute(enp, &req);
81 if (req.emr_rc != 0) {
87 * Require only Modes and DefaultMode fields, unless the current mode
88 * was requested (CurrentMode field was added for Medford).
90 if (req.emr_out_length_used <
91 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
95 if ((current_modep != NULL) && (req.emr_out_length_used <
96 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) {
101 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
103 if (current_modep != NULL) {
104 *current_modep = MCDI_OUT_DWORD(req,
105 GET_PORT_MODES_OUT_CURRENT_MODE);
108 if (default_modep != NULL) {
109 *default_modep = MCDI_OUT_DWORD(req,
110 GET_PORT_MODES_OUT_DEFAULT_MODE);
120 EFSYS_PROBE1(fail1, efx_rc_t, rc);
125 __checkReturn efx_rc_t
126 ef10_nic_get_port_mode_bandwidth(
128 __out uint32_t *bandwidth_mbpsp)
131 uint32_t current_mode;
132 efx_port_t *epp = &(enp->en_port);
134 uint32_t single_lane;
140 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
141 ¤t_mode, NULL)) != 0) {
142 /* No port mode info available. */
146 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_25000FDX))
151 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_50000FDX))
156 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_100000FDX))
161 switch (current_mode) {
162 case TLV_PORT_MODE_1x1_NA: /* mode 0 */
163 bandwidth = single_lane;
165 case TLV_PORT_MODE_1x2_NA: /* mode 10 */
166 case TLV_PORT_MODE_NA_1x2: /* mode 11 */
167 bandwidth = dual_lane;
169 case TLV_PORT_MODE_1x1_1x1: /* mode 2 */
170 bandwidth = single_lane + single_lane;
172 case TLV_PORT_MODE_4x1_NA: /* mode 4 */
173 case TLV_PORT_MODE_NA_4x1: /* mode 8 */
174 bandwidth = 4 * single_lane;
176 case TLV_PORT_MODE_2x1_2x1: /* mode 5 */
177 bandwidth = (2 * single_lane) + (2 * single_lane);
179 case TLV_PORT_MODE_1x2_1x2: /* mode 12 */
180 bandwidth = dual_lane + dual_lane;
182 case TLV_PORT_MODE_1x2_2x1: /* mode 17 */
183 case TLV_PORT_MODE_2x1_1x2: /* mode 18 */
184 bandwidth = dual_lane + (2 * single_lane);
186 /* Legacy Medford-only mode. Do not use (see bug63270) */
187 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2: /* mode 9 */
188 bandwidth = 4 * single_lane;
190 case TLV_PORT_MODE_1x4_NA: /* mode 1 */
191 case TLV_PORT_MODE_NA_1x4: /* mode 22 */
192 bandwidth = quad_lane;
194 case TLV_PORT_MODE_2x2_NA: /* mode 13 */
195 case TLV_PORT_MODE_NA_2x2: /* mode 14 */
196 bandwidth = 2 * dual_lane;
198 case TLV_PORT_MODE_1x4_2x1: /* mode 6 */
199 case TLV_PORT_MODE_2x1_1x4: /* mode 7 */
200 bandwidth = quad_lane + (2 * single_lane);
202 case TLV_PORT_MODE_1x4_1x2: /* mode 15 */
203 case TLV_PORT_MODE_1x2_1x4: /* mode 16 */
204 bandwidth = quad_lane + dual_lane;
206 case TLV_PORT_MODE_1x4_1x4: /* mode 3 */
207 bandwidth = quad_lane + quad_lane;
214 *bandwidth_mbpsp = bandwidth;
221 EFSYS_PROBE1(fail1, efx_rc_t, rc);
226 static __checkReturn efx_rc_t
227 efx_mcdi_vadaptor_alloc(
229 __in uint32_t port_id)
232 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_ALLOC_IN_LEN,
233 MC_CMD_VADAPTOR_ALLOC_OUT_LEN);
236 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
238 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
239 req.emr_in_buf = payload;
240 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
241 req.emr_out_buf = payload;
242 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
244 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
245 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
246 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
247 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
249 efx_mcdi_execute(enp, &req);
251 if (req.emr_rc != 0) {
259 EFSYS_PROBE1(fail1, efx_rc_t, rc);
264 static __checkReturn efx_rc_t
265 efx_mcdi_vadaptor_free(
267 __in uint32_t port_id)
270 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_FREE_IN_LEN,
271 MC_CMD_VADAPTOR_FREE_OUT_LEN);
274 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
275 req.emr_in_buf = payload;
276 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
277 req.emr_out_buf = payload;
278 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
280 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
282 efx_mcdi_execute(enp, &req);
284 if (req.emr_rc != 0) {
292 EFSYS_PROBE1(fail1, efx_rc_t, rc);
297 __checkReturn efx_rc_t
298 efx_mcdi_get_mac_address_pf(
300 __out_ecount_opt(6) uint8_t mac_addrp[6])
303 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
304 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
307 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
309 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
310 req.emr_in_buf = payload;
311 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
312 req.emr_out_buf = payload;
313 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
315 efx_mcdi_execute(enp, &req);
317 if (req.emr_rc != 0) {
322 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
327 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
332 if (mac_addrp != NULL) {
335 addrp = MCDI_OUT2(req, uint8_t,
336 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
338 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
348 EFSYS_PROBE1(fail1, efx_rc_t, rc);
353 __checkReturn efx_rc_t
354 efx_mcdi_get_mac_address_vf(
356 __out_ecount_opt(6) uint8_t mac_addrp[6])
359 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
360 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
363 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
365 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
366 req.emr_in_buf = payload;
367 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
368 req.emr_out_buf = payload;
369 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
371 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
372 EVB_PORT_ID_ASSIGNED);
374 efx_mcdi_execute(enp, &req);
376 if (req.emr_rc != 0) {
381 if (req.emr_out_length_used <
382 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
387 if (MCDI_OUT_DWORD(req,
388 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
393 if (mac_addrp != NULL) {
396 addrp = MCDI_OUT2(req, uint8_t,
397 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
399 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
409 EFSYS_PROBE1(fail1, efx_rc_t, rc);
414 __checkReturn efx_rc_t
417 __out uint32_t *sys_freqp,
418 __out uint32_t *dpcpu_freqp)
421 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CLOCK_IN_LEN,
422 MC_CMD_GET_CLOCK_OUT_LEN);
425 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
427 req.emr_cmd = MC_CMD_GET_CLOCK;
428 req.emr_in_buf = payload;
429 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
430 req.emr_out_buf = payload;
431 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
433 efx_mcdi_execute(enp, &req);
435 if (req.emr_rc != 0) {
440 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
445 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
446 if (*sys_freqp == 0) {
450 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
451 if (*dpcpu_freqp == 0) {
465 EFSYS_PROBE1(fail1, efx_rc_t, rc);
470 __checkReturn efx_rc_t
471 efx_mcdi_get_rxdp_config(
473 __out uint32_t *end_paddingp)
476 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_RXDP_CONFIG_IN_LEN,
477 MC_CMD_GET_RXDP_CONFIG_OUT_LEN);
478 uint32_t end_padding;
481 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
482 req.emr_in_buf = payload;
483 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
484 req.emr_out_buf = payload;
485 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
487 efx_mcdi_execute(enp, &req);
488 if (req.emr_rc != 0) {
493 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
494 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
495 /* RX DMA end padding is disabled */
498 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
499 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
500 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
503 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
506 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
515 *end_paddingp = end_padding;
522 EFSYS_PROBE1(fail1, efx_rc_t, rc);
527 __checkReturn efx_rc_t
528 efx_mcdi_get_vector_cfg(
530 __out_opt uint32_t *vec_basep,
531 __out_opt uint32_t *pf_nvecp,
532 __out_opt uint32_t *vf_nvecp)
535 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_VECTOR_CFG_IN_LEN,
536 MC_CMD_GET_VECTOR_CFG_OUT_LEN);
539 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
540 req.emr_in_buf = payload;
541 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
542 req.emr_out_buf = payload;
543 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
545 efx_mcdi_execute(enp, &req);
547 if (req.emr_rc != 0) {
552 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
557 if (vec_basep != NULL)
558 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
559 if (pf_nvecp != NULL)
560 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
561 if (vf_nvecp != NULL)
562 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
569 EFSYS_PROBE1(fail1, efx_rc_t, rc);
574 static __checkReturn efx_rc_t
577 __in uint32_t min_vi_count,
578 __in uint32_t max_vi_count,
579 __out uint32_t *vi_basep,
580 __out uint32_t *vi_countp,
581 __out uint32_t *vi_shiftp)
584 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_VIS_IN_LEN,
585 MC_CMD_ALLOC_VIS_EXT_OUT_LEN);
588 if (vi_countp == NULL) {
593 req.emr_cmd = MC_CMD_ALLOC_VIS;
594 req.emr_in_buf = payload;
595 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
596 req.emr_out_buf = payload;
597 req.emr_out_length = MC_CMD_ALLOC_VIS_EXT_OUT_LEN;
599 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
600 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
602 efx_mcdi_execute(enp, &req);
604 if (req.emr_rc != 0) {
609 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
614 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
615 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
617 /* Report VI_SHIFT if available (always zero for Huntington) */
618 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
621 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
630 EFSYS_PROBE1(fail1, efx_rc_t, rc);
636 static __checkReturn efx_rc_t
643 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
644 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
646 req.emr_cmd = MC_CMD_FREE_VIS;
647 req.emr_in_buf = NULL;
648 req.emr_in_length = 0;
649 req.emr_out_buf = NULL;
650 req.emr_out_length = 0;
652 efx_mcdi_execute_quiet(enp, &req);
654 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
655 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
663 EFSYS_PROBE1(fail1, efx_rc_t, rc);
669 static __checkReturn efx_rc_t
670 efx_mcdi_alloc_piobuf(
672 __out efx_piobuf_handle_t *handlep)
675 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_PIOBUF_IN_LEN,
676 MC_CMD_ALLOC_PIOBUF_OUT_LEN);
679 if (handlep == NULL) {
684 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
685 req.emr_in_buf = payload;
686 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
687 req.emr_out_buf = payload;
688 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
690 efx_mcdi_execute_quiet(enp, &req);
692 if (req.emr_rc != 0) {
697 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
702 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
711 EFSYS_PROBE1(fail1, efx_rc_t, rc);
716 static __checkReturn efx_rc_t
717 efx_mcdi_free_piobuf(
719 __in efx_piobuf_handle_t handle)
722 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FREE_PIOBUF_IN_LEN,
723 MC_CMD_FREE_PIOBUF_OUT_LEN);
726 req.emr_cmd = MC_CMD_FREE_PIOBUF;
727 req.emr_in_buf = payload;
728 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
729 req.emr_out_buf = payload;
730 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
732 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
734 efx_mcdi_execute_quiet(enp, &req);
736 if (req.emr_rc != 0) {
744 EFSYS_PROBE1(fail1, efx_rc_t, rc);
749 static __checkReturn efx_rc_t
750 efx_mcdi_link_piobuf(
752 __in uint32_t vi_index,
753 __in efx_piobuf_handle_t handle)
756 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_LINK_PIOBUF_IN_LEN,
757 MC_CMD_LINK_PIOBUF_OUT_LEN);
760 req.emr_cmd = MC_CMD_LINK_PIOBUF;
761 req.emr_in_buf = payload;
762 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
763 req.emr_out_buf = payload;
764 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
766 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
767 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
769 efx_mcdi_execute(enp, &req);
771 if (req.emr_rc != 0) {
779 EFSYS_PROBE1(fail1, efx_rc_t, rc);
784 static __checkReturn efx_rc_t
785 efx_mcdi_unlink_piobuf(
787 __in uint32_t vi_index)
790 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_UNLINK_PIOBUF_IN_LEN,
791 MC_CMD_UNLINK_PIOBUF_OUT_LEN);
794 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
795 req.emr_in_buf = payload;
796 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
797 req.emr_out_buf = payload;
798 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
800 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
802 efx_mcdi_execute_quiet(enp, &req);
804 if (req.emr_rc != 0) {
812 EFSYS_PROBE1(fail1, efx_rc_t, rc);
818 ef10_nic_alloc_piobufs(
820 __in uint32_t max_piobuf_count)
822 efx_piobuf_handle_t *handlep;
825 EFSYS_ASSERT3U(max_piobuf_count, <=,
826 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
828 enp->en_arch.ef10.ena_piobuf_count = 0;
830 for (i = 0; i < max_piobuf_count; i++) {
831 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
833 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0)
836 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
837 enp->en_arch.ef10.ena_piobuf_count++;
843 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
844 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
846 (void) efx_mcdi_free_piobuf(enp, *handlep);
847 *handlep = EFX_PIOBUF_HANDLE_INVALID;
849 enp->en_arch.ef10.ena_piobuf_count = 0;
854 ef10_nic_free_piobufs(
857 efx_piobuf_handle_t *handlep;
860 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
861 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
863 (void) efx_mcdi_free_piobuf(enp, *handlep);
864 *handlep = EFX_PIOBUF_HANDLE_INVALID;
866 enp->en_arch.ef10.ena_piobuf_count = 0;
869 /* Sub-allocate a block from a piobuf */
870 __checkReturn efx_rc_t
872 __inout efx_nic_t *enp,
873 __out uint32_t *bufnump,
874 __out efx_piobuf_handle_t *handlep,
875 __out uint32_t *blknump,
876 __out uint32_t *offsetp,
879 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
880 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
881 uint32_t blk_per_buf;
885 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
886 EFSYS_ASSERT(bufnump);
887 EFSYS_ASSERT(handlep);
888 EFSYS_ASSERT(blknump);
889 EFSYS_ASSERT(offsetp);
892 if ((edcp->edc_pio_alloc_size == 0) ||
893 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
897 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
899 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
900 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
905 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
906 for (blk = 0; blk < blk_per_buf; blk++) {
907 if ((*map & (1u << blk)) == 0) {
917 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
920 *sizep = edcp->edc_pio_alloc_size;
921 *offsetp = blk * (*sizep);
928 EFSYS_PROBE1(fail1, efx_rc_t, rc);
933 /* Free a piobuf sub-allocated block */
934 __checkReturn efx_rc_t
936 __inout efx_nic_t *enp,
937 __in uint32_t bufnum,
938 __in uint32_t blknum)
943 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
944 (blknum >= (8 * sizeof (*map)))) {
949 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
950 if ((*map & (1u << blknum)) == 0) {
954 *map &= ~(1u << blknum);
961 EFSYS_PROBE1(fail1, efx_rc_t, rc);
966 __checkReturn efx_rc_t
968 __inout efx_nic_t *enp,
969 __in uint32_t vi_index,
970 __in efx_piobuf_handle_t handle)
972 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
975 __checkReturn efx_rc_t
977 __inout efx_nic_t *enp,
978 __in uint32_t vi_index)
980 return (efx_mcdi_unlink_piobuf(enp, vi_index));
983 static __checkReturn efx_rc_t
984 ef10_mcdi_get_pf_count(
986 __out uint32_t *pf_countp)
989 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PF_COUNT_IN_LEN,
990 MC_CMD_GET_PF_COUNT_OUT_LEN);
993 req.emr_cmd = MC_CMD_GET_PF_COUNT;
994 req.emr_in_buf = payload;
995 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN;
996 req.emr_out_buf = payload;
997 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN;
999 efx_mcdi_execute(enp, &req);
1001 if (req.emr_rc != 0) {
1006 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) {
1011 *pf_countp = *MCDI_OUT(req, uint8_t,
1012 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST);
1014 EFSYS_ASSERT(*pf_countp != 0);
1021 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1026 static __checkReturn efx_rc_t
1027 ef10_get_datapath_caps(
1028 __in efx_nic_t *enp)
1030 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1032 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CAPABILITIES_IN_LEN,
1033 MC_CMD_GET_CAPABILITIES_V5_OUT_LEN);
1036 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0)
1040 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
1041 req.emr_in_buf = payload;
1042 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
1043 req.emr_out_buf = payload;
1044 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V5_OUT_LEN;
1046 efx_mcdi_execute_quiet(enp, &req);
1048 if (req.emr_rc != 0) {
1053 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
1058 #define CAP_FLAGS1(_req, _flag) \
1059 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_OUT_FLAGS1) & \
1060 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN)))
1062 #define CAP_FLAGS2(_req, _flag) \
1063 (((_req).emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) && \
1064 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V2_OUT_FLAGS2) & \
1065 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN))))
1068 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
1069 * We only support the 14 byte prefix here.
1071 if (CAP_FLAGS1(req, RX_PREFIX_LEN_14) == 0) {
1075 encp->enc_rx_prefix_size = 14;
1077 #if EFSYS_OPT_RX_SCALE
1078 /* Check if the firmware supports additional RSS modes */
1079 if (CAP_FLAGS1(req, ADDITIONAL_RSS_MODES))
1080 encp->enc_rx_scale_additional_modes_supported = B_TRUE;
1082 encp->enc_rx_scale_additional_modes_supported = B_FALSE;
1083 #endif /* EFSYS_OPT_RX_SCALE */
1085 /* Check if the firmware supports TSO */
1086 if (CAP_FLAGS1(req, TX_TSO))
1087 encp->enc_fw_assisted_tso_enabled = B_TRUE;
1089 encp->enc_fw_assisted_tso_enabled = B_FALSE;
1091 /* Check if the firmware supports FATSOv2 */
1092 if (CAP_FLAGS2(req, TX_TSO_V2)) {
1093 encp->enc_fw_assisted_tso_v2_enabled = B_TRUE;
1094 encp->enc_fw_assisted_tso_v2_n_contexts = MCDI_OUT_WORD(req,
1095 GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS);
1097 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
1098 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
1101 /* Check if the firmware supports FATSOv2 encap */
1102 if (CAP_FLAGS2(req, TX_TSO_V2_ENCAP))
1103 encp->enc_fw_assisted_tso_v2_encap_enabled = B_TRUE;
1105 encp->enc_fw_assisted_tso_v2_encap_enabled = B_FALSE;
1107 /* Check if the firmware has vadapter/vport/vswitch support */
1108 if (CAP_FLAGS1(req, EVB))
1109 encp->enc_datapath_cap_evb = B_TRUE;
1111 encp->enc_datapath_cap_evb = B_FALSE;
1113 /* Check if the firmware supports VLAN insertion */
1114 if (CAP_FLAGS1(req, TX_VLAN_INSERTION))
1115 encp->enc_hw_tx_insert_vlan_enabled = B_TRUE;
1117 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
1119 /* Check if the firmware supports RX event batching */
1120 if (CAP_FLAGS1(req, RX_BATCHING))
1121 encp->enc_rx_batching_enabled = B_TRUE;
1123 encp->enc_rx_batching_enabled = B_FALSE;
1126 * Even if batching isn't reported as supported, we may still get
1127 * batched events (see bug61153).
1129 encp->enc_rx_batch_max = 16;
1131 /* Check if the firmware supports disabling scatter on RXQs */
1132 if (CAP_FLAGS1(req, RX_DISABLE_SCATTER))
1133 encp->enc_rx_disable_scatter_supported = B_TRUE;
1135 encp->enc_rx_disable_scatter_supported = B_FALSE;
1137 /* Check if the firmware supports packed stream mode */
1138 if (CAP_FLAGS1(req, RX_PACKED_STREAM))
1139 encp->enc_rx_packed_stream_supported = B_TRUE;
1141 encp->enc_rx_packed_stream_supported = B_FALSE;
1144 * Check if the firmware supports configurable buffer sizes
1145 * for packed stream mode (otherwise buffer size is 1Mbyte)
1147 if (CAP_FLAGS1(req, RX_PACKED_STREAM_VAR_BUFFERS))
1148 encp->enc_rx_var_packed_stream_supported = B_TRUE;
1150 encp->enc_rx_var_packed_stream_supported = B_FALSE;
1152 /* Check if the firmware supports equal stride super-buffer mode */
1153 if (CAP_FLAGS2(req, EQUAL_STRIDE_SUPER_BUFFER))
1154 encp->enc_rx_es_super_buffer_supported = B_TRUE;
1156 encp->enc_rx_es_super_buffer_supported = B_FALSE;
1158 /* Check if the firmware supports FW subvariant w/o Tx checksumming */
1159 if (CAP_FLAGS2(req, FW_SUBVARIANT_NO_TX_CSUM))
1160 encp->enc_fw_subvariant_no_tx_csum_supported = B_TRUE;
1162 encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE;
1164 /* Check if the firmware supports set mac with running filters */
1165 if (CAP_FLAGS1(req, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED))
1166 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
1168 encp->enc_allow_set_mac_with_installed_filters = B_FALSE;
1171 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows
1172 * specifying which parameters to configure.
1174 if (CAP_FLAGS1(req, SET_MAC_ENHANCED))
1175 encp->enc_enhanced_set_mac_supported = B_TRUE;
1177 encp->enc_enhanced_set_mac_supported = B_FALSE;
1180 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows
1181 * us to let the firmware choose the settings to use on an EVQ.
1183 if (CAP_FLAGS2(req, INIT_EVQ_V2))
1184 encp->enc_init_evq_v2_supported = B_TRUE;
1186 encp->enc_init_evq_v2_supported = B_FALSE;
1189 * Check if the NO_CONT_EV mode for RX events is supported.
1191 if (CAP_FLAGS2(req, INIT_RXQ_NO_CONT_EV))
1192 encp->enc_no_cont_ev_mode_supported = B_TRUE;
1194 encp->enc_no_cont_ev_mode_supported = B_FALSE;
1197 * Check if buffer size may and must be specified on INIT_RXQ.
1198 * It may be always specified to efx_rx_qcreate(), but will be
1199 * just kept libefx internal if MCDI does not support it.
1201 if (CAP_FLAGS2(req, INIT_RXQ_WITH_BUFFER_SIZE))
1202 encp->enc_init_rxq_with_buffer_size = B_TRUE;
1204 encp->enc_init_rxq_with_buffer_size = B_FALSE;
1207 * Check if firmware-verified NVRAM updates must be used.
1209 * The firmware trusted installer requires all NVRAM updates to use
1210 * version 2 of MC_CMD_NVRAM_UPDATE_START (to enable verified update)
1211 * and version 2 of MC_CMD_NVRAM_UPDATE_FINISH (to verify the updated
1212 * partition and report the result).
1214 if (CAP_FLAGS2(req, NVRAM_UPDATE_REPORT_VERIFY_RESULT))
1215 encp->enc_nvram_update_verify_result_supported = B_TRUE;
1217 encp->enc_nvram_update_verify_result_supported = B_FALSE;
1219 if (CAP_FLAGS2(req, NVRAM_UPDATE_POLL_VERIFY_RESULT))
1220 encp->enc_nvram_update_poll_verify_result_supported = B_TRUE;
1222 encp->enc_nvram_update_poll_verify_result_supported = B_FALSE;
1225 * Check if firmware update via the BUNDLE partition is supported
1227 if (CAP_FLAGS2(req, BUNDLE_UPDATE))
1228 encp->enc_nvram_bundle_update_supported = B_TRUE;
1230 encp->enc_nvram_bundle_update_supported = B_FALSE;
1233 * Check if firmware provides packet memory and Rx datapath
1236 if (CAP_FLAGS1(req, PM_AND_RXDP_COUNTERS))
1237 encp->enc_pm_and_rxdp_counters = B_TRUE;
1239 encp->enc_pm_and_rxdp_counters = B_FALSE;
1242 * Check if the 40G MAC hardware is capable of reporting
1243 * statistics for Tx size bins.
1245 if (CAP_FLAGS2(req, MAC_STATS_40G_TX_SIZE_BINS))
1246 encp->enc_mac_stats_40g_tx_size_bins = B_TRUE;
1248 encp->enc_mac_stats_40g_tx_size_bins = B_FALSE;
1251 * Check if firmware supports VXLAN and NVGRE tunnels.
1252 * The capability indicates Geneve protocol support as well.
1254 if (CAP_FLAGS1(req, VXLAN_NVGRE)) {
1255 encp->enc_tunnel_encapsulations_supported =
1256 (1u << EFX_TUNNEL_PROTOCOL_VXLAN) |
1257 (1u << EFX_TUNNEL_PROTOCOL_GENEVE) |
1258 (1u << EFX_TUNNEL_PROTOCOL_NVGRE);
1260 EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES ==
1261 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
1262 encp->enc_tunnel_config_udp_entries_max =
1263 EFX_TUNNEL_MAXNENTRIES;
1265 encp->enc_tunnel_config_udp_entries_max = 0;
1269 * Check if firmware reports the VI window mode.
1270 * Medford2 has a variable VI window size (8K, 16K or 64K).
1271 * Medford and Huntington have a fixed 8K VI window size.
1273 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
1275 MCDI_OUT_BYTE(req, GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
1278 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
1279 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1281 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
1282 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_16K;
1284 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
1285 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_64K;
1288 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1291 } else if ((enp->en_family == EFX_FAMILY_HUNTINGTON) ||
1292 (enp->en_family == EFX_FAMILY_MEDFORD)) {
1293 /* Huntington and Medford have fixed 8K window size */
1294 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1296 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1299 /* Check if firmware supports extended MAC stats. */
1300 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
1301 /* Extended stats buffer supported */
1302 encp->enc_mac_stats_nstats = MCDI_OUT_WORD(req,
1303 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
1305 /* Use Siena-compatible legacy MAC stats */
1306 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS;
1309 if (encp->enc_mac_stats_nstats >= MC_CMD_MAC_NSTATS_V2)
1310 encp->enc_fec_counters = B_TRUE;
1312 encp->enc_fec_counters = B_FALSE;
1314 /* Check if the firmware provides head-of-line blocking counters */
1315 if (CAP_FLAGS2(req, RXDP_HLB_IDLE))
1316 encp->enc_hlb_counters = B_TRUE;
1318 encp->enc_hlb_counters = B_FALSE;
1320 #if EFSYS_OPT_RX_SCALE
1321 if (CAP_FLAGS1(req, RX_RSS_LIMITED)) {
1322 /* Only one exclusive RSS context is available per port. */
1323 encp->enc_rx_scale_max_exclusive_contexts = 1;
1325 switch (enp->en_family) {
1326 case EFX_FAMILY_MEDFORD2:
1327 encp->enc_rx_scale_hash_alg_mask =
1328 (1U << EFX_RX_HASHALG_TOEPLITZ);
1331 case EFX_FAMILY_MEDFORD:
1332 case EFX_FAMILY_HUNTINGTON:
1334 * Packed stream firmware variant maintains a
1335 * non-standard algorithm for hash computation.
1336 * It implies explicit XORing together
1337 * source + destination IP addresses (or last
1338 * four bytes in the case of IPv6) and using the
1339 * resulting value as the input to a Toeplitz hash.
1341 encp->enc_rx_scale_hash_alg_mask =
1342 (1U << EFX_RX_HASHALG_PACKED_STREAM);
1350 /* Port numbers cannot contribute to the hash value */
1351 encp->enc_rx_scale_l4_hash_supported = B_FALSE;
1354 * Maximum number of exclusive RSS contexts.
1355 * EF10 hardware supports 64 in total, but 6 are reserved
1356 * for shared contexts. They are a global resource so
1357 * not all may be available.
1359 encp->enc_rx_scale_max_exclusive_contexts = 64 - 6;
1361 encp->enc_rx_scale_hash_alg_mask =
1362 (1U << EFX_RX_HASHALG_TOEPLITZ);
1365 * It is possible to use port numbers as
1366 * the input data for hash computation.
1368 encp->enc_rx_scale_l4_hash_supported = B_TRUE;
1370 #endif /* EFSYS_OPT_RX_SCALE */
1372 /* Check if the firmware supports "FLAG" and "MARK" filter actions */
1373 if (CAP_FLAGS2(req, FILTER_ACTION_FLAG))
1374 encp->enc_filter_action_flag_supported = B_TRUE;
1376 encp->enc_filter_action_flag_supported = B_FALSE;
1378 if (CAP_FLAGS2(req, FILTER_ACTION_MARK))
1379 encp->enc_filter_action_mark_supported = B_TRUE;
1381 encp->enc_filter_action_mark_supported = B_FALSE;
1383 /* Get maximum supported value for "MARK" filter action */
1384 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V5_OUT_LEN)
1385 encp->enc_filter_action_mark_max = MCDI_OUT_DWORD(req,
1386 GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX);
1388 encp->enc_filter_action_mark_max = 0;
1395 #if EFSYS_OPT_RX_SCALE
1398 #endif /* EFSYS_OPT_RX_SCALE */
1406 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1412 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
1413 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
1414 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
1415 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
1416 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
1417 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
1418 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
1419 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
1420 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
1421 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
1422 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
1423 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
1425 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
1428 __checkReturn efx_rc_t
1429 ef10_get_privilege_mask(
1430 __in efx_nic_t *enp,
1431 __out uint32_t *maskp)
1433 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1437 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1442 /* Fallback for old firmware without privilege mask support */
1443 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1444 /* Assume PF has admin privilege */
1445 mask = EF10_LEGACY_PF_PRIVILEGE_MASK;
1447 /* VF is always unprivileged by default */
1448 mask = EF10_LEGACY_VF_PRIVILEGE_MASK;
1457 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1463 #define EFX_EXT_PORT_MAX 4
1464 #define EFX_EXT_PORT_NA 0xFF
1467 * Table of mapping schemes from port number to external number.
1469 * Each port number ultimately corresponds to a connector: either as part of
1470 * a cable assembly attached to a module inserted in an SFP+/QSFP+ cage on
1471 * the board, or fixed to the board (e.g. 10GBASE-T magjack on SFN5121T
1472 * "Salina"). In general:
1474 * Port number (0-based)
1476 * port mapping (n:1)
1479 * External port number (1-based)
1481 * fixed (1:1) or cable assembly (1:m)
1486 * The external numbering refers to the cages or magjacks on the board,
1487 * as visibly annotated on the board or back panel. This table describes
1488 * how to determine which external cage/magjack corresponds to the port
1489 * numbers used by the driver.
1491 * The count of consecutive port numbers that map to each external number,
1492 * is determined by the chip family and the current port mode.
1494 * For the Huntington family, the current port mode cannot be discovered,
1495 * but a single mapping is used by all modes for a given chip variant,
1496 * so the mapping used is instead the last match in the table to the full
1497 * set of port modes to which the NIC can be configured. Therefore the
1498 * ordering of entries in the mapping table is significant.
1500 static struct ef10_external_port_map_s {
1501 efx_family_t family;
1502 uint32_t modes_mask;
1503 uint8_t base_port[EFX_EXT_PORT_MAX];
1504 } __ef10_external_port_mappings[] = {
1506 * Modes used by Huntington family controllers where each port
1507 * number maps to a separate cage.
1508 * SFN7x22F (Torino):
1518 EFX_FAMILY_HUNTINGTON,
1519 (1U << TLV_PORT_MODE_10G) | /* mode 0 */
1520 (1U << TLV_PORT_MODE_10G_10G) | /* mode 2 */
1521 (1U << TLV_PORT_MODE_10G_10G_10G_10G), /* mode 4 */
1525 * Modes which for Huntington identify a chip variant where 2
1526 * adjacent port numbers map to each cage.
1534 EFX_FAMILY_HUNTINGTON,
1535 (1U << TLV_PORT_MODE_40G) | /* mode 1 */
1536 (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
1537 (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
1538 (1U << TLV_PORT_MODE_10G_10G_40G), /* mode 7 */
1539 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1542 * Modes that on Medford allocate each port number to a separate
1551 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1552 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1553 (1U << TLV_PORT_MODE_1x1_1x1), /* mode 2 */
1557 * Modes that on Medford allocate 2 adjacent port numbers to each
1566 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
1567 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 5 */
1568 (1U << TLV_PORT_MODE_1x4_2x1) | /* mode 6 */
1569 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
1570 /* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */
1571 (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */
1572 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1575 * Modes that on Medford allocate 4 adjacent port numbers to
1584 /* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */
1585 (1U << TLV_PORT_MODE_4x1_NA), /* mode 4 */
1586 { 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1589 * Modes that on Medford allocate 4 adjacent port numbers to
1598 (1U << TLV_PORT_MODE_NA_4x1), /* mode 8 */
1599 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1602 * Modes that on Medford2 allocate each port number to a separate
1610 EFX_FAMILY_MEDFORD2,
1611 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1612 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1613 (1U << TLV_PORT_MODE_1x1_1x1) | /* mode 2 */
1614 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
1615 (1U << TLV_PORT_MODE_1x2_NA) | /* mode 10 */
1616 (1U << TLV_PORT_MODE_1x2_1x2) | /* mode 12 */
1617 (1U << TLV_PORT_MODE_1x4_1x2) | /* mode 15 */
1618 (1U << TLV_PORT_MODE_1x2_1x4), /* mode 16 */
1622 * Modes that on Medford2 allocate 1 port to cage 1 and the rest
1629 EFX_FAMILY_MEDFORD2,
1630 (1U << TLV_PORT_MODE_1x2_2x1) | /* mode 17 */
1631 (1U << TLV_PORT_MODE_1x4_2x1), /* mode 6 */
1632 { 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1635 * Modes that on Medford2 allocate 2 adjacent port numbers to cage 1
1636 * and the rest to cage 2.
1643 EFX_FAMILY_MEDFORD2,
1644 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 4 */
1645 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
1646 (1U << TLV_PORT_MODE_2x2_NA) | /* mode 13 */
1647 (1U << TLV_PORT_MODE_2x1_1x2), /* mode 18 */
1648 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1651 * Modes that on Medford2 allocate up to 4 adjacent port numbers
1659 EFX_FAMILY_MEDFORD2,
1660 (1U << TLV_PORT_MODE_4x1_NA), /* mode 5 */
1661 { 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1664 * Modes that on Medford2 allocate up to 4 adjacent port numbers
1672 EFX_FAMILY_MEDFORD2,
1673 (1U << TLV_PORT_MODE_NA_4x1) | /* mode 8 */
1674 (1U << TLV_PORT_MODE_NA_1x2) | /* mode 11 */
1675 (1U << TLV_PORT_MODE_NA_2x2), /* mode 14 */
1676 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1680 static __checkReturn efx_rc_t
1681 ef10_external_port_mapping(
1682 __in efx_nic_t *enp,
1684 __out uint8_t *external_portp)
1688 uint32_t port_modes;
1691 struct ef10_external_port_map_s *mapp = NULL;
1692 int ext_index = port; /* Default 1-1 mapping */
1694 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t,
1697 * No current port mode information (i.e. Huntington)
1698 * - infer mapping from available modes
1700 if ((rc = efx_mcdi_get_port_modes(enp,
1701 &port_modes, NULL, NULL)) != 0) {
1703 * No port mode information available
1704 * - use default mapping
1709 /* Only need to scan the current mode */
1710 port_modes = 1 << current;
1714 * Infer the internal port -> external number mapping from
1715 * the possible port modes for this NIC.
1717 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1718 struct ef10_external_port_map_s *eepmp =
1719 &__ef10_external_port_mappings[i];
1720 if (eepmp->family != enp->en_family)
1722 matches = (eepmp->modes_mask & port_modes);
1725 * Some modes match. For some Huntington boards
1726 * there will be multiple matches. The mapping on the
1727 * last match is used.
1730 port_modes &= ~matches;
1734 if (port_modes != 0) {
1735 /* Some advertised modes are not supported */
1743 * External ports are assigned a sequence of consecutive
1744 * port numbers, so find the one with the closest base_port.
1746 uint32_t delta = EFX_EXT_PORT_NA;
1748 for (i = 0; i < EFX_EXT_PORT_MAX; i++) {
1749 uint32_t base = mapp->base_port[i];
1750 if ((base != EFX_EXT_PORT_NA) && (base <= port)) {
1751 if ((port - base) < delta) {
1752 delta = (port - base);
1758 *external_portp = (uint8_t)(ext_index + 1);
1763 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1768 static __checkReturn efx_rc_t
1769 ef10_set_workaround_bug26807(
1770 __in efx_nic_t *enp)
1772 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1777 * If the bug26807 workaround is enabled, then firmware has enabled
1778 * support for chained multicast filters. Firmware will reset (FLR)
1779 * functions which have filters in the hardware filter table when the
1780 * workaround is enabled/disabled.
1782 * We must recheck if the workaround is enabled after inserting the
1783 * first hardware filter, in case it has been changed since this check.
1785 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
1788 encp->enc_bug26807_workaround = B_TRUE;
1789 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
1791 * Other functions had installed filters before the
1792 * workaround was enabled, and they have been reset
1795 EFSYS_PROBE(bug26807_workaround_flr_done);
1796 /* FIXME: bump MC warm boot count ? */
1798 } else if (rc == EACCES) {
1800 * Unprivileged functions cannot enable the workaround in older
1803 encp->enc_bug26807_workaround = B_FALSE;
1804 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
1805 encp->enc_bug26807_workaround = B_FALSE;
1813 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1818 static __checkReturn efx_rc_t
1820 __in efx_nic_t *enp)
1822 const efx_nic_ops_t *enop = enp->en_enop;
1823 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
1824 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1825 ef10_link_state_t els;
1826 efx_port_t *epp = &(enp->en_port);
1827 uint32_t board_type = 0;
1828 uint32_t base, nvec;
1833 uint8_t mac_addr[6] = { 0 };
1836 /* Get the (zero-based) MCDI port number */
1837 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
1840 /* EFX MCDI interface uses one-based port numbers */
1841 emip->emi_port = port + 1;
1843 if ((rc = ef10_external_port_mapping(enp, port,
1844 &encp->enc_external_port)) != 0)
1848 * Get PCIe function number from firmware (used for
1849 * per-function privilege and dynamic config info).
1850 * - PCIe PF: pf = PF number, vf = 0xffff.
1851 * - PCIe VF: pf = parent PF, vf = VF number.
1853 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
1859 /* MAC address for this function */
1860 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1861 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
1862 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
1864 * Disable static config checking, ONLY for manufacturing test
1865 * and setup at the factory, to allow the static config to be
1868 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1869 if ((rc == 0) && (mac_addr[0] & 0x02)) {
1871 * If the static config does not include a global MAC
1872 * address pool then the board may return a locally
1873 * administered MAC address (this should only happen on
1874 * incorrectly programmed boards).
1878 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1880 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
1885 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
1887 /* Board configuration (legacy) */
1888 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
1890 /* Unprivileged functions may not be able to read board cfg */
1897 encp->enc_board_type = board_type;
1898 encp->enc_clk_mult = 1; /* not used for EF10 */
1900 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
1901 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
1905 * Firmware with support for *_FEC capability bits does not
1906 * report that the corresponding *_FEC_REQUESTED bits are supported.
1907 * Add them here so that drivers understand that they are supported.
1909 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_BASER_FEC))
1910 epp->ep_phy_cap_mask |=
1911 (1u << EFX_PHY_CAP_BASER_FEC_REQUESTED);
1912 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_RS_FEC))
1913 epp->ep_phy_cap_mask |=
1914 (1u << EFX_PHY_CAP_RS_FEC_REQUESTED);
1915 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_25G_BASER_FEC))
1916 epp->ep_phy_cap_mask |=
1917 (1u << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED);
1919 /* Obtain the default PHY advertised capabilities */
1920 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
1922 epp->ep_default_adv_cap_mask = els.epls.epls_adv_cap_mask;
1923 epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask;
1925 /* Check capabilities of running datapath firmware */
1926 if ((rc = ef10_get_datapath_caps(enp)) != 0)
1929 /* Alignment for WPTR updates */
1930 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
1932 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
1933 /* No boundary crossing limits */
1934 encp->enc_tx_dma_desc_boundary = 0;
1937 * Maximum number of bytes into the frame the TCP header can start for
1938 * firmware assisted TSO to work.
1940 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
1943 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
1944 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
1945 * resources (allocated to this PCIe function), which is zero until
1946 * after we have allocated VIs.
1948 encp->enc_evq_limit = 1024;
1949 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
1950 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
1952 encp->enc_buftbl_limit = UINT32_MAX;
1954 /* Get interrupt vector limits */
1955 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
1956 if (EFX_PCI_FUNCTION_IS_PF(encp))
1959 /* Ignore error (cannot query vector limits from a VF). */
1963 encp->enc_intr_vec_base = base;
1964 encp->enc_intr_limit = nvec;
1967 * Get the current privilege mask. Note that this may be modified
1968 * dynamically, so this value is informational only. DO NOT use
1969 * the privilege mask to check for sufficient privileges, as that
1970 * can result in time-of-check/time-of-use bugs.
1972 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
1974 encp->enc_privilege_mask = mask;
1976 if ((rc = ef10_set_workaround_bug26807(enp)) != 0)
1979 /* Get remaining controller-specific board config */
1980 if ((rc = enop->eno_board_cfg(enp)) != 0)
1987 EFSYS_PROBE(fail12);
1989 EFSYS_PROBE(fail11);
1991 EFSYS_PROBE(fail10);
2009 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2014 __checkReturn efx_rc_t
2016 __in efx_nic_t *enp)
2018 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
2019 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2022 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
2024 /* Read and clear any assertion state */
2025 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
2028 /* Exit the assertion handler */
2029 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
2033 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
2036 if ((rc = ef10_nic_board_cfg(enp)) != 0)
2040 * Set default driver config limits (based on board config).
2042 * FIXME: For now allocate a fixed number of VIs which is likely to be
2043 * sufficient and small enough to allow multiple functions on the same
2046 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
2047 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
2049 /* The client driver must configure and enable PIO buffer support */
2050 edcp->edc_max_piobuf_count = 0;
2051 edcp->edc_pio_alloc_size = 0;
2053 #if EFSYS_OPT_MAC_STATS
2054 /* Wipe the MAC statistics */
2055 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
2059 #if EFSYS_OPT_LOOPBACK
2060 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
2064 #if EFSYS_OPT_MON_STATS
2065 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
2066 /* Unprivileged functions do not have access to sensors */
2072 encp->enc_features = enp->en_features;
2076 #if EFSYS_OPT_MON_STATS
2080 #if EFSYS_OPT_LOOPBACK
2084 #if EFSYS_OPT_MAC_STATS
2095 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2100 __checkReturn efx_rc_t
2101 ef10_nic_set_drv_limits(
2102 __inout efx_nic_t *enp,
2103 __in efx_drv_limits_t *edlp)
2105 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
2106 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2107 uint32_t min_evq_count, max_evq_count;
2108 uint32_t min_rxq_count, max_rxq_count;
2109 uint32_t min_txq_count, max_txq_count;
2117 /* Get minimum required and maximum usable VI limits */
2118 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
2119 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
2120 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
2122 edcp->edc_min_vi_count =
2123 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
2125 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
2126 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
2127 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
2129 edcp->edc_max_vi_count =
2130 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
2133 * Check limits for sub-allocated piobuf blocks.
2134 * PIO is optional, so don't fail if the limits are incorrect.
2136 if ((encp->enc_piobuf_size == 0) ||
2137 (encp->enc_piobuf_limit == 0) ||
2138 (edlp->edl_min_pio_alloc_size == 0) ||
2139 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
2141 edcp->edc_max_piobuf_count = 0;
2142 edcp->edc_pio_alloc_size = 0;
2144 uint32_t blk_size, blk_count, blks_per_piobuf;
2147 MAX(edlp->edl_min_pio_alloc_size,
2148 encp->enc_piobuf_min_alloc_size);
2150 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
2151 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
2153 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
2155 /* A zero max pio alloc count means unlimited */
2156 if ((edlp->edl_max_pio_alloc_count > 0) &&
2157 (edlp->edl_max_pio_alloc_count < blk_count)) {
2158 blk_count = edlp->edl_max_pio_alloc_count;
2161 edcp->edc_pio_alloc_size = blk_size;
2162 edcp->edc_max_piobuf_count =
2163 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
2169 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2175 __checkReturn efx_rc_t
2177 __in efx_nic_t *enp)
2180 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ENTITY_RESET_IN_LEN,
2181 MC_CMD_ENTITY_RESET_OUT_LEN);
2184 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
2185 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
2187 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
2190 req.emr_cmd = MC_CMD_ENTITY_RESET;
2191 req.emr_in_buf = payload;
2192 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
2193 req.emr_out_buf = payload;
2194 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
2196 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
2197 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
2199 efx_mcdi_execute(enp, &req);
2201 if (req.emr_rc != 0) {
2206 /* Clear RX/TX DMA queue errors */
2207 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
2216 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2221 __checkReturn efx_rc_t
2223 __in efx_nic_t *enp)
2225 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2226 uint32_t min_vi_count, max_vi_count;
2227 uint32_t vi_count, vi_base, vi_shift;
2231 uint32_t vi_window_size;
2234 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
2236 /* Enable reporting of some events (e.g. link change) */
2237 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
2240 /* Allocate (optional) on-chip PIO buffers */
2241 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
2244 * For best performance, PIO writes should use a write-combined
2245 * (WC) memory mapping. Using a separate WC mapping for the PIO
2246 * aperture of each VI would be a burden to drivers (and not
2247 * possible if the host page size is >4Kbyte).
2249 * To avoid this we use a single uncached (UC) mapping for VI
2250 * register access, and a single WC mapping for extra VIs used
2253 * Each piobuf must be linked to a VI in the WC mapping, and to
2254 * each VI that is using a sub-allocated block from the piobuf.
2256 min_vi_count = edcp->edc_min_vi_count;
2258 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
2260 /* Ensure that the previously attached driver's VIs are freed */
2261 if ((rc = efx_mcdi_free_vis(enp)) != 0)
2265 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
2266 * fails then retrying the request for fewer VI resources may succeed.
2269 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
2270 &vi_base, &vi_count, &vi_shift)) != 0)
2273 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
2275 if (vi_count < min_vi_count) {
2280 enp->en_arch.ef10.ena_vi_base = vi_base;
2281 enp->en_arch.ef10.ena_vi_count = vi_count;
2282 enp->en_arch.ef10.ena_vi_shift = vi_shift;
2284 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
2285 /* Not enough extra VIs to map piobufs */
2286 ef10_nic_free_piobufs(enp);
2289 enp->en_arch.ef10.ena_pio_write_vi_base =
2290 vi_count - enp->en_arch.ef10.ena_piobuf_count;
2292 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, !=,
2293 EFX_VI_WINDOW_SHIFT_INVALID);
2294 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, <=,
2295 EFX_VI_WINDOW_SHIFT_64K);
2296 vi_window_size = 1U << enp->en_nic_cfg.enc_vi_window_shift;
2298 /* Save UC memory mapping details */
2299 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
2300 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2301 enp->en_arch.ef10.ena_uc_mem_map_size =
2303 enp->en_arch.ef10.ena_pio_write_vi_base);
2305 enp->en_arch.ef10.ena_uc_mem_map_size =
2307 enp->en_arch.ef10.ena_vi_count);
2310 /* Save WC memory mapping details */
2311 enp->en_arch.ef10.ena_wc_mem_map_offset =
2312 enp->en_arch.ef10.ena_uc_mem_map_offset +
2313 enp->en_arch.ef10.ena_uc_mem_map_size;
2315 enp->en_arch.ef10.ena_wc_mem_map_size =
2317 enp->en_arch.ef10.ena_piobuf_count);
2319 /* Link piobufs to extra VIs in WC mapping */
2320 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2321 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2322 rc = efx_mcdi_link_piobuf(enp,
2323 enp->en_arch.ef10.ena_pio_write_vi_base + i,
2324 enp->en_arch.ef10.ena_piobuf_handle[i]);
2331 * Allocate a vAdaptor attached to our upstream vPort/pPort.
2333 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
2334 * driver has yet to bring up the EVB port. See bug 56147. In this case,
2335 * retry the request several times after waiting a while. The wait time
2336 * between retries starts small (10ms) and exponentially increases.
2337 * Total wait time is a little over two seconds. Retry logic in the
2338 * client driver may mean this whole loop is repeated if it continues to
2343 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
2344 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
2347 * Do not retry alloc for PF, or for other errors on
2353 /* VF startup before PF is ready. Retry allocation. */
2355 /* Too many attempts */
2359 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
2360 EFSYS_SLEEP(delay_us);
2362 if (delay_us < 500000)
2366 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
2367 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
2382 ef10_nic_free_piobufs(enp);
2385 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2390 __checkReturn efx_rc_t
2391 ef10_nic_get_vi_pool(
2392 __in efx_nic_t *enp,
2393 __out uint32_t *vi_countp)
2395 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
2398 * Report VIs that the client driver can use.
2399 * Do not include VIs used for PIO buffer writes.
2401 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
2406 __checkReturn efx_rc_t
2407 ef10_nic_get_bar_region(
2408 __in efx_nic_t *enp,
2409 __in efx_nic_region_t region,
2410 __out uint32_t *offsetp,
2411 __out size_t *sizep)
2415 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
2418 * TODO: Specify host memory mapping alignment and granularity
2419 * in efx_drv_limits_t so that they can be taken into account
2420 * when allocating extra VIs for PIO writes.
2424 /* UC mapped memory BAR region for VI registers */
2425 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
2426 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
2429 case EFX_REGION_PIO_WRITE_VI:
2430 /* WC mapped memory BAR region for piobuf writes */
2431 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
2432 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
2443 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2448 __checkReturn boolean_t
2449 ef10_nic_hw_unavailable(
2450 __in efx_nic_t *enp)
2454 if (enp->en_reset_flags & EFX_RESET_HW_UNAVAIL)
2457 EFX_BAR_READD(enp, ER_DZ_BIU_MC_SFT_STATUS_REG, &dword, B_FALSE);
2458 if (EFX_DWORD_FIELD(dword, EFX_DWORD_0) == 0xffffffff)
2464 ef10_nic_set_hw_unavailable(enp);
2470 ef10_nic_set_hw_unavailable(
2471 __in efx_nic_t *enp)
2473 EFSYS_PROBE(hw_unavail);
2474 enp->en_reset_flags |= EFX_RESET_HW_UNAVAIL;
2480 __in efx_nic_t *enp)
2485 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
2486 enp->en_vport_id = 0;
2488 /* Unlink piobufs from extra VIs in WC mapping */
2489 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2490 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2491 rc = efx_mcdi_unlink_piobuf(enp,
2492 enp->en_arch.ef10.ena_pio_write_vi_base + i);
2498 ef10_nic_free_piobufs(enp);
2500 (void) efx_mcdi_free_vis(enp);
2501 enp->en_arch.ef10.ena_vi_count = 0;
2506 __in efx_nic_t *enp)
2508 #if EFSYS_OPT_MON_STATS
2509 mcdi_mon_cfg_free(enp);
2510 #endif /* EFSYS_OPT_MON_STATS */
2511 (void) efx_mcdi_drv_attach(enp, B_FALSE);
2516 __checkReturn efx_rc_t
2517 ef10_nic_register_test(
2518 __in efx_nic_t *enp)
2523 _NOTE(ARGUNUSED(enp))
2524 _NOTE(CONSTANTCONDITION)
2534 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2539 #endif /* EFSYS_OPT_DIAG */
2541 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
2543 __checkReturn efx_rc_t
2544 efx_mcdi_get_nic_global(
2545 __in efx_nic_t *enp,
2547 __out uint32_t *valuep)
2550 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_NIC_GLOBAL_IN_LEN,
2551 MC_CMD_GET_NIC_GLOBAL_OUT_LEN);
2554 req.emr_cmd = MC_CMD_GET_NIC_GLOBAL;
2555 req.emr_in_buf = payload;
2556 req.emr_in_length = MC_CMD_GET_NIC_GLOBAL_IN_LEN;
2557 req.emr_out_buf = payload;
2558 req.emr_out_length = MC_CMD_GET_NIC_GLOBAL_OUT_LEN;
2560 MCDI_IN_SET_DWORD(req, GET_NIC_GLOBAL_IN_KEY, key);
2562 efx_mcdi_execute(enp, &req);
2564 if (req.emr_rc != 0) {
2569 if (req.emr_out_length_used != MC_CMD_GET_NIC_GLOBAL_OUT_LEN) {
2574 *valuep = MCDI_OUT_DWORD(req, GET_NIC_GLOBAL_OUT_VALUE);
2581 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2586 __checkReturn efx_rc_t
2587 efx_mcdi_set_nic_global(
2588 __in efx_nic_t *enp,
2590 __in uint32_t value)
2593 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_NIC_GLOBAL_IN_LEN, 0);
2596 req.emr_cmd = MC_CMD_SET_NIC_GLOBAL;
2597 req.emr_in_buf = payload;
2598 req.emr_in_length = MC_CMD_SET_NIC_GLOBAL_IN_LEN;
2599 req.emr_out_buf = NULL;
2600 req.emr_out_length = 0;
2602 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_KEY, key);
2603 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_VALUE, value);
2605 efx_mcdi_execute(enp, &req);
2607 if (req.emr_rc != 0) {
2615 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2620 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
2622 #endif /* EFX_OPTS_EF10() */