1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
13 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
15 #include "ef10_tlv_layout.h"
17 __checkReturn efx_rc_t
18 efx_mcdi_get_port_assignment(
20 __out uint32_t *portp)
23 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
24 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN);
27 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
28 enp->en_family == EFX_FAMILY_MEDFORD ||
29 enp->en_family == EFX_FAMILY_MEDFORD2);
31 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
32 req.emr_in_buf = payload;
33 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
34 req.emr_out_buf = payload;
35 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
37 efx_mcdi_execute(enp, &req);
39 if (req.emr_rc != 0) {
44 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
49 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
56 EFSYS_PROBE1(fail1, efx_rc_t, rc);
61 __checkReturn efx_rc_t
62 efx_mcdi_get_port_modes(
64 __out uint32_t *modesp,
65 __out_opt uint32_t *current_modep,
66 __out_opt uint32_t *default_modep)
69 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_MODES_IN_LEN,
70 MC_CMD_GET_PORT_MODES_OUT_LEN);
73 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
74 enp->en_family == EFX_FAMILY_MEDFORD ||
75 enp->en_family == EFX_FAMILY_MEDFORD2);
77 req.emr_cmd = MC_CMD_GET_PORT_MODES;
78 req.emr_in_buf = payload;
79 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
80 req.emr_out_buf = payload;
81 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
83 efx_mcdi_execute(enp, &req);
85 if (req.emr_rc != 0) {
91 * Require only Modes and DefaultMode fields, unless the current mode
92 * was requested (CurrentMode field was added for Medford).
94 if (req.emr_out_length_used <
95 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
99 if ((current_modep != NULL) && (req.emr_out_length_used <
100 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) {
105 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
107 if (current_modep != NULL) {
108 *current_modep = MCDI_OUT_DWORD(req,
109 GET_PORT_MODES_OUT_CURRENT_MODE);
112 if (default_modep != NULL) {
113 *default_modep = MCDI_OUT_DWORD(req,
114 GET_PORT_MODES_OUT_DEFAULT_MODE);
124 EFSYS_PROBE1(fail1, efx_rc_t, rc);
129 __checkReturn efx_rc_t
130 ef10_nic_get_port_mode_bandwidth(
132 __out uint32_t *bandwidth_mbpsp)
135 uint32_t current_mode;
136 efx_port_t *epp = &(enp->en_port);
138 uint32_t single_lane;
144 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
145 ¤t_mode, NULL)) != 0) {
146 /* No port mode info available. */
150 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_25000FDX))
155 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_50000FDX))
160 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_100000FDX))
165 switch (current_mode) {
166 case TLV_PORT_MODE_1x1_NA: /* mode 0 */
167 bandwidth = single_lane;
169 case TLV_PORT_MODE_1x2_NA: /* mode 10 */
170 case TLV_PORT_MODE_NA_1x2: /* mode 11 */
171 bandwidth = dual_lane;
173 case TLV_PORT_MODE_1x1_1x1: /* mode 2 */
174 bandwidth = single_lane + single_lane;
176 case TLV_PORT_MODE_4x1_NA: /* mode 4 */
177 case TLV_PORT_MODE_NA_4x1: /* mode 8 */
178 bandwidth = 4 * single_lane;
180 case TLV_PORT_MODE_2x1_2x1: /* mode 5 */
181 bandwidth = (2 * single_lane) + (2 * single_lane);
183 case TLV_PORT_MODE_1x2_1x2: /* mode 12 */
184 bandwidth = dual_lane + dual_lane;
186 case TLV_PORT_MODE_1x2_2x1: /* mode 17 */
187 case TLV_PORT_MODE_2x1_1x2: /* mode 18 */
188 bandwidth = dual_lane + (2 * single_lane);
190 /* Legacy Medford-only mode. Do not use (see bug63270) */
191 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2: /* mode 9 */
192 bandwidth = 4 * single_lane;
194 case TLV_PORT_MODE_1x4_NA: /* mode 1 */
195 case TLV_PORT_MODE_NA_1x4: /* mode 22 */
196 bandwidth = quad_lane;
198 case TLV_PORT_MODE_2x2_NA: /* mode 13 */
199 case TLV_PORT_MODE_NA_2x2: /* mode 14 */
200 bandwidth = 2 * dual_lane;
202 case TLV_PORT_MODE_1x4_2x1: /* mode 6 */
203 case TLV_PORT_MODE_2x1_1x4: /* mode 7 */
204 bandwidth = quad_lane + (2 * single_lane);
206 case TLV_PORT_MODE_1x4_1x2: /* mode 15 */
207 case TLV_PORT_MODE_1x2_1x4: /* mode 16 */
208 bandwidth = quad_lane + dual_lane;
210 case TLV_PORT_MODE_1x4_1x4: /* mode 3 */
211 bandwidth = quad_lane + quad_lane;
218 *bandwidth_mbpsp = bandwidth;
225 EFSYS_PROBE1(fail1, efx_rc_t, rc);
230 static __checkReturn efx_rc_t
231 efx_mcdi_vadaptor_alloc(
233 __in uint32_t port_id)
236 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_ALLOC_IN_LEN,
237 MC_CMD_VADAPTOR_ALLOC_OUT_LEN);
240 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
242 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
243 req.emr_in_buf = payload;
244 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
245 req.emr_out_buf = payload;
246 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
248 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
249 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
250 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
251 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
253 efx_mcdi_execute(enp, &req);
255 if (req.emr_rc != 0) {
263 EFSYS_PROBE1(fail1, efx_rc_t, rc);
268 static __checkReturn efx_rc_t
269 efx_mcdi_vadaptor_free(
271 __in uint32_t port_id)
274 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_FREE_IN_LEN,
275 MC_CMD_VADAPTOR_FREE_OUT_LEN);
278 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
279 req.emr_in_buf = payload;
280 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
281 req.emr_out_buf = payload;
282 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
284 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
286 efx_mcdi_execute(enp, &req);
288 if (req.emr_rc != 0) {
296 EFSYS_PROBE1(fail1, efx_rc_t, rc);
301 __checkReturn efx_rc_t
302 efx_mcdi_get_mac_address_pf(
304 __out_ecount_opt(6) uint8_t mac_addrp[6])
307 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
308 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
311 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
312 enp->en_family == EFX_FAMILY_MEDFORD ||
313 enp->en_family == EFX_FAMILY_MEDFORD2);
315 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
316 req.emr_in_buf = payload;
317 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
318 req.emr_out_buf = payload;
319 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
321 efx_mcdi_execute(enp, &req);
323 if (req.emr_rc != 0) {
328 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
333 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
338 if (mac_addrp != NULL) {
341 addrp = MCDI_OUT2(req, uint8_t,
342 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
344 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
354 EFSYS_PROBE1(fail1, efx_rc_t, rc);
359 __checkReturn efx_rc_t
360 efx_mcdi_get_mac_address_vf(
362 __out_ecount_opt(6) uint8_t mac_addrp[6])
365 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
366 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
369 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
370 enp->en_family == EFX_FAMILY_MEDFORD ||
371 enp->en_family == EFX_FAMILY_MEDFORD2);
373 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
374 req.emr_in_buf = payload;
375 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
376 req.emr_out_buf = payload;
377 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
379 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
380 EVB_PORT_ID_ASSIGNED);
382 efx_mcdi_execute(enp, &req);
384 if (req.emr_rc != 0) {
389 if (req.emr_out_length_used <
390 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
395 if (MCDI_OUT_DWORD(req,
396 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
401 if (mac_addrp != NULL) {
404 addrp = MCDI_OUT2(req, uint8_t,
405 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
407 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
417 EFSYS_PROBE1(fail1, efx_rc_t, rc);
422 __checkReturn efx_rc_t
425 __out uint32_t *sys_freqp,
426 __out uint32_t *dpcpu_freqp)
429 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CLOCK_IN_LEN,
430 MC_CMD_GET_CLOCK_OUT_LEN);
433 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
434 enp->en_family == EFX_FAMILY_MEDFORD ||
435 enp->en_family == EFX_FAMILY_MEDFORD2);
437 req.emr_cmd = MC_CMD_GET_CLOCK;
438 req.emr_in_buf = payload;
439 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
440 req.emr_out_buf = payload;
441 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
443 efx_mcdi_execute(enp, &req);
445 if (req.emr_rc != 0) {
450 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
455 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
456 if (*sys_freqp == 0) {
460 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
461 if (*dpcpu_freqp == 0) {
475 EFSYS_PROBE1(fail1, efx_rc_t, rc);
480 __checkReturn efx_rc_t
481 efx_mcdi_get_rxdp_config(
483 __out uint32_t *end_paddingp)
486 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_RXDP_CONFIG_IN_LEN,
487 MC_CMD_GET_RXDP_CONFIG_OUT_LEN);
488 uint32_t end_padding;
491 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
492 req.emr_in_buf = payload;
493 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
494 req.emr_out_buf = payload;
495 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
497 efx_mcdi_execute(enp, &req);
498 if (req.emr_rc != 0) {
503 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
504 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
505 /* RX DMA end padding is disabled */
508 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
509 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
510 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
513 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
516 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
525 *end_paddingp = end_padding;
532 EFSYS_PROBE1(fail1, efx_rc_t, rc);
537 __checkReturn efx_rc_t
538 efx_mcdi_get_vector_cfg(
540 __out_opt uint32_t *vec_basep,
541 __out_opt uint32_t *pf_nvecp,
542 __out_opt uint32_t *vf_nvecp)
545 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_VECTOR_CFG_IN_LEN,
546 MC_CMD_GET_VECTOR_CFG_OUT_LEN);
549 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
550 req.emr_in_buf = payload;
551 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
552 req.emr_out_buf = payload;
553 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
555 efx_mcdi_execute(enp, &req);
557 if (req.emr_rc != 0) {
562 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
567 if (vec_basep != NULL)
568 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
569 if (pf_nvecp != NULL)
570 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
571 if (vf_nvecp != NULL)
572 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
579 EFSYS_PROBE1(fail1, efx_rc_t, rc);
584 static __checkReturn efx_rc_t
587 __in uint32_t min_vi_count,
588 __in uint32_t max_vi_count,
589 __out uint32_t *vi_basep,
590 __out uint32_t *vi_countp,
591 __out uint32_t *vi_shiftp)
594 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_VIS_IN_LEN,
595 MC_CMD_ALLOC_VIS_EXT_OUT_LEN);
598 if (vi_countp == NULL) {
603 req.emr_cmd = MC_CMD_ALLOC_VIS;
604 req.emr_in_buf = payload;
605 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
606 req.emr_out_buf = payload;
607 req.emr_out_length = MC_CMD_ALLOC_VIS_EXT_OUT_LEN;
609 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
610 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
612 efx_mcdi_execute(enp, &req);
614 if (req.emr_rc != 0) {
619 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
624 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
625 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
627 /* Report VI_SHIFT if available (always zero for Huntington) */
628 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
631 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
640 EFSYS_PROBE1(fail1, efx_rc_t, rc);
646 static __checkReturn efx_rc_t
653 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
654 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
656 req.emr_cmd = MC_CMD_FREE_VIS;
657 req.emr_in_buf = NULL;
658 req.emr_in_length = 0;
659 req.emr_out_buf = NULL;
660 req.emr_out_length = 0;
662 efx_mcdi_execute_quiet(enp, &req);
664 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
665 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
673 EFSYS_PROBE1(fail1, efx_rc_t, rc);
679 static __checkReturn efx_rc_t
680 efx_mcdi_alloc_piobuf(
682 __out efx_piobuf_handle_t *handlep)
685 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_PIOBUF_IN_LEN,
686 MC_CMD_ALLOC_PIOBUF_OUT_LEN);
689 if (handlep == NULL) {
694 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
695 req.emr_in_buf = payload;
696 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
697 req.emr_out_buf = payload;
698 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
700 efx_mcdi_execute_quiet(enp, &req);
702 if (req.emr_rc != 0) {
707 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
712 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
721 EFSYS_PROBE1(fail1, efx_rc_t, rc);
726 static __checkReturn efx_rc_t
727 efx_mcdi_free_piobuf(
729 __in efx_piobuf_handle_t handle)
732 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FREE_PIOBUF_IN_LEN,
733 MC_CMD_FREE_PIOBUF_OUT_LEN);
736 req.emr_cmd = MC_CMD_FREE_PIOBUF;
737 req.emr_in_buf = payload;
738 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
739 req.emr_out_buf = payload;
740 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
742 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
744 efx_mcdi_execute_quiet(enp, &req);
746 if (req.emr_rc != 0) {
754 EFSYS_PROBE1(fail1, efx_rc_t, rc);
759 static __checkReturn efx_rc_t
760 efx_mcdi_link_piobuf(
762 __in uint32_t vi_index,
763 __in efx_piobuf_handle_t handle)
766 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_LINK_PIOBUF_IN_LEN,
767 MC_CMD_LINK_PIOBUF_OUT_LEN);
770 req.emr_cmd = MC_CMD_LINK_PIOBUF;
771 req.emr_in_buf = payload;
772 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
773 req.emr_out_buf = payload;
774 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
776 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
777 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
779 efx_mcdi_execute(enp, &req);
781 if (req.emr_rc != 0) {
789 EFSYS_PROBE1(fail1, efx_rc_t, rc);
794 static __checkReturn efx_rc_t
795 efx_mcdi_unlink_piobuf(
797 __in uint32_t vi_index)
800 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_UNLINK_PIOBUF_IN_LEN,
801 MC_CMD_UNLINK_PIOBUF_OUT_LEN);
804 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
805 req.emr_in_buf = payload;
806 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
807 req.emr_out_buf = payload;
808 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
810 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
812 efx_mcdi_execute_quiet(enp, &req);
814 if (req.emr_rc != 0) {
822 EFSYS_PROBE1(fail1, efx_rc_t, rc);
828 ef10_nic_alloc_piobufs(
830 __in uint32_t max_piobuf_count)
832 efx_piobuf_handle_t *handlep;
835 EFSYS_ASSERT3U(max_piobuf_count, <=,
836 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
838 enp->en_arch.ef10.ena_piobuf_count = 0;
840 for (i = 0; i < max_piobuf_count; i++) {
841 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
843 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0)
846 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
847 enp->en_arch.ef10.ena_piobuf_count++;
853 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
854 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
856 (void) efx_mcdi_free_piobuf(enp, *handlep);
857 *handlep = EFX_PIOBUF_HANDLE_INVALID;
859 enp->en_arch.ef10.ena_piobuf_count = 0;
864 ef10_nic_free_piobufs(
867 efx_piobuf_handle_t *handlep;
870 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
871 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
873 (void) efx_mcdi_free_piobuf(enp, *handlep);
874 *handlep = EFX_PIOBUF_HANDLE_INVALID;
876 enp->en_arch.ef10.ena_piobuf_count = 0;
879 /* Sub-allocate a block from a piobuf */
880 __checkReturn efx_rc_t
882 __inout efx_nic_t *enp,
883 __out uint32_t *bufnump,
884 __out efx_piobuf_handle_t *handlep,
885 __out uint32_t *blknump,
886 __out uint32_t *offsetp,
889 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
890 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
891 uint32_t blk_per_buf;
895 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
896 enp->en_family == EFX_FAMILY_MEDFORD ||
897 enp->en_family == EFX_FAMILY_MEDFORD2);
898 EFSYS_ASSERT(bufnump);
899 EFSYS_ASSERT(handlep);
900 EFSYS_ASSERT(blknump);
901 EFSYS_ASSERT(offsetp);
904 if ((edcp->edc_pio_alloc_size == 0) ||
905 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
909 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
911 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
912 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
917 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
918 for (blk = 0; blk < blk_per_buf; blk++) {
919 if ((*map & (1u << blk)) == 0) {
929 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
932 *sizep = edcp->edc_pio_alloc_size;
933 *offsetp = blk * (*sizep);
940 EFSYS_PROBE1(fail1, efx_rc_t, rc);
945 /* Free a piobuf sub-allocated block */
946 __checkReturn efx_rc_t
948 __inout efx_nic_t *enp,
949 __in uint32_t bufnum,
950 __in uint32_t blknum)
955 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
956 (blknum >= (8 * sizeof (*map)))) {
961 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
962 if ((*map & (1u << blknum)) == 0) {
966 *map &= ~(1u << blknum);
973 EFSYS_PROBE1(fail1, efx_rc_t, rc);
978 __checkReturn efx_rc_t
980 __inout efx_nic_t *enp,
981 __in uint32_t vi_index,
982 __in efx_piobuf_handle_t handle)
984 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
987 __checkReturn efx_rc_t
989 __inout efx_nic_t *enp,
990 __in uint32_t vi_index)
992 return (efx_mcdi_unlink_piobuf(enp, vi_index));
995 static __checkReturn efx_rc_t
996 ef10_mcdi_get_pf_count(
998 __out uint32_t *pf_countp)
1001 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PF_COUNT_IN_LEN,
1002 MC_CMD_GET_PF_COUNT_OUT_LEN);
1005 req.emr_cmd = MC_CMD_GET_PF_COUNT;
1006 req.emr_in_buf = payload;
1007 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN;
1008 req.emr_out_buf = payload;
1009 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN;
1011 efx_mcdi_execute(enp, &req);
1013 if (req.emr_rc != 0) {
1018 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) {
1023 *pf_countp = *MCDI_OUT(req, uint8_t,
1024 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST);
1026 EFSYS_ASSERT(*pf_countp != 0);
1033 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1038 static __checkReturn efx_rc_t
1039 ef10_get_datapath_caps(
1040 __in efx_nic_t *enp)
1042 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1044 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CAPABILITIES_IN_LEN,
1045 MC_CMD_GET_CAPABILITIES_V5_OUT_LEN);
1048 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0)
1052 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
1053 req.emr_in_buf = payload;
1054 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
1055 req.emr_out_buf = payload;
1056 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V5_OUT_LEN;
1058 efx_mcdi_execute_quiet(enp, &req);
1060 if (req.emr_rc != 0) {
1065 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
1070 #define CAP_FLAGS1(_req, _flag) \
1071 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_OUT_FLAGS1) & \
1072 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN)))
1074 #define CAP_FLAGS2(_req, _flag) \
1075 (((_req).emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) && \
1076 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V2_OUT_FLAGS2) & \
1077 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN))))
1080 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
1081 * We only support the 14 byte prefix here.
1083 if (CAP_FLAGS1(req, RX_PREFIX_LEN_14) == 0) {
1087 encp->enc_rx_prefix_size = 14;
1089 #if EFSYS_OPT_RX_SCALE
1090 /* Check if the firmware supports additional RSS modes */
1091 if (CAP_FLAGS1(req, ADDITIONAL_RSS_MODES))
1092 encp->enc_rx_scale_additional_modes_supported = B_TRUE;
1094 encp->enc_rx_scale_additional_modes_supported = B_FALSE;
1095 #endif /* EFSYS_OPT_RX_SCALE */
1097 /* Check if the firmware supports TSO */
1098 if (CAP_FLAGS1(req, TX_TSO))
1099 encp->enc_fw_assisted_tso_enabled = B_TRUE;
1101 encp->enc_fw_assisted_tso_enabled = B_FALSE;
1103 /* Check if the firmware supports FATSOv2 */
1104 if (CAP_FLAGS2(req, TX_TSO_V2)) {
1105 encp->enc_fw_assisted_tso_v2_enabled = B_TRUE;
1106 encp->enc_fw_assisted_tso_v2_n_contexts = MCDI_OUT_WORD(req,
1107 GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS);
1109 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
1110 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
1113 /* Check if the firmware supports FATSOv2 encap */
1114 if (CAP_FLAGS2(req, TX_TSO_V2_ENCAP))
1115 encp->enc_fw_assisted_tso_v2_encap_enabled = B_TRUE;
1117 encp->enc_fw_assisted_tso_v2_encap_enabled = B_FALSE;
1119 /* Check if the firmware has vadapter/vport/vswitch support */
1120 if (CAP_FLAGS1(req, EVB))
1121 encp->enc_datapath_cap_evb = B_TRUE;
1123 encp->enc_datapath_cap_evb = B_FALSE;
1125 /* Check if the firmware supports VLAN insertion */
1126 if (CAP_FLAGS1(req, TX_VLAN_INSERTION))
1127 encp->enc_hw_tx_insert_vlan_enabled = B_TRUE;
1129 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
1131 /* Check if the firmware supports RX event batching */
1132 if (CAP_FLAGS1(req, RX_BATCHING))
1133 encp->enc_rx_batching_enabled = B_TRUE;
1135 encp->enc_rx_batching_enabled = B_FALSE;
1138 * Even if batching isn't reported as supported, we may still get
1139 * batched events (see bug61153).
1141 encp->enc_rx_batch_max = 16;
1143 /* Check if the firmware supports disabling scatter on RXQs */
1144 if (CAP_FLAGS1(req, RX_DISABLE_SCATTER))
1145 encp->enc_rx_disable_scatter_supported = B_TRUE;
1147 encp->enc_rx_disable_scatter_supported = B_FALSE;
1149 /* Check if the firmware supports packed stream mode */
1150 if (CAP_FLAGS1(req, RX_PACKED_STREAM))
1151 encp->enc_rx_packed_stream_supported = B_TRUE;
1153 encp->enc_rx_packed_stream_supported = B_FALSE;
1156 * Check if the firmware supports configurable buffer sizes
1157 * for packed stream mode (otherwise buffer size is 1Mbyte)
1159 if (CAP_FLAGS1(req, RX_PACKED_STREAM_VAR_BUFFERS))
1160 encp->enc_rx_var_packed_stream_supported = B_TRUE;
1162 encp->enc_rx_var_packed_stream_supported = B_FALSE;
1164 /* Check if the firmware supports equal stride super-buffer mode */
1165 if (CAP_FLAGS2(req, EQUAL_STRIDE_SUPER_BUFFER))
1166 encp->enc_rx_es_super_buffer_supported = B_TRUE;
1168 encp->enc_rx_es_super_buffer_supported = B_FALSE;
1170 /* Check if the firmware supports FW subvariant w/o Tx checksumming */
1171 if (CAP_FLAGS2(req, FW_SUBVARIANT_NO_TX_CSUM))
1172 encp->enc_fw_subvariant_no_tx_csum_supported = B_TRUE;
1174 encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE;
1176 /* Check if the firmware supports set mac with running filters */
1177 if (CAP_FLAGS1(req, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED))
1178 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
1180 encp->enc_allow_set_mac_with_installed_filters = B_FALSE;
1183 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows
1184 * specifying which parameters to configure.
1186 if (CAP_FLAGS1(req, SET_MAC_ENHANCED))
1187 encp->enc_enhanced_set_mac_supported = B_TRUE;
1189 encp->enc_enhanced_set_mac_supported = B_FALSE;
1192 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows
1193 * us to let the firmware choose the settings to use on an EVQ.
1195 if (CAP_FLAGS2(req, INIT_EVQ_V2))
1196 encp->enc_init_evq_v2_supported = B_TRUE;
1198 encp->enc_init_evq_v2_supported = B_FALSE;
1201 * Check if the NO_CONT_EV mode for RX events is supported.
1203 if (CAP_FLAGS2(req, INIT_RXQ_NO_CONT_EV))
1204 encp->enc_no_cont_ev_mode_supported = B_TRUE;
1206 encp->enc_no_cont_ev_mode_supported = B_FALSE;
1209 * Check if buffer size may and must be specified on INIT_RXQ.
1210 * It may be always specified to efx_rx_qcreate(), but will be
1211 * just kept libefx internal if MCDI does not support it.
1213 if (CAP_FLAGS2(req, INIT_RXQ_WITH_BUFFER_SIZE))
1214 encp->enc_init_rxq_with_buffer_size = B_TRUE;
1216 encp->enc_init_rxq_with_buffer_size = B_FALSE;
1219 * Check if firmware-verified NVRAM updates must be used.
1221 * The firmware trusted installer requires all NVRAM updates to use
1222 * version 2 of MC_CMD_NVRAM_UPDATE_START (to enable verified update)
1223 * and version 2 of MC_CMD_NVRAM_UPDATE_FINISH (to verify the updated
1224 * partition and report the result).
1226 if (CAP_FLAGS2(req, NVRAM_UPDATE_REPORT_VERIFY_RESULT))
1227 encp->enc_nvram_update_verify_result_supported = B_TRUE;
1229 encp->enc_nvram_update_verify_result_supported = B_FALSE;
1232 * Check if firmware provides packet memory and Rx datapath
1235 if (CAP_FLAGS1(req, PM_AND_RXDP_COUNTERS))
1236 encp->enc_pm_and_rxdp_counters = B_TRUE;
1238 encp->enc_pm_and_rxdp_counters = B_FALSE;
1241 * Check if the 40G MAC hardware is capable of reporting
1242 * statistics for Tx size bins.
1244 if (CAP_FLAGS2(req, MAC_STATS_40G_TX_SIZE_BINS))
1245 encp->enc_mac_stats_40g_tx_size_bins = B_TRUE;
1247 encp->enc_mac_stats_40g_tx_size_bins = B_FALSE;
1250 * Check if firmware supports VXLAN and NVGRE tunnels.
1251 * The capability indicates Geneve protocol support as well.
1253 if (CAP_FLAGS1(req, VXLAN_NVGRE)) {
1254 encp->enc_tunnel_encapsulations_supported =
1255 (1u << EFX_TUNNEL_PROTOCOL_VXLAN) |
1256 (1u << EFX_TUNNEL_PROTOCOL_GENEVE) |
1257 (1u << EFX_TUNNEL_PROTOCOL_NVGRE);
1259 EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES ==
1260 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
1261 encp->enc_tunnel_config_udp_entries_max =
1262 EFX_TUNNEL_MAXNENTRIES;
1264 encp->enc_tunnel_config_udp_entries_max = 0;
1268 * Check if firmware reports the VI window mode.
1269 * Medford2 has a variable VI window size (8K, 16K or 64K).
1270 * Medford and Huntington have a fixed 8K VI window size.
1272 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
1274 MCDI_OUT_BYTE(req, GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
1277 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
1278 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1280 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
1281 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_16K;
1283 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
1284 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_64K;
1287 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1290 } else if ((enp->en_family == EFX_FAMILY_HUNTINGTON) ||
1291 (enp->en_family == EFX_FAMILY_MEDFORD)) {
1292 /* Huntington and Medford have fixed 8K window size */
1293 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1295 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1298 /* Check if firmware supports extended MAC stats. */
1299 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
1300 /* Extended stats buffer supported */
1301 encp->enc_mac_stats_nstats = MCDI_OUT_WORD(req,
1302 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
1304 /* Use Siena-compatible legacy MAC stats */
1305 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS;
1308 if (encp->enc_mac_stats_nstats >= MC_CMD_MAC_NSTATS_V2)
1309 encp->enc_fec_counters = B_TRUE;
1311 encp->enc_fec_counters = B_FALSE;
1313 /* Check if the firmware provides head-of-line blocking counters */
1314 if (CAP_FLAGS2(req, RXDP_HLB_IDLE))
1315 encp->enc_hlb_counters = B_TRUE;
1317 encp->enc_hlb_counters = B_FALSE;
1319 #if EFSYS_OPT_RX_SCALE
1320 if (CAP_FLAGS1(req, RX_RSS_LIMITED)) {
1321 /* Only one exclusive RSS context is available per port. */
1322 encp->enc_rx_scale_max_exclusive_contexts = 1;
1324 switch (enp->en_family) {
1325 case EFX_FAMILY_MEDFORD2:
1326 encp->enc_rx_scale_hash_alg_mask =
1327 (1U << EFX_RX_HASHALG_TOEPLITZ);
1330 case EFX_FAMILY_MEDFORD:
1331 case EFX_FAMILY_HUNTINGTON:
1333 * Packed stream firmware variant maintains a
1334 * non-standard algorithm for hash computation.
1335 * It implies explicit XORing together
1336 * source + destination IP addresses (or last
1337 * four bytes in the case of IPv6) and using the
1338 * resulting value as the input to a Toeplitz hash.
1340 encp->enc_rx_scale_hash_alg_mask =
1341 (1U << EFX_RX_HASHALG_PACKED_STREAM);
1349 /* Port numbers cannot contribute to the hash value */
1350 encp->enc_rx_scale_l4_hash_supported = B_FALSE;
1353 * Maximum number of exclusive RSS contexts.
1354 * EF10 hardware supports 64 in total, but 6 are reserved
1355 * for shared contexts. They are a global resource so
1356 * not all may be available.
1358 encp->enc_rx_scale_max_exclusive_contexts = 64 - 6;
1360 encp->enc_rx_scale_hash_alg_mask =
1361 (1U << EFX_RX_HASHALG_TOEPLITZ);
1364 * It is possible to use port numbers as
1365 * the input data for hash computation.
1367 encp->enc_rx_scale_l4_hash_supported = B_TRUE;
1369 #endif /* EFSYS_OPT_RX_SCALE */
1371 /* Check if the firmware supports "FLAG" and "MARK" filter actions */
1372 if (CAP_FLAGS2(req, FILTER_ACTION_FLAG))
1373 encp->enc_filter_action_flag_supported = B_TRUE;
1375 encp->enc_filter_action_flag_supported = B_FALSE;
1377 if (CAP_FLAGS2(req, FILTER_ACTION_MARK))
1378 encp->enc_filter_action_mark_supported = B_TRUE;
1380 encp->enc_filter_action_mark_supported = B_FALSE;
1382 /* Get maximum supported value for "MARK" filter action */
1383 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V5_OUT_LEN)
1384 encp->enc_filter_action_mark_max = MCDI_OUT_DWORD(req,
1385 GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX);
1387 encp->enc_filter_action_mark_max = 0;
1394 #if EFSYS_OPT_RX_SCALE
1397 #endif /* EFSYS_OPT_RX_SCALE */
1405 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1411 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
1412 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
1413 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
1414 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
1415 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
1416 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
1417 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
1418 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
1419 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
1420 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
1421 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
1422 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
1424 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
1427 __checkReturn efx_rc_t
1428 ef10_get_privilege_mask(
1429 __in efx_nic_t *enp,
1430 __out uint32_t *maskp)
1432 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1436 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1441 /* Fallback for old firmware without privilege mask support */
1442 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1443 /* Assume PF has admin privilege */
1444 mask = EF10_LEGACY_PF_PRIVILEGE_MASK;
1446 /* VF is always unprivileged by default */
1447 mask = EF10_LEGACY_VF_PRIVILEGE_MASK;
1456 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1462 #define EFX_EXT_PORT_MAX 4
1463 #define EFX_EXT_PORT_NA 0xFF
1466 * Table of mapping schemes from port number to external number.
1468 * Each port number ultimately corresponds to a connector: either as part of
1469 * a cable assembly attached to a module inserted in an SFP+/QSFP+ cage on
1470 * the board, or fixed to the board (e.g. 10GBASE-T magjack on SFN5121T
1471 * "Salina"). In general:
1473 * Port number (0-based)
1475 * port mapping (n:1)
1478 * External port number (1-based)
1480 * fixed (1:1) or cable assembly (1:m)
1485 * The external numbering refers to the cages or magjacks on the board,
1486 * as visibly annotated on the board or back panel. This table describes
1487 * how to determine which external cage/magjack corresponds to the port
1488 * numbers used by the driver.
1490 * The count of consecutive port numbers that map to each external number,
1491 * is determined by the chip family and the current port mode.
1493 * For the Huntington family, the current port mode cannot be discovered,
1494 * but a single mapping is used by all modes for a given chip variant,
1495 * so the mapping used is instead the last match in the table to the full
1496 * set of port modes to which the NIC can be configured. Therefore the
1497 * ordering of entries in the mapping table is significant.
1499 static struct ef10_external_port_map_s {
1500 efx_family_t family;
1501 uint32_t modes_mask;
1502 uint8_t base_port[EFX_EXT_PORT_MAX];
1503 } __ef10_external_port_mappings[] = {
1505 * Modes used by Huntington family controllers where each port
1506 * number maps to a separate cage.
1507 * SFN7x22F (Torino):
1517 EFX_FAMILY_HUNTINGTON,
1518 (1U << TLV_PORT_MODE_10G) | /* mode 0 */
1519 (1U << TLV_PORT_MODE_10G_10G) | /* mode 2 */
1520 (1U << TLV_PORT_MODE_10G_10G_10G_10G), /* mode 4 */
1524 * Modes which for Huntington identify a chip variant where 2
1525 * adjacent port numbers map to each cage.
1533 EFX_FAMILY_HUNTINGTON,
1534 (1U << TLV_PORT_MODE_40G) | /* mode 1 */
1535 (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
1536 (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
1537 (1U << TLV_PORT_MODE_10G_10G_40G), /* mode 7 */
1538 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1541 * Modes that on Medford allocate each port number to a separate
1550 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1551 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1552 (1U << TLV_PORT_MODE_1x1_1x1), /* mode 2 */
1556 * Modes that on Medford allocate 2 adjacent port numbers to each
1565 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
1566 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 5 */
1567 (1U << TLV_PORT_MODE_1x4_2x1) | /* mode 6 */
1568 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
1569 /* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */
1570 (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */
1571 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1574 * Modes that on Medford allocate 4 adjacent port numbers to
1583 /* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */
1584 (1U << TLV_PORT_MODE_4x1_NA), /* mode 4 */
1585 { 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1588 * Modes that on Medford allocate 4 adjacent port numbers to
1597 (1U << TLV_PORT_MODE_NA_4x1), /* mode 8 */
1598 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1601 * Modes that on Medford2 allocate each port number to a separate
1609 EFX_FAMILY_MEDFORD2,
1610 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1611 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1612 (1U << TLV_PORT_MODE_1x1_1x1) | /* mode 2 */
1613 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
1614 (1U << TLV_PORT_MODE_1x2_NA) | /* mode 10 */
1615 (1U << TLV_PORT_MODE_1x2_1x2) | /* mode 12 */
1616 (1U << TLV_PORT_MODE_1x4_1x2) | /* mode 15 */
1617 (1U << TLV_PORT_MODE_1x2_1x4), /* mode 16 */
1621 * Modes that on Medford2 allocate 1 port to cage 1 and the rest
1628 EFX_FAMILY_MEDFORD2,
1629 (1U << TLV_PORT_MODE_1x2_2x1) | /* mode 17 */
1630 (1U << TLV_PORT_MODE_1x4_2x1), /* mode 6 */
1631 { 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1634 * Modes that on Medford2 allocate 2 adjacent port numbers to cage 1
1635 * and the rest to cage 2.
1642 EFX_FAMILY_MEDFORD2,
1643 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 4 */
1644 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
1645 (1U << TLV_PORT_MODE_2x2_NA) | /* mode 13 */
1646 (1U << TLV_PORT_MODE_2x1_1x2), /* mode 18 */
1647 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1650 * Modes that on Medford2 allocate up to 4 adjacent port numbers
1658 EFX_FAMILY_MEDFORD2,
1659 (1U << TLV_PORT_MODE_4x1_NA), /* mode 5 */
1660 { 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1663 * Modes that on Medford2 allocate up to 4 adjacent port numbers
1671 EFX_FAMILY_MEDFORD2,
1672 (1U << TLV_PORT_MODE_NA_4x1) | /* mode 8 */
1673 (1U << TLV_PORT_MODE_NA_1x2) | /* mode 11 */
1674 (1U << TLV_PORT_MODE_NA_2x2), /* mode 14 */
1675 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1679 static __checkReturn efx_rc_t
1680 ef10_external_port_mapping(
1681 __in efx_nic_t *enp,
1683 __out uint8_t *external_portp)
1687 uint32_t port_modes;
1690 struct ef10_external_port_map_s *mapp = NULL;
1691 int ext_index = port; /* Default 1-1 mapping */
1693 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t,
1696 * No current port mode information (i.e. Huntington)
1697 * - infer mapping from available modes
1699 if ((rc = efx_mcdi_get_port_modes(enp,
1700 &port_modes, NULL, NULL)) != 0) {
1702 * No port mode information available
1703 * - use default mapping
1708 /* Only need to scan the current mode */
1709 port_modes = 1 << current;
1713 * Infer the internal port -> external number mapping from
1714 * the possible port modes for this NIC.
1716 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1717 struct ef10_external_port_map_s *eepmp =
1718 &__ef10_external_port_mappings[i];
1719 if (eepmp->family != enp->en_family)
1721 matches = (eepmp->modes_mask & port_modes);
1724 * Some modes match. For some Huntington boards
1725 * there will be multiple matches. The mapping on the
1726 * last match is used.
1729 port_modes &= ~matches;
1733 if (port_modes != 0) {
1734 /* Some advertised modes are not supported */
1742 * External ports are assigned a sequence of consecutive
1743 * port numbers, so find the one with the closest base_port.
1745 uint32_t delta = EFX_EXT_PORT_NA;
1747 for (i = 0; i < EFX_EXT_PORT_MAX; i++) {
1748 uint32_t base = mapp->base_port[i];
1749 if ((base != EFX_EXT_PORT_NA) && (base <= port)) {
1750 if ((port - base) < delta) {
1751 delta = (port - base);
1757 *external_portp = (uint8_t)(ext_index + 1);
1762 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1767 static __checkReturn efx_rc_t
1769 __in efx_nic_t *enp)
1771 const efx_nic_ops_t *enop = enp->en_enop;
1772 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
1773 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1774 ef10_link_state_t els;
1775 efx_port_t *epp = &(enp->en_port);
1776 uint32_t board_type = 0;
1777 uint32_t base, nvec;
1782 uint8_t mac_addr[6] = { 0 };
1785 /* Get the (zero-based) MCDI port number */
1786 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
1789 /* EFX MCDI interface uses one-based port numbers */
1790 emip->emi_port = port + 1;
1792 if ((rc = ef10_external_port_mapping(enp, port,
1793 &encp->enc_external_port)) != 0)
1797 * Get PCIe function number from firmware (used for
1798 * per-function privilege and dynamic config info).
1799 * - PCIe PF: pf = PF number, vf = 0xffff.
1800 * - PCIe VF: pf = parent PF, vf = VF number.
1802 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
1808 /* MAC address for this function */
1809 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1810 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
1811 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
1813 * Disable static config checking, ONLY for manufacturing test
1814 * and setup at the factory, to allow the static config to be
1817 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1818 if ((rc == 0) && (mac_addr[0] & 0x02)) {
1820 * If the static config does not include a global MAC
1821 * address pool then the board may return a locally
1822 * administered MAC address (this should only happen on
1823 * incorrectly programmed boards).
1827 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1829 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
1834 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
1836 /* Board configuration (legacy) */
1837 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
1839 /* Unprivileged functions may not be able to read board cfg */
1846 encp->enc_board_type = board_type;
1847 encp->enc_clk_mult = 1; /* not used for EF10 */
1849 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
1850 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
1854 * Firmware with support for *_FEC capability bits does not
1855 * report that the corresponding *_FEC_REQUESTED bits are supported.
1856 * Add them here so that drivers understand that they are supported.
1858 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_BASER_FEC))
1859 epp->ep_phy_cap_mask |=
1860 (1u << EFX_PHY_CAP_BASER_FEC_REQUESTED);
1861 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_RS_FEC))
1862 epp->ep_phy_cap_mask |=
1863 (1u << EFX_PHY_CAP_RS_FEC_REQUESTED);
1864 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_25G_BASER_FEC))
1865 epp->ep_phy_cap_mask |=
1866 (1u << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED);
1868 /* Obtain the default PHY advertised capabilities */
1869 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
1871 epp->ep_default_adv_cap_mask = els.epls.epls_adv_cap_mask;
1872 epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask;
1874 /* Check capabilities of running datapath firmware */
1875 if ((rc = ef10_get_datapath_caps(enp)) != 0)
1878 /* Alignment for WPTR updates */
1879 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
1881 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
1882 /* No boundary crossing limits */
1883 encp->enc_tx_dma_desc_boundary = 0;
1886 * Maximum number of bytes into the frame the TCP header can start for
1887 * firmware assisted TSO to work.
1889 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
1892 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
1893 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
1894 * resources (allocated to this PCIe function), which is zero until
1895 * after we have allocated VIs.
1897 encp->enc_evq_limit = 1024;
1898 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
1899 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
1901 encp->enc_buftbl_limit = 0xFFFFFFFF;
1903 /* Get interrupt vector limits */
1904 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
1905 if (EFX_PCI_FUNCTION_IS_PF(encp))
1908 /* Ignore error (cannot query vector limits from a VF). */
1912 encp->enc_intr_vec_base = base;
1913 encp->enc_intr_limit = nvec;
1916 * Get the current privilege mask. Note that this may be modified
1917 * dynamically, so this value is informational only. DO NOT use
1918 * the privilege mask to check for sufficient privileges, as that
1919 * can result in time-of-check/time-of-use bugs.
1921 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
1923 encp->enc_privilege_mask = mask;
1925 /* Get remaining controller-specific board config */
1926 if ((rc = enop->eno_board_cfg(enp)) != 0)
1933 EFSYS_PROBE(fail11);
1935 EFSYS_PROBE(fail10);
1953 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1958 __checkReturn efx_rc_t
1960 __in efx_nic_t *enp)
1962 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1963 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1966 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1967 enp->en_family == EFX_FAMILY_MEDFORD ||
1968 enp->en_family == EFX_FAMILY_MEDFORD2);
1970 /* Read and clear any assertion state */
1971 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1974 /* Exit the assertion handler */
1975 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1979 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
1982 if ((rc = ef10_nic_board_cfg(enp)) != 0)
1986 * Set default driver config limits (based on board config).
1988 * FIXME: For now allocate a fixed number of VIs which is likely to be
1989 * sufficient and small enough to allow multiple functions on the same
1992 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
1993 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
1995 /* The client driver must configure and enable PIO buffer support */
1996 edcp->edc_max_piobuf_count = 0;
1997 edcp->edc_pio_alloc_size = 0;
1999 #if EFSYS_OPT_MAC_STATS
2000 /* Wipe the MAC statistics */
2001 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
2005 #if EFSYS_OPT_LOOPBACK
2006 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
2010 #if EFSYS_OPT_MON_STATS
2011 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
2012 /* Unprivileged functions do not have access to sensors */
2018 encp->enc_features = enp->en_features;
2022 #if EFSYS_OPT_MON_STATS
2026 #if EFSYS_OPT_LOOPBACK
2030 #if EFSYS_OPT_MAC_STATS
2041 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2046 __checkReturn efx_rc_t
2047 ef10_nic_set_drv_limits(
2048 __inout efx_nic_t *enp,
2049 __in efx_drv_limits_t *edlp)
2051 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
2052 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2053 uint32_t min_evq_count, max_evq_count;
2054 uint32_t min_rxq_count, max_rxq_count;
2055 uint32_t min_txq_count, max_txq_count;
2063 /* Get minimum required and maximum usable VI limits */
2064 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
2065 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
2066 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
2068 edcp->edc_min_vi_count =
2069 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
2071 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
2072 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
2073 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
2075 edcp->edc_max_vi_count =
2076 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
2079 * Check limits for sub-allocated piobuf blocks.
2080 * PIO is optional, so don't fail if the limits are incorrect.
2082 if ((encp->enc_piobuf_size == 0) ||
2083 (encp->enc_piobuf_limit == 0) ||
2084 (edlp->edl_min_pio_alloc_size == 0) ||
2085 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
2087 edcp->edc_max_piobuf_count = 0;
2088 edcp->edc_pio_alloc_size = 0;
2090 uint32_t blk_size, blk_count, blks_per_piobuf;
2093 MAX(edlp->edl_min_pio_alloc_size,
2094 encp->enc_piobuf_min_alloc_size);
2096 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
2097 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
2099 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
2101 /* A zero max pio alloc count means unlimited */
2102 if ((edlp->edl_max_pio_alloc_count > 0) &&
2103 (edlp->edl_max_pio_alloc_count < blk_count)) {
2104 blk_count = edlp->edl_max_pio_alloc_count;
2107 edcp->edc_pio_alloc_size = blk_size;
2108 edcp->edc_max_piobuf_count =
2109 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
2115 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2121 __checkReturn efx_rc_t
2123 __in efx_nic_t *enp)
2126 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ENTITY_RESET_IN_LEN,
2127 MC_CMD_ENTITY_RESET_OUT_LEN);
2130 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
2131 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
2133 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
2136 req.emr_cmd = MC_CMD_ENTITY_RESET;
2137 req.emr_in_buf = payload;
2138 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
2139 req.emr_out_buf = payload;
2140 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
2142 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
2143 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
2145 efx_mcdi_execute(enp, &req);
2147 if (req.emr_rc != 0) {
2152 /* Clear RX/TX DMA queue errors */
2153 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
2162 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2167 __checkReturn efx_rc_t
2169 __in efx_nic_t *enp)
2171 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2172 uint32_t min_vi_count, max_vi_count;
2173 uint32_t vi_count, vi_base, vi_shift;
2177 uint32_t vi_window_size;
2180 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2181 enp->en_family == EFX_FAMILY_MEDFORD ||
2182 enp->en_family == EFX_FAMILY_MEDFORD2);
2184 /* Enable reporting of some events (e.g. link change) */
2185 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
2188 /* Allocate (optional) on-chip PIO buffers */
2189 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
2192 * For best performance, PIO writes should use a write-combined
2193 * (WC) memory mapping. Using a separate WC mapping for the PIO
2194 * aperture of each VI would be a burden to drivers (and not
2195 * possible if the host page size is >4Kbyte).
2197 * To avoid this we use a single uncached (UC) mapping for VI
2198 * register access, and a single WC mapping for extra VIs used
2201 * Each piobuf must be linked to a VI in the WC mapping, and to
2202 * each VI that is using a sub-allocated block from the piobuf.
2204 min_vi_count = edcp->edc_min_vi_count;
2206 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
2208 /* Ensure that the previously attached driver's VIs are freed */
2209 if ((rc = efx_mcdi_free_vis(enp)) != 0)
2213 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
2214 * fails then retrying the request for fewer VI resources may succeed.
2217 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
2218 &vi_base, &vi_count, &vi_shift)) != 0)
2221 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
2223 if (vi_count < min_vi_count) {
2228 enp->en_arch.ef10.ena_vi_base = vi_base;
2229 enp->en_arch.ef10.ena_vi_count = vi_count;
2230 enp->en_arch.ef10.ena_vi_shift = vi_shift;
2232 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
2233 /* Not enough extra VIs to map piobufs */
2234 ef10_nic_free_piobufs(enp);
2237 enp->en_arch.ef10.ena_pio_write_vi_base =
2238 vi_count - enp->en_arch.ef10.ena_piobuf_count;
2240 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, !=,
2241 EFX_VI_WINDOW_SHIFT_INVALID);
2242 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, <=,
2243 EFX_VI_WINDOW_SHIFT_64K);
2244 vi_window_size = 1U << enp->en_nic_cfg.enc_vi_window_shift;
2246 /* Save UC memory mapping details */
2247 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
2248 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2249 enp->en_arch.ef10.ena_uc_mem_map_size =
2251 enp->en_arch.ef10.ena_pio_write_vi_base);
2253 enp->en_arch.ef10.ena_uc_mem_map_size =
2255 enp->en_arch.ef10.ena_vi_count);
2258 /* Save WC memory mapping details */
2259 enp->en_arch.ef10.ena_wc_mem_map_offset =
2260 enp->en_arch.ef10.ena_uc_mem_map_offset +
2261 enp->en_arch.ef10.ena_uc_mem_map_size;
2263 enp->en_arch.ef10.ena_wc_mem_map_size =
2265 enp->en_arch.ef10.ena_piobuf_count);
2267 /* Link piobufs to extra VIs in WC mapping */
2268 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2269 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2270 rc = efx_mcdi_link_piobuf(enp,
2271 enp->en_arch.ef10.ena_pio_write_vi_base + i,
2272 enp->en_arch.ef10.ena_piobuf_handle[i]);
2279 * Allocate a vAdaptor attached to our upstream vPort/pPort.
2281 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
2282 * driver has yet to bring up the EVB port. See bug 56147. In this case,
2283 * retry the request several times after waiting a while. The wait time
2284 * between retries starts small (10ms) and exponentially increases.
2285 * Total wait time is a little over two seconds. Retry logic in the
2286 * client driver may mean this whole loop is repeated if it continues to
2291 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
2292 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
2295 * Do not retry alloc for PF, or for other errors on
2301 /* VF startup before PF is ready. Retry allocation. */
2303 /* Too many attempts */
2307 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
2308 EFSYS_SLEEP(delay_us);
2310 if (delay_us < 500000)
2314 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
2315 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
2330 ef10_nic_free_piobufs(enp);
2333 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2338 __checkReturn efx_rc_t
2339 ef10_nic_get_vi_pool(
2340 __in efx_nic_t *enp,
2341 __out uint32_t *vi_countp)
2343 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2344 enp->en_family == EFX_FAMILY_MEDFORD ||
2345 enp->en_family == EFX_FAMILY_MEDFORD2);
2348 * Report VIs that the client driver can use.
2349 * Do not include VIs used for PIO buffer writes.
2351 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
2356 __checkReturn efx_rc_t
2357 ef10_nic_get_bar_region(
2358 __in efx_nic_t *enp,
2359 __in efx_nic_region_t region,
2360 __out uint32_t *offsetp,
2361 __out size_t *sizep)
2365 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2366 enp->en_family == EFX_FAMILY_MEDFORD ||
2367 enp->en_family == EFX_FAMILY_MEDFORD2);
2370 * TODO: Specify host memory mapping alignment and granularity
2371 * in efx_drv_limits_t so that they can be taken into account
2372 * when allocating extra VIs for PIO writes.
2376 /* UC mapped memory BAR region for VI registers */
2377 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
2378 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
2381 case EFX_REGION_PIO_WRITE_VI:
2382 /* WC mapped memory BAR region for piobuf writes */
2383 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
2384 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
2395 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2400 __checkReturn boolean_t
2401 ef10_nic_hw_unavailable(
2402 __in efx_nic_t *enp)
2406 if (enp->en_reset_flags & EFX_RESET_HW_UNAVAIL)
2409 EFX_BAR_READD(enp, ER_DZ_BIU_MC_SFT_STATUS_REG, &dword, B_FALSE);
2410 if (EFX_DWORD_FIELD(dword, EFX_DWORD_0) == 0xffffffff)
2416 ef10_nic_set_hw_unavailable(enp);
2422 ef10_nic_set_hw_unavailable(
2423 __in efx_nic_t *enp)
2425 EFSYS_PROBE(hw_unavail);
2426 enp->en_reset_flags |= EFX_RESET_HW_UNAVAIL;
2432 __in efx_nic_t *enp)
2437 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
2438 enp->en_vport_id = 0;
2440 /* Unlink piobufs from extra VIs in WC mapping */
2441 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2442 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2443 rc = efx_mcdi_unlink_piobuf(enp,
2444 enp->en_arch.ef10.ena_pio_write_vi_base + i);
2450 ef10_nic_free_piobufs(enp);
2452 (void) efx_mcdi_free_vis(enp);
2453 enp->en_arch.ef10.ena_vi_count = 0;
2458 __in efx_nic_t *enp)
2460 #if EFSYS_OPT_MON_STATS
2461 mcdi_mon_cfg_free(enp);
2462 #endif /* EFSYS_OPT_MON_STATS */
2463 (void) efx_mcdi_drv_attach(enp, B_FALSE);
2468 __checkReturn efx_rc_t
2469 ef10_nic_register_test(
2470 __in efx_nic_t *enp)
2475 _NOTE(ARGUNUSED(enp))
2476 _NOTE(CONSTANTCONDITION)
2486 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2491 #endif /* EFSYS_OPT_DIAG */
2493 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
2495 __checkReturn efx_rc_t
2496 efx_mcdi_get_nic_global(
2497 __in efx_nic_t *enp,
2499 __out uint32_t *valuep)
2502 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_NIC_GLOBAL_IN_LEN,
2503 MC_CMD_GET_NIC_GLOBAL_OUT_LEN);
2506 req.emr_cmd = MC_CMD_GET_NIC_GLOBAL;
2507 req.emr_in_buf = payload;
2508 req.emr_in_length = MC_CMD_GET_NIC_GLOBAL_IN_LEN;
2509 req.emr_out_buf = payload;
2510 req.emr_out_length = MC_CMD_GET_NIC_GLOBAL_OUT_LEN;
2512 MCDI_IN_SET_DWORD(req, GET_NIC_GLOBAL_IN_KEY, key);
2514 efx_mcdi_execute(enp, &req);
2516 if (req.emr_rc != 0) {
2521 if (req.emr_out_length_used != MC_CMD_GET_NIC_GLOBAL_OUT_LEN) {
2526 *valuep = MCDI_OUT_DWORD(req, GET_NIC_GLOBAL_OUT_VALUE);
2533 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2538 __checkReturn efx_rc_t
2539 efx_mcdi_set_nic_global(
2540 __in efx_nic_t *enp,
2542 __in uint32_t value)
2545 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_NIC_GLOBAL_IN_LEN, 0);
2548 req.emr_cmd = MC_CMD_SET_NIC_GLOBAL;
2549 req.emr_in_buf = payload;
2550 req.emr_in_length = MC_CMD_SET_NIC_GLOBAL_IN_LEN;
2551 req.emr_out_buf = NULL;
2552 req.emr_out_length = 0;
2554 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_KEY, key);
2555 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_VALUE, value);
2557 efx_mcdi_execute(enp, &req);
2559 if (req.emr_rc != 0) {
2567 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2572 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
2574 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */