2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
33 #if EFSYS_OPT_MON_MCDI
37 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
39 #include "ef10_tlv_layout.h"
41 __checkReturn efx_rc_t
42 efx_mcdi_get_port_assignment(
44 __out uint32_t *portp)
47 uint8_t payload[MAX(MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
48 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN)];
51 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
52 enp->en_family == EFX_FAMILY_MEDFORD);
54 (void) memset(payload, 0, sizeof (payload));
55 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
56 req.emr_in_buf = payload;
57 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
58 req.emr_out_buf = payload;
59 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
61 efx_mcdi_execute(enp, &req);
63 if (req.emr_rc != 0) {
68 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
73 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
80 EFSYS_PROBE1(fail1, efx_rc_t, rc);
85 __checkReturn efx_rc_t
86 efx_mcdi_get_port_modes(
88 __out uint32_t *modesp,
89 __out_opt uint32_t *current_modep)
92 uint8_t payload[MAX(MC_CMD_GET_PORT_MODES_IN_LEN,
93 MC_CMD_GET_PORT_MODES_OUT_LEN)];
96 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
97 enp->en_family == EFX_FAMILY_MEDFORD);
99 (void) memset(payload, 0, sizeof (payload));
100 req.emr_cmd = MC_CMD_GET_PORT_MODES;
101 req.emr_in_buf = payload;
102 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
103 req.emr_out_buf = payload;
104 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
106 efx_mcdi_execute(enp, &req);
108 if (req.emr_rc != 0) {
114 * Require only Modes and DefaultMode fields, unless the current mode
115 * was requested (CurrentMode field was added for Medford).
117 if (req.emr_out_length_used <
118 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
122 if ((current_modep != NULL) && (req.emr_out_length_used <
123 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) {
128 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
130 if (current_modep != NULL) {
131 *current_modep = MCDI_OUT_DWORD(req,
132 GET_PORT_MODES_OUT_CURRENT_MODE);
142 EFSYS_PROBE1(fail1, efx_rc_t, rc);
147 __checkReturn efx_rc_t
148 ef10_nic_get_port_mode_bandwidth(
149 __in uint32_t port_mode,
150 __out uint32_t *bandwidth_mbpsp)
156 case TLV_PORT_MODE_10G:
159 case TLV_PORT_MODE_10G_10G:
160 bandwidth = 10000 * 2;
162 case TLV_PORT_MODE_10G_10G_10G_10G:
163 case TLV_PORT_MODE_10G_10G_10G_10G_Q:
164 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2:
165 case TLV_PORT_MODE_10G_10G_10G_10G_Q2:
166 bandwidth = 10000 * 4;
168 case TLV_PORT_MODE_40G:
171 case TLV_PORT_MODE_40G_40G:
172 bandwidth = 40000 * 2;
174 case TLV_PORT_MODE_40G_10G_10G:
175 case TLV_PORT_MODE_10G_10G_40G:
176 bandwidth = 40000 + (10000 * 2);
183 *bandwidth_mbpsp = bandwidth;
188 EFSYS_PROBE1(fail1, efx_rc_t, rc);
193 static __checkReturn efx_rc_t
194 efx_mcdi_vadaptor_alloc(
196 __in uint32_t port_id)
199 uint8_t payload[MAX(MC_CMD_VADAPTOR_ALLOC_IN_LEN,
200 MC_CMD_VADAPTOR_ALLOC_OUT_LEN)];
203 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
205 (void) memset(payload, 0, sizeof (payload));
206 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
207 req.emr_in_buf = payload;
208 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
209 req.emr_out_buf = payload;
210 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
212 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
213 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
214 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
215 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
217 efx_mcdi_execute(enp, &req);
219 if (req.emr_rc != 0) {
227 EFSYS_PROBE1(fail1, efx_rc_t, rc);
232 static __checkReturn efx_rc_t
233 efx_mcdi_vadaptor_free(
235 __in uint32_t port_id)
238 uint8_t payload[MAX(MC_CMD_VADAPTOR_FREE_IN_LEN,
239 MC_CMD_VADAPTOR_FREE_OUT_LEN)];
242 (void) memset(payload, 0, sizeof (payload));
243 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
244 req.emr_in_buf = payload;
245 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
246 req.emr_out_buf = payload;
247 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
249 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
251 efx_mcdi_execute(enp, &req);
253 if (req.emr_rc != 0) {
261 EFSYS_PROBE1(fail1, efx_rc_t, rc);
266 __checkReturn efx_rc_t
267 efx_mcdi_get_mac_address_pf(
269 __out_ecount_opt(6) uint8_t mac_addrp[6])
272 uint8_t payload[MAX(MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
273 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)];
276 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
277 enp->en_family == EFX_FAMILY_MEDFORD);
279 (void) memset(payload, 0, sizeof (payload));
280 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
281 req.emr_in_buf = payload;
282 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
283 req.emr_out_buf = payload;
284 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
286 efx_mcdi_execute(enp, &req);
288 if (req.emr_rc != 0) {
293 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
298 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
303 if (mac_addrp != NULL) {
306 addrp = MCDI_OUT2(req, uint8_t,
307 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
309 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
319 EFSYS_PROBE1(fail1, efx_rc_t, rc);
324 __checkReturn efx_rc_t
325 efx_mcdi_get_mac_address_vf(
327 __out_ecount_opt(6) uint8_t mac_addrp[6])
330 uint8_t payload[MAX(MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
331 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX)];
334 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
335 enp->en_family == EFX_FAMILY_MEDFORD);
337 (void) memset(payload, 0, sizeof (payload));
338 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
339 req.emr_in_buf = payload;
340 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
341 req.emr_out_buf = payload;
342 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
344 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
345 EVB_PORT_ID_ASSIGNED);
347 efx_mcdi_execute(enp, &req);
349 if (req.emr_rc != 0) {
354 if (req.emr_out_length_used <
355 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
360 if (MCDI_OUT_DWORD(req,
361 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
366 if (mac_addrp != NULL) {
369 addrp = MCDI_OUT2(req, uint8_t,
370 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
372 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
382 EFSYS_PROBE1(fail1, efx_rc_t, rc);
387 __checkReturn efx_rc_t
390 __out uint32_t *sys_freqp,
391 __out uint32_t *dpcpu_freqp)
394 uint8_t payload[MAX(MC_CMD_GET_CLOCK_IN_LEN,
395 MC_CMD_GET_CLOCK_OUT_LEN)];
398 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
399 enp->en_family == EFX_FAMILY_MEDFORD);
401 (void) memset(payload, 0, sizeof (payload));
402 req.emr_cmd = MC_CMD_GET_CLOCK;
403 req.emr_in_buf = payload;
404 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
405 req.emr_out_buf = payload;
406 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
408 efx_mcdi_execute(enp, &req);
410 if (req.emr_rc != 0) {
415 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
420 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
421 if (*sys_freqp == 0) {
425 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
426 if (*dpcpu_freqp == 0) {
440 EFSYS_PROBE1(fail1, efx_rc_t, rc);
445 __checkReturn efx_rc_t
446 efx_mcdi_get_vector_cfg(
448 __out_opt uint32_t *vec_basep,
449 __out_opt uint32_t *pf_nvecp,
450 __out_opt uint32_t *vf_nvecp)
453 uint8_t payload[MAX(MC_CMD_GET_VECTOR_CFG_IN_LEN,
454 MC_CMD_GET_VECTOR_CFG_OUT_LEN)];
457 (void) memset(payload, 0, sizeof (payload));
458 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
459 req.emr_in_buf = payload;
460 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
461 req.emr_out_buf = payload;
462 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
464 efx_mcdi_execute(enp, &req);
466 if (req.emr_rc != 0) {
471 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
476 if (vec_basep != NULL)
477 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
478 if (pf_nvecp != NULL)
479 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
480 if (vf_nvecp != NULL)
481 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
488 EFSYS_PROBE1(fail1, efx_rc_t, rc);
493 static __checkReturn efx_rc_t
494 efx_mcdi_get_capabilities(
496 __out uint32_t *flagsp,
497 __out uint32_t *flags2p,
498 __out uint32_t *tso2ncp)
501 uint8_t payload[MAX(MC_CMD_GET_CAPABILITIES_IN_LEN,
502 MC_CMD_GET_CAPABILITIES_V2_OUT_LEN)];
505 (void) memset(payload, 0, sizeof (payload));
506 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
507 req.emr_in_buf = payload;
508 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
509 req.emr_out_buf = payload;
510 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V2_OUT_LEN;
512 efx_mcdi_execute(enp, &req);
514 if (req.emr_rc != 0) {
519 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
524 *flagsp = MCDI_OUT_DWORD(req, GET_CAPABILITIES_OUT_FLAGS1);
526 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
530 *flags2p = MCDI_OUT_DWORD(req, GET_CAPABILITIES_V2_OUT_FLAGS2);
531 *tso2ncp = MCDI_OUT_WORD(req,
532 GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS);
540 EFSYS_PROBE1(fail1, efx_rc_t, rc);
546 static __checkReturn efx_rc_t
549 __in uint32_t min_vi_count,
550 __in uint32_t max_vi_count,
551 __out uint32_t *vi_basep,
552 __out uint32_t *vi_countp,
553 __out uint32_t *vi_shiftp)
556 uint8_t payload[MAX(MC_CMD_ALLOC_VIS_IN_LEN,
557 MC_CMD_ALLOC_VIS_OUT_LEN)];
560 if (vi_countp == NULL) {
565 (void) memset(payload, 0, sizeof (payload));
566 req.emr_cmd = MC_CMD_ALLOC_VIS;
567 req.emr_in_buf = payload;
568 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
569 req.emr_out_buf = payload;
570 req.emr_out_length = MC_CMD_ALLOC_VIS_OUT_LEN;
572 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
573 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
575 efx_mcdi_execute(enp, &req);
577 if (req.emr_rc != 0) {
582 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
587 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
588 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
590 /* Report VI_SHIFT if available (always zero for Huntington) */
591 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
594 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
603 EFSYS_PROBE1(fail1, efx_rc_t, rc);
609 static __checkReturn efx_rc_t
616 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
617 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
619 req.emr_cmd = MC_CMD_FREE_VIS;
620 req.emr_in_buf = NULL;
621 req.emr_in_length = 0;
622 req.emr_out_buf = NULL;
623 req.emr_out_length = 0;
625 efx_mcdi_execute_quiet(enp, &req);
627 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
628 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
636 EFSYS_PROBE1(fail1, efx_rc_t, rc);
642 static __checkReturn efx_rc_t
643 efx_mcdi_alloc_piobuf(
645 __out efx_piobuf_handle_t *handlep)
648 uint8_t payload[MAX(MC_CMD_ALLOC_PIOBUF_IN_LEN,
649 MC_CMD_ALLOC_PIOBUF_OUT_LEN)];
652 if (handlep == NULL) {
657 (void) memset(payload, 0, sizeof (payload));
658 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
659 req.emr_in_buf = payload;
660 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
661 req.emr_out_buf = payload;
662 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
664 efx_mcdi_execute_quiet(enp, &req);
666 if (req.emr_rc != 0) {
671 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
676 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
685 EFSYS_PROBE1(fail1, efx_rc_t, rc);
690 static __checkReturn efx_rc_t
691 efx_mcdi_free_piobuf(
693 __in efx_piobuf_handle_t handle)
696 uint8_t payload[MAX(MC_CMD_FREE_PIOBUF_IN_LEN,
697 MC_CMD_FREE_PIOBUF_OUT_LEN)];
700 (void) memset(payload, 0, sizeof (payload));
701 req.emr_cmd = MC_CMD_FREE_PIOBUF;
702 req.emr_in_buf = payload;
703 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
704 req.emr_out_buf = payload;
705 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
707 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
709 efx_mcdi_execute_quiet(enp, &req);
711 if (req.emr_rc != 0) {
719 EFSYS_PROBE1(fail1, efx_rc_t, rc);
724 static __checkReturn efx_rc_t
725 efx_mcdi_link_piobuf(
727 __in uint32_t vi_index,
728 __in efx_piobuf_handle_t handle)
731 uint8_t payload[MAX(MC_CMD_LINK_PIOBUF_IN_LEN,
732 MC_CMD_LINK_PIOBUF_OUT_LEN)];
735 (void) memset(payload, 0, sizeof (payload));
736 req.emr_cmd = MC_CMD_LINK_PIOBUF;
737 req.emr_in_buf = payload;
738 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
739 req.emr_out_buf = payload;
740 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
742 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
743 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
745 efx_mcdi_execute(enp, &req);
747 if (req.emr_rc != 0) {
755 EFSYS_PROBE1(fail1, efx_rc_t, rc);
760 static __checkReturn efx_rc_t
761 efx_mcdi_unlink_piobuf(
763 __in uint32_t vi_index)
766 uint8_t payload[MAX(MC_CMD_UNLINK_PIOBUF_IN_LEN,
767 MC_CMD_UNLINK_PIOBUF_OUT_LEN)];
770 (void) memset(payload, 0, sizeof (payload));
771 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
772 req.emr_in_buf = payload;
773 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
774 req.emr_out_buf = payload;
775 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
777 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
779 efx_mcdi_execute_quiet(enp, &req);
781 if (req.emr_rc != 0) {
789 EFSYS_PROBE1(fail1, efx_rc_t, rc);
795 ef10_nic_alloc_piobufs(
797 __in uint32_t max_piobuf_count)
799 efx_piobuf_handle_t *handlep;
802 EFSYS_ASSERT3U(max_piobuf_count, <=,
803 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
805 enp->en_arch.ef10.ena_piobuf_count = 0;
807 for (i = 0; i < max_piobuf_count; i++) {
808 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
810 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0)
813 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
814 enp->en_arch.ef10.ena_piobuf_count++;
820 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
821 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
823 efx_mcdi_free_piobuf(enp, *handlep);
824 *handlep = EFX_PIOBUF_HANDLE_INVALID;
826 enp->en_arch.ef10.ena_piobuf_count = 0;
831 ef10_nic_free_piobufs(
834 efx_piobuf_handle_t *handlep;
837 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
838 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
840 efx_mcdi_free_piobuf(enp, *handlep);
841 *handlep = EFX_PIOBUF_HANDLE_INVALID;
843 enp->en_arch.ef10.ena_piobuf_count = 0;
846 /* Sub-allocate a block from a piobuf */
847 __checkReturn efx_rc_t
849 __inout efx_nic_t *enp,
850 __out uint32_t *bufnump,
851 __out efx_piobuf_handle_t *handlep,
852 __out uint32_t *blknump,
853 __out uint32_t *offsetp,
856 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
857 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
858 uint32_t blk_per_buf;
862 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
863 enp->en_family == EFX_FAMILY_MEDFORD);
864 EFSYS_ASSERT(bufnump);
865 EFSYS_ASSERT(handlep);
866 EFSYS_ASSERT(blknump);
867 EFSYS_ASSERT(offsetp);
870 if ((edcp->edc_pio_alloc_size == 0) ||
871 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
875 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
877 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
878 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
883 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
884 for (blk = 0; blk < blk_per_buf; blk++) {
885 if ((*map & (1u << blk)) == 0) {
895 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
898 *sizep = edcp->edc_pio_alloc_size;
899 *offsetp = blk * (*sizep);
906 EFSYS_PROBE1(fail1, efx_rc_t, rc);
911 /* Free a piobuf sub-allocated block */
912 __checkReturn efx_rc_t
914 __inout efx_nic_t *enp,
915 __in uint32_t bufnum,
916 __in uint32_t blknum)
921 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
922 (blknum >= (8 * sizeof (*map)))) {
927 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
928 if ((*map & (1u << blknum)) == 0) {
932 *map &= ~(1u << blknum);
939 EFSYS_PROBE1(fail1, efx_rc_t, rc);
944 __checkReturn efx_rc_t
946 __inout efx_nic_t *enp,
947 __in uint32_t vi_index,
948 __in efx_piobuf_handle_t handle)
950 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
953 __checkReturn efx_rc_t
955 __inout efx_nic_t *enp,
956 __in uint32_t vi_index)
958 return (efx_mcdi_unlink_piobuf(enp, vi_index));
961 static __checkReturn efx_rc_t
962 ef10_mcdi_get_pf_count(
964 __out uint32_t *pf_countp)
967 uint8_t payload[MAX(MC_CMD_GET_PF_COUNT_IN_LEN,
968 MC_CMD_GET_PF_COUNT_OUT_LEN)];
971 (void) memset(payload, 0, sizeof (payload));
972 req.emr_cmd = MC_CMD_GET_PF_COUNT;
973 req.emr_in_buf = payload;
974 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN;
975 req.emr_out_buf = payload;
976 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN;
978 efx_mcdi_execute(enp, &req);
980 if (req.emr_rc != 0) {
985 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) {
990 *pf_countp = *MCDI_OUT(req, uint8_t,
991 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST);
993 EFSYS_ASSERT(*pf_countp != 0);
1000 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1005 __checkReturn efx_rc_t
1006 ef10_get_datapath_caps(
1007 __in efx_nic_t *enp)
1009 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1015 if ((rc = efx_mcdi_get_capabilities(enp, &flags, &flags2,
1019 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0)
1022 #define CAP_FLAG(flags1, field) \
1023 ((flags1) & (1 << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## field ## _LBN)))
1025 #define CAP_FLAG2(flags2, field) \
1026 ((flags2) & (1 << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## field ## _LBN)))
1029 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
1030 * We only support the 14 byte prefix here.
1032 if (CAP_FLAG(flags, RX_PREFIX_LEN_14) == 0) {
1036 encp->enc_rx_prefix_size = 14;
1038 /* Check if the firmware supports TSO */
1039 encp->enc_fw_assisted_tso_enabled =
1040 CAP_FLAG(flags, TX_TSO) ? B_TRUE : B_FALSE;
1042 /* Check if the firmware supports FATSOv2 */
1043 encp->enc_fw_assisted_tso_v2_enabled =
1044 CAP_FLAG2(flags2, TX_TSO_V2) ? B_TRUE : B_FALSE;
1046 /* Get the number of TSO contexts (FATSOv2) */
1047 encp->enc_fw_assisted_tso_v2_n_contexts =
1048 CAP_FLAG2(flags2, TX_TSO_V2) ? tso2nc : 0;
1050 /* Check if the firmware has vadapter/vport/vswitch support */
1051 encp->enc_datapath_cap_evb =
1052 CAP_FLAG(flags, EVB) ? B_TRUE : B_FALSE;
1054 /* Check if the firmware supports VLAN insertion */
1055 encp->enc_hw_tx_insert_vlan_enabled =
1056 CAP_FLAG(flags, TX_VLAN_INSERTION) ? B_TRUE : B_FALSE;
1058 /* Check if the firmware supports RX event batching */
1059 encp->enc_rx_batching_enabled =
1060 CAP_FLAG(flags, RX_BATCHING) ? B_TRUE : B_FALSE;
1063 * Even if batching isn't reported as supported, we may still get
1064 * batched events (see bug61153).
1066 encp->enc_rx_batch_max = 16;
1068 /* Check if the firmware supports disabling scatter on RXQs */
1069 encp->enc_rx_disable_scatter_supported =
1070 CAP_FLAG(flags, RX_DISABLE_SCATTER) ? B_TRUE : B_FALSE;
1072 /* Check if the firmware supports packed stream mode */
1073 encp->enc_rx_packed_stream_supported =
1074 CAP_FLAG(flags, RX_PACKED_STREAM) ? B_TRUE : B_FALSE;
1077 * Check if the firmware supports configurable buffer sizes
1078 * for packed stream mode (otherwise buffer size is 1Mbyte)
1080 encp->enc_rx_var_packed_stream_supported =
1081 CAP_FLAG(flags, RX_PACKED_STREAM_VAR_BUFFERS) ? B_TRUE : B_FALSE;
1083 /* Check if the firmware supports set mac with running filters */
1084 encp->enc_allow_set_mac_with_installed_filters =
1085 CAP_FLAG(flags, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED) ?
1089 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows
1090 * specifying which parameters to configure.
1092 encp->enc_enhanced_set_mac_supported =
1093 CAP_FLAG(flags, SET_MAC_ENHANCED) ? B_TRUE : B_FALSE;
1096 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows
1097 * us to let the firmware choose the settings to use on an EVQ.
1099 encp->enc_init_evq_v2_supported =
1100 CAP_FLAG2(flags2, INIT_EVQ_V2) ? B_TRUE : B_FALSE;
1103 * Check if firmware-verified NVRAM updates must be used.
1105 * The firmware trusted installer requires all NVRAM updates to use
1106 * version 2 of MC_CMD_NVRAM_UPDATE_START (to enable verified update)
1107 * and version 2 of MC_CMD_NVRAM_UPDATE_FINISH (to verify the updated
1108 * partition and report the result).
1110 encp->enc_fw_verified_nvram_update_required =
1111 CAP_FLAG2(flags2, NVRAM_UPDATE_REPORT_VERIFY_RESULT) ?
1115 * Check if firmware provides packet memory and Rx datapath
1118 encp->enc_pm_and_rxdp_counters =
1119 CAP_FLAG(flags, PM_AND_RXDP_COUNTERS) ? B_TRUE : B_FALSE;
1122 * Check if the 40G MAC hardware is capable of reporting
1123 * statistics for Tx size bins.
1125 encp->enc_mac_stats_40g_tx_size_bins =
1126 CAP_FLAG2(flags2, MAC_STATS_40G_TX_SIZE_BINS) ? B_TRUE : B_FALSE;
1136 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1142 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
1143 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
1144 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
1145 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
1146 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
1147 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
1148 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
1149 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
1150 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
1151 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
1152 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
1153 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
1155 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
1158 __checkReturn efx_rc_t
1159 ef10_get_privilege_mask(
1160 __in efx_nic_t *enp,
1161 __out uint32_t *maskp)
1163 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1167 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1172 /* Fallback for old firmware without privilege mask support */
1173 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1174 /* Assume PF has admin privilege */
1175 mask = EF10_LEGACY_PF_PRIVILEGE_MASK;
1177 /* VF is always unprivileged by default */
1178 mask = EF10_LEGACY_VF_PRIVILEGE_MASK;
1187 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1194 * Table of mapping schemes from port number to the number of the external
1195 * connector on the board. The external numbering does not distinguish
1196 * off-board separated outputs such as from multi-headed cables.
1198 * The count of adjacent port numbers that map to each external port
1199 * and the offset in the numbering, is determined by the chip family and
1200 * current port mode.
1202 * For the Huntington family, the current port mode cannot be discovered,
1203 * so the mapping used is instead the last match in the table to the full
1204 * set of port modes to which the NIC can be configured. Therefore the
1205 * ordering of entries in the the mapping table is significant.
1208 efx_family_t family;
1209 uint32_t modes_mask;
1212 } __ef10_external_port_mappings[] = {
1213 /* Supported modes with 1 output per external port */
1215 EFX_FAMILY_HUNTINGTON,
1216 (1 << TLV_PORT_MODE_10G) |
1217 (1 << TLV_PORT_MODE_10G_10G) |
1218 (1 << TLV_PORT_MODE_10G_10G_10G_10G),
1224 (1 << TLV_PORT_MODE_10G) |
1225 (1 << TLV_PORT_MODE_10G_10G),
1229 /* Supported modes with 2 outputs per external port */
1231 EFX_FAMILY_HUNTINGTON,
1232 (1 << TLV_PORT_MODE_40G) |
1233 (1 << TLV_PORT_MODE_40G_40G) |
1234 (1 << TLV_PORT_MODE_40G_10G_10G) |
1235 (1 << TLV_PORT_MODE_10G_10G_40G),
1241 (1 << TLV_PORT_MODE_40G) |
1242 (1 << TLV_PORT_MODE_40G_40G) |
1243 (1 << TLV_PORT_MODE_40G_10G_10G) |
1244 (1 << TLV_PORT_MODE_10G_10G_40G) |
1245 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2),
1249 /* Supported modes with 4 outputs per external port */
1252 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q) |
1253 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1),
1259 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q2),
1265 __checkReturn efx_rc_t
1266 ef10_external_port_mapping(
1267 __in efx_nic_t *enp,
1269 __out uint8_t *external_portp)
1273 uint32_t port_modes;
1276 int32_t count = 1; /* Default 1-1 mapping */
1277 int32_t offset = 1; /* Default starting external port number */
1279 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t)) != 0) {
1281 * No current port mode information
1282 * - infer mapping from available modes
1284 if ((rc = efx_mcdi_get_port_modes(enp,
1285 &port_modes, NULL)) != 0) {
1287 * No port mode information available
1288 * - use default mapping
1293 /* Only need to scan the current mode */
1294 port_modes = 1 << current;
1298 * Infer the internal port -> external port mapping from
1299 * the possible port modes for this NIC.
1301 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1302 if (__ef10_external_port_mappings[i].family !=
1305 matches = (__ef10_external_port_mappings[i].modes_mask &
1308 count = __ef10_external_port_mappings[i].count;
1309 offset = __ef10_external_port_mappings[i].offset;
1310 port_modes &= ~matches;
1314 if (port_modes != 0) {
1315 /* Some advertised modes are not supported */
1322 * Scale as required by last matched mode and then convert to
1323 * correctly offset numbering
1325 *external_portp = (uint8_t)((port / count) + offset);
1329 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1335 __checkReturn efx_rc_t
1337 __in efx_nic_t *enp)
1339 const efx_nic_ops_t *enop = enp->en_enop;
1340 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1341 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1344 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1345 enp->en_family == EFX_FAMILY_MEDFORD);
1347 /* Read and clear any assertion state */
1348 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1351 /* Exit the assertion handler */
1352 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1356 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
1359 if ((rc = enop->eno_board_cfg(enp)) != 0)
1364 * Set default driver config limits (based on board config).
1366 * FIXME: For now allocate a fixed number of VIs which is likely to be
1367 * sufficient and small enough to allow multiple functions on the same
1370 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
1371 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
1373 /* The client driver must configure and enable PIO buffer support */
1374 edcp->edc_max_piobuf_count = 0;
1375 edcp->edc_pio_alloc_size = 0;
1377 #if EFSYS_OPT_MAC_STATS
1378 /* Wipe the MAC statistics */
1379 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
1383 #if EFSYS_OPT_LOOPBACK
1384 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
1388 #if EFSYS_OPT_MON_STATS
1389 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
1390 /* Unprivileged functions do not have access to sensors */
1396 encp->enc_features = enp->en_features;
1400 #if EFSYS_OPT_MON_STATS
1404 #if EFSYS_OPT_LOOPBACK
1408 #if EFSYS_OPT_MAC_STATS
1419 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1424 __checkReturn efx_rc_t
1425 ef10_nic_set_drv_limits(
1426 __inout efx_nic_t *enp,
1427 __in efx_drv_limits_t *edlp)
1429 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1430 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1431 uint32_t min_evq_count, max_evq_count;
1432 uint32_t min_rxq_count, max_rxq_count;
1433 uint32_t min_txq_count, max_txq_count;
1441 /* Get minimum required and maximum usable VI limits */
1442 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
1443 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
1444 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
1446 edcp->edc_min_vi_count =
1447 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
1449 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
1450 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
1451 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
1453 edcp->edc_max_vi_count =
1454 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
1457 * Check limits for sub-allocated piobuf blocks.
1458 * PIO is optional, so don't fail if the limits are incorrect.
1460 if ((encp->enc_piobuf_size == 0) ||
1461 (encp->enc_piobuf_limit == 0) ||
1462 (edlp->edl_min_pio_alloc_size == 0) ||
1463 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
1465 edcp->edc_max_piobuf_count = 0;
1466 edcp->edc_pio_alloc_size = 0;
1468 uint32_t blk_size, blk_count, blks_per_piobuf;
1471 MAX(edlp->edl_min_pio_alloc_size,
1472 encp->enc_piobuf_min_alloc_size);
1474 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
1475 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
1477 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
1479 /* A zero max pio alloc count means unlimited */
1480 if ((edlp->edl_max_pio_alloc_count > 0) &&
1481 (edlp->edl_max_pio_alloc_count < blk_count)) {
1482 blk_count = edlp->edl_max_pio_alloc_count;
1485 edcp->edc_pio_alloc_size = blk_size;
1486 edcp->edc_max_piobuf_count =
1487 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
1493 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1499 __checkReturn efx_rc_t
1501 __in efx_nic_t *enp)
1504 uint8_t payload[MAX(MC_CMD_ENTITY_RESET_IN_LEN,
1505 MC_CMD_ENTITY_RESET_OUT_LEN)];
1508 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
1509 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1511 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1514 (void) memset(payload, 0, sizeof (payload));
1515 req.emr_cmd = MC_CMD_ENTITY_RESET;
1516 req.emr_in_buf = payload;
1517 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
1518 req.emr_out_buf = payload;
1519 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
1521 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
1522 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
1524 efx_mcdi_execute(enp, &req);
1526 if (req.emr_rc != 0) {
1531 /* Clear RX/TX DMA queue errors */
1532 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
1541 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1546 __checkReturn efx_rc_t
1548 __in efx_nic_t *enp)
1550 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1551 uint32_t min_vi_count, max_vi_count;
1552 uint32_t vi_count, vi_base, vi_shift;
1558 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1559 enp->en_family == EFX_FAMILY_MEDFORD);
1561 /* Enable reporting of some events (e.g. link change) */
1562 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
1565 /* Allocate (optional) on-chip PIO buffers */
1566 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
1569 * For best performance, PIO writes should use a write-combined
1570 * (WC) memory mapping. Using a separate WC mapping for the PIO
1571 * aperture of each VI would be a burden to drivers (and not
1572 * possible if the host page size is >4Kbyte).
1574 * To avoid this we use a single uncached (UC) mapping for VI
1575 * register access, and a single WC mapping for extra VIs used
1578 * Each piobuf must be linked to a VI in the WC mapping, and to
1579 * each VI that is using a sub-allocated block from the piobuf.
1581 min_vi_count = edcp->edc_min_vi_count;
1583 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
1585 /* Ensure that the previously attached driver's VIs are freed */
1586 if ((rc = efx_mcdi_free_vis(enp)) != 0)
1590 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
1591 * fails then retrying the request for fewer VI resources may succeed.
1594 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
1595 &vi_base, &vi_count, &vi_shift)) != 0)
1598 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
1600 if (vi_count < min_vi_count) {
1605 enp->en_arch.ef10.ena_vi_base = vi_base;
1606 enp->en_arch.ef10.ena_vi_count = vi_count;
1607 enp->en_arch.ef10.ena_vi_shift = vi_shift;
1609 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
1610 /* Not enough extra VIs to map piobufs */
1611 ef10_nic_free_piobufs(enp);
1614 enp->en_arch.ef10.ena_pio_write_vi_base =
1615 vi_count - enp->en_arch.ef10.ena_piobuf_count;
1617 /* Save UC memory mapping details */
1618 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
1619 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1620 enp->en_arch.ef10.ena_uc_mem_map_size =
1621 (ER_DZ_TX_PIOBUF_STEP *
1622 enp->en_arch.ef10.ena_pio_write_vi_base);
1624 enp->en_arch.ef10.ena_uc_mem_map_size =
1625 (ER_DZ_TX_PIOBUF_STEP *
1626 enp->en_arch.ef10.ena_vi_count);
1629 /* Save WC memory mapping details */
1630 enp->en_arch.ef10.ena_wc_mem_map_offset =
1631 enp->en_arch.ef10.ena_uc_mem_map_offset +
1632 enp->en_arch.ef10.ena_uc_mem_map_size;
1634 enp->en_arch.ef10.ena_wc_mem_map_size =
1635 (ER_DZ_TX_PIOBUF_STEP *
1636 enp->en_arch.ef10.ena_piobuf_count);
1638 /* Link piobufs to extra VIs in WC mapping */
1639 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1640 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1641 rc = efx_mcdi_link_piobuf(enp,
1642 enp->en_arch.ef10.ena_pio_write_vi_base + i,
1643 enp->en_arch.ef10.ena_piobuf_handle[i]);
1650 * Allocate a vAdaptor attached to our upstream vPort/pPort.
1652 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
1653 * driver has yet to bring up the EVB port. See bug 56147. In this case,
1654 * retry the request several times after waiting a while. The wait time
1655 * between retries starts small (10ms) and exponentially increases.
1656 * Total wait time is a little over two seconds. Retry logic in the
1657 * client driver may mean this whole loop is repeated if it continues to
1662 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
1663 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
1666 * Do not retry alloc for PF, or for other errors on
1672 /* VF startup before PF is ready. Retry allocation. */
1674 /* Too many attempts */
1678 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
1679 EFSYS_SLEEP(delay_us);
1681 if (delay_us < 500000)
1685 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
1686 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
1701 ef10_nic_free_piobufs(enp);
1704 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1709 __checkReturn efx_rc_t
1710 ef10_nic_get_vi_pool(
1711 __in efx_nic_t *enp,
1712 __out uint32_t *vi_countp)
1714 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1715 enp->en_family == EFX_FAMILY_MEDFORD);
1718 * Report VIs that the client driver can use.
1719 * Do not include VIs used for PIO buffer writes.
1721 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
1726 __checkReturn efx_rc_t
1727 ef10_nic_get_bar_region(
1728 __in efx_nic_t *enp,
1729 __in efx_nic_region_t region,
1730 __out uint32_t *offsetp,
1731 __out size_t *sizep)
1735 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1736 enp->en_family == EFX_FAMILY_MEDFORD);
1739 * TODO: Specify host memory mapping alignment and granularity
1740 * in efx_drv_limits_t so that they can be taken into account
1741 * when allocating extra VIs for PIO writes.
1745 /* UC mapped memory BAR region for VI registers */
1746 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
1747 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
1750 case EFX_REGION_PIO_WRITE_VI:
1751 /* WC mapped memory BAR region for piobuf writes */
1752 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
1753 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
1764 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1771 __in efx_nic_t *enp)
1776 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
1777 enp->en_vport_id = 0;
1779 /* Unlink piobufs from extra VIs in WC mapping */
1780 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1781 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1782 rc = efx_mcdi_unlink_piobuf(enp,
1783 enp->en_arch.ef10.ena_pio_write_vi_base + i);
1789 ef10_nic_free_piobufs(enp);
1791 (void) efx_mcdi_free_vis(enp);
1792 enp->en_arch.ef10.ena_vi_count = 0;
1797 __in efx_nic_t *enp)
1799 #if EFSYS_OPT_MON_STATS
1800 mcdi_mon_cfg_free(enp);
1801 #endif /* EFSYS_OPT_MON_STATS */
1802 (void) efx_mcdi_drv_attach(enp, B_FALSE);
1807 __checkReturn efx_rc_t
1808 ef10_nic_register_test(
1809 __in efx_nic_t *enp)
1814 _NOTE(ARGUNUSED(enp))
1815 _NOTE(CONSTANTCONDITION)
1825 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1830 #endif /* EFSYS_OPT_DIAG */
1833 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */