1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
13 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
15 #include "ef10_tlv_layout.h"
17 __checkReturn efx_rc_t
18 efx_mcdi_get_port_assignment(
20 __out uint32_t *portp)
23 uint8_t payload[MAX(MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
24 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN)];
27 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
28 enp->en_family == EFX_FAMILY_MEDFORD ||
29 enp->en_family == EFX_FAMILY_MEDFORD2);
31 (void) memset(payload, 0, sizeof (payload));
32 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
33 req.emr_in_buf = payload;
34 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
35 req.emr_out_buf = payload;
36 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
38 efx_mcdi_execute(enp, &req);
40 if (req.emr_rc != 0) {
45 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
50 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
57 EFSYS_PROBE1(fail1, efx_rc_t, rc);
62 __checkReturn efx_rc_t
63 efx_mcdi_get_port_modes(
65 __out uint32_t *modesp,
66 __out_opt uint32_t *current_modep)
69 uint8_t payload[MAX(MC_CMD_GET_PORT_MODES_IN_LEN,
70 MC_CMD_GET_PORT_MODES_OUT_LEN)];
73 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
74 enp->en_family == EFX_FAMILY_MEDFORD ||
75 enp->en_family == EFX_FAMILY_MEDFORD2);
77 (void) memset(payload, 0, sizeof (payload));
78 req.emr_cmd = MC_CMD_GET_PORT_MODES;
79 req.emr_in_buf = payload;
80 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
81 req.emr_out_buf = payload;
82 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
84 efx_mcdi_execute(enp, &req);
86 if (req.emr_rc != 0) {
92 * Require only Modes and DefaultMode fields, unless the current mode
93 * was requested (CurrentMode field was added for Medford).
95 if (req.emr_out_length_used <
96 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
100 if ((current_modep != NULL) && (req.emr_out_length_used <
101 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) {
106 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
108 if (current_modep != NULL) {
109 *current_modep = MCDI_OUT_DWORD(req,
110 GET_PORT_MODES_OUT_CURRENT_MODE);
120 EFSYS_PROBE1(fail1, efx_rc_t, rc);
125 __checkReturn efx_rc_t
126 ef10_nic_get_port_mode_bandwidth(
127 __in uint32_t port_mode,
128 __out uint32_t *bandwidth_mbpsp)
134 case TLV_PORT_MODE_10G:
137 case TLV_PORT_MODE_10G_10G:
138 bandwidth = 10000 * 2;
140 case TLV_PORT_MODE_10G_10G_10G_10G:
141 case TLV_PORT_MODE_10G_10G_10G_10G_Q:
142 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2:
143 case TLV_PORT_MODE_10G_10G_10G_10G_Q2:
144 bandwidth = 10000 * 4;
146 case TLV_PORT_MODE_40G:
149 case TLV_PORT_MODE_40G_40G:
150 bandwidth = 40000 * 2;
152 case TLV_PORT_MODE_40G_10G_10G:
153 case TLV_PORT_MODE_10G_10G_40G:
154 bandwidth = 40000 + (10000 * 2);
161 *bandwidth_mbpsp = bandwidth;
166 EFSYS_PROBE1(fail1, efx_rc_t, rc);
171 static __checkReturn efx_rc_t
172 efx_mcdi_vadaptor_alloc(
174 __in uint32_t port_id)
177 uint8_t payload[MAX(MC_CMD_VADAPTOR_ALLOC_IN_LEN,
178 MC_CMD_VADAPTOR_ALLOC_OUT_LEN)];
181 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
183 (void) memset(payload, 0, sizeof (payload));
184 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
185 req.emr_in_buf = payload;
186 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
187 req.emr_out_buf = payload;
188 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
190 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
191 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
192 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
193 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
195 efx_mcdi_execute(enp, &req);
197 if (req.emr_rc != 0) {
205 EFSYS_PROBE1(fail1, efx_rc_t, rc);
210 static __checkReturn efx_rc_t
211 efx_mcdi_vadaptor_free(
213 __in uint32_t port_id)
216 uint8_t payload[MAX(MC_CMD_VADAPTOR_FREE_IN_LEN,
217 MC_CMD_VADAPTOR_FREE_OUT_LEN)];
220 (void) memset(payload, 0, sizeof (payload));
221 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
222 req.emr_in_buf = payload;
223 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
224 req.emr_out_buf = payload;
225 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
227 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
229 efx_mcdi_execute(enp, &req);
231 if (req.emr_rc != 0) {
239 EFSYS_PROBE1(fail1, efx_rc_t, rc);
244 __checkReturn efx_rc_t
245 efx_mcdi_get_mac_address_pf(
247 __out_ecount_opt(6) uint8_t mac_addrp[6])
250 uint8_t payload[MAX(MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
251 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)];
254 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
255 enp->en_family == EFX_FAMILY_MEDFORD ||
256 enp->en_family == EFX_FAMILY_MEDFORD2);
258 (void) memset(payload, 0, sizeof (payload));
259 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
260 req.emr_in_buf = payload;
261 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
262 req.emr_out_buf = payload;
263 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
265 efx_mcdi_execute(enp, &req);
267 if (req.emr_rc != 0) {
272 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
277 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
282 if (mac_addrp != NULL) {
285 addrp = MCDI_OUT2(req, uint8_t,
286 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
288 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
298 EFSYS_PROBE1(fail1, efx_rc_t, rc);
303 __checkReturn efx_rc_t
304 efx_mcdi_get_mac_address_vf(
306 __out_ecount_opt(6) uint8_t mac_addrp[6])
309 uint8_t payload[MAX(MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
310 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX)];
313 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
314 enp->en_family == EFX_FAMILY_MEDFORD ||
315 enp->en_family == EFX_FAMILY_MEDFORD2);
317 (void) memset(payload, 0, sizeof (payload));
318 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
319 req.emr_in_buf = payload;
320 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
321 req.emr_out_buf = payload;
322 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
324 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
325 EVB_PORT_ID_ASSIGNED);
327 efx_mcdi_execute(enp, &req);
329 if (req.emr_rc != 0) {
334 if (req.emr_out_length_used <
335 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
340 if (MCDI_OUT_DWORD(req,
341 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
346 if (mac_addrp != NULL) {
349 addrp = MCDI_OUT2(req, uint8_t,
350 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
352 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
362 EFSYS_PROBE1(fail1, efx_rc_t, rc);
367 __checkReturn efx_rc_t
370 __out uint32_t *sys_freqp,
371 __out uint32_t *dpcpu_freqp)
374 uint8_t payload[MAX(MC_CMD_GET_CLOCK_IN_LEN,
375 MC_CMD_GET_CLOCK_OUT_LEN)];
378 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
379 enp->en_family == EFX_FAMILY_MEDFORD ||
380 enp->en_family == EFX_FAMILY_MEDFORD2);
382 (void) memset(payload, 0, sizeof (payload));
383 req.emr_cmd = MC_CMD_GET_CLOCK;
384 req.emr_in_buf = payload;
385 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
386 req.emr_out_buf = payload;
387 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
389 efx_mcdi_execute(enp, &req);
391 if (req.emr_rc != 0) {
396 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
401 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
402 if (*sys_freqp == 0) {
406 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
407 if (*dpcpu_freqp == 0) {
421 EFSYS_PROBE1(fail1, efx_rc_t, rc);
426 __checkReturn efx_rc_t
427 efx_mcdi_get_rxdp_config(
429 __out uint32_t *end_paddingp)
432 uint8_t payload[MAX(MC_CMD_GET_RXDP_CONFIG_IN_LEN,
433 MC_CMD_GET_RXDP_CONFIG_OUT_LEN)];
434 uint32_t end_padding;
437 memset(payload, 0, sizeof (payload));
438 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
439 req.emr_in_buf = payload;
440 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
441 req.emr_out_buf = payload;
442 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
444 efx_mcdi_execute(enp, &req);
445 if (req.emr_rc != 0) {
450 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
451 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
452 /* RX DMA end padding is disabled */
455 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
456 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
457 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
460 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
463 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
472 *end_paddingp = end_padding;
479 EFSYS_PROBE1(fail1, efx_rc_t, rc);
484 __checkReturn efx_rc_t
485 efx_mcdi_get_vector_cfg(
487 __out_opt uint32_t *vec_basep,
488 __out_opt uint32_t *pf_nvecp,
489 __out_opt uint32_t *vf_nvecp)
492 uint8_t payload[MAX(MC_CMD_GET_VECTOR_CFG_IN_LEN,
493 MC_CMD_GET_VECTOR_CFG_OUT_LEN)];
496 (void) memset(payload, 0, sizeof (payload));
497 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
498 req.emr_in_buf = payload;
499 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
500 req.emr_out_buf = payload;
501 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
503 efx_mcdi_execute(enp, &req);
505 if (req.emr_rc != 0) {
510 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
515 if (vec_basep != NULL)
516 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
517 if (pf_nvecp != NULL)
518 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
519 if (vf_nvecp != NULL)
520 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
527 EFSYS_PROBE1(fail1, efx_rc_t, rc);
532 static __checkReturn efx_rc_t
535 __in uint32_t min_vi_count,
536 __in uint32_t max_vi_count,
537 __out uint32_t *vi_basep,
538 __out uint32_t *vi_countp,
539 __out uint32_t *vi_shiftp)
542 uint8_t payload[MAX(MC_CMD_ALLOC_VIS_IN_LEN,
543 MC_CMD_ALLOC_VIS_EXT_OUT_LEN)];
546 if (vi_countp == NULL) {
551 (void) memset(payload, 0, sizeof (payload));
552 req.emr_cmd = MC_CMD_ALLOC_VIS;
553 req.emr_in_buf = payload;
554 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
555 req.emr_out_buf = payload;
556 req.emr_out_length = MC_CMD_ALLOC_VIS_EXT_OUT_LEN;
558 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
559 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
561 efx_mcdi_execute(enp, &req);
563 if (req.emr_rc != 0) {
568 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
573 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
574 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
576 /* Report VI_SHIFT if available (always zero for Huntington) */
577 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
580 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
589 EFSYS_PROBE1(fail1, efx_rc_t, rc);
595 static __checkReturn efx_rc_t
602 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
603 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
605 req.emr_cmd = MC_CMD_FREE_VIS;
606 req.emr_in_buf = NULL;
607 req.emr_in_length = 0;
608 req.emr_out_buf = NULL;
609 req.emr_out_length = 0;
611 efx_mcdi_execute_quiet(enp, &req);
613 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
614 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
622 EFSYS_PROBE1(fail1, efx_rc_t, rc);
628 static __checkReturn efx_rc_t
629 efx_mcdi_alloc_piobuf(
631 __out efx_piobuf_handle_t *handlep)
634 uint8_t payload[MAX(MC_CMD_ALLOC_PIOBUF_IN_LEN,
635 MC_CMD_ALLOC_PIOBUF_OUT_LEN)];
638 if (handlep == NULL) {
643 (void) memset(payload, 0, sizeof (payload));
644 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
645 req.emr_in_buf = payload;
646 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
647 req.emr_out_buf = payload;
648 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
650 efx_mcdi_execute_quiet(enp, &req);
652 if (req.emr_rc != 0) {
657 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
662 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
671 EFSYS_PROBE1(fail1, efx_rc_t, rc);
676 static __checkReturn efx_rc_t
677 efx_mcdi_free_piobuf(
679 __in efx_piobuf_handle_t handle)
682 uint8_t payload[MAX(MC_CMD_FREE_PIOBUF_IN_LEN,
683 MC_CMD_FREE_PIOBUF_OUT_LEN)];
686 (void) memset(payload, 0, sizeof (payload));
687 req.emr_cmd = MC_CMD_FREE_PIOBUF;
688 req.emr_in_buf = payload;
689 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
690 req.emr_out_buf = payload;
691 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
693 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
695 efx_mcdi_execute_quiet(enp, &req);
697 if (req.emr_rc != 0) {
705 EFSYS_PROBE1(fail1, efx_rc_t, rc);
710 static __checkReturn efx_rc_t
711 efx_mcdi_link_piobuf(
713 __in uint32_t vi_index,
714 __in efx_piobuf_handle_t handle)
717 uint8_t payload[MAX(MC_CMD_LINK_PIOBUF_IN_LEN,
718 MC_CMD_LINK_PIOBUF_OUT_LEN)];
721 (void) memset(payload, 0, sizeof (payload));
722 req.emr_cmd = MC_CMD_LINK_PIOBUF;
723 req.emr_in_buf = payload;
724 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
725 req.emr_out_buf = payload;
726 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
728 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
729 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
731 efx_mcdi_execute(enp, &req);
733 if (req.emr_rc != 0) {
741 EFSYS_PROBE1(fail1, efx_rc_t, rc);
746 static __checkReturn efx_rc_t
747 efx_mcdi_unlink_piobuf(
749 __in uint32_t vi_index)
752 uint8_t payload[MAX(MC_CMD_UNLINK_PIOBUF_IN_LEN,
753 MC_CMD_UNLINK_PIOBUF_OUT_LEN)];
756 (void) memset(payload, 0, sizeof (payload));
757 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
758 req.emr_in_buf = payload;
759 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
760 req.emr_out_buf = payload;
761 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
763 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
765 efx_mcdi_execute_quiet(enp, &req);
767 if (req.emr_rc != 0) {
775 EFSYS_PROBE1(fail1, efx_rc_t, rc);
781 ef10_nic_alloc_piobufs(
783 __in uint32_t max_piobuf_count)
785 efx_piobuf_handle_t *handlep;
788 EFSYS_ASSERT3U(max_piobuf_count, <=,
789 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
791 enp->en_arch.ef10.ena_piobuf_count = 0;
793 for (i = 0; i < max_piobuf_count; i++) {
794 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
796 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0)
799 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
800 enp->en_arch.ef10.ena_piobuf_count++;
806 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
807 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
809 efx_mcdi_free_piobuf(enp, *handlep);
810 *handlep = EFX_PIOBUF_HANDLE_INVALID;
812 enp->en_arch.ef10.ena_piobuf_count = 0;
817 ef10_nic_free_piobufs(
820 efx_piobuf_handle_t *handlep;
823 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
824 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
826 efx_mcdi_free_piobuf(enp, *handlep);
827 *handlep = EFX_PIOBUF_HANDLE_INVALID;
829 enp->en_arch.ef10.ena_piobuf_count = 0;
832 /* Sub-allocate a block from a piobuf */
833 __checkReturn efx_rc_t
835 __inout efx_nic_t *enp,
836 __out uint32_t *bufnump,
837 __out efx_piobuf_handle_t *handlep,
838 __out uint32_t *blknump,
839 __out uint32_t *offsetp,
842 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
843 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
844 uint32_t blk_per_buf;
848 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
849 enp->en_family == EFX_FAMILY_MEDFORD ||
850 enp->en_family == EFX_FAMILY_MEDFORD2);
851 EFSYS_ASSERT(bufnump);
852 EFSYS_ASSERT(handlep);
853 EFSYS_ASSERT(blknump);
854 EFSYS_ASSERT(offsetp);
857 if ((edcp->edc_pio_alloc_size == 0) ||
858 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
862 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
864 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
865 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
870 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
871 for (blk = 0; blk < blk_per_buf; blk++) {
872 if ((*map & (1u << blk)) == 0) {
882 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
885 *sizep = edcp->edc_pio_alloc_size;
886 *offsetp = blk * (*sizep);
893 EFSYS_PROBE1(fail1, efx_rc_t, rc);
898 /* Free a piobuf sub-allocated block */
899 __checkReturn efx_rc_t
901 __inout efx_nic_t *enp,
902 __in uint32_t bufnum,
903 __in uint32_t blknum)
908 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
909 (blknum >= (8 * sizeof (*map)))) {
914 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
915 if ((*map & (1u << blknum)) == 0) {
919 *map &= ~(1u << blknum);
926 EFSYS_PROBE1(fail1, efx_rc_t, rc);
931 __checkReturn efx_rc_t
933 __inout efx_nic_t *enp,
934 __in uint32_t vi_index,
935 __in efx_piobuf_handle_t handle)
937 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
940 __checkReturn efx_rc_t
942 __inout efx_nic_t *enp,
943 __in uint32_t vi_index)
945 return (efx_mcdi_unlink_piobuf(enp, vi_index));
948 static __checkReturn efx_rc_t
949 ef10_mcdi_get_pf_count(
951 __out uint32_t *pf_countp)
954 uint8_t payload[MAX(MC_CMD_GET_PF_COUNT_IN_LEN,
955 MC_CMD_GET_PF_COUNT_OUT_LEN)];
958 (void) memset(payload, 0, sizeof (payload));
959 req.emr_cmd = MC_CMD_GET_PF_COUNT;
960 req.emr_in_buf = payload;
961 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN;
962 req.emr_out_buf = payload;
963 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN;
965 efx_mcdi_execute(enp, &req);
967 if (req.emr_rc != 0) {
972 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) {
977 *pf_countp = *MCDI_OUT(req, uint8_t,
978 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST);
980 EFSYS_ASSERT(*pf_countp != 0);
987 EFSYS_PROBE1(fail1, efx_rc_t, rc);
992 __checkReturn efx_rc_t
993 ef10_get_datapath_caps(
996 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1002 if ((rc = efx_mcdi_get_capabilities(enp, &flags, NULL, NULL,
1003 &flags2, &tso2nc)) != 0)
1006 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0)
1009 #define CAP_FLAG(flags1, field) \
1010 ((flags1) & (1 << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## field ## _LBN)))
1012 #define CAP_FLAG2(flags2, field) \
1013 ((flags2) & (1 << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## field ## _LBN)))
1016 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
1017 * We only support the 14 byte prefix here.
1019 if (CAP_FLAG(flags, RX_PREFIX_LEN_14) == 0) {
1023 encp->enc_rx_prefix_size = 14;
1025 /* Check if the firmware supports TSO */
1026 encp->enc_fw_assisted_tso_enabled =
1027 CAP_FLAG(flags, TX_TSO) ? B_TRUE : B_FALSE;
1029 /* Check if the firmware supports FATSOv2 */
1030 encp->enc_fw_assisted_tso_v2_enabled =
1031 CAP_FLAG2(flags2, TX_TSO_V2) ? B_TRUE : B_FALSE;
1033 /* Get the number of TSO contexts (FATSOv2) */
1034 encp->enc_fw_assisted_tso_v2_n_contexts =
1035 CAP_FLAG2(flags2, TX_TSO_V2) ? tso2nc : 0;
1037 /* Check if the firmware has vadapter/vport/vswitch support */
1038 encp->enc_datapath_cap_evb =
1039 CAP_FLAG(flags, EVB) ? B_TRUE : B_FALSE;
1041 /* Check if the firmware supports VLAN insertion */
1042 encp->enc_hw_tx_insert_vlan_enabled =
1043 CAP_FLAG(flags, TX_VLAN_INSERTION) ? B_TRUE : B_FALSE;
1045 /* Check if the firmware supports RX event batching */
1046 encp->enc_rx_batching_enabled =
1047 CAP_FLAG(flags, RX_BATCHING) ? B_TRUE : B_FALSE;
1050 * Even if batching isn't reported as supported, we may still get
1051 * batched events (see bug61153).
1053 encp->enc_rx_batch_max = 16;
1055 /* Check if the firmware supports disabling scatter on RXQs */
1056 encp->enc_rx_disable_scatter_supported =
1057 CAP_FLAG(flags, RX_DISABLE_SCATTER) ? B_TRUE : B_FALSE;
1059 /* Check if the firmware supports packed stream mode */
1060 encp->enc_rx_packed_stream_supported =
1061 CAP_FLAG(flags, RX_PACKED_STREAM) ? B_TRUE : B_FALSE;
1064 * Check if the firmware supports configurable buffer sizes
1065 * for packed stream mode (otherwise buffer size is 1Mbyte)
1067 encp->enc_rx_var_packed_stream_supported =
1068 CAP_FLAG(flags, RX_PACKED_STREAM_VAR_BUFFERS) ? B_TRUE : B_FALSE;
1070 /* Check if the firmware supports set mac with running filters */
1071 encp->enc_allow_set_mac_with_installed_filters =
1072 CAP_FLAG(flags, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED) ?
1076 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows
1077 * specifying which parameters to configure.
1079 encp->enc_enhanced_set_mac_supported =
1080 CAP_FLAG(flags, SET_MAC_ENHANCED) ? B_TRUE : B_FALSE;
1083 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows
1084 * us to let the firmware choose the settings to use on an EVQ.
1086 encp->enc_init_evq_v2_supported =
1087 CAP_FLAG2(flags2, INIT_EVQ_V2) ? B_TRUE : B_FALSE;
1090 * Check if firmware-verified NVRAM updates must be used.
1092 * The firmware trusted installer requires all NVRAM updates to use
1093 * version 2 of MC_CMD_NVRAM_UPDATE_START (to enable verified update)
1094 * and version 2 of MC_CMD_NVRAM_UPDATE_FINISH (to verify the updated
1095 * partition and report the result).
1097 encp->enc_nvram_update_verify_result_supported =
1098 CAP_FLAG2(flags2, NVRAM_UPDATE_REPORT_VERIFY_RESULT) ?
1102 * Check if firmware provides packet memory and Rx datapath
1105 encp->enc_pm_and_rxdp_counters =
1106 CAP_FLAG(flags, PM_AND_RXDP_COUNTERS) ? B_TRUE : B_FALSE;
1109 * Check if the 40G MAC hardware is capable of reporting
1110 * statistics for Tx size bins.
1112 encp->enc_mac_stats_40g_tx_size_bins =
1113 CAP_FLAG2(flags2, MAC_STATS_40G_TX_SIZE_BINS) ? B_TRUE : B_FALSE;
1116 * Check if firmware supports VXLAN and NVGRE tunnels.
1117 * The capability indicates Geneve protocol support as well.
1119 if (CAP_FLAG(flags, VXLAN_NVGRE)) {
1120 encp->enc_tunnel_encapsulations_supported =
1121 (1u << EFX_TUNNEL_PROTOCOL_VXLAN) |
1122 (1u << EFX_TUNNEL_PROTOCOL_GENEVE) |
1123 (1u << EFX_TUNNEL_PROTOCOL_NVGRE);
1125 EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES ==
1126 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
1127 encp->enc_tunnel_config_udp_entries_max =
1128 EFX_TUNNEL_MAXNENTRIES;
1130 encp->enc_tunnel_config_udp_entries_max = 0;
1141 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1147 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
1148 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
1149 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
1150 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
1151 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
1152 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
1153 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
1154 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
1155 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
1156 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
1157 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
1158 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
1160 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
1163 __checkReturn efx_rc_t
1164 ef10_get_privilege_mask(
1165 __in efx_nic_t *enp,
1166 __out uint32_t *maskp)
1168 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1172 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1177 /* Fallback for old firmware without privilege mask support */
1178 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1179 /* Assume PF has admin privilege */
1180 mask = EF10_LEGACY_PF_PRIVILEGE_MASK;
1182 /* VF is always unprivileged by default */
1183 mask = EF10_LEGACY_VF_PRIVILEGE_MASK;
1192 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1199 * Table of mapping schemes from port number to the number of the external
1200 * connector on the board. The external numbering does not distinguish
1201 * off-board separated outputs such as from multi-headed cables.
1203 * The count of adjacent port numbers that map to each external port
1204 * and the offset in the numbering, is determined by the chip family and
1205 * current port mode.
1207 * For the Huntington family, the current port mode cannot be discovered,
1208 * so the mapping used is instead the last match in the table to the full
1209 * set of port modes to which the NIC can be configured. Therefore the
1210 * ordering of entries in the mapping table is significant.
1213 efx_family_t family;
1214 uint32_t modes_mask;
1217 } __ef10_external_port_mappings[] = {
1218 /* Supported modes with 1 output per external port */
1220 EFX_FAMILY_HUNTINGTON,
1221 (1 << TLV_PORT_MODE_10G) |
1222 (1 << TLV_PORT_MODE_10G_10G) |
1223 (1 << TLV_PORT_MODE_10G_10G_10G_10G),
1229 (1 << TLV_PORT_MODE_10G) |
1230 (1 << TLV_PORT_MODE_10G_10G),
1234 /* Supported modes with 2 outputs per external port */
1236 EFX_FAMILY_HUNTINGTON,
1237 (1 << TLV_PORT_MODE_40G) |
1238 (1 << TLV_PORT_MODE_40G_40G) |
1239 (1 << TLV_PORT_MODE_40G_10G_10G) |
1240 (1 << TLV_PORT_MODE_10G_10G_40G),
1246 (1 << TLV_PORT_MODE_40G) |
1247 (1 << TLV_PORT_MODE_40G_40G) |
1248 (1 << TLV_PORT_MODE_40G_10G_10G) |
1249 (1 << TLV_PORT_MODE_10G_10G_40G) |
1250 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2),
1254 /* Supported modes with 4 outputs per external port */
1257 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q) |
1258 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1),
1264 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q2),
1270 __checkReturn efx_rc_t
1271 ef10_external_port_mapping(
1272 __in efx_nic_t *enp,
1274 __out uint8_t *external_portp)
1278 uint32_t port_modes;
1281 int32_t count = 1; /* Default 1-1 mapping */
1282 int32_t offset = 1; /* Default starting external port number */
1284 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t)) != 0) {
1286 * No current port mode information
1287 * - infer mapping from available modes
1289 if ((rc = efx_mcdi_get_port_modes(enp,
1290 &port_modes, NULL)) != 0) {
1292 * No port mode information available
1293 * - use default mapping
1298 /* Only need to scan the current mode */
1299 port_modes = 1 << current;
1303 * Infer the internal port -> external port mapping from
1304 * the possible port modes for this NIC.
1306 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1307 if (__ef10_external_port_mappings[i].family !=
1310 matches = (__ef10_external_port_mappings[i].modes_mask &
1313 count = __ef10_external_port_mappings[i].count;
1314 offset = __ef10_external_port_mappings[i].offset;
1315 port_modes &= ~matches;
1319 if (port_modes != 0) {
1320 /* Some advertised modes are not supported */
1327 * Scale as required by last matched mode and then convert to
1328 * correctly offset numbering
1330 *external_portp = (uint8_t)((port / count) + offset);
1334 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1340 __checkReturn efx_rc_t
1342 __in efx_nic_t *enp)
1344 const efx_nic_ops_t *enop = enp->en_enop;
1345 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1346 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1349 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1350 enp->en_family == EFX_FAMILY_MEDFORD ||
1351 enp->en_family == EFX_FAMILY_MEDFORD2);
1353 /* Read and clear any assertion state */
1354 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1357 /* Exit the assertion handler */
1358 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1362 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
1365 if ((rc = enop->eno_board_cfg(enp)) != 0)
1370 * Set default driver config limits (based on board config).
1372 * FIXME: For now allocate a fixed number of VIs which is likely to be
1373 * sufficient and small enough to allow multiple functions on the same
1376 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
1377 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
1379 /* The client driver must configure and enable PIO buffer support */
1380 edcp->edc_max_piobuf_count = 0;
1381 edcp->edc_pio_alloc_size = 0;
1383 #if EFSYS_OPT_MAC_STATS
1384 /* Wipe the MAC statistics */
1385 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
1389 #if EFSYS_OPT_LOOPBACK
1390 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
1394 #if EFSYS_OPT_MON_STATS
1395 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
1396 /* Unprivileged functions do not have access to sensors */
1402 encp->enc_features = enp->en_features;
1406 #if EFSYS_OPT_MON_STATS
1410 #if EFSYS_OPT_LOOPBACK
1414 #if EFSYS_OPT_MAC_STATS
1425 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1430 __checkReturn efx_rc_t
1431 ef10_nic_set_drv_limits(
1432 __inout efx_nic_t *enp,
1433 __in efx_drv_limits_t *edlp)
1435 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1436 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1437 uint32_t min_evq_count, max_evq_count;
1438 uint32_t min_rxq_count, max_rxq_count;
1439 uint32_t min_txq_count, max_txq_count;
1447 /* Get minimum required and maximum usable VI limits */
1448 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
1449 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
1450 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
1452 edcp->edc_min_vi_count =
1453 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
1455 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
1456 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
1457 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
1459 edcp->edc_max_vi_count =
1460 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
1463 * Check limits for sub-allocated piobuf blocks.
1464 * PIO is optional, so don't fail if the limits are incorrect.
1466 if ((encp->enc_piobuf_size == 0) ||
1467 (encp->enc_piobuf_limit == 0) ||
1468 (edlp->edl_min_pio_alloc_size == 0) ||
1469 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
1471 edcp->edc_max_piobuf_count = 0;
1472 edcp->edc_pio_alloc_size = 0;
1474 uint32_t blk_size, blk_count, blks_per_piobuf;
1477 MAX(edlp->edl_min_pio_alloc_size,
1478 encp->enc_piobuf_min_alloc_size);
1480 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
1481 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
1483 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
1485 /* A zero max pio alloc count means unlimited */
1486 if ((edlp->edl_max_pio_alloc_count > 0) &&
1487 (edlp->edl_max_pio_alloc_count < blk_count)) {
1488 blk_count = edlp->edl_max_pio_alloc_count;
1491 edcp->edc_pio_alloc_size = blk_size;
1492 edcp->edc_max_piobuf_count =
1493 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
1499 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1505 __checkReturn efx_rc_t
1507 __in efx_nic_t *enp)
1510 uint8_t payload[MAX(MC_CMD_ENTITY_RESET_IN_LEN,
1511 MC_CMD_ENTITY_RESET_OUT_LEN)];
1514 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
1515 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1517 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1520 (void) memset(payload, 0, sizeof (payload));
1521 req.emr_cmd = MC_CMD_ENTITY_RESET;
1522 req.emr_in_buf = payload;
1523 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
1524 req.emr_out_buf = payload;
1525 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
1527 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
1528 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
1530 efx_mcdi_execute(enp, &req);
1532 if (req.emr_rc != 0) {
1537 /* Clear RX/TX DMA queue errors */
1538 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
1547 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1552 __checkReturn efx_rc_t
1554 __in efx_nic_t *enp)
1556 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1557 uint32_t min_vi_count, max_vi_count;
1558 uint32_t vi_count, vi_base, vi_shift;
1564 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1565 enp->en_family == EFX_FAMILY_MEDFORD ||
1566 enp->en_family == EFX_FAMILY_MEDFORD2);
1568 /* Enable reporting of some events (e.g. link change) */
1569 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
1572 /* Allocate (optional) on-chip PIO buffers */
1573 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
1576 * For best performance, PIO writes should use a write-combined
1577 * (WC) memory mapping. Using a separate WC mapping for the PIO
1578 * aperture of each VI would be a burden to drivers (and not
1579 * possible if the host page size is >4Kbyte).
1581 * To avoid this we use a single uncached (UC) mapping for VI
1582 * register access, and a single WC mapping for extra VIs used
1585 * Each piobuf must be linked to a VI in the WC mapping, and to
1586 * each VI that is using a sub-allocated block from the piobuf.
1588 min_vi_count = edcp->edc_min_vi_count;
1590 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
1592 /* Ensure that the previously attached driver's VIs are freed */
1593 if ((rc = efx_mcdi_free_vis(enp)) != 0)
1597 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
1598 * fails then retrying the request for fewer VI resources may succeed.
1601 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
1602 &vi_base, &vi_count, &vi_shift)) != 0)
1605 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
1607 if (vi_count < min_vi_count) {
1612 enp->en_arch.ef10.ena_vi_base = vi_base;
1613 enp->en_arch.ef10.ena_vi_count = vi_count;
1614 enp->en_arch.ef10.ena_vi_shift = vi_shift;
1616 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
1617 /* Not enough extra VIs to map piobufs */
1618 ef10_nic_free_piobufs(enp);
1621 enp->en_arch.ef10.ena_pio_write_vi_base =
1622 vi_count - enp->en_arch.ef10.ena_piobuf_count;
1624 /* Save UC memory mapping details */
1625 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
1626 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1627 enp->en_arch.ef10.ena_uc_mem_map_size =
1628 (ER_DZ_TX_PIOBUF_STEP *
1629 enp->en_arch.ef10.ena_pio_write_vi_base);
1631 enp->en_arch.ef10.ena_uc_mem_map_size =
1632 (ER_DZ_TX_PIOBUF_STEP *
1633 enp->en_arch.ef10.ena_vi_count);
1636 /* Save WC memory mapping details */
1637 enp->en_arch.ef10.ena_wc_mem_map_offset =
1638 enp->en_arch.ef10.ena_uc_mem_map_offset +
1639 enp->en_arch.ef10.ena_uc_mem_map_size;
1641 enp->en_arch.ef10.ena_wc_mem_map_size =
1642 (ER_DZ_TX_PIOBUF_STEP *
1643 enp->en_arch.ef10.ena_piobuf_count);
1645 /* Link piobufs to extra VIs in WC mapping */
1646 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1647 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1648 rc = efx_mcdi_link_piobuf(enp,
1649 enp->en_arch.ef10.ena_pio_write_vi_base + i,
1650 enp->en_arch.ef10.ena_piobuf_handle[i]);
1657 * Allocate a vAdaptor attached to our upstream vPort/pPort.
1659 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
1660 * driver has yet to bring up the EVB port. See bug 56147. In this case,
1661 * retry the request several times after waiting a while. The wait time
1662 * between retries starts small (10ms) and exponentially increases.
1663 * Total wait time is a little over two seconds. Retry logic in the
1664 * client driver may mean this whole loop is repeated if it continues to
1669 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
1670 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
1673 * Do not retry alloc for PF, or for other errors on
1679 /* VF startup before PF is ready. Retry allocation. */
1681 /* Too many attempts */
1685 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
1686 EFSYS_SLEEP(delay_us);
1688 if (delay_us < 500000)
1692 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
1693 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
1708 ef10_nic_free_piobufs(enp);
1711 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1716 __checkReturn efx_rc_t
1717 ef10_nic_get_vi_pool(
1718 __in efx_nic_t *enp,
1719 __out uint32_t *vi_countp)
1721 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1722 enp->en_family == EFX_FAMILY_MEDFORD ||
1723 enp->en_family == EFX_FAMILY_MEDFORD2);
1726 * Report VIs that the client driver can use.
1727 * Do not include VIs used for PIO buffer writes.
1729 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
1734 __checkReturn efx_rc_t
1735 ef10_nic_get_bar_region(
1736 __in efx_nic_t *enp,
1737 __in efx_nic_region_t region,
1738 __out uint32_t *offsetp,
1739 __out size_t *sizep)
1743 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1744 enp->en_family == EFX_FAMILY_MEDFORD ||
1745 enp->en_family == EFX_FAMILY_MEDFORD2);
1748 * TODO: Specify host memory mapping alignment and granularity
1749 * in efx_drv_limits_t so that they can be taken into account
1750 * when allocating extra VIs for PIO writes.
1754 /* UC mapped memory BAR region for VI registers */
1755 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
1756 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
1759 case EFX_REGION_PIO_WRITE_VI:
1760 /* WC mapped memory BAR region for piobuf writes */
1761 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
1762 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
1773 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1780 __in efx_nic_t *enp)
1785 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
1786 enp->en_vport_id = 0;
1788 /* Unlink piobufs from extra VIs in WC mapping */
1789 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1790 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1791 rc = efx_mcdi_unlink_piobuf(enp,
1792 enp->en_arch.ef10.ena_pio_write_vi_base + i);
1798 ef10_nic_free_piobufs(enp);
1800 (void) efx_mcdi_free_vis(enp);
1801 enp->en_arch.ef10.ena_vi_count = 0;
1806 __in efx_nic_t *enp)
1808 #if EFSYS_OPT_MON_STATS
1809 mcdi_mon_cfg_free(enp);
1810 #endif /* EFSYS_OPT_MON_STATS */
1811 (void) efx_mcdi_drv_attach(enp, B_FALSE);
1816 __checkReturn efx_rc_t
1817 ef10_nic_register_test(
1818 __in efx_nic_t *enp)
1823 _NOTE(ARGUNUSED(enp))
1824 _NOTE(CONSTANTCONDITION)
1834 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1839 #endif /* EFSYS_OPT_DIAG */
1842 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */