2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
33 #if EFSYS_OPT_MON_MCDI
37 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
39 #include "ef10_tlv_layout.h"
41 __checkReturn efx_rc_t
42 efx_mcdi_get_port_assignment(
44 __out uint32_t *portp)
47 uint8_t payload[MAX(MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
48 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN)];
51 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
52 enp->en_family == EFX_FAMILY_MEDFORD);
54 (void) memset(payload, 0, sizeof (payload));
55 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
56 req.emr_in_buf = payload;
57 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
58 req.emr_out_buf = payload;
59 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
61 efx_mcdi_execute(enp, &req);
63 if (req.emr_rc != 0) {
68 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
73 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
80 EFSYS_PROBE1(fail1, efx_rc_t, rc);
85 __checkReturn efx_rc_t
86 efx_mcdi_get_port_modes(
88 __out uint32_t *modesp,
89 __out_opt uint32_t *current_modep)
92 uint8_t payload[MAX(MC_CMD_GET_PORT_MODES_IN_LEN,
93 MC_CMD_GET_PORT_MODES_OUT_LEN)];
96 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
97 enp->en_family == EFX_FAMILY_MEDFORD);
99 (void) memset(payload, 0, sizeof (payload));
100 req.emr_cmd = MC_CMD_GET_PORT_MODES;
101 req.emr_in_buf = payload;
102 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
103 req.emr_out_buf = payload;
104 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
106 efx_mcdi_execute(enp, &req);
108 if (req.emr_rc != 0) {
114 * Require only Modes and DefaultMode fields, unless the current mode
115 * was requested (CurrentMode field was added for Medford).
117 if (req.emr_out_length_used <
118 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
122 if ((current_modep != NULL) && (req.emr_out_length_used <
123 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) {
128 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
130 if (current_modep != NULL) {
131 *current_modep = MCDI_OUT_DWORD(req,
132 GET_PORT_MODES_OUT_CURRENT_MODE);
142 EFSYS_PROBE1(fail1, efx_rc_t, rc);
147 __checkReturn efx_rc_t
148 ef10_nic_get_port_mode_bandwidth(
149 __in uint32_t port_mode,
150 __out uint32_t *bandwidth_mbpsp)
156 case TLV_PORT_MODE_10G:
159 case TLV_PORT_MODE_10G_10G:
160 bandwidth = 10000 * 2;
162 case TLV_PORT_MODE_10G_10G_10G_10G:
163 case TLV_PORT_MODE_10G_10G_10G_10G_Q:
164 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2:
165 case TLV_PORT_MODE_10G_10G_10G_10G_Q2:
166 bandwidth = 10000 * 4;
168 case TLV_PORT_MODE_40G:
171 case TLV_PORT_MODE_40G_40G:
172 bandwidth = 40000 * 2;
174 case TLV_PORT_MODE_40G_10G_10G:
175 case TLV_PORT_MODE_10G_10G_40G:
176 bandwidth = 40000 + (10000 * 2);
183 *bandwidth_mbpsp = bandwidth;
188 EFSYS_PROBE1(fail1, efx_rc_t, rc);
193 static __checkReturn efx_rc_t
194 efx_mcdi_vadaptor_alloc(
196 __in uint32_t port_id)
199 uint8_t payload[MAX(MC_CMD_VADAPTOR_ALLOC_IN_LEN,
200 MC_CMD_VADAPTOR_ALLOC_OUT_LEN)];
203 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
205 (void) memset(payload, 0, sizeof (payload));
206 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
207 req.emr_in_buf = payload;
208 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
209 req.emr_out_buf = payload;
210 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
212 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
213 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
214 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
215 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
217 efx_mcdi_execute(enp, &req);
219 if (req.emr_rc != 0) {
227 EFSYS_PROBE1(fail1, efx_rc_t, rc);
232 static __checkReturn efx_rc_t
233 efx_mcdi_vadaptor_free(
235 __in uint32_t port_id)
238 uint8_t payload[MAX(MC_CMD_VADAPTOR_FREE_IN_LEN,
239 MC_CMD_VADAPTOR_FREE_OUT_LEN)];
242 (void) memset(payload, 0, sizeof (payload));
243 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
244 req.emr_in_buf = payload;
245 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
246 req.emr_out_buf = payload;
247 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
249 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
251 efx_mcdi_execute(enp, &req);
253 if (req.emr_rc != 0) {
261 EFSYS_PROBE1(fail1, efx_rc_t, rc);
266 __checkReturn efx_rc_t
267 efx_mcdi_get_mac_address_pf(
269 __out_ecount_opt(6) uint8_t mac_addrp[6])
272 uint8_t payload[MAX(MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
273 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)];
276 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
277 enp->en_family == EFX_FAMILY_MEDFORD);
279 (void) memset(payload, 0, sizeof (payload));
280 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
281 req.emr_in_buf = payload;
282 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
283 req.emr_out_buf = payload;
284 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
286 efx_mcdi_execute(enp, &req);
288 if (req.emr_rc != 0) {
293 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
298 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
303 if (mac_addrp != NULL) {
306 addrp = MCDI_OUT2(req, uint8_t,
307 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
309 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
319 EFSYS_PROBE1(fail1, efx_rc_t, rc);
324 __checkReturn efx_rc_t
325 efx_mcdi_get_mac_address_vf(
327 __out_ecount_opt(6) uint8_t mac_addrp[6])
330 uint8_t payload[MAX(MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
331 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX)];
334 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
335 enp->en_family == EFX_FAMILY_MEDFORD);
337 (void) memset(payload, 0, sizeof (payload));
338 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
339 req.emr_in_buf = payload;
340 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
341 req.emr_out_buf = payload;
342 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
344 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
345 EVB_PORT_ID_ASSIGNED);
347 efx_mcdi_execute(enp, &req);
349 if (req.emr_rc != 0) {
354 if (req.emr_out_length_used <
355 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
360 if (MCDI_OUT_DWORD(req,
361 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
366 if (mac_addrp != NULL) {
369 addrp = MCDI_OUT2(req, uint8_t,
370 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
372 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
382 EFSYS_PROBE1(fail1, efx_rc_t, rc);
387 __checkReturn efx_rc_t
390 __out uint32_t *sys_freqp,
391 __out uint32_t *dpcpu_freqp)
394 uint8_t payload[MAX(MC_CMD_GET_CLOCK_IN_LEN,
395 MC_CMD_GET_CLOCK_OUT_LEN)];
398 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
399 enp->en_family == EFX_FAMILY_MEDFORD);
401 (void) memset(payload, 0, sizeof (payload));
402 req.emr_cmd = MC_CMD_GET_CLOCK;
403 req.emr_in_buf = payload;
404 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
405 req.emr_out_buf = payload;
406 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
408 efx_mcdi_execute(enp, &req);
410 if (req.emr_rc != 0) {
415 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
420 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
421 if (*sys_freqp == 0) {
425 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
426 if (*dpcpu_freqp == 0) {
440 EFSYS_PROBE1(fail1, efx_rc_t, rc);
445 __checkReturn efx_rc_t
446 efx_mcdi_get_vector_cfg(
448 __out_opt uint32_t *vec_basep,
449 __out_opt uint32_t *pf_nvecp,
450 __out_opt uint32_t *vf_nvecp)
453 uint8_t payload[MAX(MC_CMD_GET_VECTOR_CFG_IN_LEN,
454 MC_CMD_GET_VECTOR_CFG_OUT_LEN)];
457 (void) memset(payload, 0, sizeof (payload));
458 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
459 req.emr_in_buf = payload;
460 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
461 req.emr_out_buf = payload;
462 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
464 efx_mcdi_execute(enp, &req);
466 if (req.emr_rc != 0) {
471 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
476 if (vec_basep != NULL)
477 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
478 if (pf_nvecp != NULL)
479 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
480 if (vf_nvecp != NULL)
481 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
488 EFSYS_PROBE1(fail1, efx_rc_t, rc);
493 static __checkReturn efx_rc_t
496 __in uint32_t min_vi_count,
497 __in uint32_t max_vi_count,
498 __out uint32_t *vi_basep,
499 __out uint32_t *vi_countp,
500 __out uint32_t *vi_shiftp)
503 uint8_t payload[MAX(MC_CMD_ALLOC_VIS_IN_LEN,
504 MC_CMD_ALLOC_VIS_EXT_OUT_LEN)];
507 if (vi_countp == NULL) {
512 (void) memset(payload, 0, sizeof (payload));
513 req.emr_cmd = MC_CMD_ALLOC_VIS;
514 req.emr_in_buf = payload;
515 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
516 req.emr_out_buf = payload;
517 req.emr_out_length = MC_CMD_ALLOC_VIS_EXT_OUT_LEN;
519 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
520 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
522 efx_mcdi_execute(enp, &req);
524 if (req.emr_rc != 0) {
529 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
534 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
535 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
537 /* Report VI_SHIFT if available (always zero for Huntington) */
538 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
541 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
550 EFSYS_PROBE1(fail1, efx_rc_t, rc);
556 static __checkReturn efx_rc_t
563 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
564 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
566 req.emr_cmd = MC_CMD_FREE_VIS;
567 req.emr_in_buf = NULL;
568 req.emr_in_length = 0;
569 req.emr_out_buf = NULL;
570 req.emr_out_length = 0;
572 efx_mcdi_execute_quiet(enp, &req);
574 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
575 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
583 EFSYS_PROBE1(fail1, efx_rc_t, rc);
589 static __checkReturn efx_rc_t
590 efx_mcdi_alloc_piobuf(
592 __out efx_piobuf_handle_t *handlep)
595 uint8_t payload[MAX(MC_CMD_ALLOC_PIOBUF_IN_LEN,
596 MC_CMD_ALLOC_PIOBUF_OUT_LEN)];
599 if (handlep == NULL) {
604 (void) memset(payload, 0, sizeof (payload));
605 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
606 req.emr_in_buf = payload;
607 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
608 req.emr_out_buf = payload;
609 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
611 efx_mcdi_execute_quiet(enp, &req);
613 if (req.emr_rc != 0) {
618 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
623 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
632 EFSYS_PROBE1(fail1, efx_rc_t, rc);
637 static __checkReturn efx_rc_t
638 efx_mcdi_free_piobuf(
640 __in efx_piobuf_handle_t handle)
643 uint8_t payload[MAX(MC_CMD_FREE_PIOBUF_IN_LEN,
644 MC_CMD_FREE_PIOBUF_OUT_LEN)];
647 (void) memset(payload, 0, sizeof (payload));
648 req.emr_cmd = MC_CMD_FREE_PIOBUF;
649 req.emr_in_buf = payload;
650 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
651 req.emr_out_buf = payload;
652 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
654 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
656 efx_mcdi_execute_quiet(enp, &req);
658 if (req.emr_rc != 0) {
666 EFSYS_PROBE1(fail1, efx_rc_t, rc);
671 static __checkReturn efx_rc_t
672 efx_mcdi_link_piobuf(
674 __in uint32_t vi_index,
675 __in efx_piobuf_handle_t handle)
678 uint8_t payload[MAX(MC_CMD_LINK_PIOBUF_IN_LEN,
679 MC_CMD_LINK_PIOBUF_OUT_LEN)];
682 (void) memset(payload, 0, sizeof (payload));
683 req.emr_cmd = MC_CMD_LINK_PIOBUF;
684 req.emr_in_buf = payload;
685 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
686 req.emr_out_buf = payload;
687 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
689 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
690 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
692 efx_mcdi_execute(enp, &req);
694 if (req.emr_rc != 0) {
702 EFSYS_PROBE1(fail1, efx_rc_t, rc);
707 static __checkReturn efx_rc_t
708 efx_mcdi_unlink_piobuf(
710 __in uint32_t vi_index)
713 uint8_t payload[MAX(MC_CMD_UNLINK_PIOBUF_IN_LEN,
714 MC_CMD_UNLINK_PIOBUF_OUT_LEN)];
717 (void) memset(payload, 0, sizeof (payload));
718 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
719 req.emr_in_buf = payload;
720 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
721 req.emr_out_buf = payload;
722 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
724 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
726 efx_mcdi_execute_quiet(enp, &req);
728 if (req.emr_rc != 0) {
736 EFSYS_PROBE1(fail1, efx_rc_t, rc);
742 ef10_nic_alloc_piobufs(
744 __in uint32_t max_piobuf_count)
746 efx_piobuf_handle_t *handlep;
749 EFSYS_ASSERT3U(max_piobuf_count, <=,
750 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
752 enp->en_arch.ef10.ena_piobuf_count = 0;
754 for (i = 0; i < max_piobuf_count; i++) {
755 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
757 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0)
760 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
761 enp->en_arch.ef10.ena_piobuf_count++;
767 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
768 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
770 efx_mcdi_free_piobuf(enp, *handlep);
771 *handlep = EFX_PIOBUF_HANDLE_INVALID;
773 enp->en_arch.ef10.ena_piobuf_count = 0;
778 ef10_nic_free_piobufs(
781 efx_piobuf_handle_t *handlep;
784 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
785 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
787 efx_mcdi_free_piobuf(enp, *handlep);
788 *handlep = EFX_PIOBUF_HANDLE_INVALID;
790 enp->en_arch.ef10.ena_piobuf_count = 0;
793 /* Sub-allocate a block from a piobuf */
794 __checkReturn efx_rc_t
796 __inout efx_nic_t *enp,
797 __out uint32_t *bufnump,
798 __out efx_piobuf_handle_t *handlep,
799 __out uint32_t *blknump,
800 __out uint32_t *offsetp,
803 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
804 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
805 uint32_t blk_per_buf;
809 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
810 enp->en_family == EFX_FAMILY_MEDFORD);
811 EFSYS_ASSERT(bufnump);
812 EFSYS_ASSERT(handlep);
813 EFSYS_ASSERT(blknump);
814 EFSYS_ASSERT(offsetp);
817 if ((edcp->edc_pio_alloc_size == 0) ||
818 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
822 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
824 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
825 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
830 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
831 for (blk = 0; blk < blk_per_buf; blk++) {
832 if ((*map & (1u << blk)) == 0) {
842 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
845 *sizep = edcp->edc_pio_alloc_size;
846 *offsetp = blk * (*sizep);
853 EFSYS_PROBE1(fail1, efx_rc_t, rc);
858 /* Free a piobuf sub-allocated block */
859 __checkReturn efx_rc_t
861 __inout efx_nic_t *enp,
862 __in uint32_t bufnum,
863 __in uint32_t blknum)
868 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
869 (blknum >= (8 * sizeof (*map)))) {
874 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
875 if ((*map & (1u << blknum)) == 0) {
879 *map &= ~(1u << blknum);
886 EFSYS_PROBE1(fail1, efx_rc_t, rc);
891 __checkReturn efx_rc_t
893 __inout efx_nic_t *enp,
894 __in uint32_t vi_index,
895 __in efx_piobuf_handle_t handle)
897 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
900 __checkReturn efx_rc_t
902 __inout efx_nic_t *enp,
903 __in uint32_t vi_index)
905 return (efx_mcdi_unlink_piobuf(enp, vi_index));
908 static __checkReturn efx_rc_t
909 ef10_mcdi_get_pf_count(
911 __out uint32_t *pf_countp)
914 uint8_t payload[MAX(MC_CMD_GET_PF_COUNT_IN_LEN,
915 MC_CMD_GET_PF_COUNT_OUT_LEN)];
918 (void) memset(payload, 0, sizeof (payload));
919 req.emr_cmd = MC_CMD_GET_PF_COUNT;
920 req.emr_in_buf = payload;
921 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN;
922 req.emr_out_buf = payload;
923 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN;
925 efx_mcdi_execute(enp, &req);
927 if (req.emr_rc != 0) {
932 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) {
937 *pf_countp = *MCDI_OUT(req, uint8_t,
938 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST);
940 EFSYS_ASSERT(*pf_countp != 0);
947 EFSYS_PROBE1(fail1, efx_rc_t, rc);
952 __checkReturn efx_rc_t
953 ef10_get_datapath_caps(
956 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
962 if ((rc = efx_mcdi_get_capabilities(enp, &flags, NULL, NULL,
963 &flags2, &tso2nc)) != 0)
966 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0)
969 #define CAP_FLAG(flags1, field) \
970 ((flags1) & (1 << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## field ## _LBN)))
972 #define CAP_FLAG2(flags2, field) \
973 ((flags2) & (1 << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## field ## _LBN)))
976 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
977 * We only support the 14 byte prefix here.
979 if (CAP_FLAG(flags, RX_PREFIX_LEN_14) == 0) {
983 encp->enc_rx_prefix_size = 14;
985 /* Check if the firmware supports TSO */
986 encp->enc_fw_assisted_tso_enabled =
987 CAP_FLAG(flags, TX_TSO) ? B_TRUE : B_FALSE;
989 /* Check if the firmware supports FATSOv2 */
990 encp->enc_fw_assisted_tso_v2_enabled =
991 CAP_FLAG2(flags2, TX_TSO_V2) ? B_TRUE : B_FALSE;
993 /* Get the number of TSO contexts (FATSOv2) */
994 encp->enc_fw_assisted_tso_v2_n_contexts =
995 CAP_FLAG2(flags2, TX_TSO_V2) ? tso2nc : 0;
997 /* Check if the firmware has vadapter/vport/vswitch support */
998 encp->enc_datapath_cap_evb =
999 CAP_FLAG(flags, EVB) ? B_TRUE : B_FALSE;
1001 /* Check if the firmware supports VLAN insertion */
1002 encp->enc_hw_tx_insert_vlan_enabled =
1003 CAP_FLAG(flags, TX_VLAN_INSERTION) ? B_TRUE : B_FALSE;
1005 /* Check if the firmware supports RX event batching */
1006 encp->enc_rx_batching_enabled =
1007 CAP_FLAG(flags, RX_BATCHING) ? B_TRUE : B_FALSE;
1010 * Even if batching isn't reported as supported, we may still get
1011 * batched events (see bug61153).
1013 encp->enc_rx_batch_max = 16;
1015 /* Check if the firmware supports disabling scatter on RXQs */
1016 encp->enc_rx_disable_scatter_supported =
1017 CAP_FLAG(flags, RX_DISABLE_SCATTER) ? B_TRUE : B_FALSE;
1019 /* Check if the firmware supports packed stream mode */
1020 encp->enc_rx_packed_stream_supported =
1021 CAP_FLAG(flags, RX_PACKED_STREAM) ? B_TRUE : B_FALSE;
1024 * Check if the firmware supports configurable buffer sizes
1025 * for packed stream mode (otherwise buffer size is 1Mbyte)
1027 encp->enc_rx_var_packed_stream_supported =
1028 CAP_FLAG(flags, RX_PACKED_STREAM_VAR_BUFFERS) ? B_TRUE : B_FALSE;
1030 /* Check if the firmware supports set mac with running filters */
1031 encp->enc_allow_set_mac_with_installed_filters =
1032 CAP_FLAG(flags, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED) ?
1036 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows
1037 * specifying which parameters to configure.
1039 encp->enc_enhanced_set_mac_supported =
1040 CAP_FLAG(flags, SET_MAC_ENHANCED) ? B_TRUE : B_FALSE;
1043 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows
1044 * us to let the firmware choose the settings to use on an EVQ.
1046 encp->enc_init_evq_v2_supported =
1047 CAP_FLAG2(flags2, INIT_EVQ_V2) ? B_TRUE : B_FALSE;
1050 * Check if firmware-verified NVRAM updates must be used.
1052 * The firmware trusted installer requires all NVRAM updates to use
1053 * version 2 of MC_CMD_NVRAM_UPDATE_START (to enable verified update)
1054 * and version 2 of MC_CMD_NVRAM_UPDATE_FINISH (to verify the updated
1055 * partition and report the result).
1057 encp->enc_fw_verified_nvram_update_required =
1058 CAP_FLAG2(flags2, NVRAM_UPDATE_REPORT_VERIFY_RESULT) ?
1062 * Check if firmware provides packet memory and Rx datapath
1065 encp->enc_pm_and_rxdp_counters =
1066 CAP_FLAG(flags, PM_AND_RXDP_COUNTERS) ? B_TRUE : B_FALSE;
1069 * Check if the 40G MAC hardware is capable of reporting
1070 * statistics for Tx size bins.
1072 encp->enc_mac_stats_40g_tx_size_bins =
1073 CAP_FLAG2(flags2, MAC_STATS_40G_TX_SIZE_BINS) ? B_TRUE : B_FALSE;
1083 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1089 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
1090 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
1091 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
1092 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
1093 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
1094 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
1095 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
1096 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
1097 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
1098 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
1099 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
1100 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
1102 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
1105 __checkReturn efx_rc_t
1106 ef10_get_privilege_mask(
1107 __in efx_nic_t *enp,
1108 __out uint32_t *maskp)
1110 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1114 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1119 /* Fallback for old firmware without privilege mask support */
1120 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1121 /* Assume PF has admin privilege */
1122 mask = EF10_LEGACY_PF_PRIVILEGE_MASK;
1124 /* VF is always unprivileged by default */
1125 mask = EF10_LEGACY_VF_PRIVILEGE_MASK;
1134 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1141 * Table of mapping schemes from port number to the number of the external
1142 * connector on the board. The external numbering does not distinguish
1143 * off-board separated outputs such as from multi-headed cables.
1145 * The count of adjacent port numbers that map to each external port
1146 * and the offset in the numbering, is determined by the chip family and
1147 * current port mode.
1149 * For the Huntington family, the current port mode cannot be discovered,
1150 * so the mapping used is instead the last match in the table to the full
1151 * set of port modes to which the NIC can be configured. Therefore the
1152 * ordering of entries in the the mapping table is significant.
1155 efx_family_t family;
1156 uint32_t modes_mask;
1159 } __ef10_external_port_mappings[] = {
1160 /* Supported modes with 1 output per external port */
1162 EFX_FAMILY_HUNTINGTON,
1163 (1 << TLV_PORT_MODE_10G) |
1164 (1 << TLV_PORT_MODE_10G_10G) |
1165 (1 << TLV_PORT_MODE_10G_10G_10G_10G),
1171 (1 << TLV_PORT_MODE_10G) |
1172 (1 << TLV_PORT_MODE_10G_10G),
1176 /* Supported modes with 2 outputs per external port */
1178 EFX_FAMILY_HUNTINGTON,
1179 (1 << TLV_PORT_MODE_40G) |
1180 (1 << TLV_PORT_MODE_40G_40G) |
1181 (1 << TLV_PORT_MODE_40G_10G_10G) |
1182 (1 << TLV_PORT_MODE_10G_10G_40G),
1188 (1 << TLV_PORT_MODE_40G) |
1189 (1 << TLV_PORT_MODE_40G_40G) |
1190 (1 << TLV_PORT_MODE_40G_10G_10G) |
1191 (1 << TLV_PORT_MODE_10G_10G_40G) |
1192 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2),
1196 /* Supported modes with 4 outputs per external port */
1199 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q) |
1200 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1),
1206 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q2),
1212 __checkReturn efx_rc_t
1213 ef10_external_port_mapping(
1214 __in efx_nic_t *enp,
1216 __out uint8_t *external_portp)
1220 uint32_t port_modes;
1223 int32_t count = 1; /* Default 1-1 mapping */
1224 int32_t offset = 1; /* Default starting external port number */
1226 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t)) != 0) {
1228 * No current port mode information
1229 * - infer mapping from available modes
1231 if ((rc = efx_mcdi_get_port_modes(enp,
1232 &port_modes, NULL)) != 0) {
1234 * No port mode information available
1235 * - use default mapping
1240 /* Only need to scan the current mode */
1241 port_modes = 1 << current;
1245 * Infer the internal port -> external port mapping from
1246 * the possible port modes for this NIC.
1248 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1249 if (__ef10_external_port_mappings[i].family !=
1252 matches = (__ef10_external_port_mappings[i].modes_mask &
1255 count = __ef10_external_port_mappings[i].count;
1256 offset = __ef10_external_port_mappings[i].offset;
1257 port_modes &= ~matches;
1261 if (port_modes != 0) {
1262 /* Some advertised modes are not supported */
1269 * Scale as required by last matched mode and then convert to
1270 * correctly offset numbering
1272 *external_portp = (uint8_t)((port / count) + offset);
1276 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1282 __checkReturn efx_rc_t
1284 __in efx_nic_t *enp)
1286 const efx_nic_ops_t *enop = enp->en_enop;
1287 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1288 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1291 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1292 enp->en_family == EFX_FAMILY_MEDFORD);
1294 /* Read and clear any assertion state */
1295 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1298 /* Exit the assertion handler */
1299 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1303 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
1306 if ((rc = enop->eno_board_cfg(enp)) != 0)
1311 * Set default driver config limits (based on board config).
1313 * FIXME: For now allocate a fixed number of VIs which is likely to be
1314 * sufficient and small enough to allow multiple functions on the same
1317 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
1318 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
1320 /* The client driver must configure and enable PIO buffer support */
1321 edcp->edc_max_piobuf_count = 0;
1322 edcp->edc_pio_alloc_size = 0;
1324 #if EFSYS_OPT_MAC_STATS
1325 /* Wipe the MAC statistics */
1326 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
1330 #if EFSYS_OPT_LOOPBACK
1331 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
1335 #if EFSYS_OPT_MON_STATS
1336 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
1337 /* Unprivileged functions do not have access to sensors */
1343 encp->enc_features = enp->en_features;
1347 #if EFSYS_OPT_MON_STATS
1351 #if EFSYS_OPT_LOOPBACK
1355 #if EFSYS_OPT_MAC_STATS
1366 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1371 __checkReturn efx_rc_t
1372 ef10_nic_set_drv_limits(
1373 __inout efx_nic_t *enp,
1374 __in efx_drv_limits_t *edlp)
1376 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1377 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1378 uint32_t min_evq_count, max_evq_count;
1379 uint32_t min_rxq_count, max_rxq_count;
1380 uint32_t min_txq_count, max_txq_count;
1388 /* Get minimum required and maximum usable VI limits */
1389 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
1390 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
1391 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
1393 edcp->edc_min_vi_count =
1394 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
1396 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
1397 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
1398 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
1400 edcp->edc_max_vi_count =
1401 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
1404 * Check limits for sub-allocated piobuf blocks.
1405 * PIO is optional, so don't fail if the limits are incorrect.
1407 if ((encp->enc_piobuf_size == 0) ||
1408 (encp->enc_piobuf_limit == 0) ||
1409 (edlp->edl_min_pio_alloc_size == 0) ||
1410 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
1412 edcp->edc_max_piobuf_count = 0;
1413 edcp->edc_pio_alloc_size = 0;
1415 uint32_t blk_size, blk_count, blks_per_piobuf;
1418 MAX(edlp->edl_min_pio_alloc_size,
1419 encp->enc_piobuf_min_alloc_size);
1421 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
1422 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
1424 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
1426 /* A zero max pio alloc count means unlimited */
1427 if ((edlp->edl_max_pio_alloc_count > 0) &&
1428 (edlp->edl_max_pio_alloc_count < blk_count)) {
1429 blk_count = edlp->edl_max_pio_alloc_count;
1432 edcp->edc_pio_alloc_size = blk_size;
1433 edcp->edc_max_piobuf_count =
1434 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
1440 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1446 __checkReturn efx_rc_t
1448 __in efx_nic_t *enp)
1451 uint8_t payload[MAX(MC_CMD_ENTITY_RESET_IN_LEN,
1452 MC_CMD_ENTITY_RESET_OUT_LEN)];
1455 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
1456 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1458 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1461 (void) memset(payload, 0, sizeof (payload));
1462 req.emr_cmd = MC_CMD_ENTITY_RESET;
1463 req.emr_in_buf = payload;
1464 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
1465 req.emr_out_buf = payload;
1466 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
1468 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
1469 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
1471 efx_mcdi_execute(enp, &req);
1473 if (req.emr_rc != 0) {
1478 /* Clear RX/TX DMA queue errors */
1479 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
1488 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1493 __checkReturn efx_rc_t
1495 __in efx_nic_t *enp)
1497 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1498 uint32_t min_vi_count, max_vi_count;
1499 uint32_t vi_count, vi_base, vi_shift;
1505 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1506 enp->en_family == EFX_FAMILY_MEDFORD);
1508 /* Enable reporting of some events (e.g. link change) */
1509 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
1512 /* Allocate (optional) on-chip PIO buffers */
1513 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
1516 * For best performance, PIO writes should use a write-combined
1517 * (WC) memory mapping. Using a separate WC mapping for the PIO
1518 * aperture of each VI would be a burden to drivers (and not
1519 * possible if the host page size is >4Kbyte).
1521 * To avoid this we use a single uncached (UC) mapping for VI
1522 * register access, and a single WC mapping for extra VIs used
1525 * Each piobuf must be linked to a VI in the WC mapping, and to
1526 * each VI that is using a sub-allocated block from the piobuf.
1528 min_vi_count = edcp->edc_min_vi_count;
1530 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
1532 /* Ensure that the previously attached driver's VIs are freed */
1533 if ((rc = efx_mcdi_free_vis(enp)) != 0)
1537 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
1538 * fails then retrying the request for fewer VI resources may succeed.
1541 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
1542 &vi_base, &vi_count, &vi_shift)) != 0)
1545 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
1547 if (vi_count < min_vi_count) {
1552 enp->en_arch.ef10.ena_vi_base = vi_base;
1553 enp->en_arch.ef10.ena_vi_count = vi_count;
1554 enp->en_arch.ef10.ena_vi_shift = vi_shift;
1556 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
1557 /* Not enough extra VIs to map piobufs */
1558 ef10_nic_free_piobufs(enp);
1561 enp->en_arch.ef10.ena_pio_write_vi_base =
1562 vi_count - enp->en_arch.ef10.ena_piobuf_count;
1564 /* Save UC memory mapping details */
1565 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
1566 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1567 enp->en_arch.ef10.ena_uc_mem_map_size =
1568 (ER_DZ_TX_PIOBUF_STEP *
1569 enp->en_arch.ef10.ena_pio_write_vi_base);
1571 enp->en_arch.ef10.ena_uc_mem_map_size =
1572 (ER_DZ_TX_PIOBUF_STEP *
1573 enp->en_arch.ef10.ena_vi_count);
1576 /* Save WC memory mapping details */
1577 enp->en_arch.ef10.ena_wc_mem_map_offset =
1578 enp->en_arch.ef10.ena_uc_mem_map_offset +
1579 enp->en_arch.ef10.ena_uc_mem_map_size;
1581 enp->en_arch.ef10.ena_wc_mem_map_size =
1582 (ER_DZ_TX_PIOBUF_STEP *
1583 enp->en_arch.ef10.ena_piobuf_count);
1585 /* Link piobufs to extra VIs in WC mapping */
1586 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1587 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1588 rc = efx_mcdi_link_piobuf(enp,
1589 enp->en_arch.ef10.ena_pio_write_vi_base + i,
1590 enp->en_arch.ef10.ena_piobuf_handle[i]);
1597 * Allocate a vAdaptor attached to our upstream vPort/pPort.
1599 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
1600 * driver has yet to bring up the EVB port. See bug 56147. In this case,
1601 * retry the request several times after waiting a while. The wait time
1602 * between retries starts small (10ms) and exponentially increases.
1603 * Total wait time is a little over two seconds. Retry logic in the
1604 * client driver may mean this whole loop is repeated if it continues to
1609 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
1610 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
1613 * Do not retry alloc for PF, or for other errors on
1619 /* VF startup before PF is ready. Retry allocation. */
1621 /* Too many attempts */
1625 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
1626 EFSYS_SLEEP(delay_us);
1628 if (delay_us < 500000)
1632 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
1633 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
1648 ef10_nic_free_piobufs(enp);
1651 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1656 __checkReturn efx_rc_t
1657 ef10_nic_get_vi_pool(
1658 __in efx_nic_t *enp,
1659 __out uint32_t *vi_countp)
1661 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1662 enp->en_family == EFX_FAMILY_MEDFORD);
1665 * Report VIs that the client driver can use.
1666 * Do not include VIs used for PIO buffer writes.
1668 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
1673 __checkReturn efx_rc_t
1674 ef10_nic_get_bar_region(
1675 __in efx_nic_t *enp,
1676 __in efx_nic_region_t region,
1677 __out uint32_t *offsetp,
1678 __out size_t *sizep)
1682 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1683 enp->en_family == EFX_FAMILY_MEDFORD);
1686 * TODO: Specify host memory mapping alignment and granularity
1687 * in efx_drv_limits_t so that they can be taken into account
1688 * when allocating extra VIs for PIO writes.
1692 /* UC mapped memory BAR region for VI registers */
1693 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
1694 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
1697 case EFX_REGION_PIO_WRITE_VI:
1698 /* WC mapped memory BAR region for piobuf writes */
1699 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
1700 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
1711 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1718 __in efx_nic_t *enp)
1723 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
1724 enp->en_vport_id = 0;
1726 /* Unlink piobufs from extra VIs in WC mapping */
1727 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1728 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1729 rc = efx_mcdi_unlink_piobuf(enp,
1730 enp->en_arch.ef10.ena_pio_write_vi_base + i);
1736 ef10_nic_free_piobufs(enp);
1738 (void) efx_mcdi_free_vis(enp);
1739 enp->en_arch.ef10.ena_vi_count = 0;
1744 __in efx_nic_t *enp)
1746 #if EFSYS_OPT_MON_STATS
1747 mcdi_mon_cfg_free(enp);
1748 #endif /* EFSYS_OPT_MON_STATS */
1749 (void) efx_mcdi_drv_attach(enp, B_FALSE);
1754 __checkReturn efx_rc_t
1755 ef10_nic_register_test(
1756 __in efx_nic_t *enp)
1761 _NOTE(ARGUNUSED(enp))
1762 _NOTE(CONSTANTCONDITION)
1772 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1777 #endif /* EFSYS_OPT_DIAG */
1780 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */