1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2012-2019 Solarflare Communications Inc.
15 #include "ef10_tlv_layout.h"
17 __checkReturn efx_rc_t
18 efx_mcdi_get_port_assignment(
20 __out uint32_t *portp)
23 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
24 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN);
27 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
29 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
30 req.emr_in_buf = payload;
31 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
32 req.emr_out_buf = payload;
33 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
35 efx_mcdi_execute(enp, &req);
37 if (req.emr_rc != 0) {
42 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
47 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
54 EFSYS_PROBE1(fail1, efx_rc_t, rc);
59 __checkReturn efx_rc_t
60 efx_mcdi_get_port_modes(
62 __out uint32_t *modesp,
63 __out_opt uint32_t *current_modep,
64 __out_opt uint32_t *default_modep)
67 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_MODES_IN_LEN,
68 MC_CMD_GET_PORT_MODES_OUT_LEN);
71 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
73 req.emr_cmd = MC_CMD_GET_PORT_MODES;
74 req.emr_in_buf = payload;
75 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
76 req.emr_out_buf = payload;
77 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
79 efx_mcdi_execute(enp, &req);
81 if (req.emr_rc != 0) {
87 * Require only Modes and DefaultMode fields, unless the current mode
88 * was requested (CurrentMode field was added for Medford).
90 if (req.emr_out_length_used <
91 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
95 if ((current_modep != NULL) && (req.emr_out_length_used <
96 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) {
101 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
103 if (current_modep != NULL) {
104 *current_modep = MCDI_OUT_DWORD(req,
105 GET_PORT_MODES_OUT_CURRENT_MODE);
108 if (default_modep != NULL) {
109 *default_modep = MCDI_OUT_DWORD(req,
110 GET_PORT_MODES_OUT_DEFAULT_MODE);
120 EFSYS_PROBE1(fail1, efx_rc_t, rc);
125 __checkReturn efx_rc_t
126 ef10_nic_get_port_mode_bandwidth(
128 __out uint32_t *bandwidth_mbpsp)
131 uint32_t current_mode;
132 efx_port_t *epp = &(enp->en_port);
134 uint32_t single_lane;
140 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
141 ¤t_mode, NULL)) != 0) {
142 /* No port mode info available. */
146 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_25000FDX))
151 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_50000FDX))
156 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_100000FDX))
161 switch (current_mode) {
162 case TLV_PORT_MODE_1x1_NA: /* mode 0 */
163 bandwidth = single_lane;
165 case TLV_PORT_MODE_1x2_NA: /* mode 10 */
166 case TLV_PORT_MODE_NA_1x2: /* mode 11 */
167 bandwidth = dual_lane;
169 case TLV_PORT_MODE_1x1_1x1: /* mode 2 */
170 bandwidth = single_lane + single_lane;
172 case TLV_PORT_MODE_4x1_NA: /* mode 4 */
173 case TLV_PORT_MODE_NA_4x1: /* mode 8 */
174 bandwidth = 4 * single_lane;
176 case TLV_PORT_MODE_2x1_2x1: /* mode 5 */
177 bandwidth = (2 * single_lane) + (2 * single_lane);
179 case TLV_PORT_MODE_1x2_1x2: /* mode 12 */
180 bandwidth = dual_lane + dual_lane;
182 case TLV_PORT_MODE_1x2_2x1: /* mode 17 */
183 case TLV_PORT_MODE_2x1_1x2: /* mode 18 */
184 bandwidth = dual_lane + (2 * single_lane);
186 /* Legacy Medford-only mode. Do not use (see bug63270) */
187 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2: /* mode 9 */
188 bandwidth = 4 * single_lane;
190 case TLV_PORT_MODE_1x4_NA: /* mode 1 */
191 case TLV_PORT_MODE_NA_1x4: /* mode 22 */
192 bandwidth = quad_lane;
194 case TLV_PORT_MODE_2x2_NA: /* mode 13 */
195 case TLV_PORT_MODE_NA_2x2: /* mode 14 */
196 bandwidth = 2 * dual_lane;
198 case TLV_PORT_MODE_1x4_2x1: /* mode 6 */
199 case TLV_PORT_MODE_2x1_1x4: /* mode 7 */
200 bandwidth = quad_lane + (2 * single_lane);
202 case TLV_PORT_MODE_1x4_1x2: /* mode 15 */
203 case TLV_PORT_MODE_1x2_1x4: /* mode 16 */
204 bandwidth = quad_lane + dual_lane;
206 case TLV_PORT_MODE_1x4_1x4: /* mode 3 */
207 bandwidth = quad_lane + quad_lane;
214 *bandwidth_mbpsp = bandwidth;
221 EFSYS_PROBE1(fail1, efx_rc_t, rc);
226 __checkReturn efx_rc_t
227 efx_mcdi_vadaptor_alloc(
229 __in uint32_t port_id)
232 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_ALLOC_IN_LEN,
233 MC_CMD_VADAPTOR_ALLOC_OUT_LEN);
236 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
237 req.emr_in_buf = payload;
238 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
239 req.emr_out_buf = payload;
240 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
242 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
243 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
244 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
245 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
247 efx_mcdi_execute(enp, &req);
249 if (req.emr_rc != 0) {
257 EFSYS_PROBE1(fail1, efx_rc_t, rc);
262 __checkReturn efx_rc_t
263 efx_mcdi_vadaptor_free(
265 __in uint32_t port_id)
268 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_FREE_IN_LEN,
269 MC_CMD_VADAPTOR_FREE_OUT_LEN);
272 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
273 req.emr_in_buf = payload;
274 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
275 req.emr_out_buf = payload;
276 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
278 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
280 efx_mcdi_execute(enp, &req);
282 if (req.emr_rc != 0) {
290 EFSYS_PROBE1(fail1, efx_rc_t, rc);
295 __checkReturn efx_rc_t
296 efx_mcdi_get_mac_address_pf(
298 __out_ecount_opt(6) uint8_t mac_addrp[6])
301 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
302 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
305 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
307 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
308 req.emr_in_buf = payload;
309 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
310 req.emr_out_buf = payload;
311 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
313 efx_mcdi_execute(enp, &req);
315 if (req.emr_rc != 0) {
320 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
325 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
330 if (mac_addrp != NULL) {
333 addrp = MCDI_OUT2(req, uint8_t,
334 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
336 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
346 EFSYS_PROBE1(fail1, efx_rc_t, rc);
351 __checkReturn efx_rc_t
352 efx_mcdi_get_mac_address_vf(
354 __out_ecount_opt(6) uint8_t mac_addrp[6])
357 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
358 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
361 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
363 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
364 req.emr_in_buf = payload;
365 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
366 req.emr_out_buf = payload;
367 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
369 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
370 EVB_PORT_ID_ASSIGNED);
372 efx_mcdi_execute(enp, &req);
374 if (req.emr_rc != 0) {
379 if (req.emr_out_length_used <
380 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
385 if (MCDI_OUT_DWORD(req,
386 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
391 if (mac_addrp != NULL) {
394 addrp = MCDI_OUT2(req, uint8_t,
395 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
397 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
407 EFSYS_PROBE1(fail1, efx_rc_t, rc);
412 __checkReturn efx_rc_t
415 __out uint32_t *sys_freqp,
416 __out uint32_t *dpcpu_freqp)
419 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CLOCK_IN_LEN,
420 MC_CMD_GET_CLOCK_OUT_LEN);
423 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
425 req.emr_cmd = MC_CMD_GET_CLOCK;
426 req.emr_in_buf = payload;
427 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
428 req.emr_out_buf = payload;
429 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
431 efx_mcdi_execute(enp, &req);
433 if (req.emr_rc != 0) {
438 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
443 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
444 if (*sys_freqp == 0) {
448 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
449 if (*dpcpu_freqp == 0) {
463 EFSYS_PROBE1(fail1, efx_rc_t, rc);
468 __checkReturn efx_rc_t
469 efx_mcdi_get_rxdp_config(
471 __out uint32_t *end_paddingp)
474 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_RXDP_CONFIG_IN_LEN,
475 MC_CMD_GET_RXDP_CONFIG_OUT_LEN);
476 uint32_t end_padding;
479 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
480 req.emr_in_buf = payload;
481 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
482 req.emr_out_buf = payload;
483 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
485 efx_mcdi_execute(enp, &req);
486 if (req.emr_rc != 0) {
491 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
492 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
493 /* RX DMA end padding is disabled */
496 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
497 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
498 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
501 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
504 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
513 *end_paddingp = end_padding;
520 EFSYS_PROBE1(fail1, efx_rc_t, rc);
525 __checkReturn efx_rc_t
526 efx_mcdi_get_vector_cfg(
528 __out_opt uint32_t *vec_basep,
529 __out_opt uint32_t *pf_nvecp,
530 __out_opt uint32_t *vf_nvecp)
533 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_VECTOR_CFG_IN_LEN,
534 MC_CMD_GET_VECTOR_CFG_OUT_LEN);
537 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
538 req.emr_in_buf = payload;
539 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
540 req.emr_out_buf = payload;
541 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
543 efx_mcdi_execute(enp, &req);
545 if (req.emr_rc != 0) {
550 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
555 if (vec_basep != NULL)
556 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
557 if (pf_nvecp != NULL)
558 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
559 if (vf_nvecp != NULL)
560 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
567 EFSYS_PROBE1(fail1, efx_rc_t, rc);
572 static __checkReturn efx_rc_t
575 __in uint32_t min_vi_count,
576 __in uint32_t max_vi_count,
577 __out uint32_t *vi_basep,
578 __out uint32_t *vi_countp,
579 __out uint32_t *vi_shiftp)
582 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_VIS_IN_LEN,
583 MC_CMD_ALLOC_VIS_EXT_OUT_LEN);
586 if (vi_countp == NULL) {
591 req.emr_cmd = MC_CMD_ALLOC_VIS;
592 req.emr_in_buf = payload;
593 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
594 req.emr_out_buf = payload;
595 req.emr_out_length = MC_CMD_ALLOC_VIS_EXT_OUT_LEN;
597 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
598 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
600 efx_mcdi_execute(enp, &req);
602 if (req.emr_rc != 0) {
607 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
612 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
613 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
615 /* Report VI_SHIFT if available (always zero for Huntington) */
616 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
619 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
628 EFSYS_PROBE1(fail1, efx_rc_t, rc);
634 static __checkReturn efx_rc_t
641 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
642 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
644 req.emr_cmd = MC_CMD_FREE_VIS;
645 req.emr_in_buf = NULL;
646 req.emr_in_length = 0;
647 req.emr_out_buf = NULL;
648 req.emr_out_length = 0;
650 efx_mcdi_execute_quiet(enp, &req);
652 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
653 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
661 EFSYS_PROBE1(fail1, efx_rc_t, rc);
667 static __checkReturn efx_rc_t
668 efx_mcdi_alloc_piobuf(
670 __out efx_piobuf_handle_t *handlep)
673 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_PIOBUF_IN_LEN,
674 MC_CMD_ALLOC_PIOBUF_OUT_LEN);
677 if (handlep == NULL) {
682 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
683 req.emr_in_buf = payload;
684 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
685 req.emr_out_buf = payload;
686 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
688 efx_mcdi_execute_quiet(enp, &req);
690 if (req.emr_rc != 0) {
695 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
700 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
709 EFSYS_PROBE1(fail1, efx_rc_t, rc);
714 static __checkReturn efx_rc_t
715 efx_mcdi_free_piobuf(
717 __in efx_piobuf_handle_t handle)
720 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FREE_PIOBUF_IN_LEN,
721 MC_CMD_FREE_PIOBUF_OUT_LEN);
724 req.emr_cmd = MC_CMD_FREE_PIOBUF;
725 req.emr_in_buf = payload;
726 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
727 req.emr_out_buf = payload;
728 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
730 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
732 efx_mcdi_execute_quiet(enp, &req);
734 if (req.emr_rc != 0) {
742 EFSYS_PROBE1(fail1, efx_rc_t, rc);
747 static __checkReturn efx_rc_t
748 efx_mcdi_link_piobuf(
750 __in uint32_t vi_index,
751 __in efx_piobuf_handle_t handle)
754 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_LINK_PIOBUF_IN_LEN,
755 MC_CMD_LINK_PIOBUF_OUT_LEN);
758 req.emr_cmd = MC_CMD_LINK_PIOBUF;
759 req.emr_in_buf = payload;
760 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
761 req.emr_out_buf = payload;
762 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
764 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
765 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
767 efx_mcdi_execute(enp, &req);
769 if (req.emr_rc != 0) {
777 EFSYS_PROBE1(fail1, efx_rc_t, rc);
782 static __checkReturn efx_rc_t
783 efx_mcdi_unlink_piobuf(
785 __in uint32_t vi_index)
788 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_UNLINK_PIOBUF_IN_LEN,
789 MC_CMD_UNLINK_PIOBUF_OUT_LEN);
792 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
793 req.emr_in_buf = payload;
794 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
795 req.emr_out_buf = payload;
796 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
798 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
800 efx_mcdi_execute_quiet(enp, &req);
802 if (req.emr_rc != 0) {
810 EFSYS_PROBE1(fail1, efx_rc_t, rc);
816 ef10_nic_alloc_piobufs(
818 __in uint32_t max_piobuf_count)
820 efx_piobuf_handle_t *handlep;
823 EFSYS_ASSERT3U(max_piobuf_count, <=,
824 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
826 enp->en_arch.ef10.ena_piobuf_count = 0;
828 for (i = 0; i < max_piobuf_count; i++) {
829 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
831 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0)
834 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
835 enp->en_arch.ef10.ena_piobuf_count++;
841 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
842 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
844 (void) efx_mcdi_free_piobuf(enp, *handlep);
845 *handlep = EFX_PIOBUF_HANDLE_INVALID;
847 enp->en_arch.ef10.ena_piobuf_count = 0;
852 ef10_nic_free_piobufs(
855 efx_piobuf_handle_t *handlep;
858 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
859 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
861 (void) efx_mcdi_free_piobuf(enp, *handlep);
862 *handlep = EFX_PIOBUF_HANDLE_INVALID;
864 enp->en_arch.ef10.ena_piobuf_count = 0;
867 /* Sub-allocate a block from a piobuf */
868 __checkReturn efx_rc_t
870 __inout efx_nic_t *enp,
871 __out uint32_t *bufnump,
872 __out efx_piobuf_handle_t *handlep,
873 __out uint32_t *blknump,
874 __out uint32_t *offsetp,
877 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
878 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
879 uint32_t blk_per_buf;
883 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
884 EFSYS_ASSERT(bufnump);
885 EFSYS_ASSERT(handlep);
886 EFSYS_ASSERT(blknump);
887 EFSYS_ASSERT(offsetp);
890 if ((edcp->edc_pio_alloc_size == 0) ||
891 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
895 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
897 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
898 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
903 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
904 for (blk = 0; blk < blk_per_buf; blk++) {
905 if ((*map & (1u << blk)) == 0) {
915 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
918 *sizep = edcp->edc_pio_alloc_size;
919 *offsetp = blk * (*sizep);
926 EFSYS_PROBE1(fail1, efx_rc_t, rc);
931 /* Free a piobuf sub-allocated block */
932 __checkReturn efx_rc_t
934 __inout efx_nic_t *enp,
935 __in uint32_t bufnum,
936 __in uint32_t blknum)
941 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
942 (blknum >= (8 * sizeof (*map)))) {
947 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
948 if ((*map & (1u << blknum)) == 0) {
952 *map &= ~(1u << blknum);
959 EFSYS_PROBE1(fail1, efx_rc_t, rc);
964 __checkReturn efx_rc_t
966 __inout efx_nic_t *enp,
967 __in uint32_t vi_index,
968 __in efx_piobuf_handle_t handle)
970 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
973 __checkReturn efx_rc_t
975 __inout efx_nic_t *enp,
976 __in uint32_t vi_index)
978 return (efx_mcdi_unlink_piobuf(enp, vi_index));
981 static __checkReturn efx_rc_t
982 ef10_mcdi_get_pf_count(
984 __out uint32_t *pf_countp)
987 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PF_COUNT_IN_LEN,
988 MC_CMD_GET_PF_COUNT_OUT_LEN);
991 req.emr_cmd = MC_CMD_GET_PF_COUNT;
992 req.emr_in_buf = payload;
993 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN;
994 req.emr_out_buf = payload;
995 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN;
997 efx_mcdi_execute(enp, &req);
999 if (req.emr_rc != 0) {
1004 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) {
1009 *pf_countp = *MCDI_OUT(req, uint8_t,
1010 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST);
1012 EFSYS_ASSERT(*pf_countp != 0);
1019 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1024 static __checkReturn efx_rc_t
1025 ef10_get_datapath_caps(
1026 __in efx_nic_t *enp)
1028 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1030 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CAPABILITIES_IN_LEN,
1031 MC_CMD_GET_CAPABILITIES_V5_OUT_LEN);
1034 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0)
1038 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
1039 req.emr_in_buf = payload;
1040 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
1041 req.emr_out_buf = payload;
1042 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V5_OUT_LEN;
1044 efx_mcdi_execute_quiet(enp, &req);
1046 if (req.emr_rc != 0) {
1051 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
1056 #define CAP_FLAGS1(_req, _flag) \
1057 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_OUT_FLAGS1) & \
1058 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN)))
1060 #define CAP_FLAGS2(_req, _flag) \
1061 (((_req).emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) && \
1062 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V2_OUT_FLAGS2) & \
1063 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN))))
1066 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
1067 * We only support the 14 byte prefix here.
1069 if (CAP_FLAGS1(req, RX_PREFIX_LEN_14) == 0) {
1073 encp->enc_rx_prefix_size = 14;
1075 #if EFSYS_OPT_RX_SCALE
1076 /* Check if the firmware supports additional RSS modes */
1077 if (CAP_FLAGS1(req, ADDITIONAL_RSS_MODES))
1078 encp->enc_rx_scale_additional_modes_supported = B_TRUE;
1080 encp->enc_rx_scale_additional_modes_supported = B_FALSE;
1081 #endif /* EFSYS_OPT_RX_SCALE */
1083 /* Check if the firmware supports TSO */
1084 if (CAP_FLAGS1(req, TX_TSO))
1085 encp->enc_fw_assisted_tso_enabled = B_TRUE;
1087 encp->enc_fw_assisted_tso_enabled = B_FALSE;
1089 /* Check if the firmware supports FATSOv2 */
1090 if (CAP_FLAGS2(req, TX_TSO_V2)) {
1091 encp->enc_fw_assisted_tso_v2_enabled = B_TRUE;
1092 encp->enc_fw_assisted_tso_v2_n_contexts = MCDI_OUT_WORD(req,
1093 GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS);
1095 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
1096 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
1099 /* Check if the firmware supports FATSOv2 encap */
1100 if (CAP_FLAGS2(req, TX_TSO_V2_ENCAP))
1101 encp->enc_fw_assisted_tso_v2_encap_enabled = B_TRUE;
1103 encp->enc_fw_assisted_tso_v2_encap_enabled = B_FALSE;
1105 /* Check if the firmware has vadapter/vport/vswitch support */
1106 if (CAP_FLAGS1(req, EVB))
1107 encp->enc_datapath_cap_evb = B_TRUE;
1109 encp->enc_datapath_cap_evb = B_FALSE;
1111 /* Check if the firmware supports vport reconfiguration */
1112 if (CAP_FLAGS1(req, VPORT_RECONFIGURE))
1113 encp->enc_vport_reconfigure_supported = B_TRUE;
1115 encp->enc_vport_reconfigure_supported = B_FALSE;
1117 /* Check if the firmware supports VLAN insertion */
1118 if (CAP_FLAGS1(req, TX_VLAN_INSERTION))
1119 encp->enc_hw_tx_insert_vlan_enabled = B_TRUE;
1121 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
1123 /* Check if the firmware supports RX event batching */
1124 if (CAP_FLAGS1(req, RX_BATCHING))
1125 encp->enc_rx_batching_enabled = B_TRUE;
1127 encp->enc_rx_batching_enabled = B_FALSE;
1130 * Even if batching isn't reported as supported, we may still get
1131 * batched events (see bug61153).
1133 encp->enc_rx_batch_max = 16;
1135 /* Check if the firmware supports disabling scatter on RXQs */
1136 if (CAP_FLAGS1(req, RX_DISABLE_SCATTER))
1137 encp->enc_rx_disable_scatter_supported = B_TRUE;
1139 encp->enc_rx_disable_scatter_supported = B_FALSE;
1141 /* Check if the firmware supports packed stream mode */
1142 if (CAP_FLAGS1(req, RX_PACKED_STREAM))
1143 encp->enc_rx_packed_stream_supported = B_TRUE;
1145 encp->enc_rx_packed_stream_supported = B_FALSE;
1148 * Check if the firmware supports configurable buffer sizes
1149 * for packed stream mode (otherwise buffer size is 1Mbyte)
1151 if (CAP_FLAGS1(req, RX_PACKED_STREAM_VAR_BUFFERS))
1152 encp->enc_rx_var_packed_stream_supported = B_TRUE;
1154 encp->enc_rx_var_packed_stream_supported = B_FALSE;
1156 /* Check if the firmware supports equal stride super-buffer mode */
1157 if (CAP_FLAGS2(req, EQUAL_STRIDE_SUPER_BUFFER))
1158 encp->enc_rx_es_super_buffer_supported = B_TRUE;
1160 encp->enc_rx_es_super_buffer_supported = B_FALSE;
1162 /* Check if the firmware supports FW subvariant w/o Tx checksumming */
1163 if (CAP_FLAGS2(req, FW_SUBVARIANT_NO_TX_CSUM))
1164 encp->enc_fw_subvariant_no_tx_csum_supported = B_TRUE;
1166 encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE;
1168 /* Check if the firmware supports set mac with running filters */
1169 if (CAP_FLAGS1(req, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED))
1170 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
1172 encp->enc_allow_set_mac_with_installed_filters = B_FALSE;
1175 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows
1176 * specifying which parameters to configure.
1178 if (CAP_FLAGS1(req, SET_MAC_ENHANCED))
1179 encp->enc_enhanced_set_mac_supported = B_TRUE;
1181 encp->enc_enhanced_set_mac_supported = B_FALSE;
1184 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows
1185 * us to let the firmware choose the settings to use on an EVQ.
1187 if (CAP_FLAGS2(req, INIT_EVQ_V2))
1188 encp->enc_init_evq_v2_supported = B_TRUE;
1190 encp->enc_init_evq_v2_supported = B_FALSE;
1193 * Check if the NO_CONT_EV mode for RX events is supported.
1195 if (CAP_FLAGS2(req, INIT_RXQ_NO_CONT_EV))
1196 encp->enc_no_cont_ev_mode_supported = B_TRUE;
1198 encp->enc_no_cont_ev_mode_supported = B_FALSE;
1201 * Check if buffer size may and must be specified on INIT_RXQ.
1202 * It may be always specified to efx_rx_qcreate(), but will be
1203 * just kept libefx internal if MCDI does not support it.
1205 if (CAP_FLAGS2(req, INIT_RXQ_WITH_BUFFER_SIZE))
1206 encp->enc_init_rxq_with_buffer_size = B_TRUE;
1208 encp->enc_init_rxq_with_buffer_size = B_FALSE;
1211 * Check if firmware-verified NVRAM updates must be used.
1213 * The firmware trusted installer requires all NVRAM updates to use
1214 * version 2 of MC_CMD_NVRAM_UPDATE_START (to enable verified update)
1215 * and version 2 of MC_CMD_NVRAM_UPDATE_FINISH (to verify the updated
1216 * partition and report the result).
1218 if (CAP_FLAGS2(req, NVRAM_UPDATE_REPORT_VERIFY_RESULT))
1219 encp->enc_nvram_update_verify_result_supported = B_TRUE;
1221 encp->enc_nvram_update_verify_result_supported = B_FALSE;
1223 if (CAP_FLAGS2(req, NVRAM_UPDATE_POLL_VERIFY_RESULT))
1224 encp->enc_nvram_update_poll_verify_result_supported = B_TRUE;
1226 encp->enc_nvram_update_poll_verify_result_supported = B_FALSE;
1229 * Check if firmware update via the BUNDLE partition is supported
1231 if (CAP_FLAGS2(req, BUNDLE_UPDATE))
1232 encp->enc_nvram_bundle_update_supported = B_TRUE;
1234 encp->enc_nvram_bundle_update_supported = B_FALSE;
1237 * Check if firmware provides packet memory and Rx datapath
1240 if (CAP_FLAGS1(req, PM_AND_RXDP_COUNTERS))
1241 encp->enc_pm_and_rxdp_counters = B_TRUE;
1243 encp->enc_pm_and_rxdp_counters = B_FALSE;
1246 * Check if the 40G MAC hardware is capable of reporting
1247 * statistics for Tx size bins.
1249 if (CAP_FLAGS2(req, MAC_STATS_40G_TX_SIZE_BINS))
1250 encp->enc_mac_stats_40g_tx_size_bins = B_TRUE;
1252 encp->enc_mac_stats_40g_tx_size_bins = B_FALSE;
1255 * Check if firmware supports VXLAN and NVGRE tunnels.
1256 * The capability indicates Geneve protocol support as well.
1258 if (CAP_FLAGS1(req, VXLAN_NVGRE)) {
1259 encp->enc_tunnel_encapsulations_supported =
1260 (1u << EFX_TUNNEL_PROTOCOL_VXLAN) |
1261 (1u << EFX_TUNNEL_PROTOCOL_GENEVE) |
1262 (1u << EFX_TUNNEL_PROTOCOL_NVGRE);
1264 EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES ==
1265 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
1266 encp->enc_tunnel_config_udp_entries_max =
1267 EFX_TUNNEL_MAXNENTRIES;
1269 encp->enc_tunnel_config_udp_entries_max = 0;
1273 * Check if firmware reports the VI window mode.
1274 * Medford2 has a variable VI window size (8K, 16K or 64K).
1275 * Medford and Huntington have a fixed 8K VI window size.
1277 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
1279 MCDI_OUT_BYTE(req, GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
1282 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
1283 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1285 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
1286 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_16K;
1288 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
1289 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_64K;
1292 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1295 } else if ((enp->en_family == EFX_FAMILY_HUNTINGTON) ||
1296 (enp->en_family == EFX_FAMILY_MEDFORD)) {
1297 /* Huntington and Medford have fixed 8K window size */
1298 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1300 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1303 /* Check if firmware supports extended MAC stats. */
1304 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
1305 /* Extended stats buffer supported */
1306 encp->enc_mac_stats_nstats = MCDI_OUT_WORD(req,
1307 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
1309 /* Use Siena-compatible legacy MAC stats */
1310 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS;
1313 if (encp->enc_mac_stats_nstats >= MC_CMD_MAC_NSTATS_V2)
1314 encp->enc_fec_counters = B_TRUE;
1316 encp->enc_fec_counters = B_FALSE;
1318 /* Check if the firmware provides head-of-line blocking counters */
1319 if (CAP_FLAGS2(req, RXDP_HLB_IDLE))
1320 encp->enc_hlb_counters = B_TRUE;
1322 encp->enc_hlb_counters = B_FALSE;
1324 #if EFSYS_OPT_RX_SCALE
1325 if (CAP_FLAGS1(req, RX_RSS_LIMITED)) {
1326 /* Only one exclusive RSS context is available per port. */
1327 encp->enc_rx_scale_max_exclusive_contexts = 1;
1329 switch (enp->en_family) {
1330 case EFX_FAMILY_MEDFORD2:
1331 encp->enc_rx_scale_hash_alg_mask =
1332 (1U << EFX_RX_HASHALG_TOEPLITZ);
1335 case EFX_FAMILY_MEDFORD:
1336 case EFX_FAMILY_HUNTINGTON:
1338 * Packed stream firmware variant maintains a
1339 * non-standard algorithm for hash computation.
1340 * It implies explicit XORing together
1341 * source + destination IP addresses (or last
1342 * four bytes in the case of IPv6) and using the
1343 * resulting value as the input to a Toeplitz hash.
1345 encp->enc_rx_scale_hash_alg_mask =
1346 (1U << EFX_RX_HASHALG_PACKED_STREAM);
1354 /* Port numbers cannot contribute to the hash value */
1355 encp->enc_rx_scale_l4_hash_supported = B_FALSE;
1358 * Maximum number of exclusive RSS contexts.
1359 * EF10 hardware supports 64 in total, but 6 are reserved
1360 * for shared contexts. They are a global resource so
1361 * not all may be available.
1363 encp->enc_rx_scale_max_exclusive_contexts = 64 - 6;
1365 encp->enc_rx_scale_hash_alg_mask =
1366 (1U << EFX_RX_HASHALG_TOEPLITZ);
1369 * It is possible to use port numbers as
1370 * the input data for hash computation.
1372 encp->enc_rx_scale_l4_hash_supported = B_TRUE;
1374 #endif /* EFSYS_OPT_RX_SCALE */
1376 /* Check if the firmware supports "FLAG" and "MARK" filter actions */
1377 if (CAP_FLAGS2(req, FILTER_ACTION_FLAG))
1378 encp->enc_filter_action_flag_supported = B_TRUE;
1380 encp->enc_filter_action_flag_supported = B_FALSE;
1382 if (CAP_FLAGS2(req, FILTER_ACTION_MARK))
1383 encp->enc_filter_action_mark_supported = B_TRUE;
1385 encp->enc_filter_action_mark_supported = B_FALSE;
1387 /* Get maximum supported value for "MARK" filter action */
1388 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V5_OUT_LEN)
1389 encp->enc_filter_action_mark_max = MCDI_OUT_DWORD(req,
1390 GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX);
1392 encp->enc_filter_action_mark_max = 0;
1399 #if EFSYS_OPT_RX_SCALE
1402 #endif /* EFSYS_OPT_RX_SCALE */
1410 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1416 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
1417 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
1418 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
1419 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
1420 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
1421 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
1422 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
1423 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
1424 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
1425 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
1426 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
1427 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
1429 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
1432 __checkReturn efx_rc_t
1433 ef10_get_privilege_mask(
1434 __in efx_nic_t *enp,
1435 __out uint32_t *maskp)
1437 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1441 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1446 /* Fallback for old firmware without privilege mask support */
1447 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1448 /* Assume PF has admin privilege */
1449 mask = EF10_LEGACY_PF_PRIVILEGE_MASK;
1451 /* VF is always unprivileged by default */
1452 mask = EF10_LEGACY_VF_PRIVILEGE_MASK;
1461 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1467 #define EFX_EXT_PORT_MAX 4
1468 #define EFX_EXT_PORT_NA 0xFF
1471 * Table of mapping schemes from port number to external number.
1473 * Each port number ultimately corresponds to a connector: either as part of
1474 * a cable assembly attached to a module inserted in an SFP+/QSFP+ cage on
1475 * the board, or fixed to the board (e.g. 10GBASE-T magjack on SFN5121T
1476 * "Salina"). In general:
1478 * Port number (0-based)
1480 * port mapping (n:1)
1483 * External port number (1-based)
1485 * fixed (1:1) or cable assembly (1:m)
1490 * The external numbering refers to the cages or magjacks on the board,
1491 * as visibly annotated on the board or back panel. This table describes
1492 * how to determine which external cage/magjack corresponds to the port
1493 * numbers used by the driver.
1495 * The count of consecutive port numbers that map to each external number,
1496 * is determined by the chip family and the current port mode.
1498 * For the Huntington family, the current port mode cannot be discovered,
1499 * but a single mapping is used by all modes for a given chip variant,
1500 * so the mapping used is instead the last match in the table to the full
1501 * set of port modes to which the NIC can be configured. Therefore the
1502 * ordering of entries in the mapping table is significant.
1504 static struct ef10_external_port_map_s {
1505 efx_family_t family;
1506 uint32_t modes_mask;
1507 uint8_t base_port[EFX_EXT_PORT_MAX];
1508 } __ef10_external_port_mappings[] = {
1510 * Modes used by Huntington family controllers where each port
1511 * number maps to a separate cage.
1512 * SFN7x22F (Torino):
1522 EFX_FAMILY_HUNTINGTON,
1523 (1U << TLV_PORT_MODE_10G) | /* mode 0 */
1524 (1U << TLV_PORT_MODE_10G_10G) | /* mode 2 */
1525 (1U << TLV_PORT_MODE_10G_10G_10G_10G), /* mode 4 */
1529 * Modes which for Huntington identify a chip variant where 2
1530 * adjacent port numbers map to each cage.
1538 EFX_FAMILY_HUNTINGTON,
1539 (1U << TLV_PORT_MODE_40G) | /* mode 1 */
1540 (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
1541 (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
1542 (1U << TLV_PORT_MODE_10G_10G_40G), /* mode 7 */
1543 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1546 * Modes that on Medford allocate each port number to a separate
1555 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1556 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1557 (1U << TLV_PORT_MODE_1x1_1x1), /* mode 2 */
1561 * Modes that on Medford allocate 2 adjacent port numbers to each
1570 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
1571 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 5 */
1572 (1U << TLV_PORT_MODE_1x4_2x1) | /* mode 6 */
1573 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
1574 /* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */
1575 (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */
1576 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1579 * Modes that on Medford allocate 4 adjacent port numbers to
1588 /* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */
1589 (1U << TLV_PORT_MODE_4x1_NA), /* mode 4 */
1590 { 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1593 * Modes that on Medford allocate 4 adjacent port numbers to
1602 (1U << TLV_PORT_MODE_NA_4x1), /* mode 8 */
1603 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1606 * Modes that on Medford2 allocate each port number to a separate
1614 EFX_FAMILY_MEDFORD2,
1615 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1616 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1617 (1U << TLV_PORT_MODE_1x1_1x1) | /* mode 2 */
1618 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
1619 (1U << TLV_PORT_MODE_1x2_NA) | /* mode 10 */
1620 (1U << TLV_PORT_MODE_1x2_1x2) | /* mode 12 */
1621 (1U << TLV_PORT_MODE_1x4_1x2) | /* mode 15 */
1622 (1U << TLV_PORT_MODE_1x2_1x4), /* mode 16 */
1626 * Modes that on Medford2 allocate 1 port to cage 1 and the rest
1633 EFX_FAMILY_MEDFORD2,
1634 (1U << TLV_PORT_MODE_1x2_2x1) | /* mode 17 */
1635 (1U << TLV_PORT_MODE_1x4_2x1), /* mode 6 */
1636 { 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1639 * Modes that on Medford2 allocate 2 adjacent port numbers to cage 1
1640 * and the rest to cage 2.
1647 EFX_FAMILY_MEDFORD2,
1648 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 4 */
1649 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
1650 (1U << TLV_PORT_MODE_2x2_NA) | /* mode 13 */
1651 (1U << TLV_PORT_MODE_2x1_1x2), /* mode 18 */
1652 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1655 * Modes that on Medford2 allocate up to 4 adjacent port numbers
1663 EFX_FAMILY_MEDFORD2,
1664 (1U << TLV_PORT_MODE_4x1_NA), /* mode 5 */
1665 { 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1668 * Modes that on Medford2 allocate up to 4 adjacent port numbers
1676 EFX_FAMILY_MEDFORD2,
1677 (1U << TLV_PORT_MODE_NA_4x1) | /* mode 8 */
1678 (1U << TLV_PORT_MODE_NA_1x2) | /* mode 11 */
1679 (1U << TLV_PORT_MODE_NA_2x2), /* mode 14 */
1680 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1684 static __checkReturn efx_rc_t
1685 ef10_external_port_mapping(
1686 __in efx_nic_t *enp,
1688 __out uint8_t *external_portp)
1692 uint32_t port_modes;
1695 struct ef10_external_port_map_s *mapp = NULL;
1696 int ext_index = port; /* Default 1-1 mapping */
1698 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t,
1701 * No current port mode information (i.e. Huntington)
1702 * - infer mapping from available modes
1704 if ((rc = efx_mcdi_get_port_modes(enp,
1705 &port_modes, NULL, NULL)) != 0) {
1707 * No port mode information available
1708 * - use default mapping
1713 /* Only need to scan the current mode */
1714 port_modes = 1 << current;
1718 * Infer the internal port -> external number mapping from
1719 * the possible port modes for this NIC.
1721 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1722 struct ef10_external_port_map_s *eepmp =
1723 &__ef10_external_port_mappings[i];
1724 if (eepmp->family != enp->en_family)
1726 matches = (eepmp->modes_mask & port_modes);
1729 * Some modes match. For some Huntington boards
1730 * there will be multiple matches. The mapping on the
1731 * last match is used.
1734 port_modes &= ~matches;
1738 if (port_modes != 0) {
1739 /* Some advertised modes are not supported */
1747 * External ports are assigned a sequence of consecutive
1748 * port numbers, so find the one with the closest base_port.
1750 uint32_t delta = EFX_EXT_PORT_NA;
1752 for (i = 0; i < EFX_EXT_PORT_MAX; i++) {
1753 uint32_t base = mapp->base_port[i];
1754 if ((base != EFX_EXT_PORT_NA) && (base <= port)) {
1755 if ((port - base) < delta) {
1756 delta = (port - base);
1762 *external_portp = (uint8_t)(ext_index + 1);
1767 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1772 static __checkReturn efx_rc_t
1773 ef10_set_workaround_bug26807(
1774 __in efx_nic_t *enp)
1776 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1781 * If the bug26807 workaround is enabled, then firmware has enabled
1782 * support for chained multicast filters. Firmware will reset (FLR)
1783 * functions which have filters in the hardware filter table when the
1784 * workaround is enabled/disabled.
1786 * We must recheck if the workaround is enabled after inserting the
1787 * first hardware filter, in case it has been changed since this check.
1789 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
1792 encp->enc_bug26807_workaround = B_TRUE;
1793 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
1795 * Other functions had installed filters before the
1796 * workaround was enabled, and they have been reset
1799 EFSYS_PROBE(bug26807_workaround_flr_done);
1800 /* FIXME: bump MC warm boot count ? */
1802 } else if (rc == EACCES) {
1804 * Unprivileged functions cannot enable the workaround in older
1807 encp->enc_bug26807_workaround = B_FALSE;
1808 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
1809 encp->enc_bug26807_workaround = B_FALSE;
1817 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1822 static __checkReturn efx_rc_t
1824 __in efx_nic_t *enp)
1826 const efx_nic_ops_t *enop = enp->en_enop;
1827 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
1828 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1829 ef10_link_state_t els;
1830 efx_port_t *epp = &(enp->en_port);
1831 uint32_t board_type = 0;
1832 uint32_t base, nvec;
1837 uint8_t mac_addr[6] = { 0 };
1840 /* Get the (zero-based) MCDI port number */
1841 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
1844 /* EFX MCDI interface uses one-based port numbers */
1845 emip->emi_port = port + 1;
1847 encp->enc_assigned_port = port;
1849 if ((rc = ef10_external_port_mapping(enp, port,
1850 &encp->enc_external_port)) != 0)
1854 * Get PCIe function number from firmware (used for
1855 * per-function privilege and dynamic config info).
1856 * - PCIe PF: pf = PF number, vf = 0xffff.
1857 * - PCIe VF: pf = parent PF, vf = VF number.
1859 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
1865 /* MAC address for this function */
1866 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1867 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
1868 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
1870 * Disable static config checking, ONLY for manufacturing test
1871 * and setup at the factory, to allow the static config to be
1874 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1875 if ((rc == 0) && (mac_addr[0] & 0x02)) {
1877 * If the static config does not include a global MAC
1878 * address pool then the board may return a locally
1879 * administered MAC address (this should only happen on
1880 * incorrectly programmed boards).
1884 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1886 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
1891 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
1893 /* Board configuration (legacy) */
1894 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
1896 /* Unprivileged functions may not be able to read board cfg */
1903 encp->enc_board_type = board_type;
1904 encp->enc_clk_mult = 1; /* not used for EF10 */
1906 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
1907 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
1911 * Firmware with support for *_FEC capability bits does not
1912 * report that the corresponding *_FEC_REQUESTED bits are supported.
1913 * Add them here so that drivers understand that they are supported.
1915 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_BASER_FEC))
1916 epp->ep_phy_cap_mask |=
1917 (1u << EFX_PHY_CAP_BASER_FEC_REQUESTED);
1918 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_RS_FEC))
1919 epp->ep_phy_cap_mask |=
1920 (1u << EFX_PHY_CAP_RS_FEC_REQUESTED);
1921 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_25G_BASER_FEC))
1922 epp->ep_phy_cap_mask |=
1923 (1u << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED);
1925 /* Obtain the default PHY advertised capabilities */
1926 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
1928 epp->ep_default_adv_cap_mask = els.epls.epls_adv_cap_mask;
1929 epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask;
1931 /* Check capabilities of running datapath firmware */
1932 if ((rc = ef10_get_datapath_caps(enp)) != 0)
1935 /* Alignment for WPTR updates */
1936 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
1938 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
1939 /* No boundary crossing limits */
1940 encp->enc_tx_dma_desc_boundary = 0;
1943 * Maximum number of bytes into the frame the TCP header can start for
1944 * firmware assisted TSO to work.
1946 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
1949 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
1950 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
1951 * resources (allocated to this PCIe function), which is zero until
1952 * after we have allocated VIs.
1954 encp->enc_evq_limit = 1024;
1955 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
1956 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
1958 encp->enc_buftbl_limit = UINT32_MAX;
1960 /* Get interrupt vector limits */
1961 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
1962 if (EFX_PCI_FUNCTION_IS_PF(encp))
1965 /* Ignore error (cannot query vector limits from a VF). */
1969 encp->enc_intr_vec_base = base;
1970 encp->enc_intr_limit = nvec;
1973 * Get the current privilege mask. Note that this may be modified
1974 * dynamically, so this value is informational only. DO NOT use
1975 * the privilege mask to check for sufficient privileges, as that
1976 * can result in time-of-check/time-of-use bugs.
1978 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
1980 encp->enc_privilege_mask = mask;
1982 if ((rc = ef10_set_workaround_bug26807(enp)) != 0)
1985 /* Get remaining controller-specific board config */
1986 if ((rc = enop->eno_board_cfg(enp)) != 0)
1993 EFSYS_PROBE(fail12);
1995 EFSYS_PROBE(fail11);
1997 EFSYS_PROBE(fail10);
2015 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2020 __checkReturn efx_rc_t
2022 __in efx_nic_t *enp)
2024 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
2025 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2028 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
2030 /* Read and clear any assertion state */
2031 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
2034 /* Exit the assertion handler */
2035 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
2039 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
2042 if ((rc = ef10_nic_board_cfg(enp)) != 0)
2046 * Set default driver config limits (based on board config).
2048 * FIXME: For now allocate a fixed number of VIs which is likely to be
2049 * sufficient and small enough to allow multiple functions on the same
2052 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
2053 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
2055 /* The client driver must configure and enable PIO buffer support */
2056 edcp->edc_max_piobuf_count = 0;
2057 edcp->edc_pio_alloc_size = 0;
2059 #if EFSYS_OPT_MAC_STATS
2060 /* Wipe the MAC statistics */
2061 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
2065 #if EFSYS_OPT_LOOPBACK
2066 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
2070 #if EFSYS_OPT_MON_STATS
2071 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
2072 /* Unprivileged functions do not have access to sensors */
2078 encp->enc_features = enp->en_features;
2082 #if EFSYS_OPT_MON_STATS
2086 #if EFSYS_OPT_LOOPBACK
2090 #if EFSYS_OPT_MAC_STATS
2101 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2106 __checkReturn efx_rc_t
2107 ef10_nic_set_drv_limits(
2108 __inout efx_nic_t *enp,
2109 __in efx_drv_limits_t *edlp)
2111 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
2112 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2113 uint32_t min_evq_count, max_evq_count;
2114 uint32_t min_rxq_count, max_rxq_count;
2115 uint32_t min_txq_count, max_txq_count;
2123 /* Get minimum required and maximum usable VI limits */
2124 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
2125 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
2126 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
2128 edcp->edc_min_vi_count =
2129 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
2131 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
2132 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
2133 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
2135 edcp->edc_max_vi_count =
2136 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
2139 * Check limits for sub-allocated piobuf blocks.
2140 * PIO is optional, so don't fail if the limits are incorrect.
2142 if ((encp->enc_piobuf_size == 0) ||
2143 (encp->enc_piobuf_limit == 0) ||
2144 (edlp->edl_min_pio_alloc_size == 0) ||
2145 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
2147 edcp->edc_max_piobuf_count = 0;
2148 edcp->edc_pio_alloc_size = 0;
2150 uint32_t blk_size, blk_count, blks_per_piobuf;
2153 MAX(edlp->edl_min_pio_alloc_size,
2154 encp->enc_piobuf_min_alloc_size);
2156 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
2157 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
2159 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
2161 /* A zero max pio alloc count means unlimited */
2162 if ((edlp->edl_max_pio_alloc_count > 0) &&
2163 (edlp->edl_max_pio_alloc_count < blk_count)) {
2164 blk_count = edlp->edl_max_pio_alloc_count;
2167 edcp->edc_pio_alloc_size = blk_size;
2168 edcp->edc_max_piobuf_count =
2169 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
2175 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2181 __checkReturn efx_rc_t
2183 __in efx_nic_t *enp)
2186 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ENTITY_RESET_IN_LEN,
2187 MC_CMD_ENTITY_RESET_OUT_LEN);
2190 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
2191 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
2193 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
2196 req.emr_cmd = MC_CMD_ENTITY_RESET;
2197 req.emr_in_buf = payload;
2198 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
2199 req.emr_out_buf = payload;
2200 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
2202 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
2203 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
2205 efx_mcdi_execute(enp, &req);
2207 if (req.emr_rc != 0) {
2212 /* Clear RX/TX DMA queue errors */
2213 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
2222 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2227 static __checkReturn efx_rc_t
2228 ef10_upstream_port_vadaptor_alloc(
2229 __in efx_nic_t *enp)
2236 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
2237 * driver has yet to bring up the EVB port. See bug 56147. In this case,
2238 * retry the request several times after waiting a while. The wait time
2239 * between retries starts small (10ms) and exponentially increases.
2240 * Total wait time is a little over two seconds. Retry logic in the
2241 * client driver may mean this whole loop is repeated if it continues to
2246 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
2247 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
2250 * Do not retry alloc for PF, or for other errors on
2256 /* VF startup before PF is ready. Retry allocation. */
2258 /* Too many attempts */
2262 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
2263 EFSYS_SLEEP(delay_us);
2265 if (delay_us < 500000)
2274 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2279 __checkReturn efx_rc_t
2281 __in efx_nic_t *enp)
2283 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2284 uint32_t min_vi_count, max_vi_count;
2285 uint32_t vi_count, vi_base, vi_shift;
2287 uint32_t vi_window_size;
2289 boolean_t alloc_vadaptor = B_TRUE;
2291 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2292 enp->en_family == EFX_FAMILY_MEDFORD ||
2293 enp->en_family == EFX_FAMILY_MEDFORD2);
2295 /* Enable reporting of some events (e.g. link change) */
2296 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
2299 /* Allocate (optional) on-chip PIO buffers */
2300 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
2303 * For best performance, PIO writes should use a write-combined
2304 * (WC) memory mapping. Using a separate WC mapping for the PIO
2305 * aperture of each VI would be a burden to drivers (and not
2306 * possible if the host page size is >4Kbyte).
2308 * To avoid this we use a single uncached (UC) mapping for VI
2309 * register access, and a single WC mapping for extra VIs used
2312 * Each piobuf must be linked to a VI in the WC mapping, and to
2313 * each VI that is using a sub-allocated block from the piobuf.
2315 min_vi_count = edcp->edc_min_vi_count;
2317 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
2319 /* Ensure that the previously attached driver's VIs are freed */
2320 if ((rc = efx_mcdi_free_vis(enp)) != 0)
2324 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
2325 * fails then retrying the request for fewer VI resources may succeed.
2328 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
2329 &vi_base, &vi_count, &vi_shift)) != 0)
2332 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
2334 if (vi_count < min_vi_count) {
2339 enp->en_arch.ef10.ena_vi_base = vi_base;
2340 enp->en_arch.ef10.ena_vi_count = vi_count;
2341 enp->en_arch.ef10.ena_vi_shift = vi_shift;
2343 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
2344 /* Not enough extra VIs to map piobufs */
2345 ef10_nic_free_piobufs(enp);
2348 enp->en_arch.ef10.ena_pio_write_vi_base =
2349 vi_count - enp->en_arch.ef10.ena_piobuf_count;
2351 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, !=,
2352 EFX_VI_WINDOW_SHIFT_INVALID);
2353 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, <=,
2354 EFX_VI_WINDOW_SHIFT_64K);
2355 vi_window_size = 1U << enp->en_nic_cfg.enc_vi_window_shift;
2357 /* Save UC memory mapping details */
2358 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
2359 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2360 enp->en_arch.ef10.ena_uc_mem_map_size =
2362 enp->en_arch.ef10.ena_pio_write_vi_base);
2364 enp->en_arch.ef10.ena_uc_mem_map_size =
2366 enp->en_arch.ef10.ena_vi_count);
2369 /* Save WC memory mapping details */
2370 enp->en_arch.ef10.ena_wc_mem_map_offset =
2371 enp->en_arch.ef10.ena_uc_mem_map_offset +
2372 enp->en_arch.ef10.ena_uc_mem_map_size;
2374 enp->en_arch.ef10.ena_wc_mem_map_size =
2376 enp->en_arch.ef10.ena_piobuf_count);
2378 /* Link piobufs to extra VIs in WC mapping */
2379 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2380 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2381 rc = efx_mcdi_link_piobuf(enp,
2382 enp->en_arch.ef10.ena_pio_write_vi_base + i,
2383 enp->en_arch.ef10.ena_piobuf_handle[i]);
2390 * For SR-IOV use case, vAdaptor is allocated for PF and associated VFs
2391 * during NIC initialization when vSwitch is created and vports are
2392 * allocated. Hence, skip vAdaptor allocation for EVB and update vport
2393 * id in NIC structure with the one allocated for PF.
2396 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
2398 if ((enp->en_vswitchp != NULL) && (enp->en_vswitchp->ev_evcp != NULL)) {
2399 /* For EVB use vport allocated on vswitch */
2400 enp->en_vport_id = enp->en_vswitchp->ev_evcp->evc_vport_id;
2401 alloc_vadaptor = B_FALSE;
2404 if (alloc_vadaptor != B_FALSE) {
2405 /* Allocate a vAdaptor attached to our upstream vPort/pPort */
2406 if ((rc = ef10_upstream_port_vadaptor_alloc(enp)) != 0)
2409 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
2422 ef10_nic_free_piobufs(enp);
2425 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2430 __checkReturn efx_rc_t
2431 ef10_nic_get_vi_pool(
2432 __in efx_nic_t *enp,
2433 __out uint32_t *vi_countp)
2435 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
2438 * Report VIs that the client driver can use.
2439 * Do not include VIs used for PIO buffer writes.
2441 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
2446 __checkReturn efx_rc_t
2447 ef10_nic_get_bar_region(
2448 __in efx_nic_t *enp,
2449 __in efx_nic_region_t region,
2450 __out uint32_t *offsetp,
2451 __out size_t *sizep)
2455 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
2458 * TODO: Specify host memory mapping alignment and granularity
2459 * in efx_drv_limits_t so that they can be taken into account
2460 * when allocating extra VIs for PIO writes.
2464 /* UC mapped memory BAR region for VI registers */
2465 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
2466 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
2469 case EFX_REGION_PIO_WRITE_VI:
2470 /* WC mapped memory BAR region for piobuf writes */
2471 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
2472 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
2483 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2488 __checkReturn boolean_t
2489 ef10_nic_hw_unavailable(
2490 __in efx_nic_t *enp)
2494 if (enp->en_reset_flags & EFX_RESET_HW_UNAVAIL)
2497 EFX_BAR_READD(enp, ER_DZ_BIU_MC_SFT_STATUS_REG, &dword, B_FALSE);
2498 if (EFX_DWORD_FIELD(dword, EFX_DWORD_0) == 0xffffffff)
2504 ef10_nic_set_hw_unavailable(enp);
2510 ef10_nic_set_hw_unavailable(
2511 __in efx_nic_t *enp)
2513 EFSYS_PROBE(hw_unavail);
2514 enp->en_reset_flags |= EFX_RESET_HW_UNAVAIL;
2520 __in efx_nic_t *enp)
2524 boolean_t do_vadaptor_free = B_TRUE;
2527 if (enp->en_vswitchp != NULL) {
2529 * For SR-IOV the vAdaptor is freed with the vswitch,
2530 * so do not free it here.
2532 do_vadaptor_free = B_FALSE;
2535 if (do_vadaptor_free != B_FALSE) {
2536 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
2537 enp->en_vport_id = EVB_PORT_ID_NULL;
2540 /* Unlink piobufs from extra VIs in WC mapping */
2541 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2542 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2543 rc = efx_mcdi_unlink_piobuf(enp,
2544 enp->en_arch.ef10.ena_pio_write_vi_base + i);
2550 ef10_nic_free_piobufs(enp);
2552 (void) efx_mcdi_free_vis(enp);
2553 enp->en_arch.ef10.ena_vi_count = 0;
2558 __in efx_nic_t *enp)
2560 #if EFSYS_OPT_MON_STATS
2561 mcdi_mon_cfg_free(enp);
2562 #endif /* EFSYS_OPT_MON_STATS */
2563 (void) efx_mcdi_drv_attach(enp, B_FALSE);
2568 __checkReturn efx_rc_t
2569 ef10_nic_register_test(
2570 __in efx_nic_t *enp)
2575 _NOTE(ARGUNUSED(enp))
2576 _NOTE(CONSTANTCONDITION)
2586 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2591 #endif /* EFSYS_OPT_DIAG */
2593 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
2595 __checkReturn efx_rc_t
2596 efx_mcdi_get_nic_global(
2597 __in efx_nic_t *enp,
2599 __out uint32_t *valuep)
2602 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_NIC_GLOBAL_IN_LEN,
2603 MC_CMD_GET_NIC_GLOBAL_OUT_LEN);
2606 req.emr_cmd = MC_CMD_GET_NIC_GLOBAL;
2607 req.emr_in_buf = payload;
2608 req.emr_in_length = MC_CMD_GET_NIC_GLOBAL_IN_LEN;
2609 req.emr_out_buf = payload;
2610 req.emr_out_length = MC_CMD_GET_NIC_GLOBAL_OUT_LEN;
2612 MCDI_IN_SET_DWORD(req, GET_NIC_GLOBAL_IN_KEY, key);
2614 efx_mcdi_execute(enp, &req);
2616 if (req.emr_rc != 0) {
2621 if (req.emr_out_length_used != MC_CMD_GET_NIC_GLOBAL_OUT_LEN) {
2626 *valuep = MCDI_OUT_DWORD(req, GET_NIC_GLOBAL_OUT_VALUE);
2633 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2638 __checkReturn efx_rc_t
2639 efx_mcdi_set_nic_global(
2640 __in efx_nic_t *enp,
2642 __in uint32_t value)
2645 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_NIC_GLOBAL_IN_LEN, 0);
2648 req.emr_cmd = MC_CMD_SET_NIC_GLOBAL;
2649 req.emr_in_buf = payload;
2650 req.emr_in_length = MC_CMD_SET_NIC_GLOBAL_IN_LEN;
2651 req.emr_out_buf = NULL;
2652 req.emr_out_length = 0;
2654 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_KEY, key);
2655 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_VALUE, value);
2657 efx_mcdi_execute(enp, &req);
2659 if (req.emr_rc != 0) {
2667 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2672 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
2674 #endif /* EFX_OPTS_EF10() */