1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
13 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
15 #include "ef10_tlv_layout.h"
17 __checkReturn efx_rc_t
18 efx_mcdi_get_port_assignment(
20 __out uint32_t *portp)
23 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
24 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN);
27 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
28 enp->en_family == EFX_FAMILY_MEDFORD ||
29 enp->en_family == EFX_FAMILY_MEDFORD2);
31 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
32 req.emr_in_buf = payload;
33 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
34 req.emr_out_buf = payload;
35 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
37 efx_mcdi_execute(enp, &req);
39 if (req.emr_rc != 0) {
44 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
49 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
56 EFSYS_PROBE1(fail1, efx_rc_t, rc);
61 __checkReturn efx_rc_t
62 efx_mcdi_get_port_modes(
64 __out uint32_t *modesp,
65 __out_opt uint32_t *current_modep,
66 __out_opt uint32_t *default_modep)
69 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_MODES_IN_LEN,
70 MC_CMD_GET_PORT_MODES_OUT_LEN);
73 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
74 enp->en_family == EFX_FAMILY_MEDFORD ||
75 enp->en_family == EFX_FAMILY_MEDFORD2);
77 req.emr_cmd = MC_CMD_GET_PORT_MODES;
78 req.emr_in_buf = payload;
79 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
80 req.emr_out_buf = payload;
81 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
83 efx_mcdi_execute(enp, &req);
85 if (req.emr_rc != 0) {
91 * Require only Modes and DefaultMode fields, unless the current mode
92 * was requested (CurrentMode field was added for Medford).
94 if (req.emr_out_length_used <
95 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
99 if ((current_modep != NULL) && (req.emr_out_length_used <
100 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) {
105 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
107 if (current_modep != NULL) {
108 *current_modep = MCDI_OUT_DWORD(req,
109 GET_PORT_MODES_OUT_CURRENT_MODE);
112 if (default_modep != NULL) {
113 *default_modep = MCDI_OUT_DWORD(req,
114 GET_PORT_MODES_OUT_DEFAULT_MODE);
124 EFSYS_PROBE1(fail1, efx_rc_t, rc);
129 __checkReturn efx_rc_t
130 ef10_nic_get_port_mode_bandwidth(
132 __out uint32_t *bandwidth_mbpsp)
135 uint32_t current_mode;
136 efx_port_t *epp = &(enp->en_port);
138 uint32_t single_lane;
144 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
145 ¤t_mode, NULL)) != 0) {
146 /* No port mode info available. */
150 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_25000FDX))
155 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_50000FDX))
160 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_100000FDX))
165 switch (current_mode) {
166 case TLV_PORT_MODE_1x1_NA: /* mode 0 */
167 bandwidth = single_lane;
169 case TLV_PORT_MODE_1x2_NA: /* mode 10 */
170 case TLV_PORT_MODE_NA_1x2: /* mode 11 */
171 bandwidth = dual_lane;
173 case TLV_PORT_MODE_1x1_1x1: /* mode 2 */
174 bandwidth = single_lane + single_lane;
176 case TLV_PORT_MODE_4x1_NA: /* mode 4 */
177 case TLV_PORT_MODE_NA_4x1: /* mode 8 */
178 bandwidth = 4 * single_lane;
180 case TLV_PORT_MODE_2x1_2x1: /* mode 5 */
181 bandwidth = (2 * single_lane) + (2 * single_lane);
183 case TLV_PORT_MODE_1x2_1x2: /* mode 12 */
184 bandwidth = dual_lane + dual_lane;
186 case TLV_PORT_MODE_1x2_2x1: /* mode 17 */
187 case TLV_PORT_MODE_2x1_1x2: /* mode 18 */
188 bandwidth = dual_lane + (2 * single_lane);
190 /* Legacy Medford-only mode. Do not use (see bug63270) */
191 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2: /* mode 9 */
192 bandwidth = 4 * single_lane;
194 case TLV_PORT_MODE_1x4_NA: /* mode 1 */
195 case TLV_PORT_MODE_NA_1x4: /* mode 22 */
196 bandwidth = quad_lane;
198 case TLV_PORT_MODE_2x2_NA: /* mode 13 */
199 case TLV_PORT_MODE_NA_2x2: /* mode 14 */
200 bandwidth = 2 * dual_lane;
202 case TLV_PORT_MODE_1x4_2x1: /* mode 6 */
203 case TLV_PORT_MODE_2x1_1x4: /* mode 7 */
204 bandwidth = quad_lane + (2 * single_lane);
206 case TLV_PORT_MODE_1x4_1x2: /* mode 15 */
207 case TLV_PORT_MODE_1x2_1x4: /* mode 16 */
208 bandwidth = quad_lane + dual_lane;
210 case TLV_PORT_MODE_1x4_1x4: /* mode 3 */
211 bandwidth = quad_lane + quad_lane;
218 *bandwidth_mbpsp = bandwidth;
225 EFSYS_PROBE1(fail1, efx_rc_t, rc);
230 static __checkReturn efx_rc_t
231 efx_mcdi_vadaptor_alloc(
233 __in uint32_t port_id)
236 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_ALLOC_IN_LEN,
237 MC_CMD_VADAPTOR_ALLOC_OUT_LEN);
240 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
242 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
243 req.emr_in_buf = payload;
244 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
245 req.emr_out_buf = payload;
246 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
248 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
249 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
250 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
251 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
253 efx_mcdi_execute(enp, &req);
255 if (req.emr_rc != 0) {
263 EFSYS_PROBE1(fail1, efx_rc_t, rc);
268 static __checkReturn efx_rc_t
269 efx_mcdi_vadaptor_free(
271 __in uint32_t port_id)
274 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_FREE_IN_LEN,
275 MC_CMD_VADAPTOR_FREE_OUT_LEN);
278 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
279 req.emr_in_buf = payload;
280 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
281 req.emr_out_buf = payload;
282 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
284 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
286 efx_mcdi_execute(enp, &req);
288 if (req.emr_rc != 0) {
296 EFSYS_PROBE1(fail1, efx_rc_t, rc);
301 __checkReturn efx_rc_t
302 efx_mcdi_get_mac_address_pf(
304 __out_ecount_opt(6) uint8_t mac_addrp[6])
307 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
308 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
311 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
312 enp->en_family == EFX_FAMILY_MEDFORD ||
313 enp->en_family == EFX_FAMILY_MEDFORD2);
315 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
316 req.emr_in_buf = payload;
317 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
318 req.emr_out_buf = payload;
319 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
321 efx_mcdi_execute(enp, &req);
323 if (req.emr_rc != 0) {
328 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
333 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
338 if (mac_addrp != NULL) {
341 addrp = MCDI_OUT2(req, uint8_t,
342 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
344 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
354 EFSYS_PROBE1(fail1, efx_rc_t, rc);
359 __checkReturn efx_rc_t
360 efx_mcdi_get_mac_address_vf(
362 __out_ecount_opt(6) uint8_t mac_addrp[6])
365 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
366 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
369 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
370 enp->en_family == EFX_FAMILY_MEDFORD ||
371 enp->en_family == EFX_FAMILY_MEDFORD2);
373 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
374 req.emr_in_buf = payload;
375 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
376 req.emr_out_buf = payload;
377 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
379 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
380 EVB_PORT_ID_ASSIGNED);
382 efx_mcdi_execute(enp, &req);
384 if (req.emr_rc != 0) {
389 if (req.emr_out_length_used <
390 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
395 if (MCDI_OUT_DWORD(req,
396 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
401 if (mac_addrp != NULL) {
404 addrp = MCDI_OUT2(req, uint8_t,
405 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
407 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
417 EFSYS_PROBE1(fail1, efx_rc_t, rc);
422 __checkReturn efx_rc_t
425 __out uint32_t *sys_freqp,
426 __out uint32_t *dpcpu_freqp)
429 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CLOCK_IN_LEN,
430 MC_CMD_GET_CLOCK_OUT_LEN);
433 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
434 enp->en_family == EFX_FAMILY_MEDFORD ||
435 enp->en_family == EFX_FAMILY_MEDFORD2);
437 req.emr_cmd = MC_CMD_GET_CLOCK;
438 req.emr_in_buf = payload;
439 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
440 req.emr_out_buf = payload;
441 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
443 efx_mcdi_execute(enp, &req);
445 if (req.emr_rc != 0) {
450 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
455 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
456 if (*sys_freqp == 0) {
460 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
461 if (*dpcpu_freqp == 0) {
475 EFSYS_PROBE1(fail1, efx_rc_t, rc);
480 __checkReturn efx_rc_t
481 efx_mcdi_get_rxdp_config(
483 __out uint32_t *end_paddingp)
486 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_RXDP_CONFIG_IN_LEN,
487 MC_CMD_GET_RXDP_CONFIG_OUT_LEN);
488 uint32_t end_padding;
491 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
492 req.emr_in_buf = payload;
493 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
494 req.emr_out_buf = payload;
495 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
497 efx_mcdi_execute(enp, &req);
498 if (req.emr_rc != 0) {
503 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
504 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
505 /* RX DMA end padding is disabled */
508 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
509 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
510 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
513 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
516 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
525 *end_paddingp = end_padding;
532 EFSYS_PROBE1(fail1, efx_rc_t, rc);
537 __checkReturn efx_rc_t
538 efx_mcdi_get_vector_cfg(
540 __out_opt uint32_t *vec_basep,
541 __out_opt uint32_t *pf_nvecp,
542 __out_opt uint32_t *vf_nvecp)
545 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_VECTOR_CFG_IN_LEN,
546 MC_CMD_GET_VECTOR_CFG_OUT_LEN);
549 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
550 req.emr_in_buf = payload;
551 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
552 req.emr_out_buf = payload;
553 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
555 efx_mcdi_execute(enp, &req);
557 if (req.emr_rc != 0) {
562 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
567 if (vec_basep != NULL)
568 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
569 if (pf_nvecp != NULL)
570 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
571 if (vf_nvecp != NULL)
572 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
579 EFSYS_PROBE1(fail1, efx_rc_t, rc);
584 static __checkReturn efx_rc_t
587 __in uint32_t min_vi_count,
588 __in uint32_t max_vi_count,
589 __out uint32_t *vi_basep,
590 __out uint32_t *vi_countp,
591 __out uint32_t *vi_shiftp)
594 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_VIS_IN_LEN,
595 MC_CMD_ALLOC_VIS_EXT_OUT_LEN);
598 if (vi_countp == NULL) {
603 req.emr_cmd = MC_CMD_ALLOC_VIS;
604 req.emr_in_buf = payload;
605 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
606 req.emr_out_buf = payload;
607 req.emr_out_length = MC_CMD_ALLOC_VIS_EXT_OUT_LEN;
609 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
610 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
612 efx_mcdi_execute(enp, &req);
614 if (req.emr_rc != 0) {
619 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
624 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
625 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
627 /* Report VI_SHIFT if available (always zero for Huntington) */
628 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
631 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
640 EFSYS_PROBE1(fail1, efx_rc_t, rc);
646 static __checkReturn efx_rc_t
653 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
654 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
656 req.emr_cmd = MC_CMD_FREE_VIS;
657 req.emr_in_buf = NULL;
658 req.emr_in_length = 0;
659 req.emr_out_buf = NULL;
660 req.emr_out_length = 0;
662 efx_mcdi_execute_quiet(enp, &req);
664 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
665 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
673 EFSYS_PROBE1(fail1, efx_rc_t, rc);
679 static __checkReturn efx_rc_t
680 efx_mcdi_alloc_piobuf(
682 __out efx_piobuf_handle_t *handlep)
685 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_PIOBUF_IN_LEN,
686 MC_CMD_ALLOC_PIOBUF_OUT_LEN);
689 if (handlep == NULL) {
694 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
695 req.emr_in_buf = payload;
696 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
697 req.emr_out_buf = payload;
698 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
700 efx_mcdi_execute_quiet(enp, &req);
702 if (req.emr_rc != 0) {
707 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
712 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
721 EFSYS_PROBE1(fail1, efx_rc_t, rc);
726 static __checkReturn efx_rc_t
727 efx_mcdi_free_piobuf(
729 __in efx_piobuf_handle_t handle)
732 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FREE_PIOBUF_IN_LEN,
733 MC_CMD_FREE_PIOBUF_OUT_LEN);
736 req.emr_cmd = MC_CMD_FREE_PIOBUF;
737 req.emr_in_buf = payload;
738 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
739 req.emr_out_buf = payload;
740 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
742 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
744 efx_mcdi_execute_quiet(enp, &req);
746 if (req.emr_rc != 0) {
754 EFSYS_PROBE1(fail1, efx_rc_t, rc);
759 static __checkReturn efx_rc_t
760 efx_mcdi_link_piobuf(
762 __in uint32_t vi_index,
763 __in efx_piobuf_handle_t handle)
766 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_LINK_PIOBUF_IN_LEN,
767 MC_CMD_LINK_PIOBUF_OUT_LEN);
770 req.emr_cmd = MC_CMD_LINK_PIOBUF;
771 req.emr_in_buf = payload;
772 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
773 req.emr_out_buf = payload;
774 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
776 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
777 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
779 efx_mcdi_execute(enp, &req);
781 if (req.emr_rc != 0) {
789 EFSYS_PROBE1(fail1, efx_rc_t, rc);
794 static __checkReturn efx_rc_t
795 efx_mcdi_unlink_piobuf(
797 __in uint32_t vi_index)
800 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_UNLINK_PIOBUF_IN_LEN,
801 MC_CMD_UNLINK_PIOBUF_OUT_LEN);
804 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
805 req.emr_in_buf = payload;
806 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
807 req.emr_out_buf = payload;
808 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
810 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
812 efx_mcdi_execute_quiet(enp, &req);
814 if (req.emr_rc != 0) {
822 EFSYS_PROBE1(fail1, efx_rc_t, rc);
828 ef10_nic_alloc_piobufs(
830 __in uint32_t max_piobuf_count)
832 efx_piobuf_handle_t *handlep;
835 EFSYS_ASSERT3U(max_piobuf_count, <=,
836 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
838 enp->en_arch.ef10.ena_piobuf_count = 0;
840 for (i = 0; i < max_piobuf_count; i++) {
841 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
843 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0)
846 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
847 enp->en_arch.ef10.ena_piobuf_count++;
853 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
854 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
856 (void) efx_mcdi_free_piobuf(enp, *handlep);
857 *handlep = EFX_PIOBUF_HANDLE_INVALID;
859 enp->en_arch.ef10.ena_piobuf_count = 0;
864 ef10_nic_free_piobufs(
867 efx_piobuf_handle_t *handlep;
870 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
871 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
873 (void) efx_mcdi_free_piobuf(enp, *handlep);
874 *handlep = EFX_PIOBUF_HANDLE_INVALID;
876 enp->en_arch.ef10.ena_piobuf_count = 0;
879 /* Sub-allocate a block from a piobuf */
880 __checkReturn efx_rc_t
882 __inout efx_nic_t *enp,
883 __out uint32_t *bufnump,
884 __out efx_piobuf_handle_t *handlep,
885 __out uint32_t *blknump,
886 __out uint32_t *offsetp,
889 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
890 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
891 uint32_t blk_per_buf;
895 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
896 enp->en_family == EFX_FAMILY_MEDFORD ||
897 enp->en_family == EFX_FAMILY_MEDFORD2);
898 EFSYS_ASSERT(bufnump);
899 EFSYS_ASSERT(handlep);
900 EFSYS_ASSERT(blknump);
901 EFSYS_ASSERT(offsetp);
904 if ((edcp->edc_pio_alloc_size == 0) ||
905 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
909 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
911 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
912 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
917 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
918 for (blk = 0; blk < blk_per_buf; blk++) {
919 if ((*map & (1u << blk)) == 0) {
929 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
932 *sizep = edcp->edc_pio_alloc_size;
933 *offsetp = blk * (*sizep);
940 EFSYS_PROBE1(fail1, efx_rc_t, rc);
945 /* Free a piobuf sub-allocated block */
946 __checkReturn efx_rc_t
948 __inout efx_nic_t *enp,
949 __in uint32_t bufnum,
950 __in uint32_t blknum)
955 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
956 (blknum >= (8 * sizeof (*map)))) {
961 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
962 if ((*map & (1u << blknum)) == 0) {
966 *map &= ~(1u << blknum);
973 EFSYS_PROBE1(fail1, efx_rc_t, rc);
978 __checkReturn efx_rc_t
980 __inout efx_nic_t *enp,
981 __in uint32_t vi_index,
982 __in efx_piobuf_handle_t handle)
984 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
987 __checkReturn efx_rc_t
989 __inout efx_nic_t *enp,
990 __in uint32_t vi_index)
992 return (efx_mcdi_unlink_piobuf(enp, vi_index));
995 static __checkReturn efx_rc_t
996 ef10_mcdi_get_pf_count(
998 __out uint32_t *pf_countp)
1001 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PF_COUNT_IN_LEN,
1002 MC_CMD_GET_PF_COUNT_OUT_LEN);
1005 req.emr_cmd = MC_CMD_GET_PF_COUNT;
1006 req.emr_in_buf = payload;
1007 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN;
1008 req.emr_out_buf = payload;
1009 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN;
1011 efx_mcdi_execute(enp, &req);
1013 if (req.emr_rc != 0) {
1018 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) {
1023 *pf_countp = *MCDI_OUT(req, uint8_t,
1024 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST);
1026 EFSYS_ASSERT(*pf_countp != 0);
1033 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1038 static __checkReturn efx_rc_t
1039 ef10_get_datapath_caps(
1040 __in efx_nic_t *enp)
1042 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1044 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CAPABILITIES_IN_LEN,
1045 MC_CMD_GET_CAPABILITIES_V5_OUT_LEN);
1048 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0)
1052 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
1053 req.emr_in_buf = payload;
1054 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
1055 req.emr_out_buf = payload;
1056 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V5_OUT_LEN;
1058 efx_mcdi_execute_quiet(enp, &req);
1060 if (req.emr_rc != 0) {
1065 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
1070 #define CAP_FLAGS1(_req, _flag) \
1071 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_OUT_FLAGS1) & \
1072 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN)))
1074 #define CAP_FLAGS2(_req, _flag) \
1075 (((_req).emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) && \
1076 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V2_OUT_FLAGS2) & \
1077 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN))))
1080 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
1081 * We only support the 14 byte prefix here.
1083 if (CAP_FLAGS1(req, RX_PREFIX_LEN_14) == 0) {
1087 encp->enc_rx_prefix_size = 14;
1089 #if EFSYS_OPT_RX_SCALE
1090 /* Check if the firmware supports additional RSS modes */
1091 if (CAP_FLAGS1(req, ADDITIONAL_RSS_MODES))
1092 encp->enc_rx_scale_additional_modes_supported = B_TRUE;
1094 encp->enc_rx_scale_additional_modes_supported = B_FALSE;
1095 #endif /* EFSYS_OPT_RX_SCALE */
1097 /* Check if the firmware supports TSO */
1098 if (CAP_FLAGS1(req, TX_TSO))
1099 encp->enc_fw_assisted_tso_enabled = B_TRUE;
1101 encp->enc_fw_assisted_tso_enabled = B_FALSE;
1103 /* Check if the firmware supports FATSOv2 */
1104 if (CAP_FLAGS2(req, TX_TSO_V2)) {
1105 encp->enc_fw_assisted_tso_v2_enabled = B_TRUE;
1106 encp->enc_fw_assisted_tso_v2_n_contexts = MCDI_OUT_WORD(req,
1107 GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS);
1109 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
1110 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
1113 /* Check if the firmware supports FATSOv2 encap */
1114 if (CAP_FLAGS2(req, TX_TSO_V2_ENCAP))
1115 encp->enc_fw_assisted_tso_v2_encap_enabled = B_TRUE;
1117 encp->enc_fw_assisted_tso_v2_encap_enabled = B_FALSE;
1119 /* Check if the firmware has vadapter/vport/vswitch support */
1120 if (CAP_FLAGS1(req, EVB))
1121 encp->enc_datapath_cap_evb = B_TRUE;
1123 encp->enc_datapath_cap_evb = B_FALSE;
1125 /* Check if the firmware supports VLAN insertion */
1126 if (CAP_FLAGS1(req, TX_VLAN_INSERTION))
1127 encp->enc_hw_tx_insert_vlan_enabled = B_TRUE;
1129 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
1131 /* Check if the firmware supports RX event batching */
1132 if (CAP_FLAGS1(req, RX_BATCHING))
1133 encp->enc_rx_batching_enabled = B_TRUE;
1135 encp->enc_rx_batching_enabled = B_FALSE;
1138 * Even if batching isn't reported as supported, we may still get
1139 * batched events (see bug61153).
1141 encp->enc_rx_batch_max = 16;
1143 /* Check if the firmware supports disabling scatter on RXQs */
1144 if (CAP_FLAGS1(req, RX_DISABLE_SCATTER))
1145 encp->enc_rx_disable_scatter_supported = B_TRUE;
1147 encp->enc_rx_disable_scatter_supported = B_FALSE;
1149 /* Check if the firmware supports packed stream mode */
1150 if (CAP_FLAGS1(req, RX_PACKED_STREAM))
1151 encp->enc_rx_packed_stream_supported = B_TRUE;
1153 encp->enc_rx_packed_stream_supported = B_FALSE;
1156 * Check if the firmware supports configurable buffer sizes
1157 * for packed stream mode (otherwise buffer size is 1Mbyte)
1159 if (CAP_FLAGS1(req, RX_PACKED_STREAM_VAR_BUFFERS))
1160 encp->enc_rx_var_packed_stream_supported = B_TRUE;
1162 encp->enc_rx_var_packed_stream_supported = B_FALSE;
1164 /* Check if the firmware supports equal stride super-buffer mode */
1165 if (CAP_FLAGS2(req, EQUAL_STRIDE_SUPER_BUFFER))
1166 encp->enc_rx_es_super_buffer_supported = B_TRUE;
1168 encp->enc_rx_es_super_buffer_supported = B_FALSE;
1170 /* Check if the firmware supports FW subvariant w/o Tx checksumming */
1171 if (CAP_FLAGS2(req, FW_SUBVARIANT_NO_TX_CSUM))
1172 encp->enc_fw_subvariant_no_tx_csum_supported = B_TRUE;
1174 encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE;
1176 /* Check if the firmware supports set mac with running filters */
1177 if (CAP_FLAGS1(req, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED))
1178 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
1180 encp->enc_allow_set_mac_with_installed_filters = B_FALSE;
1183 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows
1184 * specifying which parameters to configure.
1186 if (CAP_FLAGS1(req, SET_MAC_ENHANCED))
1187 encp->enc_enhanced_set_mac_supported = B_TRUE;
1189 encp->enc_enhanced_set_mac_supported = B_FALSE;
1192 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows
1193 * us to let the firmware choose the settings to use on an EVQ.
1195 if (CAP_FLAGS2(req, INIT_EVQ_V2))
1196 encp->enc_init_evq_v2_supported = B_TRUE;
1198 encp->enc_init_evq_v2_supported = B_FALSE;
1201 * Check if firmware-verified NVRAM updates must be used.
1203 * The firmware trusted installer requires all NVRAM updates to use
1204 * version 2 of MC_CMD_NVRAM_UPDATE_START (to enable verified update)
1205 * and version 2 of MC_CMD_NVRAM_UPDATE_FINISH (to verify the updated
1206 * partition and report the result).
1208 if (CAP_FLAGS2(req, NVRAM_UPDATE_REPORT_VERIFY_RESULT))
1209 encp->enc_nvram_update_verify_result_supported = B_TRUE;
1211 encp->enc_nvram_update_verify_result_supported = B_FALSE;
1214 * Check if firmware provides packet memory and Rx datapath
1217 if (CAP_FLAGS1(req, PM_AND_RXDP_COUNTERS))
1218 encp->enc_pm_and_rxdp_counters = B_TRUE;
1220 encp->enc_pm_and_rxdp_counters = B_FALSE;
1223 * Check if the 40G MAC hardware is capable of reporting
1224 * statistics for Tx size bins.
1226 if (CAP_FLAGS2(req, MAC_STATS_40G_TX_SIZE_BINS))
1227 encp->enc_mac_stats_40g_tx_size_bins = B_TRUE;
1229 encp->enc_mac_stats_40g_tx_size_bins = B_FALSE;
1232 * Check if firmware supports VXLAN and NVGRE tunnels.
1233 * The capability indicates Geneve protocol support as well.
1235 if (CAP_FLAGS1(req, VXLAN_NVGRE)) {
1236 encp->enc_tunnel_encapsulations_supported =
1237 (1u << EFX_TUNNEL_PROTOCOL_VXLAN) |
1238 (1u << EFX_TUNNEL_PROTOCOL_GENEVE) |
1239 (1u << EFX_TUNNEL_PROTOCOL_NVGRE);
1241 EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES ==
1242 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
1243 encp->enc_tunnel_config_udp_entries_max =
1244 EFX_TUNNEL_MAXNENTRIES;
1246 encp->enc_tunnel_config_udp_entries_max = 0;
1250 * Check if firmware reports the VI window mode.
1251 * Medford2 has a variable VI window size (8K, 16K or 64K).
1252 * Medford and Huntington have a fixed 8K VI window size.
1254 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
1256 MCDI_OUT_BYTE(req, GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
1259 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
1260 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1262 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
1263 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_16K;
1265 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
1266 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_64K;
1269 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1272 } else if ((enp->en_family == EFX_FAMILY_HUNTINGTON) ||
1273 (enp->en_family == EFX_FAMILY_MEDFORD)) {
1274 /* Huntington and Medford have fixed 8K window size */
1275 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1277 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1280 /* Check if firmware supports extended MAC stats. */
1281 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
1282 /* Extended stats buffer supported */
1283 encp->enc_mac_stats_nstats = MCDI_OUT_WORD(req,
1284 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
1286 /* Use Siena-compatible legacy MAC stats */
1287 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS;
1290 if (encp->enc_mac_stats_nstats >= MC_CMD_MAC_NSTATS_V2)
1291 encp->enc_fec_counters = B_TRUE;
1293 encp->enc_fec_counters = B_FALSE;
1295 /* Check if the firmware provides head-of-line blocking counters */
1296 if (CAP_FLAGS2(req, RXDP_HLB_IDLE))
1297 encp->enc_hlb_counters = B_TRUE;
1299 encp->enc_hlb_counters = B_FALSE;
1301 #if EFSYS_OPT_RX_SCALE
1302 if (CAP_FLAGS1(req, RX_RSS_LIMITED)) {
1303 /* Only one exclusive RSS context is available per port. */
1304 encp->enc_rx_scale_max_exclusive_contexts = 1;
1306 switch (enp->en_family) {
1307 case EFX_FAMILY_MEDFORD2:
1308 encp->enc_rx_scale_hash_alg_mask =
1309 (1U << EFX_RX_HASHALG_TOEPLITZ);
1312 case EFX_FAMILY_MEDFORD:
1313 case EFX_FAMILY_HUNTINGTON:
1315 * Packed stream firmware variant maintains a
1316 * non-standard algorithm for hash computation.
1317 * It implies explicit XORing together
1318 * source + destination IP addresses (or last
1319 * four bytes in the case of IPv6) and using the
1320 * resulting value as the input to a Toeplitz hash.
1322 encp->enc_rx_scale_hash_alg_mask =
1323 (1U << EFX_RX_HASHALG_PACKED_STREAM);
1331 /* Port numbers cannot contribute to the hash value */
1332 encp->enc_rx_scale_l4_hash_supported = B_FALSE;
1335 * Maximum number of exclusive RSS contexts.
1336 * EF10 hardware supports 64 in total, but 6 are reserved
1337 * for shared contexts. They are a global resource so
1338 * not all may be available.
1340 encp->enc_rx_scale_max_exclusive_contexts = 64 - 6;
1342 encp->enc_rx_scale_hash_alg_mask =
1343 (1U << EFX_RX_HASHALG_TOEPLITZ);
1346 * It is possible to use port numbers as
1347 * the input data for hash computation.
1349 encp->enc_rx_scale_l4_hash_supported = B_TRUE;
1351 #endif /* EFSYS_OPT_RX_SCALE */
1353 /* Check if the firmware supports "FLAG" and "MARK" filter actions */
1354 if (CAP_FLAGS2(req, FILTER_ACTION_FLAG))
1355 encp->enc_filter_action_flag_supported = B_TRUE;
1357 encp->enc_filter_action_flag_supported = B_FALSE;
1359 if (CAP_FLAGS2(req, FILTER_ACTION_MARK))
1360 encp->enc_filter_action_mark_supported = B_TRUE;
1362 encp->enc_filter_action_mark_supported = B_FALSE;
1364 /* Get maximum supported value for "MARK" filter action */
1365 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V5_OUT_LEN)
1366 encp->enc_filter_action_mark_max = MCDI_OUT_DWORD(req,
1367 GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX);
1369 encp->enc_filter_action_mark_max = 0;
1376 #if EFSYS_OPT_RX_SCALE
1379 #endif /* EFSYS_OPT_RX_SCALE */
1387 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1393 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
1394 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
1395 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
1396 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
1397 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
1398 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
1399 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
1400 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
1401 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
1402 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
1403 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
1404 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
1406 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
1409 __checkReturn efx_rc_t
1410 ef10_get_privilege_mask(
1411 __in efx_nic_t *enp,
1412 __out uint32_t *maskp)
1414 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1418 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1423 /* Fallback for old firmware without privilege mask support */
1424 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1425 /* Assume PF has admin privilege */
1426 mask = EF10_LEGACY_PF_PRIVILEGE_MASK;
1428 /* VF is always unprivileged by default */
1429 mask = EF10_LEGACY_VF_PRIVILEGE_MASK;
1438 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1444 #define EFX_EXT_PORT_MAX 4
1445 #define EFX_EXT_PORT_NA 0xFF
1448 * Table of mapping schemes from port number to external number.
1450 * Each port number ultimately corresponds to a connector: either as part of
1451 * a cable assembly attached to a module inserted in an SFP+/QSFP+ cage on
1452 * the board, or fixed to the board (e.g. 10GBASE-T magjack on SFN5121T
1453 * "Salina"). In general:
1455 * Port number (0-based)
1457 * port mapping (n:1)
1460 * External port number (1-based)
1462 * fixed (1:1) or cable assembly (1:m)
1467 * The external numbering refers to the cages or magjacks on the board,
1468 * as visibly annotated on the board or back panel. This table describes
1469 * how to determine which external cage/magjack corresponds to the port
1470 * numbers used by the driver.
1472 * The count of consecutive port numbers that map to each external number,
1473 * is determined by the chip family and the current port mode.
1475 * For the Huntington family, the current port mode cannot be discovered,
1476 * but a single mapping is used by all modes for a given chip variant,
1477 * so the mapping used is instead the last match in the table to the full
1478 * set of port modes to which the NIC can be configured. Therefore the
1479 * ordering of entries in the mapping table is significant.
1481 static struct ef10_external_port_map_s {
1482 efx_family_t family;
1483 uint32_t modes_mask;
1484 uint8_t base_port[EFX_EXT_PORT_MAX];
1485 } __ef10_external_port_mappings[] = {
1487 * Modes used by Huntington family controllers where each port
1488 * number maps to a separate cage.
1489 * SFN7x22F (Torino):
1499 EFX_FAMILY_HUNTINGTON,
1500 (1U << TLV_PORT_MODE_10G) | /* mode 0 */
1501 (1U << TLV_PORT_MODE_10G_10G) | /* mode 2 */
1502 (1U << TLV_PORT_MODE_10G_10G_10G_10G), /* mode 4 */
1506 * Modes which for Huntington identify a chip variant where 2
1507 * adjacent port numbers map to each cage.
1515 EFX_FAMILY_HUNTINGTON,
1516 (1U << TLV_PORT_MODE_40G) | /* mode 1 */
1517 (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
1518 (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
1519 (1U << TLV_PORT_MODE_10G_10G_40G), /* mode 7 */
1520 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1523 * Modes that on Medford allocate each port number to a separate
1532 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1533 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1534 (1U << TLV_PORT_MODE_1x1_1x1), /* mode 2 */
1538 * Modes that on Medford allocate 2 adjacent port numbers to each
1547 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
1548 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 5 */
1549 (1U << TLV_PORT_MODE_1x4_2x1) | /* mode 6 */
1550 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
1551 /* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */
1552 (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */
1553 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1556 * Modes that on Medford allocate 4 adjacent port numbers to
1565 /* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */
1566 (1U << TLV_PORT_MODE_4x1_NA), /* mode 4 */
1567 { 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1570 * Modes that on Medford allocate 4 adjacent port numbers to
1579 (1U << TLV_PORT_MODE_NA_4x1), /* mode 8 */
1580 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1583 * Modes that on Medford2 allocate each port number to a separate
1591 EFX_FAMILY_MEDFORD2,
1592 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1593 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1594 (1U << TLV_PORT_MODE_1x1_1x1) | /* mode 2 */
1595 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
1596 (1U << TLV_PORT_MODE_1x2_NA) | /* mode 10 */
1597 (1U << TLV_PORT_MODE_1x2_1x2) | /* mode 12 */
1598 (1U << TLV_PORT_MODE_1x4_1x2) | /* mode 15 */
1599 (1U << TLV_PORT_MODE_1x2_1x4), /* mode 16 */
1603 * Modes that on Medford2 allocate 1 port to cage 1 and the rest
1610 EFX_FAMILY_MEDFORD2,
1611 (1U << TLV_PORT_MODE_1x2_2x1) | /* mode 17 */
1612 (1U << TLV_PORT_MODE_1x4_2x1), /* mode 6 */
1613 { 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1616 * Modes that on Medford2 allocate 2 adjacent port numbers to cage 1
1617 * and the rest to cage 2.
1624 EFX_FAMILY_MEDFORD2,
1625 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 4 */
1626 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
1627 (1U << TLV_PORT_MODE_2x2_NA) | /* mode 13 */
1628 (1U << TLV_PORT_MODE_2x1_1x2), /* mode 18 */
1629 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1632 * Modes that on Medford2 allocate up to 4 adjacent port numbers
1640 EFX_FAMILY_MEDFORD2,
1641 (1U << TLV_PORT_MODE_4x1_NA), /* mode 5 */
1642 { 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1645 * Modes that on Medford2 allocate up to 4 adjacent port numbers
1653 EFX_FAMILY_MEDFORD2,
1654 (1U << TLV_PORT_MODE_NA_4x1) | /* mode 8 */
1655 (1U << TLV_PORT_MODE_NA_1x2) | /* mode 11 */
1656 (1U << TLV_PORT_MODE_NA_2x2), /* mode 14 */
1657 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1661 static __checkReturn efx_rc_t
1662 ef10_external_port_mapping(
1663 __in efx_nic_t *enp,
1665 __out uint8_t *external_portp)
1669 uint32_t port_modes;
1672 struct ef10_external_port_map_s *mapp = NULL;
1673 int ext_index = port; /* Default 1-1 mapping */
1675 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t,
1678 * No current port mode information (i.e. Huntington)
1679 * - infer mapping from available modes
1681 if ((rc = efx_mcdi_get_port_modes(enp,
1682 &port_modes, NULL, NULL)) != 0) {
1684 * No port mode information available
1685 * - use default mapping
1690 /* Only need to scan the current mode */
1691 port_modes = 1 << current;
1695 * Infer the internal port -> external number mapping from
1696 * the possible port modes for this NIC.
1698 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1699 struct ef10_external_port_map_s *eepmp =
1700 &__ef10_external_port_mappings[i];
1701 if (eepmp->family != enp->en_family)
1703 matches = (eepmp->modes_mask & port_modes);
1706 * Some modes match. For some Huntington boards
1707 * there will be multiple matches. The mapping on the
1708 * last match is used.
1711 port_modes &= ~matches;
1715 if (port_modes != 0) {
1716 /* Some advertised modes are not supported */
1724 * External ports are assigned a sequence of consecutive
1725 * port numbers, so find the one with the closest base_port.
1727 uint32_t delta = EFX_EXT_PORT_NA;
1729 for (i = 0; i < EFX_EXT_PORT_MAX; i++) {
1730 uint32_t base = mapp->base_port[i];
1731 if ((base != EFX_EXT_PORT_NA) && (base <= port)) {
1732 if ((port - base) < delta) {
1733 delta = (port - base);
1739 *external_portp = (uint8_t)(ext_index + 1);
1744 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1749 static __checkReturn efx_rc_t
1751 __in efx_nic_t *enp)
1753 const efx_nic_ops_t *enop = enp->en_enop;
1754 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
1755 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1756 ef10_link_state_t els;
1757 efx_port_t *epp = &(enp->en_port);
1758 uint32_t board_type = 0;
1759 uint32_t base, nvec;
1764 uint8_t mac_addr[6] = { 0 };
1767 /* Get the (zero-based) MCDI port number */
1768 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
1771 /* EFX MCDI interface uses one-based port numbers */
1772 emip->emi_port = port + 1;
1774 if ((rc = ef10_external_port_mapping(enp, port,
1775 &encp->enc_external_port)) != 0)
1779 * Get PCIe function number from firmware (used for
1780 * per-function privilege and dynamic config info).
1781 * - PCIe PF: pf = PF number, vf = 0xffff.
1782 * - PCIe VF: pf = parent PF, vf = VF number.
1784 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
1790 /* MAC address for this function */
1791 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1792 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
1793 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
1795 * Disable static config checking, ONLY for manufacturing test
1796 * and setup at the factory, to allow the static config to be
1799 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1800 if ((rc == 0) && (mac_addr[0] & 0x02)) {
1802 * If the static config does not include a global MAC
1803 * address pool then the board may return a locally
1804 * administered MAC address (this should only happen on
1805 * incorrectly programmed boards).
1809 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1811 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
1816 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
1818 /* Board configuration (legacy) */
1819 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
1821 /* Unprivileged functions may not be able to read board cfg */
1828 encp->enc_board_type = board_type;
1829 encp->enc_clk_mult = 1; /* not used for EF10 */
1831 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
1832 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
1836 * Firmware with support for *_FEC capability bits does not
1837 * report that the corresponding *_FEC_REQUESTED bits are supported.
1838 * Add them here so that drivers understand that they are supported.
1840 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_BASER_FEC))
1841 epp->ep_phy_cap_mask |=
1842 (1u << EFX_PHY_CAP_BASER_FEC_REQUESTED);
1843 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_RS_FEC))
1844 epp->ep_phy_cap_mask |=
1845 (1u << EFX_PHY_CAP_RS_FEC_REQUESTED);
1846 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_25G_BASER_FEC))
1847 epp->ep_phy_cap_mask |=
1848 (1u << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED);
1850 /* Obtain the default PHY advertised capabilities */
1851 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
1853 epp->ep_default_adv_cap_mask = els.epls.epls_adv_cap_mask;
1854 epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask;
1856 /* Check capabilities of running datapath firmware */
1857 if ((rc = ef10_get_datapath_caps(enp)) != 0)
1860 /* Alignment for WPTR updates */
1861 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
1863 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
1864 /* No boundary crossing limits */
1865 encp->enc_tx_dma_desc_boundary = 0;
1868 * Maximum number of bytes into the frame the TCP header can start for
1869 * firmware assisted TSO to work.
1871 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
1874 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
1875 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
1876 * resources (allocated to this PCIe function), which is zero until
1877 * after we have allocated VIs.
1879 encp->enc_evq_limit = 1024;
1880 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
1881 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
1883 encp->enc_buftbl_limit = 0xFFFFFFFF;
1885 /* Get interrupt vector limits */
1886 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
1887 if (EFX_PCI_FUNCTION_IS_PF(encp))
1890 /* Ignore error (cannot query vector limits from a VF). */
1894 encp->enc_intr_vec_base = base;
1895 encp->enc_intr_limit = nvec;
1898 * Get the current privilege mask. Note that this may be modified
1899 * dynamically, so this value is informational only. DO NOT use
1900 * the privilege mask to check for sufficient privileges, as that
1901 * can result in time-of-check/time-of-use bugs.
1903 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
1905 encp->enc_privilege_mask = mask;
1907 /* Get remaining controller-specific board config */
1908 if ((rc = enop->eno_board_cfg(enp)) != 0)
1915 EFSYS_PROBE(fail11);
1917 EFSYS_PROBE(fail10);
1935 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1940 __checkReturn efx_rc_t
1942 __in efx_nic_t *enp)
1944 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1945 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1948 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1949 enp->en_family == EFX_FAMILY_MEDFORD ||
1950 enp->en_family == EFX_FAMILY_MEDFORD2);
1952 /* Read and clear any assertion state */
1953 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1956 /* Exit the assertion handler */
1957 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1961 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
1964 if ((rc = ef10_nic_board_cfg(enp)) != 0)
1968 * Set default driver config limits (based on board config).
1970 * FIXME: For now allocate a fixed number of VIs which is likely to be
1971 * sufficient and small enough to allow multiple functions on the same
1974 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
1975 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
1977 /* The client driver must configure and enable PIO buffer support */
1978 edcp->edc_max_piobuf_count = 0;
1979 edcp->edc_pio_alloc_size = 0;
1981 #if EFSYS_OPT_MAC_STATS
1982 /* Wipe the MAC statistics */
1983 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
1987 #if EFSYS_OPT_LOOPBACK
1988 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
1992 #if EFSYS_OPT_MON_STATS
1993 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
1994 /* Unprivileged functions do not have access to sensors */
2000 encp->enc_features = enp->en_features;
2004 #if EFSYS_OPT_MON_STATS
2008 #if EFSYS_OPT_LOOPBACK
2012 #if EFSYS_OPT_MAC_STATS
2023 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2028 __checkReturn efx_rc_t
2029 ef10_nic_set_drv_limits(
2030 __inout efx_nic_t *enp,
2031 __in efx_drv_limits_t *edlp)
2033 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
2034 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2035 uint32_t min_evq_count, max_evq_count;
2036 uint32_t min_rxq_count, max_rxq_count;
2037 uint32_t min_txq_count, max_txq_count;
2045 /* Get minimum required and maximum usable VI limits */
2046 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
2047 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
2048 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
2050 edcp->edc_min_vi_count =
2051 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
2053 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
2054 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
2055 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
2057 edcp->edc_max_vi_count =
2058 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
2061 * Check limits for sub-allocated piobuf blocks.
2062 * PIO is optional, so don't fail if the limits are incorrect.
2064 if ((encp->enc_piobuf_size == 0) ||
2065 (encp->enc_piobuf_limit == 0) ||
2066 (edlp->edl_min_pio_alloc_size == 0) ||
2067 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
2069 edcp->edc_max_piobuf_count = 0;
2070 edcp->edc_pio_alloc_size = 0;
2072 uint32_t blk_size, blk_count, blks_per_piobuf;
2075 MAX(edlp->edl_min_pio_alloc_size,
2076 encp->enc_piobuf_min_alloc_size);
2078 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
2079 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
2081 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
2083 /* A zero max pio alloc count means unlimited */
2084 if ((edlp->edl_max_pio_alloc_count > 0) &&
2085 (edlp->edl_max_pio_alloc_count < blk_count)) {
2086 blk_count = edlp->edl_max_pio_alloc_count;
2089 edcp->edc_pio_alloc_size = blk_size;
2090 edcp->edc_max_piobuf_count =
2091 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
2097 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2103 __checkReturn efx_rc_t
2105 __in efx_nic_t *enp)
2108 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ENTITY_RESET_IN_LEN,
2109 MC_CMD_ENTITY_RESET_OUT_LEN);
2112 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
2113 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
2115 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
2118 req.emr_cmd = MC_CMD_ENTITY_RESET;
2119 req.emr_in_buf = payload;
2120 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
2121 req.emr_out_buf = payload;
2122 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
2124 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
2125 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
2127 efx_mcdi_execute(enp, &req);
2129 if (req.emr_rc != 0) {
2134 /* Clear RX/TX DMA queue errors */
2135 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
2144 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2149 __checkReturn efx_rc_t
2151 __in efx_nic_t *enp)
2153 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2154 uint32_t min_vi_count, max_vi_count;
2155 uint32_t vi_count, vi_base, vi_shift;
2159 uint32_t vi_window_size;
2162 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2163 enp->en_family == EFX_FAMILY_MEDFORD ||
2164 enp->en_family == EFX_FAMILY_MEDFORD2);
2166 /* Enable reporting of some events (e.g. link change) */
2167 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
2170 /* Allocate (optional) on-chip PIO buffers */
2171 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
2174 * For best performance, PIO writes should use a write-combined
2175 * (WC) memory mapping. Using a separate WC mapping for the PIO
2176 * aperture of each VI would be a burden to drivers (and not
2177 * possible if the host page size is >4Kbyte).
2179 * To avoid this we use a single uncached (UC) mapping for VI
2180 * register access, and a single WC mapping for extra VIs used
2183 * Each piobuf must be linked to a VI in the WC mapping, and to
2184 * each VI that is using a sub-allocated block from the piobuf.
2186 min_vi_count = edcp->edc_min_vi_count;
2188 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
2190 /* Ensure that the previously attached driver's VIs are freed */
2191 if ((rc = efx_mcdi_free_vis(enp)) != 0)
2195 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
2196 * fails then retrying the request for fewer VI resources may succeed.
2199 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
2200 &vi_base, &vi_count, &vi_shift)) != 0)
2203 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
2205 if (vi_count < min_vi_count) {
2210 enp->en_arch.ef10.ena_vi_base = vi_base;
2211 enp->en_arch.ef10.ena_vi_count = vi_count;
2212 enp->en_arch.ef10.ena_vi_shift = vi_shift;
2214 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
2215 /* Not enough extra VIs to map piobufs */
2216 ef10_nic_free_piobufs(enp);
2219 enp->en_arch.ef10.ena_pio_write_vi_base =
2220 vi_count - enp->en_arch.ef10.ena_piobuf_count;
2222 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, !=,
2223 EFX_VI_WINDOW_SHIFT_INVALID);
2224 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, <=,
2225 EFX_VI_WINDOW_SHIFT_64K);
2226 vi_window_size = 1U << enp->en_nic_cfg.enc_vi_window_shift;
2228 /* Save UC memory mapping details */
2229 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
2230 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2231 enp->en_arch.ef10.ena_uc_mem_map_size =
2233 enp->en_arch.ef10.ena_pio_write_vi_base);
2235 enp->en_arch.ef10.ena_uc_mem_map_size =
2237 enp->en_arch.ef10.ena_vi_count);
2240 /* Save WC memory mapping details */
2241 enp->en_arch.ef10.ena_wc_mem_map_offset =
2242 enp->en_arch.ef10.ena_uc_mem_map_offset +
2243 enp->en_arch.ef10.ena_uc_mem_map_size;
2245 enp->en_arch.ef10.ena_wc_mem_map_size =
2247 enp->en_arch.ef10.ena_piobuf_count);
2249 /* Link piobufs to extra VIs in WC mapping */
2250 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2251 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2252 rc = efx_mcdi_link_piobuf(enp,
2253 enp->en_arch.ef10.ena_pio_write_vi_base + i,
2254 enp->en_arch.ef10.ena_piobuf_handle[i]);
2261 * Allocate a vAdaptor attached to our upstream vPort/pPort.
2263 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
2264 * driver has yet to bring up the EVB port. See bug 56147. In this case,
2265 * retry the request several times after waiting a while. The wait time
2266 * between retries starts small (10ms) and exponentially increases.
2267 * Total wait time is a little over two seconds. Retry logic in the
2268 * client driver may mean this whole loop is repeated if it continues to
2273 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
2274 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
2277 * Do not retry alloc for PF, or for other errors on
2283 /* VF startup before PF is ready. Retry allocation. */
2285 /* Too many attempts */
2289 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
2290 EFSYS_SLEEP(delay_us);
2292 if (delay_us < 500000)
2296 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
2297 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
2312 ef10_nic_free_piobufs(enp);
2315 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2320 __checkReturn efx_rc_t
2321 ef10_nic_get_vi_pool(
2322 __in efx_nic_t *enp,
2323 __out uint32_t *vi_countp)
2325 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2326 enp->en_family == EFX_FAMILY_MEDFORD ||
2327 enp->en_family == EFX_FAMILY_MEDFORD2);
2330 * Report VIs that the client driver can use.
2331 * Do not include VIs used for PIO buffer writes.
2333 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
2338 __checkReturn efx_rc_t
2339 ef10_nic_get_bar_region(
2340 __in efx_nic_t *enp,
2341 __in efx_nic_region_t region,
2342 __out uint32_t *offsetp,
2343 __out size_t *sizep)
2347 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2348 enp->en_family == EFX_FAMILY_MEDFORD ||
2349 enp->en_family == EFX_FAMILY_MEDFORD2);
2352 * TODO: Specify host memory mapping alignment and granularity
2353 * in efx_drv_limits_t so that they can be taken into account
2354 * when allocating extra VIs for PIO writes.
2358 /* UC mapped memory BAR region for VI registers */
2359 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
2360 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
2363 case EFX_REGION_PIO_WRITE_VI:
2364 /* WC mapped memory BAR region for piobuf writes */
2365 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
2366 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
2377 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2382 __checkReturn boolean_t
2383 ef10_nic_hw_unavailable(
2384 __in efx_nic_t *enp)
2388 if (enp->en_reset_flags & EFX_RESET_HW_UNAVAIL)
2391 EFX_BAR_READD(enp, ER_DZ_BIU_MC_SFT_STATUS_REG, &dword, B_FALSE);
2392 if (EFX_DWORD_FIELD(dword, EFX_DWORD_0) == 0xffffffff)
2398 ef10_nic_set_hw_unavailable(enp);
2404 ef10_nic_set_hw_unavailable(
2405 __in efx_nic_t *enp)
2407 EFSYS_PROBE(hw_unavail);
2408 enp->en_reset_flags |= EFX_RESET_HW_UNAVAIL;
2414 __in efx_nic_t *enp)
2419 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
2420 enp->en_vport_id = 0;
2422 /* Unlink piobufs from extra VIs in WC mapping */
2423 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2424 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2425 rc = efx_mcdi_unlink_piobuf(enp,
2426 enp->en_arch.ef10.ena_pio_write_vi_base + i);
2432 ef10_nic_free_piobufs(enp);
2434 (void) efx_mcdi_free_vis(enp);
2435 enp->en_arch.ef10.ena_vi_count = 0;
2440 __in efx_nic_t *enp)
2442 #if EFSYS_OPT_MON_STATS
2443 mcdi_mon_cfg_free(enp);
2444 #endif /* EFSYS_OPT_MON_STATS */
2445 (void) efx_mcdi_drv_attach(enp, B_FALSE);
2450 __checkReturn efx_rc_t
2451 ef10_nic_register_test(
2452 __in efx_nic_t *enp)
2457 _NOTE(ARGUNUSED(enp))
2458 _NOTE(CONSTANTCONDITION)
2468 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2473 #endif /* EFSYS_OPT_DIAG */
2475 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
2477 __checkReturn efx_rc_t
2478 efx_mcdi_get_nic_global(
2479 __in efx_nic_t *enp,
2481 __out uint32_t *valuep)
2484 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_NIC_GLOBAL_IN_LEN,
2485 MC_CMD_GET_NIC_GLOBAL_OUT_LEN);
2488 req.emr_cmd = MC_CMD_GET_NIC_GLOBAL;
2489 req.emr_in_buf = payload;
2490 req.emr_in_length = MC_CMD_GET_NIC_GLOBAL_IN_LEN;
2491 req.emr_out_buf = payload;
2492 req.emr_out_length = MC_CMD_GET_NIC_GLOBAL_OUT_LEN;
2494 MCDI_IN_SET_DWORD(req, GET_NIC_GLOBAL_IN_KEY, key);
2496 efx_mcdi_execute(enp, &req);
2498 if (req.emr_rc != 0) {
2503 if (req.emr_out_length_used != MC_CMD_GET_NIC_GLOBAL_OUT_LEN) {
2508 *valuep = MCDI_OUT_DWORD(req, GET_NIC_GLOBAL_OUT_VALUE);
2515 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2520 __checkReturn efx_rc_t
2521 efx_mcdi_set_nic_global(
2522 __in efx_nic_t *enp,
2524 __in uint32_t value)
2527 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_NIC_GLOBAL_IN_LEN, 0);
2530 req.emr_cmd = MC_CMD_SET_NIC_GLOBAL;
2531 req.emr_in_buf = payload;
2532 req.emr_in_length = MC_CMD_SET_NIC_GLOBAL_IN_LEN;
2533 req.emr_out_buf = NULL;
2534 req.emr_out_length = 0;
2536 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_KEY, key);
2537 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_VALUE, value);
2539 efx_mcdi_execute(enp, &req);
2541 if (req.emr_rc != 0) {
2549 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2554 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
2556 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */