2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
34 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
36 #include "ef10_tlv_layout.h"
38 __checkReturn efx_rc_t
39 efx_mcdi_get_port_assignment(
41 __out uint32_t *portp)
44 uint8_t payload[MAX(MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
45 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN)];
48 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
49 enp->en_family == EFX_FAMILY_MEDFORD);
51 (void) memset(payload, 0, sizeof (payload));
52 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
53 req.emr_in_buf = payload;
54 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
55 req.emr_out_buf = payload;
56 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
58 efx_mcdi_execute(enp, &req);
60 if (req.emr_rc != 0) {
65 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
70 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
77 EFSYS_PROBE1(fail1, efx_rc_t, rc);
82 __checkReturn efx_rc_t
83 efx_mcdi_get_port_modes(
85 __out uint32_t *modesp,
86 __out_opt uint32_t *current_modep)
89 uint8_t payload[MAX(MC_CMD_GET_PORT_MODES_IN_LEN,
90 MC_CMD_GET_PORT_MODES_OUT_LEN)];
93 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
94 enp->en_family == EFX_FAMILY_MEDFORD);
96 (void) memset(payload, 0, sizeof (payload));
97 req.emr_cmd = MC_CMD_GET_PORT_MODES;
98 req.emr_in_buf = payload;
99 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
100 req.emr_out_buf = payload;
101 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
103 efx_mcdi_execute(enp, &req);
105 if (req.emr_rc != 0) {
111 * Require only Modes and DefaultMode fields, unless the current mode
112 * was requested (CurrentMode field was added for Medford).
114 if (req.emr_out_length_used <
115 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
119 if ((current_modep != NULL) && (req.emr_out_length_used <
120 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) {
125 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
127 if (current_modep != NULL) {
128 *current_modep = MCDI_OUT_DWORD(req,
129 GET_PORT_MODES_OUT_CURRENT_MODE);
139 EFSYS_PROBE1(fail1, efx_rc_t, rc);
144 __checkReturn efx_rc_t
145 ef10_nic_get_port_mode_bandwidth(
146 __in uint32_t port_mode,
147 __out uint32_t *bandwidth_mbpsp)
153 case TLV_PORT_MODE_10G:
156 case TLV_PORT_MODE_10G_10G:
157 bandwidth = 10000 * 2;
159 case TLV_PORT_MODE_10G_10G_10G_10G:
160 case TLV_PORT_MODE_10G_10G_10G_10G_Q:
161 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2:
162 case TLV_PORT_MODE_10G_10G_10G_10G_Q2:
163 bandwidth = 10000 * 4;
165 case TLV_PORT_MODE_40G:
168 case TLV_PORT_MODE_40G_40G:
169 bandwidth = 40000 * 2;
171 case TLV_PORT_MODE_40G_10G_10G:
172 case TLV_PORT_MODE_10G_10G_40G:
173 bandwidth = 40000 + (10000 * 2);
180 *bandwidth_mbpsp = bandwidth;
185 EFSYS_PROBE1(fail1, efx_rc_t, rc);
190 static __checkReturn efx_rc_t
191 efx_mcdi_vadaptor_alloc(
193 __in uint32_t port_id)
196 uint8_t payload[MAX(MC_CMD_VADAPTOR_ALLOC_IN_LEN,
197 MC_CMD_VADAPTOR_ALLOC_OUT_LEN)];
200 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
202 (void) memset(payload, 0, sizeof (payload));
203 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
204 req.emr_in_buf = payload;
205 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
206 req.emr_out_buf = payload;
207 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
209 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
210 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
211 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
212 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
214 efx_mcdi_execute(enp, &req);
216 if (req.emr_rc != 0) {
224 EFSYS_PROBE1(fail1, efx_rc_t, rc);
229 static __checkReturn efx_rc_t
230 efx_mcdi_vadaptor_free(
232 __in uint32_t port_id)
235 uint8_t payload[MAX(MC_CMD_VADAPTOR_FREE_IN_LEN,
236 MC_CMD_VADAPTOR_FREE_OUT_LEN)];
239 (void) memset(payload, 0, sizeof (payload));
240 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
241 req.emr_in_buf = payload;
242 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
243 req.emr_out_buf = payload;
244 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
246 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
248 efx_mcdi_execute(enp, &req);
250 if (req.emr_rc != 0) {
258 EFSYS_PROBE1(fail1, efx_rc_t, rc);
263 __checkReturn efx_rc_t
264 efx_mcdi_get_mac_address_pf(
266 __out_ecount_opt(6) uint8_t mac_addrp[6])
269 uint8_t payload[MAX(MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
270 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)];
273 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
274 enp->en_family == EFX_FAMILY_MEDFORD);
276 (void) memset(payload, 0, sizeof (payload));
277 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
278 req.emr_in_buf = payload;
279 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
280 req.emr_out_buf = payload;
281 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
283 efx_mcdi_execute(enp, &req);
285 if (req.emr_rc != 0) {
290 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
295 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
300 if (mac_addrp != NULL) {
303 addrp = MCDI_OUT2(req, uint8_t,
304 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
306 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
316 EFSYS_PROBE1(fail1, efx_rc_t, rc);
321 __checkReturn efx_rc_t
322 efx_mcdi_get_mac_address_vf(
324 __out_ecount_opt(6) uint8_t mac_addrp[6])
327 uint8_t payload[MAX(MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
328 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX)];
331 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
332 enp->en_family == EFX_FAMILY_MEDFORD);
334 (void) memset(payload, 0, sizeof (payload));
335 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
336 req.emr_in_buf = payload;
337 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
338 req.emr_out_buf = payload;
339 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
341 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
342 EVB_PORT_ID_ASSIGNED);
344 efx_mcdi_execute(enp, &req);
346 if (req.emr_rc != 0) {
351 if (req.emr_out_length_used <
352 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
357 if (MCDI_OUT_DWORD(req,
358 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
363 if (mac_addrp != NULL) {
366 addrp = MCDI_OUT2(req, uint8_t,
367 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
369 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
379 EFSYS_PROBE1(fail1, efx_rc_t, rc);
384 __checkReturn efx_rc_t
387 __out uint32_t *sys_freqp,
388 __out uint32_t *dpcpu_freqp)
391 uint8_t payload[MAX(MC_CMD_GET_CLOCK_IN_LEN,
392 MC_CMD_GET_CLOCK_OUT_LEN)];
395 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
396 enp->en_family == EFX_FAMILY_MEDFORD);
398 (void) memset(payload, 0, sizeof (payload));
399 req.emr_cmd = MC_CMD_GET_CLOCK;
400 req.emr_in_buf = payload;
401 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
402 req.emr_out_buf = payload;
403 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
405 efx_mcdi_execute(enp, &req);
407 if (req.emr_rc != 0) {
412 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
417 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
418 if (*sys_freqp == 0) {
422 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
423 if (*dpcpu_freqp == 0) {
437 EFSYS_PROBE1(fail1, efx_rc_t, rc);
442 __checkReturn efx_rc_t
443 efx_mcdi_get_vector_cfg(
445 __out_opt uint32_t *vec_basep,
446 __out_opt uint32_t *pf_nvecp,
447 __out_opt uint32_t *vf_nvecp)
450 uint8_t payload[MAX(MC_CMD_GET_VECTOR_CFG_IN_LEN,
451 MC_CMD_GET_VECTOR_CFG_OUT_LEN)];
454 (void) memset(payload, 0, sizeof (payload));
455 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
456 req.emr_in_buf = payload;
457 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
458 req.emr_out_buf = payload;
459 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
461 efx_mcdi_execute(enp, &req);
463 if (req.emr_rc != 0) {
468 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
473 if (vec_basep != NULL)
474 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
475 if (pf_nvecp != NULL)
476 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
477 if (vf_nvecp != NULL)
478 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
485 EFSYS_PROBE1(fail1, efx_rc_t, rc);
490 static __checkReturn efx_rc_t
491 efx_mcdi_get_capabilities(
493 __out uint32_t *flagsp,
494 __out uint32_t *flags2p,
495 __out uint32_t *tso2ncp)
498 uint8_t payload[MAX(MC_CMD_GET_CAPABILITIES_IN_LEN,
499 MC_CMD_GET_CAPABILITIES_V2_OUT_LEN)];
502 (void) memset(payload, 0, sizeof (payload));
503 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
504 req.emr_in_buf = payload;
505 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
506 req.emr_out_buf = payload;
507 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V2_OUT_LEN;
509 efx_mcdi_execute(enp, &req);
511 if (req.emr_rc != 0) {
516 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
521 *flagsp = MCDI_OUT_DWORD(req, GET_CAPABILITIES_OUT_FLAGS1);
523 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
527 *flags2p = MCDI_OUT_DWORD(req, GET_CAPABILITIES_V2_OUT_FLAGS2);
528 *tso2ncp = MCDI_OUT_WORD(req,
529 GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS);
537 EFSYS_PROBE1(fail1, efx_rc_t, rc);
543 static __checkReturn efx_rc_t
546 __in uint32_t min_vi_count,
547 __in uint32_t max_vi_count,
548 __out uint32_t *vi_basep,
549 __out uint32_t *vi_countp,
550 __out uint32_t *vi_shiftp)
553 uint8_t payload[MAX(MC_CMD_ALLOC_VIS_IN_LEN,
554 MC_CMD_ALLOC_VIS_OUT_LEN)];
557 if (vi_countp == NULL) {
562 (void) memset(payload, 0, sizeof (payload));
563 req.emr_cmd = MC_CMD_ALLOC_VIS;
564 req.emr_in_buf = payload;
565 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
566 req.emr_out_buf = payload;
567 req.emr_out_length = MC_CMD_ALLOC_VIS_OUT_LEN;
569 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
570 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
572 efx_mcdi_execute(enp, &req);
574 if (req.emr_rc != 0) {
579 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
584 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
585 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
587 /* Report VI_SHIFT if available (always zero for Huntington) */
588 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
591 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
600 EFSYS_PROBE1(fail1, efx_rc_t, rc);
606 static __checkReturn efx_rc_t
613 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
614 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
616 req.emr_cmd = MC_CMD_FREE_VIS;
617 req.emr_in_buf = NULL;
618 req.emr_in_length = 0;
619 req.emr_out_buf = NULL;
620 req.emr_out_length = 0;
622 efx_mcdi_execute_quiet(enp, &req);
624 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
625 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
633 EFSYS_PROBE1(fail1, efx_rc_t, rc);
639 static __checkReturn efx_rc_t
640 efx_mcdi_alloc_piobuf(
642 __out efx_piobuf_handle_t *handlep)
645 uint8_t payload[MAX(MC_CMD_ALLOC_PIOBUF_IN_LEN,
646 MC_CMD_ALLOC_PIOBUF_OUT_LEN)];
649 if (handlep == NULL) {
654 (void) memset(payload, 0, sizeof (payload));
655 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
656 req.emr_in_buf = payload;
657 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
658 req.emr_out_buf = payload;
659 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
661 efx_mcdi_execute_quiet(enp, &req);
663 if (req.emr_rc != 0) {
668 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
673 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
682 EFSYS_PROBE1(fail1, efx_rc_t, rc);
687 static __checkReturn efx_rc_t
688 efx_mcdi_free_piobuf(
690 __in efx_piobuf_handle_t handle)
693 uint8_t payload[MAX(MC_CMD_FREE_PIOBUF_IN_LEN,
694 MC_CMD_FREE_PIOBUF_OUT_LEN)];
697 (void) memset(payload, 0, sizeof (payload));
698 req.emr_cmd = MC_CMD_FREE_PIOBUF;
699 req.emr_in_buf = payload;
700 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
701 req.emr_out_buf = payload;
702 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
704 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
706 efx_mcdi_execute_quiet(enp, &req);
708 if (req.emr_rc != 0) {
716 EFSYS_PROBE1(fail1, efx_rc_t, rc);
721 static __checkReturn efx_rc_t
722 efx_mcdi_link_piobuf(
724 __in uint32_t vi_index,
725 __in efx_piobuf_handle_t handle)
728 uint8_t payload[MAX(MC_CMD_LINK_PIOBUF_IN_LEN,
729 MC_CMD_LINK_PIOBUF_OUT_LEN)];
732 (void) memset(payload, 0, sizeof (payload));
733 req.emr_cmd = MC_CMD_LINK_PIOBUF;
734 req.emr_in_buf = payload;
735 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
736 req.emr_out_buf = payload;
737 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
739 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
740 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
742 efx_mcdi_execute(enp, &req);
744 if (req.emr_rc != 0) {
752 EFSYS_PROBE1(fail1, efx_rc_t, rc);
757 static __checkReturn efx_rc_t
758 efx_mcdi_unlink_piobuf(
760 __in uint32_t vi_index)
763 uint8_t payload[MAX(MC_CMD_UNLINK_PIOBUF_IN_LEN,
764 MC_CMD_UNLINK_PIOBUF_OUT_LEN)];
767 (void) memset(payload, 0, sizeof (payload));
768 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
769 req.emr_in_buf = payload;
770 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
771 req.emr_out_buf = payload;
772 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
774 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
776 efx_mcdi_execute_quiet(enp, &req);
778 if (req.emr_rc != 0) {
786 EFSYS_PROBE1(fail1, efx_rc_t, rc);
792 ef10_nic_alloc_piobufs(
794 __in uint32_t max_piobuf_count)
796 efx_piobuf_handle_t *handlep;
799 EFSYS_ASSERT3U(max_piobuf_count, <=,
800 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
802 enp->en_arch.ef10.ena_piobuf_count = 0;
804 for (i = 0; i < max_piobuf_count; i++) {
805 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
807 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0)
810 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
811 enp->en_arch.ef10.ena_piobuf_count++;
817 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
818 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
820 efx_mcdi_free_piobuf(enp, *handlep);
821 *handlep = EFX_PIOBUF_HANDLE_INVALID;
823 enp->en_arch.ef10.ena_piobuf_count = 0;
828 ef10_nic_free_piobufs(
831 efx_piobuf_handle_t *handlep;
834 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
835 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
837 efx_mcdi_free_piobuf(enp, *handlep);
838 *handlep = EFX_PIOBUF_HANDLE_INVALID;
840 enp->en_arch.ef10.ena_piobuf_count = 0;
843 /* Sub-allocate a block from a piobuf */
844 __checkReturn efx_rc_t
846 __inout efx_nic_t *enp,
847 __out uint32_t *bufnump,
848 __out efx_piobuf_handle_t *handlep,
849 __out uint32_t *blknump,
850 __out uint32_t *offsetp,
853 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
854 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
855 uint32_t blk_per_buf;
859 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
860 enp->en_family == EFX_FAMILY_MEDFORD);
861 EFSYS_ASSERT(bufnump);
862 EFSYS_ASSERT(handlep);
863 EFSYS_ASSERT(blknump);
864 EFSYS_ASSERT(offsetp);
867 if ((edcp->edc_pio_alloc_size == 0) ||
868 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
872 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
874 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
875 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
880 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
881 for (blk = 0; blk < blk_per_buf; blk++) {
882 if ((*map & (1u << blk)) == 0) {
892 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
895 *sizep = edcp->edc_pio_alloc_size;
896 *offsetp = blk * (*sizep);
903 EFSYS_PROBE1(fail1, efx_rc_t, rc);
908 /* Free a piobuf sub-allocated block */
909 __checkReturn efx_rc_t
911 __inout efx_nic_t *enp,
912 __in uint32_t bufnum,
913 __in uint32_t blknum)
918 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
919 (blknum >= (8 * sizeof (*map)))) {
924 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
925 if ((*map & (1u << blknum)) == 0) {
929 *map &= ~(1u << blknum);
936 EFSYS_PROBE1(fail1, efx_rc_t, rc);
941 __checkReturn efx_rc_t
943 __inout efx_nic_t *enp,
944 __in uint32_t vi_index,
945 __in efx_piobuf_handle_t handle)
947 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
950 __checkReturn efx_rc_t
952 __inout efx_nic_t *enp,
953 __in uint32_t vi_index)
955 return (efx_mcdi_unlink_piobuf(enp, vi_index));
958 static __checkReturn efx_rc_t
959 ef10_mcdi_get_pf_count(
961 __out uint32_t *pf_countp)
964 uint8_t payload[MAX(MC_CMD_GET_PF_COUNT_IN_LEN,
965 MC_CMD_GET_PF_COUNT_OUT_LEN)];
968 (void) memset(payload, 0, sizeof (payload));
969 req.emr_cmd = MC_CMD_GET_PF_COUNT;
970 req.emr_in_buf = payload;
971 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN;
972 req.emr_out_buf = payload;
973 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN;
975 efx_mcdi_execute(enp, &req);
977 if (req.emr_rc != 0) {
982 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) {
987 *pf_countp = *MCDI_OUT(req, uint8_t,
988 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST);
990 EFSYS_ASSERT(*pf_countp != 0);
997 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1002 __checkReturn efx_rc_t
1003 ef10_get_datapath_caps(
1004 __in efx_nic_t *enp)
1006 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1012 if ((rc = efx_mcdi_get_capabilities(enp, &flags, &flags2,
1016 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0)
1019 #define CAP_FLAG(flags1, field) \
1020 ((flags1) & (1 << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## field ## _LBN)))
1022 #define CAP_FLAG2(flags2, field) \
1023 ((flags2) & (1 << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## field ## _LBN)))
1026 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
1027 * We only support the 14 byte prefix here.
1029 if (CAP_FLAG(flags, RX_PREFIX_LEN_14) == 0) {
1033 encp->enc_rx_prefix_size = 14;
1035 /* Check if the firmware supports TSO */
1036 encp->enc_fw_assisted_tso_enabled =
1037 CAP_FLAG(flags, TX_TSO) ? B_TRUE : B_FALSE;
1039 /* Check if the firmware supports FATSOv2 */
1040 encp->enc_fw_assisted_tso_v2_enabled =
1041 CAP_FLAG2(flags2, TX_TSO_V2) ? B_TRUE : B_FALSE;
1043 /* Get the number of TSO contexts (FATSOv2) */
1044 encp->enc_fw_assisted_tso_v2_n_contexts =
1045 CAP_FLAG2(flags2, TX_TSO_V2) ? tso2nc : 0;
1047 /* Check if the firmware has vadapter/vport/vswitch support */
1048 encp->enc_datapath_cap_evb =
1049 CAP_FLAG(flags, EVB) ? B_TRUE : B_FALSE;
1051 /* Check if the firmware supports VLAN insertion */
1052 encp->enc_hw_tx_insert_vlan_enabled =
1053 CAP_FLAG(flags, TX_VLAN_INSERTION) ? B_TRUE : B_FALSE;
1055 /* Check if the firmware supports RX event batching */
1056 encp->enc_rx_batching_enabled =
1057 CAP_FLAG(flags, RX_BATCHING) ? B_TRUE : B_FALSE;
1060 * Even if batching isn't reported as supported, we may still get
1061 * batched events (see bug61153).
1063 encp->enc_rx_batch_max = 16;
1065 /* Check if the firmware supports disabling scatter on RXQs */
1066 encp->enc_rx_disable_scatter_supported =
1067 CAP_FLAG(flags, RX_DISABLE_SCATTER) ? B_TRUE : B_FALSE;
1069 /* Check if the firmware supports packed stream mode */
1070 encp->enc_rx_packed_stream_supported =
1071 CAP_FLAG(flags, RX_PACKED_STREAM) ? B_TRUE : B_FALSE;
1074 * Check if the firmware supports configurable buffer sizes
1075 * for packed stream mode (otherwise buffer size is 1Mbyte)
1077 encp->enc_rx_var_packed_stream_supported =
1078 CAP_FLAG(flags, RX_PACKED_STREAM_VAR_BUFFERS) ? B_TRUE : B_FALSE;
1080 /* Check if the firmware supports set mac with running filters */
1081 encp->enc_allow_set_mac_with_installed_filters =
1082 CAP_FLAG(flags, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED) ?
1086 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows
1087 * specifying which parameters to configure.
1089 encp->enc_enhanced_set_mac_supported =
1090 CAP_FLAG(flags, SET_MAC_ENHANCED) ? B_TRUE : B_FALSE;
1093 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows
1094 * us to let the firmware choose the settings to use on an EVQ.
1096 encp->enc_init_evq_v2_supported =
1097 CAP_FLAG2(flags2, INIT_EVQ_V2) ? B_TRUE : B_FALSE;
1100 * Check if firmware-verified NVRAM updates must be used.
1102 * The firmware trusted installer requires all NVRAM updates to use
1103 * version 2 of MC_CMD_NVRAM_UPDATE_START (to enable verified update)
1104 * and version 2 of MC_CMD_NVRAM_UPDATE_FINISH (to verify the updated
1105 * partition and report the result).
1107 encp->enc_fw_verified_nvram_update_required =
1108 CAP_FLAG2(flags2, NVRAM_UPDATE_REPORT_VERIFY_RESULT) ?
1112 * Check if firmware provides packet memory and Rx datapath
1115 encp->enc_pm_and_rxdp_counters =
1116 CAP_FLAG(flags, PM_AND_RXDP_COUNTERS) ? B_TRUE : B_FALSE;
1119 * Check if the 40G MAC hardware is capable of reporting
1120 * statistics for Tx size bins.
1122 encp->enc_mac_stats_40g_tx_size_bins =
1123 CAP_FLAG2(flags2, MAC_STATS_40G_TX_SIZE_BINS) ? B_TRUE : B_FALSE;
1133 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1139 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
1140 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
1141 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
1142 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
1143 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
1144 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
1145 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
1146 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
1147 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
1148 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
1149 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
1150 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
1152 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
1155 __checkReturn efx_rc_t
1156 ef10_get_privilege_mask(
1157 __in efx_nic_t *enp,
1158 __out uint32_t *maskp)
1160 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1164 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1169 /* Fallback for old firmware without privilege mask support */
1170 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1171 /* Assume PF has admin privilege */
1172 mask = EF10_LEGACY_PF_PRIVILEGE_MASK;
1174 /* VF is always unprivileged by default */
1175 mask = EF10_LEGACY_VF_PRIVILEGE_MASK;
1184 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1191 * Table of mapping schemes from port number to the number of the external
1192 * connector on the board. The external numbering does not distinguish
1193 * off-board separated outputs such as from multi-headed cables.
1195 * The count of adjacent port numbers that map to each external port
1196 * and the offset in the numbering, is determined by the chip family and
1197 * current port mode.
1199 * For the Huntington family, the current port mode cannot be discovered,
1200 * so the mapping used is instead the last match in the table to the full
1201 * set of port modes to which the NIC can be configured. Therefore the
1202 * ordering of entries in the the mapping table is significant.
1205 efx_family_t family;
1206 uint32_t modes_mask;
1209 } __ef10_external_port_mappings[] = {
1210 /* Supported modes with 1 output per external port */
1212 EFX_FAMILY_HUNTINGTON,
1213 (1 << TLV_PORT_MODE_10G) |
1214 (1 << TLV_PORT_MODE_10G_10G) |
1215 (1 << TLV_PORT_MODE_10G_10G_10G_10G),
1221 (1 << TLV_PORT_MODE_10G) |
1222 (1 << TLV_PORT_MODE_10G_10G),
1226 /* Supported modes with 2 outputs per external port */
1228 EFX_FAMILY_HUNTINGTON,
1229 (1 << TLV_PORT_MODE_40G) |
1230 (1 << TLV_PORT_MODE_40G_40G) |
1231 (1 << TLV_PORT_MODE_40G_10G_10G) |
1232 (1 << TLV_PORT_MODE_10G_10G_40G),
1238 (1 << TLV_PORT_MODE_40G) |
1239 (1 << TLV_PORT_MODE_40G_40G) |
1240 (1 << TLV_PORT_MODE_40G_10G_10G) |
1241 (1 << TLV_PORT_MODE_10G_10G_40G) |
1242 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2),
1246 /* Supported modes with 4 outputs per external port */
1249 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q) |
1250 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1),
1256 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q2),
1262 __checkReturn efx_rc_t
1263 ef10_external_port_mapping(
1264 __in efx_nic_t *enp,
1266 __out uint8_t *external_portp)
1270 uint32_t port_modes;
1273 int32_t count = 1; /* Default 1-1 mapping */
1274 int32_t offset = 1; /* Default starting external port number */
1276 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t)) != 0) {
1278 * No current port mode information
1279 * - infer mapping from available modes
1281 if ((rc = efx_mcdi_get_port_modes(enp,
1282 &port_modes, NULL)) != 0) {
1284 * No port mode information available
1285 * - use default mapping
1290 /* Only need to scan the current mode */
1291 port_modes = 1 << current;
1295 * Infer the internal port -> external port mapping from
1296 * the possible port modes for this NIC.
1298 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1299 if (__ef10_external_port_mappings[i].family !=
1302 matches = (__ef10_external_port_mappings[i].modes_mask &
1305 count = __ef10_external_port_mappings[i].count;
1306 offset = __ef10_external_port_mappings[i].offset;
1307 port_modes &= ~matches;
1311 if (port_modes != 0) {
1312 /* Some advertised modes are not supported */
1319 * Scale as required by last matched mode and then convert to
1320 * correctly offset numbering
1322 *external_portp = (uint8_t)((port / count) + offset);
1326 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1332 __checkReturn efx_rc_t
1334 __in efx_nic_t *enp)
1336 const efx_nic_ops_t *enop = enp->en_enop;
1337 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1338 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1341 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1342 enp->en_family == EFX_FAMILY_MEDFORD);
1344 /* Read and clear any assertion state */
1345 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1348 /* Exit the assertion handler */
1349 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1353 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
1356 if ((rc = enop->eno_board_cfg(enp)) != 0)
1361 * Set default driver config limits (based on board config).
1363 * FIXME: For now allocate a fixed number of VIs which is likely to be
1364 * sufficient and small enough to allow multiple functions on the same
1367 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
1368 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
1370 /* The client driver must configure and enable PIO buffer support */
1371 edcp->edc_max_piobuf_count = 0;
1372 edcp->edc_pio_alloc_size = 0;
1374 #if EFSYS_OPT_MAC_STATS
1375 /* Wipe the MAC statistics */
1376 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
1380 encp->enc_features = enp->en_features;
1384 #if EFSYS_OPT_MAC_STATS
1395 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1400 __checkReturn efx_rc_t
1401 ef10_nic_set_drv_limits(
1402 __inout efx_nic_t *enp,
1403 __in efx_drv_limits_t *edlp)
1405 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1406 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1407 uint32_t min_evq_count, max_evq_count;
1408 uint32_t min_rxq_count, max_rxq_count;
1409 uint32_t min_txq_count, max_txq_count;
1417 /* Get minimum required and maximum usable VI limits */
1418 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
1419 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
1420 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
1422 edcp->edc_min_vi_count =
1423 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
1425 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
1426 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
1427 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
1429 edcp->edc_max_vi_count =
1430 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
1433 * Check limits for sub-allocated piobuf blocks.
1434 * PIO is optional, so don't fail if the limits are incorrect.
1436 if ((encp->enc_piobuf_size == 0) ||
1437 (encp->enc_piobuf_limit == 0) ||
1438 (edlp->edl_min_pio_alloc_size == 0) ||
1439 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
1441 edcp->edc_max_piobuf_count = 0;
1442 edcp->edc_pio_alloc_size = 0;
1444 uint32_t blk_size, blk_count, blks_per_piobuf;
1447 MAX(edlp->edl_min_pio_alloc_size,
1448 encp->enc_piobuf_min_alloc_size);
1450 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
1451 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
1453 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
1455 /* A zero max pio alloc count means unlimited */
1456 if ((edlp->edl_max_pio_alloc_count > 0) &&
1457 (edlp->edl_max_pio_alloc_count < blk_count)) {
1458 blk_count = edlp->edl_max_pio_alloc_count;
1461 edcp->edc_pio_alloc_size = blk_size;
1462 edcp->edc_max_piobuf_count =
1463 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
1469 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1475 __checkReturn efx_rc_t
1477 __in efx_nic_t *enp)
1480 uint8_t payload[MAX(MC_CMD_ENTITY_RESET_IN_LEN,
1481 MC_CMD_ENTITY_RESET_OUT_LEN)];
1484 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
1485 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1487 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1490 (void) memset(payload, 0, sizeof (payload));
1491 req.emr_cmd = MC_CMD_ENTITY_RESET;
1492 req.emr_in_buf = payload;
1493 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
1494 req.emr_out_buf = payload;
1495 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
1497 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
1498 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
1500 efx_mcdi_execute(enp, &req);
1502 if (req.emr_rc != 0) {
1507 /* Clear RX/TX DMA queue errors */
1508 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
1517 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1522 __checkReturn efx_rc_t
1524 __in efx_nic_t *enp)
1526 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1527 uint32_t min_vi_count, max_vi_count;
1528 uint32_t vi_count, vi_base, vi_shift;
1534 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1535 enp->en_family == EFX_FAMILY_MEDFORD);
1537 /* Enable reporting of some events (e.g. link change) */
1538 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
1541 /* Allocate (optional) on-chip PIO buffers */
1542 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
1545 * For best performance, PIO writes should use a write-combined
1546 * (WC) memory mapping. Using a separate WC mapping for the PIO
1547 * aperture of each VI would be a burden to drivers (and not
1548 * possible if the host page size is >4Kbyte).
1550 * To avoid this we use a single uncached (UC) mapping for VI
1551 * register access, and a single WC mapping for extra VIs used
1554 * Each piobuf must be linked to a VI in the WC mapping, and to
1555 * each VI that is using a sub-allocated block from the piobuf.
1557 min_vi_count = edcp->edc_min_vi_count;
1559 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
1561 /* Ensure that the previously attached driver's VIs are freed */
1562 if ((rc = efx_mcdi_free_vis(enp)) != 0)
1566 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
1567 * fails then retrying the request for fewer VI resources may succeed.
1570 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
1571 &vi_base, &vi_count, &vi_shift)) != 0)
1574 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
1576 if (vi_count < min_vi_count) {
1581 enp->en_arch.ef10.ena_vi_base = vi_base;
1582 enp->en_arch.ef10.ena_vi_count = vi_count;
1583 enp->en_arch.ef10.ena_vi_shift = vi_shift;
1585 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
1586 /* Not enough extra VIs to map piobufs */
1587 ef10_nic_free_piobufs(enp);
1590 enp->en_arch.ef10.ena_pio_write_vi_base =
1591 vi_count - enp->en_arch.ef10.ena_piobuf_count;
1593 /* Save UC memory mapping details */
1594 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
1595 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1596 enp->en_arch.ef10.ena_uc_mem_map_size =
1597 (ER_DZ_TX_PIOBUF_STEP *
1598 enp->en_arch.ef10.ena_pio_write_vi_base);
1600 enp->en_arch.ef10.ena_uc_mem_map_size =
1601 (ER_DZ_TX_PIOBUF_STEP *
1602 enp->en_arch.ef10.ena_vi_count);
1605 /* Save WC memory mapping details */
1606 enp->en_arch.ef10.ena_wc_mem_map_offset =
1607 enp->en_arch.ef10.ena_uc_mem_map_offset +
1608 enp->en_arch.ef10.ena_uc_mem_map_size;
1610 enp->en_arch.ef10.ena_wc_mem_map_size =
1611 (ER_DZ_TX_PIOBUF_STEP *
1612 enp->en_arch.ef10.ena_piobuf_count);
1614 /* Link piobufs to extra VIs in WC mapping */
1615 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1616 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1617 rc = efx_mcdi_link_piobuf(enp,
1618 enp->en_arch.ef10.ena_pio_write_vi_base + i,
1619 enp->en_arch.ef10.ena_piobuf_handle[i]);
1626 * Allocate a vAdaptor attached to our upstream vPort/pPort.
1628 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
1629 * driver has yet to bring up the EVB port. See bug 56147. In this case,
1630 * retry the request several times after waiting a while. The wait time
1631 * between retries starts small (10ms) and exponentially increases.
1632 * Total wait time is a little over two seconds. Retry logic in the
1633 * client driver may mean this whole loop is repeated if it continues to
1638 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
1639 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
1642 * Do not retry alloc for PF, or for other errors on
1648 /* VF startup before PF is ready. Retry allocation. */
1650 /* Too many attempts */
1654 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
1655 EFSYS_SLEEP(delay_us);
1657 if (delay_us < 500000)
1661 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
1662 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
1677 ef10_nic_free_piobufs(enp);
1680 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1685 __checkReturn efx_rc_t
1686 ef10_nic_get_vi_pool(
1687 __in efx_nic_t *enp,
1688 __out uint32_t *vi_countp)
1690 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1691 enp->en_family == EFX_FAMILY_MEDFORD);
1694 * Report VIs that the client driver can use.
1695 * Do not include VIs used for PIO buffer writes.
1697 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
1702 __checkReturn efx_rc_t
1703 ef10_nic_get_bar_region(
1704 __in efx_nic_t *enp,
1705 __in efx_nic_region_t region,
1706 __out uint32_t *offsetp,
1707 __out size_t *sizep)
1711 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1712 enp->en_family == EFX_FAMILY_MEDFORD);
1715 * TODO: Specify host memory mapping alignment and granularity
1716 * in efx_drv_limits_t so that they can be taken into account
1717 * when allocating extra VIs for PIO writes.
1721 /* UC mapped memory BAR region for VI registers */
1722 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
1723 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
1726 case EFX_REGION_PIO_WRITE_VI:
1727 /* WC mapped memory BAR region for piobuf writes */
1728 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
1729 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
1740 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1747 __in efx_nic_t *enp)
1752 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
1753 enp->en_vport_id = 0;
1755 /* Unlink piobufs from extra VIs in WC mapping */
1756 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1757 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1758 rc = efx_mcdi_unlink_piobuf(enp,
1759 enp->en_arch.ef10.ena_pio_write_vi_base + i);
1765 ef10_nic_free_piobufs(enp);
1767 (void) efx_mcdi_free_vis(enp);
1768 enp->en_arch.ef10.ena_vi_count = 0;
1773 __in efx_nic_t *enp)
1775 (void) efx_mcdi_drv_attach(enp, B_FALSE);
1780 __checkReturn efx_rc_t
1781 ef10_nic_register_test(
1782 __in efx_nic_t *enp)
1787 _NOTE(ARGUNUSED(enp))
1788 _NOTE(CONSTANTCONDITION)
1798 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1803 #endif /* EFSYS_OPT_DIAG */
1806 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */