1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
13 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
15 #include "ef10_tlv_layout.h"
17 __checkReturn efx_rc_t
18 efx_mcdi_get_port_assignment(
20 __out uint32_t *portp)
23 uint8_t payload[MAX(MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
24 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN)];
27 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
28 enp->en_family == EFX_FAMILY_MEDFORD ||
29 enp->en_family == EFX_FAMILY_MEDFORD2);
31 (void) memset(payload, 0, sizeof (payload));
32 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
33 req.emr_in_buf = payload;
34 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
35 req.emr_out_buf = payload;
36 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
38 efx_mcdi_execute(enp, &req);
40 if (req.emr_rc != 0) {
45 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
50 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
57 EFSYS_PROBE1(fail1, efx_rc_t, rc);
62 __checkReturn efx_rc_t
63 efx_mcdi_get_port_modes(
65 __out uint32_t *modesp,
66 __out_opt uint32_t *current_modep)
69 uint8_t payload[MAX(MC_CMD_GET_PORT_MODES_IN_LEN,
70 MC_CMD_GET_PORT_MODES_OUT_LEN)];
73 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
74 enp->en_family == EFX_FAMILY_MEDFORD ||
75 enp->en_family == EFX_FAMILY_MEDFORD2);
77 (void) memset(payload, 0, sizeof (payload));
78 req.emr_cmd = MC_CMD_GET_PORT_MODES;
79 req.emr_in_buf = payload;
80 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
81 req.emr_out_buf = payload;
82 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
84 efx_mcdi_execute(enp, &req);
86 if (req.emr_rc != 0) {
92 * Require only Modes and DefaultMode fields, unless the current mode
93 * was requested (CurrentMode field was added for Medford).
95 if (req.emr_out_length_used <
96 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
100 if ((current_modep != NULL) && (req.emr_out_length_used <
101 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) {
106 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
108 if (current_modep != NULL) {
109 *current_modep = MCDI_OUT_DWORD(req,
110 GET_PORT_MODES_OUT_CURRENT_MODE);
120 EFSYS_PROBE1(fail1, efx_rc_t, rc);
125 __checkReturn efx_rc_t
126 ef10_nic_get_port_mode_bandwidth(
127 __in uint32_t port_mode,
128 __out uint32_t *bandwidth_mbpsp)
134 case TLV_PORT_MODE_10G:
137 case TLV_PORT_MODE_10G_10G:
138 bandwidth = 10000 * 2;
140 case TLV_PORT_MODE_10G_10G_10G_10G:
141 case TLV_PORT_MODE_10G_10G_10G_10G_Q:
142 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2:
143 case TLV_PORT_MODE_10G_10G_10G_10G_Q2:
144 bandwidth = 10000 * 4;
146 case TLV_PORT_MODE_40G:
149 case TLV_PORT_MODE_40G_40G:
150 bandwidth = 40000 * 2;
152 case TLV_PORT_MODE_40G_10G_10G:
153 case TLV_PORT_MODE_10G_10G_40G:
154 bandwidth = 40000 + (10000 * 2);
161 *bandwidth_mbpsp = bandwidth;
166 EFSYS_PROBE1(fail1, efx_rc_t, rc);
171 static __checkReturn efx_rc_t
172 efx_mcdi_vadaptor_alloc(
174 __in uint32_t port_id)
177 uint8_t payload[MAX(MC_CMD_VADAPTOR_ALLOC_IN_LEN,
178 MC_CMD_VADAPTOR_ALLOC_OUT_LEN)];
181 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
183 (void) memset(payload, 0, sizeof (payload));
184 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
185 req.emr_in_buf = payload;
186 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
187 req.emr_out_buf = payload;
188 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
190 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
191 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
192 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
193 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
195 efx_mcdi_execute(enp, &req);
197 if (req.emr_rc != 0) {
205 EFSYS_PROBE1(fail1, efx_rc_t, rc);
210 static __checkReturn efx_rc_t
211 efx_mcdi_vadaptor_free(
213 __in uint32_t port_id)
216 uint8_t payload[MAX(MC_CMD_VADAPTOR_FREE_IN_LEN,
217 MC_CMD_VADAPTOR_FREE_OUT_LEN)];
220 (void) memset(payload, 0, sizeof (payload));
221 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
222 req.emr_in_buf = payload;
223 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
224 req.emr_out_buf = payload;
225 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
227 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
229 efx_mcdi_execute(enp, &req);
231 if (req.emr_rc != 0) {
239 EFSYS_PROBE1(fail1, efx_rc_t, rc);
244 __checkReturn efx_rc_t
245 efx_mcdi_get_mac_address_pf(
247 __out_ecount_opt(6) uint8_t mac_addrp[6])
250 uint8_t payload[MAX(MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
251 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)];
254 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
255 enp->en_family == EFX_FAMILY_MEDFORD ||
256 enp->en_family == EFX_FAMILY_MEDFORD2);
258 (void) memset(payload, 0, sizeof (payload));
259 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
260 req.emr_in_buf = payload;
261 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
262 req.emr_out_buf = payload;
263 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
265 efx_mcdi_execute(enp, &req);
267 if (req.emr_rc != 0) {
272 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
277 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
282 if (mac_addrp != NULL) {
285 addrp = MCDI_OUT2(req, uint8_t,
286 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
288 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
298 EFSYS_PROBE1(fail1, efx_rc_t, rc);
303 __checkReturn efx_rc_t
304 efx_mcdi_get_mac_address_vf(
306 __out_ecount_opt(6) uint8_t mac_addrp[6])
309 uint8_t payload[MAX(MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
310 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX)];
313 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
314 enp->en_family == EFX_FAMILY_MEDFORD ||
315 enp->en_family == EFX_FAMILY_MEDFORD2);
317 (void) memset(payload, 0, sizeof (payload));
318 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
319 req.emr_in_buf = payload;
320 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
321 req.emr_out_buf = payload;
322 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
324 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
325 EVB_PORT_ID_ASSIGNED);
327 efx_mcdi_execute(enp, &req);
329 if (req.emr_rc != 0) {
334 if (req.emr_out_length_used <
335 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
340 if (MCDI_OUT_DWORD(req,
341 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
346 if (mac_addrp != NULL) {
349 addrp = MCDI_OUT2(req, uint8_t,
350 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
352 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
362 EFSYS_PROBE1(fail1, efx_rc_t, rc);
367 __checkReturn efx_rc_t
370 __out uint32_t *sys_freqp,
371 __out uint32_t *dpcpu_freqp)
374 uint8_t payload[MAX(MC_CMD_GET_CLOCK_IN_LEN,
375 MC_CMD_GET_CLOCK_OUT_LEN)];
378 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
379 enp->en_family == EFX_FAMILY_MEDFORD ||
380 enp->en_family == EFX_FAMILY_MEDFORD2);
382 (void) memset(payload, 0, sizeof (payload));
383 req.emr_cmd = MC_CMD_GET_CLOCK;
384 req.emr_in_buf = payload;
385 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
386 req.emr_out_buf = payload;
387 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
389 efx_mcdi_execute(enp, &req);
391 if (req.emr_rc != 0) {
396 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
401 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
402 if (*sys_freqp == 0) {
406 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
407 if (*dpcpu_freqp == 0) {
421 EFSYS_PROBE1(fail1, efx_rc_t, rc);
426 __checkReturn efx_rc_t
427 efx_mcdi_get_rxdp_config(
429 __out uint32_t *end_paddingp)
432 uint8_t payload[MAX(MC_CMD_GET_RXDP_CONFIG_IN_LEN,
433 MC_CMD_GET_RXDP_CONFIG_OUT_LEN)];
434 uint32_t end_padding;
437 memset(payload, 0, sizeof (payload));
438 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
439 req.emr_in_buf = payload;
440 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
441 req.emr_out_buf = payload;
442 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
444 efx_mcdi_execute(enp, &req);
445 if (req.emr_rc != 0) {
450 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
451 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
452 /* RX DMA end padding is disabled */
455 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
456 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
457 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
460 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
463 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
472 *end_paddingp = end_padding;
479 EFSYS_PROBE1(fail1, efx_rc_t, rc);
484 __checkReturn efx_rc_t
485 efx_mcdi_get_vector_cfg(
487 __out_opt uint32_t *vec_basep,
488 __out_opt uint32_t *pf_nvecp,
489 __out_opt uint32_t *vf_nvecp)
492 uint8_t payload[MAX(MC_CMD_GET_VECTOR_CFG_IN_LEN,
493 MC_CMD_GET_VECTOR_CFG_OUT_LEN)];
496 (void) memset(payload, 0, sizeof (payload));
497 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
498 req.emr_in_buf = payload;
499 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
500 req.emr_out_buf = payload;
501 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
503 efx_mcdi_execute(enp, &req);
505 if (req.emr_rc != 0) {
510 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
515 if (vec_basep != NULL)
516 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
517 if (pf_nvecp != NULL)
518 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
519 if (vf_nvecp != NULL)
520 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
527 EFSYS_PROBE1(fail1, efx_rc_t, rc);
532 static __checkReturn efx_rc_t
535 __in uint32_t min_vi_count,
536 __in uint32_t max_vi_count,
537 __out uint32_t *vi_basep,
538 __out uint32_t *vi_countp,
539 __out uint32_t *vi_shiftp)
542 uint8_t payload[MAX(MC_CMD_ALLOC_VIS_IN_LEN,
543 MC_CMD_ALLOC_VIS_EXT_OUT_LEN)];
546 if (vi_countp == NULL) {
551 (void) memset(payload, 0, sizeof (payload));
552 req.emr_cmd = MC_CMD_ALLOC_VIS;
553 req.emr_in_buf = payload;
554 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
555 req.emr_out_buf = payload;
556 req.emr_out_length = MC_CMD_ALLOC_VIS_EXT_OUT_LEN;
558 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
559 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
561 efx_mcdi_execute(enp, &req);
563 if (req.emr_rc != 0) {
568 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
573 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
574 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
576 /* Report VI_SHIFT if available (always zero for Huntington) */
577 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
580 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
589 EFSYS_PROBE1(fail1, efx_rc_t, rc);
595 static __checkReturn efx_rc_t
602 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
603 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
605 req.emr_cmd = MC_CMD_FREE_VIS;
606 req.emr_in_buf = NULL;
607 req.emr_in_length = 0;
608 req.emr_out_buf = NULL;
609 req.emr_out_length = 0;
611 efx_mcdi_execute_quiet(enp, &req);
613 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
614 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
622 EFSYS_PROBE1(fail1, efx_rc_t, rc);
628 static __checkReturn efx_rc_t
629 efx_mcdi_alloc_piobuf(
631 __out efx_piobuf_handle_t *handlep)
634 uint8_t payload[MAX(MC_CMD_ALLOC_PIOBUF_IN_LEN,
635 MC_CMD_ALLOC_PIOBUF_OUT_LEN)];
638 if (handlep == NULL) {
643 (void) memset(payload, 0, sizeof (payload));
644 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
645 req.emr_in_buf = payload;
646 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
647 req.emr_out_buf = payload;
648 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
650 efx_mcdi_execute_quiet(enp, &req);
652 if (req.emr_rc != 0) {
657 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
662 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
671 EFSYS_PROBE1(fail1, efx_rc_t, rc);
676 static __checkReturn efx_rc_t
677 efx_mcdi_free_piobuf(
679 __in efx_piobuf_handle_t handle)
682 uint8_t payload[MAX(MC_CMD_FREE_PIOBUF_IN_LEN,
683 MC_CMD_FREE_PIOBUF_OUT_LEN)];
686 (void) memset(payload, 0, sizeof (payload));
687 req.emr_cmd = MC_CMD_FREE_PIOBUF;
688 req.emr_in_buf = payload;
689 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
690 req.emr_out_buf = payload;
691 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
693 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
695 efx_mcdi_execute_quiet(enp, &req);
697 if (req.emr_rc != 0) {
705 EFSYS_PROBE1(fail1, efx_rc_t, rc);
710 static __checkReturn efx_rc_t
711 efx_mcdi_link_piobuf(
713 __in uint32_t vi_index,
714 __in efx_piobuf_handle_t handle)
717 uint8_t payload[MAX(MC_CMD_LINK_PIOBUF_IN_LEN,
718 MC_CMD_LINK_PIOBUF_OUT_LEN)];
721 (void) memset(payload, 0, sizeof (payload));
722 req.emr_cmd = MC_CMD_LINK_PIOBUF;
723 req.emr_in_buf = payload;
724 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
725 req.emr_out_buf = payload;
726 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
728 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
729 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
731 efx_mcdi_execute(enp, &req);
733 if (req.emr_rc != 0) {
741 EFSYS_PROBE1(fail1, efx_rc_t, rc);
746 static __checkReturn efx_rc_t
747 efx_mcdi_unlink_piobuf(
749 __in uint32_t vi_index)
752 uint8_t payload[MAX(MC_CMD_UNLINK_PIOBUF_IN_LEN,
753 MC_CMD_UNLINK_PIOBUF_OUT_LEN)];
756 (void) memset(payload, 0, sizeof (payload));
757 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
758 req.emr_in_buf = payload;
759 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
760 req.emr_out_buf = payload;
761 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
763 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
765 efx_mcdi_execute_quiet(enp, &req);
767 if (req.emr_rc != 0) {
775 EFSYS_PROBE1(fail1, efx_rc_t, rc);
781 ef10_nic_alloc_piobufs(
783 __in uint32_t max_piobuf_count)
785 efx_piobuf_handle_t *handlep;
788 EFSYS_ASSERT3U(max_piobuf_count, <=,
789 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
791 enp->en_arch.ef10.ena_piobuf_count = 0;
793 for (i = 0; i < max_piobuf_count; i++) {
794 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
796 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0)
799 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
800 enp->en_arch.ef10.ena_piobuf_count++;
806 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
807 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
809 efx_mcdi_free_piobuf(enp, *handlep);
810 *handlep = EFX_PIOBUF_HANDLE_INVALID;
812 enp->en_arch.ef10.ena_piobuf_count = 0;
817 ef10_nic_free_piobufs(
820 efx_piobuf_handle_t *handlep;
823 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
824 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
826 efx_mcdi_free_piobuf(enp, *handlep);
827 *handlep = EFX_PIOBUF_HANDLE_INVALID;
829 enp->en_arch.ef10.ena_piobuf_count = 0;
832 /* Sub-allocate a block from a piobuf */
833 __checkReturn efx_rc_t
835 __inout efx_nic_t *enp,
836 __out uint32_t *bufnump,
837 __out efx_piobuf_handle_t *handlep,
838 __out uint32_t *blknump,
839 __out uint32_t *offsetp,
842 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
843 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
844 uint32_t blk_per_buf;
848 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
849 enp->en_family == EFX_FAMILY_MEDFORD ||
850 enp->en_family == EFX_FAMILY_MEDFORD2);
851 EFSYS_ASSERT(bufnump);
852 EFSYS_ASSERT(handlep);
853 EFSYS_ASSERT(blknump);
854 EFSYS_ASSERT(offsetp);
857 if ((edcp->edc_pio_alloc_size == 0) ||
858 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
862 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
864 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
865 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
870 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
871 for (blk = 0; blk < blk_per_buf; blk++) {
872 if ((*map & (1u << blk)) == 0) {
882 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
885 *sizep = edcp->edc_pio_alloc_size;
886 *offsetp = blk * (*sizep);
893 EFSYS_PROBE1(fail1, efx_rc_t, rc);
898 /* Free a piobuf sub-allocated block */
899 __checkReturn efx_rc_t
901 __inout efx_nic_t *enp,
902 __in uint32_t bufnum,
903 __in uint32_t blknum)
908 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
909 (blknum >= (8 * sizeof (*map)))) {
914 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
915 if ((*map & (1u << blknum)) == 0) {
919 *map &= ~(1u << blknum);
926 EFSYS_PROBE1(fail1, efx_rc_t, rc);
931 __checkReturn efx_rc_t
933 __inout efx_nic_t *enp,
934 __in uint32_t vi_index,
935 __in efx_piobuf_handle_t handle)
937 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
940 __checkReturn efx_rc_t
942 __inout efx_nic_t *enp,
943 __in uint32_t vi_index)
945 return (efx_mcdi_unlink_piobuf(enp, vi_index));
948 static __checkReturn efx_rc_t
949 ef10_mcdi_get_pf_count(
951 __out uint32_t *pf_countp)
954 uint8_t payload[MAX(MC_CMD_GET_PF_COUNT_IN_LEN,
955 MC_CMD_GET_PF_COUNT_OUT_LEN)];
958 (void) memset(payload, 0, sizeof (payload));
959 req.emr_cmd = MC_CMD_GET_PF_COUNT;
960 req.emr_in_buf = payload;
961 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN;
962 req.emr_out_buf = payload;
963 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN;
965 efx_mcdi_execute(enp, &req);
967 if (req.emr_rc != 0) {
972 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) {
977 *pf_countp = *MCDI_OUT(req, uint8_t,
978 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST);
980 EFSYS_ASSERT(*pf_countp != 0);
987 EFSYS_PROBE1(fail1, efx_rc_t, rc);
992 static __checkReturn efx_rc_t
993 ef10_get_datapath_caps(
996 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
998 uint8_t payload[MAX(MC_CMD_GET_CAPABILITIES_IN_LEN,
999 MC_CMD_GET_CAPABILITIES_V4_OUT_LEN)];
1002 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0)
1006 (void) memset(payload, 0, sizeof (payload));
1007 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
1008 req.emr_in_buf = payload;
1009 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
1010 req.emr_out_buf = payload;
1011 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V4_OUT_LEN;
1013 efx_mcdi_execute_quiet(enp, &req);
1015 if (req.emr_rc != 0) {
1020 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
1025 #define CAP_FLAGS1(_req, _flag) \
1026 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_OUT_FLAGS1) & \
1027 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN)))
1029 #define CAP_FLAGS2(_req, _flag) \
1030 (((_req).emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) && \
1031 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V2_OUT_FLAGS2) & \
1032 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN))))
1035 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
1036 * We only support the 14 byte prefix here.
1038 if (CAP_FLAGS1(req, RX_PREFIX_LEN_14) == 0) {
1042 encp->enc_rx_prefix_size = 14;
1044 /* Check if the firmware supports additional RSS modes */
1045 if (CAP_FLAGS1(req, ADDITIONAL_RSS_MODES))
1046 encp->enc_rx_scale_additional_modes_supported = B_TRUE;
1048 encp->enc_rx_scale_additional_modes_supported = B_FALSE;
1050 /* Check if the firmware supports TSO */
1051 if (CAP_FLAGS1(req, TX_TSO))
1052 encp->enc_fw_assisted_tso_enabled = B_TRUE;
1054 encp->enc_fw_assisted_tso_enabled = B_FALSE;
1056 /* Check if the firmware supports FATSOv2 */
1057 if (CAP_FLAGS2(req, TX_TSO_V2)) {
1058 encp->enc_fw_assisted_tso_v2_enabled = B_TRUE;
1059 encp->enc_fw_assisted_tso_v2_n_contexts = MCDI_OUT_WORD(req,
1060 GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS);
1062 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
1063 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
1066 /* Check if the firmware supports FATSOv2 encap */
1067 if (CAP_FLAGS2(req, TX_TSO_V2_ENCAP))
1068 encp->enc_fw_assisted_tso_v2_encap_enabled = B_TRUE;
1070 encp->enc_fw_assisted_tso_v2_encap_enabled = B_FALSE;
1072 /* Check if the firmware has vadapter/vport/vswitch support */
1073 if (CAP_FLAGS1(req, EVB))
1074 encp->enc_datapath_cap_evb = B_TRUE;
1076 encp->enc_datapath_cap_evb = B_FALSE;
1078 /* Check if the firmware supports VLAN insertion */
1079 if (CAP_FLAGS1(req, TX_VLAN_INSERTION))
1080 encp->enc_hw_tx_insert_vlan_enabled = B_TRUE;
1082 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
1084 /* Check if the firmware supports RX event batching */
1085 if (CAP_FLAGS1(req, RX_BATCHING))
1086 encp->enc_rx_batching_enabled = B_TRUE;
1088 encp->enc_rx_batching_enabled = B_FALSE;
1091 * Even if batching isn't reported as supported, we may still get
1092 * batched events (see bug61153).
1094 encp->enc_rx_batch_max = 16;
1096 /* Check if the firmware supports disabling scatter on RXQs */
1097 if (CAP_FLAGS1(req, RX_DISABLE_SCATTER))
1098 encp->enc_rx_disable_scatter_supported = B_TRUE;
1100 encp->enc_rx_disable_scatter_supported = B_FALSE;
1102 /* Check if the firmware supports packed stream mode */
1103 if (CAP_FLAGS1(req, RX_PACKED_STREAM))
1104 encp->enc_rx_packed_stream_supported = B_TRUE;
1106 encp->enc_rx_packed_stream_supported = B_FALSE;
1109 * Check if the firmware supports configurable buffer sizes
1110 * for packed stream mode (otherwise buffer size is 1Mbyte)
1112 if (CAP_FLAGS1(req, RX_PACKED_STREAM_VAR_BUFFERS))
1113 encp->enc_rx_var_packed_stream_supported = B_TRUE;
1115 encp->enc_rx_var_packed_stream_supported = B_FALSE;
1117 /* Check if the firmware supports FW subvariant w/o Tx checksumming */
1118 if (CAP_FLAGS2(req, FW_SUBVARIANT_NO_TX_CSUM))
1119 encp->enc_fw_subvariant_no_tx_csum_supported = B_TRUE;
1121 encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE;
1123 /* Check if the firmware supports set mac with running filters */
1124 if (CAP_FLAGS1(req, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED))
1125 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
1127 encp->enc_allow_set_mac_with_installed_filters = B_FALSE;
1130 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows
1131 * specifying which parameters to configure.
1133 if (CAP_FLAGS1(req, SET_MAC_ENHANCED))
1134 encp->enc_enhanced_set_mac_supported = B_TRUE;
1136 encp->enc_enhanced_set_mac_supported = B_FALSE;
1139 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows
1140 * us to let the firmware choose the settings to use on an EVQ.
1142 if (CAP_FLAGS2(req, INIT_EVQ_V2))
1143 encp->enc_init_evq_v2_supported = B_TRUE;
1145 encp->enc_init_evq_v2_supported = B_FALSE;
1148 * Check if firmware-verified NVRAM updates must be used.
1150 * The firmware trusted installer requires all NVRAM updates to use
1151 * version 2 of MC_CMD_NVRAM_UPDATE_START (to enable verified update)
1152 * and version 2 of MC_CMD_NVRAM_UPDATE_FINISH (to verify the updated
1153 * partition and report the result).
1155 if (CAP_FLAGS2(req, NVRAM_UPDATE_REPORT_VERIFY_RESULT))
1156 encp->enc_nvram_update_verify_result_supported = B_TRUE;
1158 encp->enc_nvram_update_verify_result_supported = B_FALSE;
1161 * Check if firmware provides packet memory and Rx datapath
1164 if (CAP_FLAGS1(req, PM_AND_RXDP_COUNTERS))
1165 encp->enc_pm_and_rxdp_counters = B_TRUE;
1167 encp->enc_pm_and_rxdp_counters = B_FALSE;
1170 * Check if the 40G MAC hardware is capable of reporting
1171 * statistics for Tx size bins.
1173 if (CAP_FLAGS2(req, MAC_STATS_40G_TX_SIZE_BINS))
1174 encp->enc_mac_stats_40g_tx_size_bins = B_TRUE;
1176 encp->enc_mac_stats_40g_tx_size_bins = B_FALSE;
1179 * Check if firmware supports VXLAN and NVGRE tunnels.
1180 * The capability indicates Geneve protocol support as well.
1182 if (CAP_FLAGS1(req, VXLAN_NVGRE)) {
1183 encp->enc_tunnel_encapsulations_supported =
1184 (1u << EFX_TUNNEL_PROTOCOL_VXLAN) |
1185 (1u << EFX_TUNNEL_PROTOCOL_GENEVE) |
1186 (1u << EFX_TUNNEL_PROTOCOL_NVGRE);
1188 EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES ==
1189 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
1190 encp->enc_tunnel_config_udp_entries_max =
1191 EFX_TUNNEL_MAXNENTRIES;
1193 encp->enc_tunnel_config_udp_entries_max = 0;
1197 * Check if firmware reports the VI window mode.
1198 * Medford2 has a variable VI window size (8K, 16K or 64K).
1199 * Medford and Huntington have a fixed 8K VI window size.
1201 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
1203 MCDI_OUT_BYTE(req, GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
1206 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
1207 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1209 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
1210 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_16K;
1212 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
1213 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_64K;
1216 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1219 } else if ((enp->en_family == EFX_FAMILY_HUNTINGTON) ||
1220 (enp->en_family == EFX_FAMILY_MEDFORD)) {
1221 /* Huntington and Medford have fixed 8K window size */
1222 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1224 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1227 /* Check if firmware supports extended MAC stats. */
1228 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
1229 /* Extended stats buffer supported */
1230 encp->enc_mac_stats_nstats = MCDI_OUT_WORD(req,
1231 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
1233 /* Use Siena-compatible legacy MAC stats */
1234 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS;
1237 if (encp->enc_mac_stats_nstats >= MC_CMD_MAC_NSTATS_V2)
1238 encp->enc_fec_counters = B_TRUE;
1240 encp->enc_fec_counters = B_FALSE;
1254 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1260 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
1261 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
1262 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
1263 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
1264 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
1265 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
1266 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
1267 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
1268 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
1269 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
1270 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
1271 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
1273 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
1276 __checkReturn efx_rc_t
1277 ef10_get_privilege_mask(
1278 __in efx_nic_t *enp,
1279 __out uint32_t *maskp)
1281 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1285 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1290 /* Fallback for old firmware without privilege mask support */
1291 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1292 /* Assume PF has admin privilege */
1293 mask = EF10_LEGACY_PF_PRIVILEGE_MASK;
1295 /* VF is always unprivileged by default */
1296 mask = EF10_LEGACY_VF_PRIVILEGE_MASK;
1305 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1312 * Table of mapping schemes from port number to external number.
1314 * Each port number ultimately corresponds to a connector: either as part of
1315 * a cable assembly attached to a module inserted in an SFP+/QSFP+ cage on
1316 * the board, or fixed to the board (e.g. 10GBASE-T magjack on SFN5121T
1317 * "Salina"). In general:
1319 * Port number (0-based)
1321 * port mapping (n:1)
1324 * External port number (normally 1-based)
1326 * fixed (1:1) or cable assembly (1:m)
1331 * The external numbering refers to the cages or magjacks on the board,
1332 * as visibly annotated on the board or back panel. This table describes
1333 * how to determine which external cage/magjack corresponds to the port
1334 * numbers used by the driver.
1336 * The count of adjacent port numbers that map to each external number,
1337 * and the offset in the numbering, is determined by the chip family and
1338 * current port mode.
1340 * For the Huntington family, the current port mode cannot be discovered,
1341 * but a single mapping is used by all modes for a given chip variant,
1342 * so the mapping used is instead the last match in the table to the full
1343 * set of port modes to which the NIC can be configured. Therefore the
1344 * ordering of entries in the mapping table is significant.
1346 static struct ef10_external_port_map_s {
1347 efx_family_t family;
1348 uint32_t modes_mask;
1351 } __ef10_external_port_mappings[] = {
1353 * Modes used by Huntington family controllers where each port
1354 * number maps to a separate cage.
1355 * SFN7x22F (Torino):
1365 EFX_FAMILY_HUNTINGTON,
1366 (1U << TLV_PORT_MODE_10G) | /* mode 0 */
1367 (1U << TLV_PORT_MODE_10G_10G) | /* mode 2 */
1368 (1U << TLV_PORT_MODE_10G_10G_10G_10G), /* mode 4 */
1369 1, /* ports per cage */
1373 * Modes which for Huntington identify a chip variant where 2
1374 * adjacent port numbers map to each cage.
1382 EFX_FAMILY_HUNTINGTON,
1383 (1U << TLV_PORT_MODE_40G) | /* mode 1 */
1384 (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
1385 (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
1386 (1U << TLV_PORT_MODE_10G_10G_40G), /* mode 7 */
1387 2, /* ports per cage */
1391 * Modes that on Medford allocate each port number to a separate
1400 (1U << TLV_PORT_MODE_10G) | /* mode 0 */
1401 (1U << TLV_PORT_MODE_10G_10G), /* mode 2 */
1402 1, /* ports per cage */
1406 * Modes that on Medford allocate 2 adjacent port numbers to each
1415 (1U << TLV_PORT_MODE_40G) | /* mode 1 */
1416 (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
1417 (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
1418 (1U << TLV_PORT_MODE_10G_10G_40G) | /* mode 7 */
1419 /* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */
1420 (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */
1421 2, /* ports per cage */
1425 * Modes that on Medford allocate 4 adjacent port numbers to each
1426 * connector, starting on cage 1.
1434 (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q) | /* mode 5 */
1435 /* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */
1436 (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1), /* mode 4 */
1437 4, /* ports per cage */
1441 * Modes that on Medford allocate 4 adjacent port numbers to each
1442 * connector, starting on cage 2.
1450 (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q2), /* mode 8 */
1451 4, /* ports per cage */
1455 * Modes that on Medford2 allocate each port number to a separate
1463 EFX_FAMILY_MEDFORD2,
1464 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1465 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1466 (1U << TLV_PORT_MODE_1x1_1x1) | /* mode 2 */
1467 (1U << TLV_PORT_MODE_1x2_NA) | /* mode 10 */
1468 (1U << TLV_PORT_MODE_1x2_1x2) | /* mode 12 */
1469 (1U << TLV_PORT_MODE_1x4_1x2) | /* mode 15 */
1470 (1U << TLV_PORT_MODE_1x2_1x4), /* mode 16 */
1471 1, /* ports per cage */
1475 * FIXME: Some port modes are not representable in this mapping:
1476 * - TLV_PORT_MODE_1x2_2x1 (mode 17):
1482 * Modes that on Medford2 allocate 2 adjacent port numbers to each
1483 * cage, starting on cage 1.
1490 EFX_FAMILY_MEDFORD2,
1491 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
1492 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 4 */
1493 (1U << TLV_PORT_MODE_1x4_2x1) | /* mode 6 */
1494 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
1495 (1U << TLV_PORT_MODE_2x2_NA) | /* mode 13 */
1496 (1U << TLV_PORT_MODE_2x1_1x2), /* mode 18 */
1497 2, /* ports per cage */
1501 * Modes that on Medford2 allocate 2 adjacent port numbers to each
1502 * cage, starting on cage 2.
1507 EFX_FAMILY_MEDFORD2,
1508 (1U << TLV_PORT_MODE_NA_2x2), /* mode 14 */
1509 2, /* ports per cage */
1513 * Modes that on Medford2 allocate 4 adjacent port numbers to each
1514 * connector, starting on cage 1.
1521 EFX_FAMILY_MEDFORD2,
1522 (1U << TLV_PORT_MODE_4x1_NA), /* mode 5 */
1523 4, /* ports per cage */
1527 * Modes that on Medford2 allocate 4 adjacent port numbers to each
1528 * connector, starting on cage 2.
1535 EFX_FAMILY_MEDFORD2,
1536 (1U << TLV_PORT_MODE_NA_4x1) | /* mode 8 */
1537 (1U << TLV_PORT_MODE_NA_1x2), /* mode 11 */
1538 4, /* ports per cage */
1543 static __checkReturn efx_rc_t
1544 ef10_external_port_mapping(
1545 __in efx_nic_t *enp,
1547 __out uint8_t *external_portp)
1551 uint32_t port_modes;
1554 int32_t count = 1; /* Default 1-1 mapping */
1555 int32_t offset = 1; /* Default starting external port number */
1557 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t)) != 0) {
1559 * No current port mode information (i.e. Huntington)
1560 * - infer mapping from available modes
1562 if ((rc = efx_mcdi_get_port_modes(enp,
1563 &port_modes, NULL)) != 0) {
1565 * No port mode information available
1566 * - use default mapping
1571 /* Only need to scan the current mode */
1572 port_modes = 1 << current;
1576 * Infer the internal port -> external number mapping from
1577 * the possible port modes for this NIC.
1579 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1580 struct ef10_external_port_map_s *eepmp =
1581 &__ef10_external_port_mappings[i];
1582 if (eepmp->family != enp->en_family)
1584 matches = (eepmp->modes_mask & port_modes);
1587 * Some modes match. For some Huntington boards
1588 * there will be multiple matches. The mapping on the
1589 * last match is used.
1591 count = eepmp->count;
1592 offset = eepmp->offset;
1593 port_modes &= ~matches;
1597 if (port_modes != 0) {
1598 /* Some advertised modes are not supported */
1605 * Scale as required by last matched mode and then convert to
1606 * correctly offset numbering
1608 *external_portp = (uint8_t)((port / count) + offset);
1612 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1617 static __checkReturn efx_rc_t
1619 __in efx_nic_t *enp)
1621 const efx_nic_ops_t *enop = enp->en_enop;
1622 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
1623 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1624 ef10_link_state_t els;
1625 efx_port_t *epp = &(enp->en_port);
1626 uint32_t board_type = 0;
1627 uint32_t base, nvec;
1632 uint8_t mac_addr[6] = { 0 };
1635 /* Get the (zero-based) MCDI port number */
1636 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
1639 /* EFX MCDI interface uses one-based port numbers */
1640 emip->emi_port = port + 1;
1642 if ((rc = ef10_external_port_mapping(enp, port,
1643 &encp->enc_external_port)) != 0)
1647 * Get PCIe function number from firmware (used for
1648 * per-function privilege and dynamic config info).
1649 * - PCIe PF: pf = PF number, vf = 0xffff.
1650 * - PCIe VF: pf = parent PF, vf = VF number.
1652 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
1658 /* MAC address for this function */
1659 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1660 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
1661 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
1663 * Disable static config checking, ONLY for manufacturing test
1664 * and setup at the factory, to allow the static config to be
1667 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1668 if ((rc == 0) && (mac_addr[0] & 0x02)) {
1670 * If the static config does not include a global MAC
1671 * address pool then the board may return a locally
1672 * administered MAC address (this should only happen on
1673 * incorrectly programmed boards).
1677 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1679 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
1684 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
1686 /* Board configuration (legacy) */
1687 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
1689 /* Unprivileged functions may not be able to read board cfg */
1696 encp->enc_board_type = board_type;
1697 encp->enc_clk_mult = 1; /* not used for EF10 */
1699 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
1700 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
1703 /* Obtain the default PHY advertised capabilities */
1704 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
1706 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
1707 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
1709 /* Check capabilities of running datapath firmware */
1710 if ((rc = ef10_get_datapath_caps(enp)) != 0)
1713 /* Alignment for WPTR updates */
1714 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
1717 * Maximum number of exclusive RSS contexts. EF10 hardware supports 64
1718 * in total, but 6 are reserved for shared contexts. They are a global
1719 * resource so not all may be available.
1721 encp->enc_rx_scale_max_exclusive_contexts = 64 - 6;
1723 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
1724 /* No boundary crossing limits */
1725 encp->enc_tx_dma_desc_boundary = 0;
1728 * Maximum number of bytes into the frame the TCP header can start for
1729 * firmware assisted TSO to work.
1731 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
1734 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
1735 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
1736 * resources (allocated to this PCIe function), which is zero until
1737 * after we have allocated VIs.
1739 encp->enc_evq_limit = 1024;
1740 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
1741 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
1743 encp->enc_buftbl_limit = 0xFFFFFFFF;
1745 /* Get interrupt vector limits */
1746 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
1747 if (EFX_PCI_FUNCTION_IS_PF(encp))
1750 /* Ignore error (cannot query vector limits from a VF). */
1754 encp->enc_intr_vec_base = base;
1755 encp->enc_intr_limit = nvec;
1758 * Get the current privilege mask. Note that this may be modified
1759 * dynamically, so this value is informational only. DO NOT use
1760 * the privilege mask to check for sufficient privileges, as that
1761 * can result in time-of-check/time-of-use bugs.
1763 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
1765 encp->enc_privilege_mask = mask;
1767 /* Get remaining controller-specific board config */
1768 if ((rc = enop->eno_board_cfg(enp)) != 0)
1775 EFSYS_PROBE(fail11);
1777 EFSYS_PROBE(fail10);
1795 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1800 __checkReturn efx_rc_t
1802 __in efx_nic_t *enp)
1804 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1805 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1808 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1809 enp->en_family == EFX_FAMILY_MEDFORD ||
1810 enp->en_family == EFX_FAMILY_MEDFORD2);
1812 /* Read and clear any assertion state */
1813 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1816 /* Exit the assertion handler */
1817 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1821 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
1824 if ((rc = ef10_nic_board_cfg(enp)) != 0)
1828 * Set default driver config limits (based on board config).
1830 * FIXME: For now allocate a fixed number of VIs which is likely to be
1831 * sufficient and small enough to allow multiple functions on the same
1834 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
1835 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
1837 /* The client driver must configure and enable PIO buffer support */
1838 edcp->edc_max_piobuf_count = 0;
1839 edcp->edc_pio_alloc_size = 0;
1841 #if EFSYS_OPT_MAC_STATS
1842 /* Wipe the MAC statistics */
1843 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
1847 #if EFSYS_OPT_LOOPBACK
1848 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
1852 #if EFSYS_OPT_MON_STATS
1853 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
1854 /* Unprivileged functions do not have access to sensors */
1860 encp->enc_features = enp->en_features;
1864 #if EFSYS_OPT_MON_STATS
1868 #if EFSYS_OPT_LOOPBACK
1872 #if EFSYS_OPT_MAC_STATS
1883 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1888 __checkReturn efx_rc_t
1889 ef10_nic_set_drv_limits(
1890 __inout efx_nic_t *enp,
1891 __in efx_drv_limits_t *edlp)
1893 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1894 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1895 uint32_t min_evq_count, max_evq_count;
1896 uint32_t min_rxq_count, max_rxq_count;
1897 uint32_t min_txq_count, max_txq_count;
1905 /* Get minimum required and maximum usable VI limits */
1906 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
1907 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
1908 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
1910 edcp->edc_min_vi_count =
1911 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
1913 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
1914 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
1915 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
1917 edcp->edc_max_vi_count =
1918 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
1921 * Check limits for sub-allocated piobuf blocks.
1922 * PIO is optional, so don't fail if the limits are incorrect.
1924 if ((encp->enc_piobuf_size == 0) ||
1925 (encp->enc_piobuf_limit == 0) ||
1926 (edlp->edl_min_pio_alloc_size == 0) ||
1927 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
1929 edcp->edc_max_piobuf_count = 0;
1930 edcp->edc_pio_alloc_size = 0;
1932 uint32_t blk_size, blk_count, blks_per_piobuf;
1935 MAX(edlp->edl_min_pio_alloc_size,
1936 encp->enc_piobuf_min_alloc_size);
1938 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
1939 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
1941 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
1943 /* A zero max pio alloc count means unlimited */
1944 if ((edlp->edl_max_pio_alloc_count > 0) &&
1945 (edlp->edl_max_pio_alloc_count < blk_count)) {
1946 blk_count = edlp->edl_max_pio_alloc_count;
1949 edcp->edc_pio_alloc_size = blk_size;
1950 edcp->edc_max_piobuf_count =
1951 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
1957 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1963 __checkReturn efx_rc_t
1965 __in efx_nic_t *enp)
1968 uint8_t payload[MAX(MC_CMD_ENTITY_RESET_IN_LEN,
1969 MC_CMD_ENTITY_RESET_OUT_LEN)];
1972 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
1973 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1975 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1978 (void) memset(payload, 0, sizeof (payload));
1979 req.emr_cmd = MC_CMD_ENTITY_RESET;
1980 req.emr_in_buf = payload;
1981 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
1982 req.emr_out_buf = payload;
1983 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
1985 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
1986 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
1988 efx_mcdi_execute(enp, &req);
1990 if (req.emr_rc != 0) {
1995 /* Clear RX/TX DMA queue errors */
1996 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
2005 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2010 __checkReturn efx_rc_t
2012 __in efx_nic_t *enp)
2014 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2015 uint32_t min_vi_count, max_vi_count;
2016 uint32_t vi_count, vi_base, vi_shift;
2020 uint32_t vi_window_size;
2023 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2024 enp->en_family == EFX_FAMILY_MEDFORD ||
2025 enp->en_family == EFX_FAMILY_MEDFORD2);
2027 /* Enable reporting of some events (e.g. link change) */
2028 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
2031 /* Allocate (optional) on-chip PIO buffers */
2032 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
2035 * For best performance, PIO writes should use a write-combined
2036 * (WC) memory mapping. Using a separate WC mapping for the PIO
2037 * aperture of each VI would be a burden to drivers (and not
2038 * possible if the host page size is >4Kbyte).
2040 * To avoid this we use a single uncached (UC) mapping for VI
2041 * register access, and a single WC mapping for extra VIs used
2044 * Each piobuf must be linked to a VI in the WC mapping, and to
2045 * each VI that is using a sub-allocated block from the piobuf.
2047 min_vi_count = edcp->edc_min_vi_count;
2049 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
2051 /* Ensure that the previously attached driver's VIs are freed */
2052 if ((rc = efx_mcdi_free_vis(enp)) != 0)
2056 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
2057 * fails then retrying the request for fewer VI resources may succeed.
2060 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
2061 &vi_base, &vi_count, &vi_shift)) != 0)
2064 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
2066 if (vi_count < min_vi_count) {
2071 enp->en_arch.ef10.ena_vi_base = vi_base;
2072 enp->en_arch.ef10.ena_vi_count = vi_count;
2073 enp->en_arch.ef10.ena_vi_shift = vi_shift;
2075 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
2076 /* Not enough extra VIs to map piobufs */
2077 ef10_nic_free_piobufs(enp);
2080 enp->en_arch.ef10.ena_pio_write_vi_base =
2081 vi_count - enp->en_arch.ef10.ena_piobuf_count;
2083 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, !=,
2084 EFX_VI_WINDOW_SHIFT_INVALID);
2085 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, <=,
2086 EFX_VI_WINDOW_SHIFT_64K);
2087 vi_window_size = 1U << enp->en_nic_cfg.enc_vi_window_shift;
2089 /* Save UC memory mapping details */
2090 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
2091 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2092 enp->en_arch.ef10.ena_uc_mem_map_size =
2094 enp->en_arch.ef10.ena_pio_write_vi_base);
2096 enp->en_arch.ef10.ena_uc_mem_map_size =
2098 enp->en_arch.ef10.ena_vi_count);
2101 /* Save WC memory mapping details */
2102 enp->en_arch.ef10.ena_wc_mem_map_offset =
2103 enp->en_arch.ef10.ena_uc_mem_map_offset +
2104 enp->en_arch.ef10.ena_uc_mem_map_size;
2106 enp->en_arch.ef10.ena_wc_mem_map_size =
2108 enp->en_arch.ef10.ena_piobuf_count);
2110 /* Link piobufs to extra VIs in WC mapping */
2111 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2112 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2113 rc = efx_mcdi_link_piobuf(enp,
2114 enp->en_arch.ef10.ena_pio_write_vi_base + i,
2115 enp->en_arch.ef10.ena_piobuf_handle[i]);
2122 * Allocate a vAdaptor attached to our upstream vPort/pPort.
2124 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
2125 * driver has yet to bring up the EVB port. See bug 56147. In this case,
2126 * retry the request several times after waiting a while. The wait time
2127 * between retries starts small (10ms) and exponentially increases.
2128 * Total wait time is a little over two seconds. Retry logic in the
2129 * client driver may mean this whole loop is repeated if it continues to
2134 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
2135 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
2138 * Do not retry alloc for PF, or for other errors on
2144 /* VF startup before PF is ready. Retry allocation. */
2146 /* Too many attempts */
2150 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
2151 EFSYS_SLEEP(delay_us);
2153 if (delay_us < 500000)
2157 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
2158 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
2173 ef10_nic_free_piobufs(enp);
2176 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2181 __checkReturn efx_rc_t
2182 ef10_nic_get_vi_pool(
2183 __in efx_nic_t *enp,
2184 __out uint32_t *vi_countp)
2186 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2187 enp->en_family == EFX_FAMILY_MEDFORD ||
2188 enp->en_family == EFX_FAMILY_MEDFORD2);
2191 * Report VIs that the client driver can use.
2192 * Do not include VIs used for PIO buffer writes.
2194 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
2199 __checkReturn efx_rc_t
2200 ef10_nic_get_bar_region(
2201 __in efx_nic_t *enp,
2202 __in efx_nic_region_t region,
2203 __out uint32_t *offsetp,
2204 __out size_t *sizep)
2208 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2209 enp->en_family == EFX_FAMILY_MEDFORD ||
2210 enp->en_family == EFX_FAMILY_MEDFORD2);
2213 * TODO: Specify host memory mapping alignment and granularity
2214 * in efx_drv_limits_t so that they can be taken into account
2215 * when allocating extra VIs for PIO writes.
2219 /* UC mapped memory BAR region for VI registers */
2220 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
2221 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
2224 case EFX_REGION_PIO_WRITE_VI:
2225 /* WC mapped memory BAR region for piobuf writes */
2226 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
2227 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
2238 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2245 __in efx_nic_t *enp)
2250 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
2251 enp->en_vport_id = 0;
2253 /* Unlink piobufs from extra VIs in WC mapping */
2254 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2255 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2256 rc = efx_mcdi_unlink_piobuf(enp,
2257 enp->en_arch.ef10.ena_pio_write_vi_base + i);
2263 ef10_nic_free_piobufs(enp);
2265 (void) efx_mcdi_free_vis(enp);
2266 enp->en_arch.ef10.ena_vi_count = 0;
2271 __in efx_nic_t *enp)
2273 #if EFSYS_OPT_MON_STATS
2274 mcdi_mon_cfg_free(enp);
2275 #endif /* EFSYS_OPT_MON_STATS */
2276 (void) efx_mcdi_drv_attach(enp, B_FALSE);
2281 __checkReturn efx_rc_t
2282 ef10_nic_register_test(
2283 __in efx_nic_t *enp)
2288 _NOTE(ARGUNUSED(enp))
2289 _NOTE(CONSTANTCONDITION)
2299 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2304 #endif /* EFSYS_OPT_DIAG */
2306 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
2308 __checkReturn efx_rc_t
2309 efx_mcdi_get_nic_global(
2310 __in efx_nic_t *enp,
2312 __out uint32_t *valuep)
2315 uint8_t payload[MAX(MC_CMD_GET_NIC_GLOBAL_IN_LEN,
2316 MC_CMD_GET_NIC_GLOBAL_OUT_LEN)];
2319 (void) memset(payload, 0, sizeof (payload));
2320 req.emr_cmd = MC_CMD_GET_NIC_GLOBAL;
2321 req.emr_in_buf = payload;
2322 req.emr_in_length = MC_CMD_GET_NIC_GLOBAL_IN_LEN;
2323 req.emr_out_buf = payload;
2324 req.emr_out_length = MC_CMD_GET_NIC_GLOBAL_OUT_LEN;
2326 MCDI_IN_SET_DWORD(req, GET_NIC_GLOBAL_IN_KEY, key);
2328 efx_mcdi_execute(enp, &req);
2330 if (req.emr_rc != 0) {
2335 if (req.emr_out_length_used != MC_CMD_GET_NIC_GLOBAL_OUT_LEN) {
2340 *valuep = MCDI_OUT_DWORD(req, GET_NIC_GLOBAL_OUT_VALUE);
2347 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2352 __checkReturn efx_rc_t
2353 efx_mcdi_set_nic_global(
2354 __in efx_nic_t *enp,
2356 __in uint32_t value)
2359 uint8_t payload[MC_CMD_SET_NIC_GLOBAL_IN_LEN];
2362 (void) memset(payload, 0, sizeof (payload));
2363 req.emr_cmd = MC_CMD_SET_NIC_GLOBAL;
2364 req.emr_in_buf = payload;
2365 req.emr_in_length = MC_CMD_SET_NIC_GLOBAL_IN_LEN;
2366 req.emr_out_buf = NULL;
2367 req.emr_out_length = 0;
2369 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_KEY, key);
2370 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_VALUE, value);
2372 efx_mcdi_execute(enp, &req);
2374 if (req.emr_rc != 0) {
2382 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2387 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
2389 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */