1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
11 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
14 static __checkReturn efx_rc_t
18 __in uint32_t target_evq,
20 __in uint32_t instance,
21 __in efsys_mem_t *esmp,
22 __in boolean_t disable_scatter,
23 __in boolean_t want_inner_classes,
24 __in uint32_t ps_bufsize)
26 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
28 uint8_t payload[MAX(MC_CMD_INIT_RXQ_EXT_IN_LEN,
29 MC_CMD_INIT_RXQ_EXT_OUT_LEN)];
30 int npages = EFX_RXQ_NBUFS(ndescs);
32 efx_qword_t *dma_addr;
36 boolean_t want_outer_classes;
38 EFSYS_ASSERT3U(ndescs, <=, EFX_RXQ_MAXNDESCS);
40 if ((esmp == NULL) || (EFSYS_MEM_SIZE(esmp) < EFX_RXQ_SIZE(ndescs))) {
46 dma_mode = MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM;
48 dma_mode = MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET;
50 if (encp->enc_tunnel_encapsulations_supported != 0 &&
51 !want_inner_classes) {
53 * WANT_OUTER_CLASSES can only be specified on hardware which
54 * supports tunnel encapsulation offloads, even though it is
55 * effectively the behaviour the hardware gives.
57 * Also, on hardware which does support such offloads, older
58 * firmware rejects the flag if the offloads are not supported
59 * by the current firmware variant, which means this may fail if
60 * the capabilities are not updated when the firmware variant
61 * changes. This is not an issue on newer firmware, as it was
62 * changed in bug 69842 (v6.4.2.1007) to permit this flag to be
63 * specified on all firmware variants.
65 want_outer_classes = B_TRUE;
67 want_outer_classes = B_FALSE;
70 (void) memset(payload, 0, sizeof (payload));
71 req.emr_cmd = MC_CMD_INIT_RXQ;
72 req.emr_in_buf = payload;
73 req.emr_in_length = MC_CMD_INIT_RXQ_EXT_IN_LEN;
74 req.emr_out_buf = payload;
75 req.emr_out_length = MC_CMD_INIT_RXQ_EXT_OUT_LEN;
77 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_SIZE, ndescs);
78 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_TARGET_EVQ, target_evq);
79 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_LABEL, label);
80 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_INSTANCE, instance);
81 MCDI_IN_POPULATE_DWORD_9(req, INIT_RXQ_EXT_IN_FLAGS,
82 INIT_RXQ_EXT_IN_FLAG_BUFF_MODE, 0,
83 INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT, 0,
84 INIT_RXQ_EXT_IN_FLAG_TIMESTAMP, 0,
85 INIT_RXQ_EXT_IN_CRC_MODE, 0,
86 INIT_RXQ_EXT_IN_FLAG_PREFIX, 1,
87 INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER, disable_scatter,
88 INIT_RXQ_EXT_IN_DMA_MODE,
90 INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE, ps_bufsize,
91 INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES, want_outer_classes);
92 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_OWNER_ID, 0);
93 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
95 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_RXQ_IN_DMA_ADDR);
96 addr = EFSYS_MEM_ADDR(esmp);
98 for (i = 0; i < npages; i++) {
99 EFX_POPULATE_QWORD_2(*dma_addr,
100 EFX_DWORD_1, (uint32_t)(addr >> 32),
101 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
104 addr += EFX_BUF_SIZE;
107 efx_mcdi_execute(enp, &req);
109 if (req.emr_rc != 0) {
119 EFSYS_PROBE1(fail1, efx_rc_t, rc);
124 static __checkReturn efx_rc_t
127 __in uint32_t instance)
130 uint8_t payload[MAX(MC_CMD_FINI_RXQ_IN_LEN,
131 MC_CMD_FINI_RXQ_OUT_LEN)];
134 (void) memset(payload, 0, sizeof (payload));
135 req.emr_cmd = MC_CMD_FINI_RXQ;
136 req.emr_in_buf = payload;
137 req.emr_in_length = MC_CMD_FINI_RXQ_IN_LEN;
138 req.emr_out_buf = payload;
139 req.emr_out_length = MC_CMD_FINI_RXQ_OUT_LEN;
141 MCDI_IN_SET_DWORD(req, FINI_RXQ_IN_INSTANCE, instance);
143 efx_mcdi_execute_quiet(enp, &req);
145 if (req.emr_rc != 0) {
154 * EALREADY is not an error, but indicates that the MC has rebooted and
155 * that the RXQ has already been destroyed.
158 EFSYS_PROBE1(fail1, efx_rc_t, rc);
163 #if EFSYS_OPT_RX_SCALE
164 static __checkReturn efx_rc_t
165 efx_mcdi_rss_context_alloc(
167 __in efx_rx_scale_context_type_t type,
168 __in uint32_t num_queues,
169 __out uint32_t *rss_contextp)
172 uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN,
173 MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)];
174 uint32_t rss_context;
175 uint32_t context_type;
178 if (num_queues > EFX_MAXRSS) {
184 case EFX_RX_SCALE_EXCLUSIVE:
185 context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE;
187 case EFX_RX_SCALE_SHARED:
188 context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
195 (void) memset(payload, 0, sizeof (payload));
196 req.emr_cmd = MC_CMD_RSS_CONTEXT_ALLOC;
197 req.emr_in_buf = payload;
198 req.emr_in_length = MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN;
199 req.emr_out_buf = payload;
200 req.emr_out_length = MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN;
202 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
203 EVB_PORT_ID_ASSIGNED);
204 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_TYPE, context_type);
207 * For exclusive contexts, NUM_QUEUES is only used to validate
208 * indirection table offsets.
209 * For shared contexts, the provided context will spread traffic over
210 * NUM_QUEUES many queues.
212 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, num_queues);
214 efx_mcdi_execute(enp, &req);
216 if (req.emr_rc != 0) {
221 if (req.emr_out_length_used < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) {
226 rss_context = MCDI_OUT_DWORD(req, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
227 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
232 *rss_contextp = rss_context;
245 EFSYS_PROBE1(fail1, efx_rc_t, rc);
249 #endif /* EFSYS_OPT_RX_SCALE */
251 #if EFSYS_OPT_RX_SCALE
253 efx_mcdi_rss_context_free(
255 __in uint32_t rss_context)
258 uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_FREE_IN_LEN,
259 MC_CMD_RSS_CONTEXT_FREE_OUT_LEN)];
262 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
267 (void) memset(payload, 0, sizeof (payload));
268 req.emr_cmd = MC_CMD_RSS_CONTEXT_FREE;
269 req.emr_in_buf = payload;
270 req.emr_in_length = MC_CMD_RSS_CONTEXT_FREE_IN_LEN;
271 req.emr_out_buf = payload;
272 req.emr_out_length = MC_CMD_RSS_CONTEXT_FREE_OUT_LEN;
274 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID, rss_context);
276 efx_mcdi_execute_quiet(enp, &req);
278 if (req.emr_rc != 0) {
288 EFSYS_PROBE1(fail1, efx_rc_t, rc);
292 #endif /* EFSYS_OPT_RX_SCALE */
294 #if EFSYS_OPT_RX_SCALE
296 efx_mcdi_rss_context_set_flags(
298 __in uint32_t rss_context,
299 __in efx_rx_hash_type_t type)
301 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
302 efx_rx_hash_type_t type_ipv4;
303 efx_rx_hash_type_t type_ipv4_tcp;
304 efx_rx_hash_type_t type_ipv6;
305 efx_rx_hash_type_t type_ipv6_tcp;
306 efx_rx_hash_type_t modes;
308 uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN,
309 MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN)];
312 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_TCP_LBN ==
313 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN);
314 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_TCP_WIDTH ==
315 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH);
316 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_LBN ==
317 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN);
318 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_WIDTH ==
319 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH);
320 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_TCP_LBN ==
321 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN);
322 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_TCP_WIDTH ==
323 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH);
324 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_LBN ==
325 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN);
326 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_WIDTH ==
327 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH);
329 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
334 (void) memset(payload, 0, sizeof (payload));
335 req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_FLAGS;
336 req.emr_in_buf = payload;
337 req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN;
338 req.emr_out_buf = payload;
339 req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN;
341 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID,
344 type_ipv4 = EFX_RX_HASH(IPV4, 2TUPLE) | EFX_RX_HASH(IPV4_TCP, 2TUPLE) |
345 EFX_RX_HASH(IPV4_UDP, 2TUPLE);
346 type_ipv4_tcp = EFX_RX_HASH(IPV4_TCP, 4TUPLE);
347 type_ipv6 = EFX_RX_HASH(IPV6, 2TUPLE) | EFX_RX_HASH(IPV6_TCP, 2TUPLE) |
348 EFX_RX_HASH(IPV6_UDP, 2TUPLE);
349 type_ipv6_tcp = EFX_RX_HASH(IPV6_TCP, 4TUPLE);
352 * Create a copy of the original hash type.
353 * The copy will be used to fill in RSS_MODE bits and
354 * may be cleared beforehand. The original variable
355 * and, thus, EN bits will remain unaffected.
360 * If the firmware lacks support for additional modes, RSS_MODE
361 * fields must contain zeros, otherwise the operation will fail.
363 if (encp->enc_rx_scale_additional_modes_supported == B_FALSE)
366 #define EXTRACT_RSS_MODE(_type, _class) \
367 (EFX_EXTRACT_NATIVE(_type, 0, 31, \
368 EFX_LOW_BIT(EFX_RX_CLASS_##_class), \
369 EFX_HIGH_BIT(EFX_RX_CLASS_##_class)) & \
370 EFX_MASK32(EFX_RX_CLASS_##_class))
372 MCDI_IN_POPULATE_DWORD_10(req, RSS_CONTEXT_SET_FLAGS_IN_FLAGS,
373 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN,
374 ((type & type_ipv4) == type_ipv4) ? 1 : 0,
375 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN,
376 ((type & type_ipv4_tcp) == type_ipv4_tcp) ? 1 : 0,
377 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN,
378 ((type & type_ipv6) == type_ipv6) ? 1 : 0,
379 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN,
380 ((type & type_ipv6_tcp) == type_ipv6_tcp) ? 1 : 0,
381 RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE,
382 EXTRACT_RSS_MODE(modes, IPV4_TCP),
383 RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE,
384 EXTRACT_RSS_MODE(modes, IPV4_UDP),
385 RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE,
386 EXTRACT_RSS_MODE(modes, IPV4),
387 RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE,
388 EXTRACT_RSS_MODE(modes, IPV6_TCP),
389 RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE,
390 EXTRACT_RSS_MODE(modes, IPV6_UDP),
391 RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE,
392 EXTRACT_RSS_MODE(modes, IPV6));
394 #undef EXTRACT_RSS_MODE
396 efx_mcdi_execute(enp, &req);
398 if (req.emr_rc != 0) {
408 EFSYS_PROBE1(fail1, efx_rc_t, rc);
412 #endif /* EFSYS_OPT_RX_SCALE */
414 #if EFSYS_OPT_RX_SCALE
416 efx_mcdi_rss_context_set_key(
418 __in uint32_t rss_context,
419 __in_ecount(n) uint8_t *key,
423 uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN,
424 MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN)];
427 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
432 (void) memset(payload, 0, sizeof (payload));
433 req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_KEY;
434 req.emr_in_buf = payload;
435 req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN;
436 req.emr_out_buf = payload;
437 req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN;
439 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
442 EFSYS_ASSERT3U(n, ==, MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
443 if (n != MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN) {
448 memcpy(MCDI_IN2(req, uint8_t, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY),
451 efx_mcdi_execute(enp, &req);
453 if (req.emr_rc != 0) {
465 EFSYS_PROBE1(fail1, efx_rc_t, rc);
469 #endif /* EFSYS_OPT_RX_SCALE */
471 #if EFSYS_OPT_RX_SCALE
473 efx_mcdi_rss_context_set_table(
475 __in uint32_t rss_context,
476 __in_ecount(n) unsigned int *table,
480 uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN,
481 MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN)];
485 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
490 (void) memset(payload, 0, sizeof (payload));
491 req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_TABLE;
492 req.emr_in_buf = payload;
493 req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN;
494 req.emr_out_buf = payload;
495 req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN;
497 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
501 MCDI_IN2(req, uint8_t, RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE);
504 i < MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN;
506 req_table[i] = (n > 0) ? (uint8_t)table[i % n] : 0;
509 efx_mcdi_execute(enp, &req);
511 if (req.emr_rc != 0) {
521 EFSYS_PROBE1(fail1, efx_rc_t, rc);
525 #endif /* EFSYS_OPT_RX_SCALE */
528 __checkReturn efx_rc_t
532 #if EFSYS_OPT_RX_SCALE
534 if (efx_mcdi_rss_context_alloc(enp, EFX_RX_SCALE_EXCLUSIVE, EFX_MAXRSS,
535 &enp->en_rss_context) == 0) {
537 * Allocated an exclusive RSS context, which allows both the
538 * indirection table and key to be modified.
540 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
541 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
544 * Failed to allocate an exclusive RSS context. Continue
545 * operation without support for RSS. The pseudo-header in
546 * received packets will not contain a Toeplitz hash value.
548 enp->en_rss_context_type = EFX_RX_SCALE_UNAVAILABLE;
549 enp->en_hash_support = EFX_RX_HASH_UNAVAILABLE;
552 #endif /* EFSYS_OPT_RX_SCALE */
557 #if EFSYS_OPT_RX_SCATTER
558 __checkReturn efx_rc_t
559 ef10_rx_scatter_enable(
561 __in unsigned int buf_size)
563 _NOTE(ARGUNUSED(enp, buf_size))
566 #endif /* EFSYS_OPT_RX_SCATTER */
568 #if EFSYS_OPT_RX_SCALE
569 __checkReturn efx_rc_t
570 ef10_rx_scale_context_alloc(
572 __in efx_rx_scale_context_type_t type,
573 __in uint32_t num_queues,
574 __out uint32_t *rss_contextp)
578 rc = efx_mcdi_rss_context_alloc(enp, type, num_queues, rss_contextp);
585 EFSYS_PROBE1(fail1, efx_rc_t, rc);
588 #endif /* EFSYS_OPT_RX_SCALE */
590 #if EFSYS_OPT_RX_SCALE
591 __checkReturn efx_rc_t
592 ef10_rx_scale_context_free(
594 __in uint32_t rss_context)
598 rc = efx_mcdi_rss_context_free(enp, rss_context);
605 EFSYS_PROBE1(fail1, efx_rc_t, rc);
608 #endif /* EFSYS_OPT_RX_SCALE */
610 #if EFSYS_OPT_RX_SCALE
611 __checkReturn efx_rc_t
612 ef10_rx_scale_mode_set(
614 __in uint32_t rss_context,
615 __in efx_rx_hash_alg_t alg,
616 __in efx_rx_hash_type_t type,
617 __in boolean_t insert)
621 EFSYS_ASSERT3U(alg, ==, EFX_RX_HASHALG_TOEPLITZ);
622 EFSYS_ASSERT3U(insert, ==, B_TRUE);
624 if ((alg != EFX_RX_HASHALG_TOEPLITZ) || (insert == B_FALSE)) {
629 if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
630 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
634 rss_context = enp->en_rss_context;
637 if ((rc = efx_mcdi_rss_context_set_flags(enp,
638 rss_context, type)) != 0)
648 EFSYS_PROBE1(fail1, efx_rc_t, rc);
652 #endif /* EFSYS_OPT_RX_SCALE */
654 #if EFSYS_OPT_RX_SCALE
655 __checkReturn efx_rc_t
656 ef10_rx_scale_key_set(
658 __in uint32_t rss_context,
659 __in_ecount(n) uint8_t *key,
664 EFX_STATIC_ASSERT(EFX_RSS_KEY_SIZE ==
665 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
667 if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
668 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
672 rss_context = enp->en_rss_context;
675 if ((rc = efx_mcdi_rss_context_set_key(enp, rss_context, key, n)) != 0)
683 EFSYS_PROBE1(fail1, efx_rc_t, rc);
687 #endif /* EFSYS_OPT_RX_SCALE */
689 #if EFSYS_OPT_RX_SCALE
690 __checkReturn efx_rc_t
691 ef10_rx_scale_tbl_set(
693 __in uint32_t rss_context,
694 __in_ecount(n) unsigned int *table,
700 if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
701 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
705 rss_context = enp->en_rss_context;
708 if ((rc = efx_mcdi_rss_context_set_table(enp,
709 rss_context, table, n)) != 0)
717 EFSYS_PROBE1(fail1, efx_rc_t, rc);
721 #endif /* EFSYS_OPT_RX_SCALE */
725 * EF10 RX pseudo-header
726 * ---------------------
728 * Receive packets are prefixed by an (optional) 14 byte pseudo-header:
730 * +00: Toeplitz hash value.
731 * (32bit little-endian)
732 * +04: Outer VLAN tag. Zero if the packet did not have an outer VLAN tag.
734 * +06: Inner VLAN tag. Zero if the packet did not have an inner VLAN tag.
736 * +08: Packet Length. Zero if the RX datapath was in cut-through mode.
737 * (16bit little-endian)
738 * +10: MAC timestamp. Zero if timestamping is not enabled.
739 * (32bit little-endian)
741 * See "The RX Pseudo-header" in SF-109306-TC.
744 __checkReturn efx_rc_t
745 ef10_rx_prefix_pktlen(
747 __in uint8_t *buffer,
748 __out uint16_t *lengthp)
750 _NOTE(ARGUNUSED(enp))
753 * The RX pseudo-header contains the packet length, excluding the
754 * pseudo-header. If the hardware receive datapath was operating in
755 * cut-through mode then the length in the RX pseudo-header will be
756 * zero, and the packet length must be obtained from the DMA length
757 * reported in the RX event.
759 *lengthp = buffer[8] | (buffer[9] << 8);
763 #if EFSYS_OPT_RX_SCALE
764 __checkReturn uint32_t
767 __in efx_rx_hash_alg_t func,
768 __in uint8_t *buffer)
770 _NOTE(ARGUNUSED(enp))
773 case EFX_RX_HASHALG_TOEPLITZ:
784 #endif /* EFSYS_OPT_RX_SCALE */
786 #if EFSYS_OPT_RX_PACKED_STREAM
788 * Fake length for RXQ descriptors in packed stream mode
789 * to make hardware happy
791 #define EFX_RXQ_PACKED_STREAM_FAKE_BUF_SIZE 32
797 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
799 __in unsigned int ndescs,
800 __in unsigned int completed,
801 __in unsigned int added)
808 _NOTE(ARGUNUSED(completed))
810 #if EFSYS_OPT_RX_PACKED_STREAM
812 * Real size of the buffer does not fit into ESF_DZ_RX_KER_BYTE_CNT
813 * and equal to 0 after applying mask. Hardware does not like it.
815 if (erp->er_ev_qstate->eers_rx_packed_stream)
816 size = EFX_RXQ_PACKED_STREAM_FAKE_BUF_SIZE;
819 /* The client driver must not overfill the queue */
820 EFSYS_ASSERT3U(added - completed + ndescs, <=,
821 EFX_RXQ_LIMIT(erp->er_mask + 1));
823 id = added & (erp->er_mask);
824 for (i = 0; i < ndescs; i++) {
825 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
826 unsigned int, id, efsys_dma_addr_t, addrp[i],
829 EFX_POPULATE_QWORD_3(qword,
830 ESF_DZ_RX_KER_BYTE_CNT, (uint32_t)(size),
831 ESF_DZ_RX_KER_BUF_ADDR_DW0,
832 (uint32_t)(addrp[i] & 0xffffffff),
833 ESF_DZ_RX_KER_BUF_ADDR_DW1,
834 (uint32_t)(addrp[i] >> 32));
836 offset = id * sizeof (efx_qword_t);
837 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
839 id = (id + 1) & (erp->er_mask);
846 __in unsigned int added,
847 __inout unsigned int *pushedp)
849 efx_nic_t *enp = erp->er_enp;
850 unsigned int pushed = *pushedp;
854 /* Hardware has alignment restriction for WPTR */
855 wptr = P2ALIGN(added, EF10_RX_WPTR_ALIGN);
861 /* Push the populated descriptors out */
862 wptr &= erp->er_mask;
864 EFX_POPULATE_DWORD_1(dword, ERF_DZ_RX_DESC_WPTR, wptr);
866 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
867 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
868 wptr, pushed & erp->er_mask);
869 EFSYS_PIO_WRITE_BARRIER();
870 EFX_BAR_VI_WRITED(enp, ER_DZ_RX_DESC_UPD_REG,
871 erp->er_index, &dword, B_FALSE);
874 #if EFSYS_OPT_RX_PACKED_STREAM
877 ef10_rx_qpush_ps_credits(
880 efx_nic_t *enp = erp->er_enp;
882 efx_evq_rxq_state_t *rxq_state = erp->er_ev_qstate;
885 EFSYS_ASSERT(rxq_state->eers_rx_packed_stream);
887 if (rxq_state->eers_rx_packed_stream_credits == 0)
891 * It is a bug if we think that FW has utilized more
892 * credits than it is allowed to have (maximum). However,
893 * make sure that we do not credit more than maximum anyway.
895 credits = MIN(rxq_state->eers_rx_packed_stream_credits,
896 EFX_RX_PACKED_STREAM_MAX_CREDITS);
897 EFX_POPULATE_DWORD_3(dword,
898 ERF_DZ_RX_DESC_MAGIC_DOORBELL, 1,
899 ERF_DZ_RX_DESC_MAGIC_CMD,
900 ERE_DZ_RX_DESC_MAGIC_CMD_PS_CREDITS,
901 ERF_DZ_RX_DESC_MAGIC_DATA, credits);
902 EFX_BAR_VI_WRITED(enp, ER_DZ_RX_DESC_UPD_REG,
903 erp->er_index, &dword, B_FALSE);
905 rxq_state->eers_rx_packed_stream_credits = 0;
909 * In accordance with SF-112241-TC the received data has the following layout:
910 * - 8 byte pseudo-header which consist of:
911 * - 4 byte little-endian timestamp
912 * - 2 byte little-endian captured length in bytes
913 * - 2 byte little-endian original packet length in bytes
914 * - captured packet bytes
915 * - optional padding to align to 64 bytes boundary
916 * - 64 bytes scratch space for the host software
918 __checkReturn uint8_t *
919 ef10_rx_qps_packet_info(
921 __in uint8_t *buffer,
922 __in uint32_t buffer_length,
923 __in uint32_t current_offset,
924 __out uint16_t *lengthp,
925 __out uint32_t *next_offsetp,
926 __out uint32_t *timestamp)
931 efx_evq_rxq_state_t *rxq_state = erp->er_ev_qstate;
933 EFSYS_ASSERT(rxq_state->eers_rx_packed_stream);
935 buffer += current_offset;
936 pkt_start = buffer + EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE;
938 qwordp = (efx_qword_t *)buffer;
939 *timestamp = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_TSTAMP);
940 *lengthp = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_ORIG_LEN);
941 buf_len = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_CAP_LEN);
943 buf_len = P2ROUNDUP(buf_len + EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE,
944 EFX_RX_PACKED_STREAM_ALIGNMENT);
946 current_offset + buf_len + EFX_RX_PACKED_STREAM_ALIGNMENT;
948 EFSYS_ASSERT3U(*next_offsetp, <=, buffer_length);
949 EFSYS_ASSERT3U(current_offset + *lengthp, <, *next_offsetp);
951 if ((*next_offsetp ^ current_offset) &
952 EFX_RX_PACKED_STREAM_MEM_PER_CREDIT)
953 rxq_state->eers_rx_packed_stream_credits++;
961 __checkReturn efx_rc_t
965 efx_nic_t *enp = erp->er_enp;
968 if ((rc = efx_mcdi_fini_rxq(enp, erp->er_index)) != 0)
975 * EALREADY is not an error, but indicates that the MC has rebooted and
976 * that the RXQ has already been destroyed. Callers need to know that
977 * the RXQ flush has completed to avoid waiting until timeout for a
978 * flush done event that will not be delivered.
981 EFSYS_PROBE1(fail1, efx_rc_t, rc);
991 _NOTE(ARGUNUSED(erp))
995 __checkReturn efx_rc_t
998 __in unsigned int index,
999 __in unsigned int label,
1000 __in efx_rxq_type_t type,
1001 __in uint32_t type_data,
1002 __in efsys_mem_t *esmp,
1005 __in unsigned int flags,
1006 __in efx_evq_t *eep,
1007 __in efx_rxq_t *erp)
1009 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1011 boolean_t disable_scatter;
1012 boolean_t want_inner_classes;
1013 unsigned int ps_buf_size;
1015 _NOTE(ARGUNUSED(id, erp, type_data))
1017 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS == (1 << ESF_DZ_RX_QLABEL_WIDTH));
1018 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1019 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1021 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1022 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1024 if (!ISP2(ndescs) ||
1025 (ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {
1029 if (index >= encp->enc_rxq_limit) {
1035 case EFX_RXQ_TYPE_DEFAULT:
1038 #if EFSYS_OPT_RX_PACKED_STREAM
1039 case EFX_RXQ_TYPE_PACKED_STREAM:
1040 switch (type_data) {
1041 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M:
1042 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M;
1044 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K:
1045 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K;
1047 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K:
1048 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K;
1050 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K:
1051 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K;
1053 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K:
1054 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K;
1061 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1067 #if EFSYS_OPT_RX_PACKED_STREAM
1068 if (ps_buf_size != 0) {
1069 /* Check if datapath firmware supports packed stream mode */
1070 if (encp->enc_rx_packed_stream_supported == B_FALSE) {
1074 /* Check if packed stream allows configurable buffer sizes */
1075 if ((ps_buf_size != MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M) &&
1076 (encp->enc_rx_var_packed_stream_supported == B_FALSE)) {
1081 #else /* EFSYS_OPT_RX_PACKED_STREAM */
1082 EFSYS_ASSERT(ps_buf_size == 0);
1083 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1085 /* Scatter can only be disabled if the firmware supports doing so */
1086 if (flags & EFX_RXQ_FLAG_SCATTER)
1087 disable_scatter = B_FALSE;
1089 disable_scatter = encp->enc_rx_disable_scatter_supported;
1091 if (flags & EFX_RXQ_FLAG_INNER_CLASSES)
1092 want_inner_classes = B_TRUE;
1094 want_inner_classes = B_FALSE;
1096 if ((rc = efx_mcdi_init_rxq(enp, ndescs, eep->ee_index, label, index,
1097 esmp, disable_scatter, want_inner_classes,
1102 erp->er_label = label;
1104 ef10_ev_rxlabel_init(eep, erp, label, type);
1106 erp->er_ev_qstate = &erp->er_eep->ee_rxq_state[label];
1112 #if EFSYS_OPT_RX_PACKED_STREAM
1117 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1120 #if EFSYS_OPT_RX_PACKED_STREAM
1123 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1127 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1134 __in efx_rxq_t *erp)
1136 efx_nic_t *enp = erp->er_enp;
1137 efx_evq_t *eep = erp->er_eep;
1138 unsigned int label = erp->er_label;
1140 ef10_ev_rxlabel_fini(eep, label);
1142 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1143 --enp->en_rx_qcount;
1145 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1150 __in efx_nic_t *enp)
1152 #if EFSYS_OPT_RX_SCALE
1153 if (enp->en_rss_context_type != EFX_RX_SCALE_UNAVAILABLE)
1154 (void) efx_mcdi_rss_context_free(enp, enp->en_rss_context);
1155 enp->en_rss_context = 0;
1156 enp->en_rss_context_type = EFX_RX_SCALE_UNAVAILABLE;
1158 _NOTE(ARGUNUSED(enp))
1159 #endif /* EFSYS_OPT_RX_SCALE */
1162 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */