1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
11 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
14 static __checkReturn efx_rc_t
18 __in uint32_t target_evq,
20 __in uint32_t instance,
21 __in efsys_mem_t *esmp,
22 __in boolean_t disable_scatter,
23 __in boolean_t want_inner_classes,
24 __in uint32_t ps_bufsize)
26 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
28 uint8_t payload[MAX(MC_CMD_INIT_RXQ_EXT_IN_LEN,
29 MC_CMD_INIT_RXQ_EXT_OUT_LEN)];
30 int npages = EFX_RXQ_NBUFS(ndescs);
32 efx_qword_t *dma_addr;
36 boolean_t want_outer_classes;
38 EFSYS_ASSERT3U(ndescs, <=, EFX_RXQ_MAXNDESCS);
41 dma_mode = MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM;
43 dma_mode = MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET;
45 if (encp->enc_tunnel_encapsulations_supported != 0 &&
46 !want_inner_classes) {
48 * WANT_OUTER_CLASSES can only be specified on hardware which
49 * supports tunnel encapsulation offloads, even though it is
50 * effectively the behaviour the hardware gives.
52 * Also, on hardware which does support such offloads, older
53 * firmware rejects the flag if the offloads are not supported
54 * by the current firmware variant, which means this may fail if
55 * the capabilities are not updated when the firmware variant
56 * changes. This is not an issue on newer firmware, as it was
57 * changed in bug 69842 (v6.4.2.1007) to permit this flag to be
58 * specified on all firmware variants.
60 want_outer_classes = B_TRUE;
62 want_outer_classes = B_FALSE;
65 (void) memset(payload, 0, sizeof (payload));
66 req.emr_cmd = MC_CMD_INIT_RXQ;
67 req.emr_in_buf = payload;
68 req.emr_in_length = MC_CMD_INIT_RXQ_EXT_IN_LEN;
69 req.emr_out_buf = payload;
70 req.emr_out_length = MC_CMD_INIT_RXQ_EXT_OUT_LEN;
72 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_SIZE, ndescs);
73 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_TARGET_EVQ, target_evq);
74 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_LABEL, label);
75 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_INSTANCE, instance);
76 MCDI_IN_POPULATE_DWORD_9(req, INIT_RXQ_EXT_IN_FLAGS,
77 INIT_RXQ_EXT_IN_FLAG_BUFF_MODE, 0,
78 INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT, 0,
79 INIT_RXQ_EXT_IN_FLAG_TIMESTAMP, 0,
80 INIT_RXQ_EXT_IN_CRC_MODE, 0,
81 INIT_RXQ_EXT_IN_FLAG_PREFIX, 1,
82 INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER, disable_scatter,
83 INIT_RXQ_EXT_IN_DMA_MODE,
85 INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE, ps_bufsize,
86 INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES, want_outer_classes);
87 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_OWNER_ID, 0);
88 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
90 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_RXQ_IN_DMA_ADDR);
91 addr = EFSYS_MEM_ADDR(esmp);
93 for (i = 0; i < npages; i++) {
94 EFX_POPULATE_QWORD_2(*dma_addr,
95 EFX_DWORD_1, (uint32_t)(addr >> 32),
96 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
102 efx_mcdi_execute(enp, &req);
104 if (req.emr_rc != 0) {
112 EFSYS_PROBE1(fail1, efx_rc_t, rc);
117 static __checkReturn efx_rc_t
120 __in uint32_t instance)
123 uint8_t payload[MAX(MC_CMD_FINI_RXQ_IN_LEN,
124 MC_CMD_FINI_RXQ_OUT_LEN)];
127 (void) memset(payload, 0, sizeof (payload));
128 req.emr_cmd = MC_CMD_FINI_RXQ;
129 req.emr_in_buf = payload;
130 req.emr_in_length = MC_CMD_FINI_RXQ_IN_LEN;
131 req.emr_out_buf = payload;
132 req.emr_out_length = MC_CMD_FINI_RXQ_OUT_LEN;
134 MCDI_IN_SET_DWORD(req, FINI_RXQ_IN_INSTANCE, instance);
136 efx_mcdi_execute_quiet(enp, &req);
138 if (req.emr_rc != 0) {
147 * EALREADY is not an error, but indicates that the MC has rebooted and
148 * that the RXQ has already been destroyed.
151 EFSYS_PROBE1(fail1, efx_rc_t, rc);
156 #if EFSYS_OPT_RX_SCALE
157 static __checkReturn efx_rc_t
158 efx_mcdi_rss_context_alloc(
160 __in efx_rx_scale_context_type_t type,
161 __in uint32_t num_queues,
162 __out uint32_t *rss_contextp)
165 uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN,
166 MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)];
167 uint32_t rss_context;
168 uint32_t context_type;
171 if (num_queues > EFX_MAXRSS) {
177 case EFX_RX_SCALE_EXCLUSIVE:
178 context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE;
180 case EFX_RX_SCALE_SHARED:
181 context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
188 (void) memset(payload, 0, sizeof (payload));
189 req.emr_cmd = MC_CMD_RSS_CONTEXT_ALLOC;
190 req.emr_in_buf = payload;
191 req.emr_in_length = MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN;
192 req.emr_out_buf = payload;
193 req.emr_out_length = MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN;
195 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
196 EVB_PORT_ID_ASSIGNED);
197 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_TYPE, context_type);
200 * For exclusive contexts, NUM_QUEUES is only used to validate
201 * indirection table offsets.
202 * For shared contexts, the provided context will spread traffic over
203 * NUM_QUEUES many queues.
205 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, num_queues);
207 efx_mcdi_execute(enp, &req);
209 if (req.emr_rc != 0) {
214 if (req.emr_out_length_used < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) {
219 rss_context = MCDI_OUT_DWORD(req, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
220 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
225 *rss_contextp = rss_context;
238 EFSYS_PROBE1(fail1, efx_rc_t, rc);
242 #endif /* EFSYS_OPT_RX_SCALE */
244 #if EFSYS_OPT_RX_SCALE
246 efx_mcdi_rss_context_free(
248 __in uint32_t rss_context)
251 uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_FREE_IN_LEN,
252 MC_CMD_RSS_CONTEXT_FREE_OUT_LEN)];
255 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
260 (void) memset(payload, 0, sizeof (payload));
261 req.emr_cmd = MC_CMD_RSS_CONTEXT_FREE;
262 req.emr_in_buf = payload;
263 req.emr_in_length = MC_CMD_RSS_CONTEXT_FREE_IN_LEN;
264 req.emr_out_buf = payload;
265 req.emr_out_length = MC_CMD_RSS_CONTEXT_FREE_OUT_LEN;
267 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID, rss_context);
269 efx_mcdi_execute_quiet(enp, &req);
271 if (req.emr_rc != 0) {
281 EFSYS_PROBE1(fail1, efx_rc_t, rc);
285 #endif /* EFSYS_OPT_RX_SCALE */
287 #if EFSYS_OPT_RX_SCALE
289 efx_mcdi_rss_context_set_flags(
291 __in uint32_t rss_context,
292 __in efx_rx_hash_type_t type)
295 uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN,
296 MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN)];
299 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
304 (void) memset(payload, 0, sizeof (payload));
305 req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_FLAGS;
306 req.emr_in_buf = payload;
307 req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN;
308 req.emr_out_buf = payload;
309 req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN;
311 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID,
314 MCDI_IN_POPULATE_DWORD_4(req, RSS_CONTEXT_SET_FLAGS_IN_FLAGS,
315 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN,
316 (type & EFX_RX_HASH_IPV4) ? 1 : 0,
317 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN,
318 (type & EFX_RX_HASH_TCPIPV4) ? 1 : 0,
319 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN,
320 (type & EFX_RX_HASH_IPV6) ? 1 : 0,
321 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN,
322 (type & EFX_RX_HASH_TCPIPV6) ? 1 : 0);
324 efx_mcdi_execute(enp, &req);
326 if (req.emr_rc != 0) {
336 EFSYS_PROBE1(fail1, efx_rc_t, rc);
340 #endif /* EFSYS_OPT_RX_SCALE */
342 #if EFSYS_OPT_RX_SCALE
344 efx_mcdi_rss_context_set_key(
346 __in uint32_t rss_context,
347 __in_ecount(n) uint8_t *key,
351 uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN,
352 MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN)];
355 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
360 (void) memset(payload, 0, sizeof (payload));
361 req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_KEY;
362 req.emr_in_buf = payload;
363 req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN;
364 req.emr_out_buf = payload;
365 req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN;
367 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
370 EFSYS_ASSERT3U(n, ==, MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
371 if (n != MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN) {
376 memcpy(MCDI_IN2(req, uint8_t, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY),
379 efx_mcdi_execute(enp, &req);
381 if (req.emr_rc != 0) {
393 EFSYS_PROBE1(fail1, efx_rc_t, rc);
397 #endif /* EFSYS_OPT_RX_SCALE */
399 #if EFSYS_OPT_RX_SCALE
401 efx_mcdi_rss_context_set_table(
403 __in uint32_t rss_context,
404 __in_ecount(n) unsigned int *table,
408 uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN,
409 MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN)];
413 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
418 (void) memset(payload, 0, sizeof (payload));
419 req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_TABLE;
420 req.emr_in_buf = payload;
421 req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN;
422 req.emr_out_buf = payload;
423 req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN;
425 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
429 MCDI_IN2(req, uint8_t, RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE);
432 i < MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN;
434 req_table[i] = (n > 0) ? (uint8_t)table[i % n] : 0;
437 efx_mcdi_execute(enp, &req);
439 if (req.emr_rc != 0) {
449 EFSYS_PROBE1(fail1, efx_rc_t, rc);
453 #endif /* EFSYS_OPT_RX_SCALE */
456 __checkReturn efx_rc_t
460 #if EFSYS_OPT_RX_SCALE
462 if (efx_mcdi_rss_context_alloc(enp, EFX_RX_SCALE_EXCLUSIVE, EFX_MAXRSS,
463 &enp->en_rss_context) == 0) {
465 * Allocated an exclusive RSS context, which allows both the
466 * indirection table and key to be modified.
468 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
469 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
472 * Failed to allocate an exclusive RSS context. Continue
473 * operation without support for RSS. The pseudo-header in
474 * received packets will not contain a Toeplitz hash value.
476 enp->en_rss_context_type = EFX_RX_SCALE_UNAVAILABLE;
477 enp->en_hash_support = EFX_RX_HASH_UNAVAILABLE;
480 #endif /* EFSYS_OPT_RX_SCALE */
485 #if EFSYS_OPT_RX_SCATTER
486 __checkReturn efx_rc_t
487 ef10_rx_scatter_enable(
489 __in unsigned int buf_size)
491 _NOTE(ARGUNUSED(enp, buf_size))
494 #endif /* EFSYS_OPT_RX_SCATTER */
496 #if EFSYS_OPT_RX_SCALE
497 __checkReturn efx_rc_t
498 ef10_rx_scale_context_alloc(
500 __in efx_rx_scale_context_type_t type,
501 __in uint32_t num_queues,
502 __out uint32_t *rss_contextp)
506 rc = efx_mcdi_rss_context_alloc(enp, type, num_queues, rss_contextp);
513 EFSYS_PROBE1(fail1, efx_rc_t, rc);
516 #endif /* EFSYS_OPT_RX_SCALE */
518 #if EFSYS_OPT_RX_SCALE
519 __checkReturn efx_rc_t
520 ef10_rx_scale_context_free(
522 __in uint32_t rss_context)
526 rc = efx_mcdi_rss_context_free(enp, rss_context);
533 EFSYS_PROBE1(fail1, efx_rc_t, rc);
536 #endif /* EFSYS_OPT_RX_SCALE */
538 #if EFSYS_OPT_RX_SCALE
539 __checkReturn efx_rc_t
540 ef10_rx_scale_mode_set(
542 __in uint32_t rss_context,
543 __in efx_rx_hash_alg_t alg,
544 __in efx_rx_hash_type_t type,
545 __in boolean_t insert)
549 EFSYS_ASSERT3U(alg, ==, EFX_RX_HASHALG_TOEPLITZ);
550 EFSYS_ASSERT3U(insert, ==, B_TRUE);
552 if ((alg != EFX_RX_HASHALG_TOEPLITZ) || (insert == B_FALSE)) {
557 if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
558 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
562 rss_context = enp->en_rss_context;
565 if ((rc = efx_mcdi_rss_context_set_flags(enp,
566 rss_context, type)) != 0)
576 EFSYS_PROBE1(fail1, efx_rc_t, rc);
580 #endif /* EFSYS_OPT_RX_SCALE */
582 #if EFSYS_OPT_RX_SCALE
583 __checkReturn efx_rc_t
584 ef10_rx_scale_key_set(
586 __in uint32_t rss_context,
587 __in_ecount(n) uint8_t *key,
592 EFX_STATIC_ASSERT(EFX_RSS_KEY_SIZE ==
593 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
595 if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
596 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
600 rss_context = enp->en_rss_context;
603 if ((rc = efx_mcdi_rss_context_set_key(enp, rss_context, key, n)) != 0)
611 EFSYS_PROBE1(fail1, efx_rc_t, rc);
615 #endif /* EFSYS_OPT_RX_SCALE */
617 #if EFSYS_OPT_RX_SCALE
618 __checkReturn efx_rc_t
619 ef10_rx_scale_tbl_set(
621 __in uint32_t rss_context,
622 __in_ecount(n) unsigned int *table,
628 if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
629 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
633 rss_context = enp->en_rss_context;
636 if ((rc = efx_mcdi_rss_context_set_table(enp,
637 rss_context, table, n)) != 0)
645 EFSYS_PROBE1(fail1, efx_rc_t, rc);
649 #endif /* EFSYS_OPT_RX_SCALE */
653 * EF10 RX pseudo-header
654 * ---------------------
656 * Receive packets are prefixed by an (optional) 14 byte pseudo-header:
658 * +00: Toeplitz hash value.
659 * (32bit little-endian)
660 * +04: Outer VLAN tag. Zero if the packet did not have an outer VLAN tag.
662 * +06: Inner VLAN tag. Zero if the packet did not have an inner VLAN tag.
664 * +08: Packet Length. Zero if the RX datapath was in cut-through mode.
665 * (16bit little-endian)
666 * +10: MAC timestamp. Zero if timestamping is not enabled.
667 * (32bit little-endian)
669 * See "The RX Pseudo-header" in SF-109306-TC.
672 __checkReturn efx_rc_t
673 ef10_rx_prefix_pktlen(
675 __in uint8_t *buffer,
676 __out uint16_t *lengthp)
678 _NOTE(ARGUNUSED(enp))
681 * The RX pseudo-header contains the packet length, excluding the
682 * pseudo-header. If the hardware receive datapath was operating in
683 * cut-through mode then the length in the RX pseudo-header will be
684 * zero, and the packet length must be obtained from the DMA length
685 * reported in the RX event.
687 *lengthp = buffer[8] | (buffer[9] << 8);
691 #if EFSYS_OPT_RX_SCALE
692 __checkReturn uint32_t
695 __in efx_rx_hash_alg_t func,
696 __in uint8_t *buffer)
698 _NOTE(ARGUNUSED(enp))
701 case EFX_RX_HASHALG_TOEPLITZ:
712 #endif /* EFSYS_OPT_RX_SCALE */
714 #if EFSYS_OPT_RX_PACKED_STREAM
716 * Fake length for RXQ descriptors in packed stream mode
717 * to make hardware happy
719 #define EFX_RXQ_PACKED_STREAM_FAKE_BUF_SIZE 32
725 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
727 __in unsigned int ndescs,
728 __in unsigned int completed,
729 __in unsigned int added)
736 _NOTE(ARGUNUSED(completed))
738 #if EFSYS_OPT_RX_PACKED_STREAM
740 * Real size of the buffer does not fit into ESF_DZ_RX_KER_BYTE_CNT
741 * and equal to 0 after applying mask. Hardware does not like it.
743 if (erp->er_ev_qstate->eers_rx_packed_stream)
744 size = EFX_RXQ_PACKED_STREAM_FAKE_BUF_SIZE;
747 /* The client driver must not overfill the queue */
748 EFSYS_ASSERT3U(added - completed + ndescs, <=,
749 EFX_RXQ_LIMIT(erp->er_mask + 1));
751 id = added & (erp->er_mask);
752 for (i = 0; i < ndescs; i++) {
753 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
754 unsigned int, id, efsys_dma_addr_t, addrp[i],
757 EFX_POPULATE_QWORD_3(qword,
758 ESF_DZ_RX_KER_BYTE_CNT, (uint32_t)(size),
759 ESF_DZ_RX_KER_BUF_ADDR_DW0,
760 (uint32_t)(addrp[i] & 0xffffffff),
761 ESF_DZ_RX_KER_BUF_ADDR_DW1,
762 (uint32_t)(addrp[i] >> 32));
764 offset = id * sizeof (efx_qword_t);
765 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
767 id = (id + 1) & (erp->er_mask);
774 __in unsigned int added,
775 __inout unsigned int *pushedp)
777 efx_nic_t *enp = erp->er_enp;
778 unsigned int pushed = *pushedp;
782 /* Hardware has alignment restriction for WPTR */
783 wptr = P2ALIGN(added, EF10_RX_WPTR_ALIGN);
789 /* Push the populated descriptors out */
790 wptr &= erp->er_mask;
792 EFX_POPULATE_DWORD_1(dword, ERF_DZ_RX_DESC_WPTR, wptr);
794 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
795 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
796 wptr, pushed & erp->er_mask);
797 EFSYS_PIO_WRITE_BARRIER();
798 EFX_BAR_TBL_WRITED(enp, ER_DZ_RX_DESC_UPD_REG,
799 erp->er_index, &dword, B_FALSE);
802 #if EFSYS_OPT_RX_PACKED_STREAM
805 ef10_rx_qpush_ps_credits(
808 efx_nic_t *enp = erp->er_enp;
810 efx_evq_rxq_state_t *rxq_state = erp->er_ev_qstate;
813 EFSYS_ASSERT(rxq_state->eers_rx_packed_stream);
815 if (rxq_state->eers_rx_packed_stream_credits == 0)
819 * It is a bug if we think that FW has utilized more
820 * credits than it is allowed to have (maximum). However,
821 * make sure that we do not credit more than maximum anyway.
823 credits = MIN(rxq_state->eers_rx_packed_stream_credits,
824 EFX_RX_PACKED_STREAM_MAX_CREDITS);
825 EFX_POPULATE_DWORD_3(dword,
826 ERF_DZ_RX_DESC_MAGIC_DOORBELL, 1,
827 ERF_DZ_RX_DESC_MAGIC_CMD,
828 ERE_DZ_RX_DESC_MAGIC_CMD_PS_CREDITS,
829 ERF_DZ_RX_DESC_MAGIC_DATA, credits);
830 EFX_BAR_TBL_WRITED(enp, ER_DZ_RX_DESC_UPD_REG,
831 erp->er_index, &dword, B_FALSE);
833 rxq_state->eers_rx_packed_stream_credits = 0;
837 * In accordance with SF-112241-TC the received data has the following layout:
838 * - 8 byte pseudo-header which consist of:
839 * - 4 byte little-endian timestamp
840 * - 2 byte little-endian captured length in bytes
841 * - 2 byte little-endian original packet length in bytes
842 * - captured packet bytes
843 * - optional padding to align to 64 bytes boundary
844 * - 64 bytes scratch space for the host software
846 __checkReturn uint8_t *
847 ef10_rx_qps_packet_info(
849 __in uint8_t *buffer,
850 __in uint32_t buffer_length,
851 __in uint32_t current_offset,
852 __out uint16_t *lengthp,
853 __out uint32_t *next_offsetp,
854 __out uint32_t *timestamp)
859 efx_evq_rxq_state_t *rxq_state = erp->er_ev_qstate;
861 EFSYS_ASSERT(rxq_state->eers_rx_packed_stream);
863 buffer += current_offset;
864 pkt_start = buffer + EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE;
866 qwordp = (efx_qword_t *)buffer;
867 *timestamp = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_TSTAMP);
868 *lengthp = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_ORIG_LEN);
869 buf_len = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_CAP_LEN);
871 buf_len = P2ROUNDUP(buf_len + EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE,
872 EFX_RX_PACKED_STREAM_ALIGNMENT);
874 current_offset + buf_len + EFX_RX_PACKED_STREAM_ALIGNMENT;
876 EFSYS_ASSERT3U(*next_offsetp, <=, buffer_length);
877 EFSYS_ASSERT3U(current_offset + *lengthp, <, *next_offsetp);
879 if ((*next_offsetp ^ current_offset) &
880 EFX_RX_PACKED_STREAM_MEM_PER_CREDIT)
881 rxq_state->eers_rx_packed_stream_credits++;
889 __checkReturn efx_rc_t
893 efx_nic_t *enp = erp->er_enp;
896 if ((rc = efx_mcdi_fini_rxq(enp, erp->er_index)) != 0)
903 * EALREADY is not an error, but indicates that the MC has rebooted and
904 * that the RXQ has already been destroyed. Callers need to know that
905 * the RXQ flush has completed to avoid waiting until timeout for a
906 * flush done event that will not be delivered.
909 EFSYS_PROBE1(fail1, efx_rc_t, rc);
919 _NOTE(ARGUNUSED(erp))
923 __checkReturn efx_rc_t
926 __in unsigned int index,
927 __in unsigned int label,
928 __in efx_rxq_type_t type,
929 __in uint32_t type_data,
930 __in efsys_mem_t *esmp,
933 __in unsigned int flags,
937 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
939 boolean_t disable_scatter;
940 boolean_t want_inner_classes;
941 unsigned int ps_buf_size;
943 _NOTE(ARGUNUSED(id, erp, type_data))
945 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS == (1 << ESF_DZ_RX_QLABEL_WIDTH));
946 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
947 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
949 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
950 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
953 (ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {
957 if (index >= encp->enc_rxq_limit) {
963 case EFX_RXQ_TYPE_DEFAULT:
966 #if EFSYS_OPT_RX_PACKED_STREAM
967 case EFX_RXQ_TYPE_PACKED_STREAM:
969 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M:
970 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M;
972 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K:
973 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K;
975 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K:
976 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K;
978 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K:
979 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K;
981 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K:
982 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K;
989 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
995 #if EFSYS_OPT_RX_PACKED_STREAM
996 if (ps_buf_size != 0) {
997 /* Check if datapath firmware supports packed stream mode */
998 if (encp->enc_rx_packed_stream_supported == B_FALSE) {
1002 /* Check if packed stream allows configurable buffer sizes */
1003 if ((ps_buf_size != MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M) &&
1004 (encp->enc_rx_var_packed_stream_supported == B_FALSE)) {
1009 #else /* EFSYS_OPT_RX_PACKED_STREAM */
1010 EFSYS_ASSERT(ps_buf_size == 0);
1011 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1013 /* Scatter can only be disabled if the firmware supports doing so */
1014 if (flags & EFX_RXQ_FLAG_SCATTER)
1015 disable_scatter = B_FALSE;
1017 disable_scatter = encp->enc_rx_disable_scatter_supported;
1019 if (flags & EFX_RXQ_FLAG_INNER_CLASSES)
1020 want_inner_classes = B_TRUE;
1022 want_inner_classes = B_FALSE;
1024 if ((rc = efx_mcdi_init_rxq(enp, ndescs, eep->ee_index, label, index,
1025 esmp, disable_scatter, want_inner_classes,
1030 erp->er_label = label;
1032 ef10_ev_rxlabel_init(eep, erp, label, type);
1034 erp->er_ev_qstate = &erp->er_eep->ee_rxq_state[label];
1040 #if EFSYS_OPT_RX_PACKED_STREAM
1045 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1048 #if EFSYS_OPT_RX_PACKED_STREAM
1051 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1055 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1062 __in efx_rxq_t *erp)
1064 efx_nic_t *enp = erp->er_enp;
1065 efx_evq_t *eep = erp->er_eep;
1066 unsigned int label = erp->er_label;
1068 ef10_ev_rxlabel_fini(eep, label);
1070 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1071 --enp->en_rx_qcount;
1073 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1078 __in efx_nic_t *enp)
1080 #if EFSYS_OPT_RX_SCALE
1081 if (enp->en_rss_context_type != EFX_RX_SCALE_UNAVAILABLE)
1082 (void) efx_mcdi_rss_context_free(enp, enp->en_rss_context);
1083 enp->en_rss_context = 0;
1084 enp->en_rss_context_type = EFX_RX_SCALE_UNAVAILABLE;
1086 _NOTE(ARGUNUSED(enp))
1087 #endif /* EFSYS_OPT_RX_SCALE */
1090 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */