1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
11 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
14 static __checkReturn efx_rc_t
18 __in uint32_t target_evq,
20 __in uint32_t instance,
21 __in efsys_mem_t *esmp,
22 __in boolean_t disable_scatter,
23 __in boolean_t want_inner_classes,
24 __in uint32_t ps_bufsize,
25 __in uint32_t es_bufs_per_desc,
26 __in uint32_t es_max_dma_len,
27 __in uint32_t es_buf_stride,
28 __in uint32_t hol_block_timeout)
30 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
32 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_INIT_RXQ_V3_IN_LEN,
33 MC_CMD_INIT_RXQ_V3_OUT_LEN);
34 int npages = EFX_RXQ_NBUFS(ndescs);
36 efx_qword_t *dma_addr;
40 boolean_t want_outer_classes;
42 EFSYS_ASSERT3U(ndescs, <=, EFX_RXQ_MAXNDESCS);
44 if ((esmp == NULL) || (EFSYS_MEM_SIZE(esmp) < EFX_RXQ_SIZE(ndescs))) {
50 dma_mode = MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM;
51 else if (es_bufs_per_desc > 0)
52 dma_mode = MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER;
54 dma_mode = MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET;
56 if (encp->enc_tunnel_encapsulations_supported != 0 &&
57 !want_inner_classes) {
59 * WANT_OUTER_CLASSES can only be specified on hardware which
60 * supports tunnel encapsulation offloads, even though it is
61 * effectively the behaviour the hardware gives.
63 * Also, on hardware which does support such offloads, older
64 * firmware rejects the flag if the offloads are not supported
65 * by the current firmware variant, which means this may fail if
66 * the capabilities are not updated when the firmware variant
67 * changes. This is not an issue on newer firmware, as it was
68 * changed in bug 69842 (v6.4.2.1007) to permit this flag to be
69 * specified on all firmware variants.
71 want_outer_classes = B_TRUE;
73 want_outer_classes = B_FALSE;
76 req.emr_cmd = MC_CMD_INIT_RXQ;
77 req.emr_in_buf = payload;
78 req.emr_in_length = MC_CMD_INIT_RXQ_V3_IN_LEN;
79 req.emr_out_buf = payload;
80 req.emr_out_length = MC_CMD_INIT_RXQ_V3_OUT_LEN;
82 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_SIZE, ndescs);
83 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_TARGET_EVQ, target_evq);
84 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_LABEL, label);
85 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_INSTANCE, instance);
86 MCDI_IN_POPULATE_DWORD_9(req, INIT_RXQ_EXT_IN_FLAGS,
87 INIT_RXQ_EXT_IN_FLAG_BUFF_MODE, 0,
88 INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT, 0,
89 INIT_RXQ_EXT_IN_FLAG_TIMESTAMP, 0,
90 INIT_RXQ_EXT_IN_CRC_MODE, 0,
91 INIT_RXQ_EXT_IN_FLAG_PREFIX, 1,
92 INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER, disable_scatter,
93 INIT_RXQ_EXT_IN_DMA_MODE,
95 INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE, ps_bufsize,
96 INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES, want_outer_classes);
97 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_OWNER_ID, 0);
98 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
100 if (es_bufs_per_desc > 0) {
101 MCDI_IN_SET_DWORD(req,
102 INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET,
104 MCDI_IN_SET_DWORD(req,
105 INIT_RXQ_V3_IN_ES_MAX_DMA_LEN, es_max_dma_len);
106 MCDI_IN_SET_DWORD(req,
107 INIT_RXQ_V3_IN_ES_PACKET_STRIDE, es_buf_stride);
108 MCDI_IN_SET_DWORD(req,
109 INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT,
113 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_RXQ_IN_DMA_ADDR);
114 addr = EFSYS_MEM_ADDR(esmp);
116 for (i = 0; i < npages; i++) {
117 EFX_POPULATE_QWORD_2(*dma_addr,
118 EFX_DWORD_1, (uint32_t)(addr >> 32),
119 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
122 addr += EFX_BUF_SIZE;
125 efx_mcdi_execute(enp, &req);
127 if (req.emr_rc != 0) {
137 EFSYS_PROBE1(fail1, efx_rc_t, rc);
142 static __checkReturn efx_rc_t
145 __in uint32_t instance)
148 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FINI_RXQ_IN_LEN,
149 MC_CMD_FINI_RXQ_OUT_LEN);
152 req.emr_cmd = MC_CMD_FINI_RXQ;
153 req.emr_in_buf = payload;
154 req.emr_in_length = MC_CMD_FINI_RXQ_IN_LEN;
155 req.emr_out_buf = payload;
156 req.emr_out_length = MC_CMD_FINI_RXQ_OUT_LEN;
158 MCDI_IN_SET_DWORD(req, FINI_RXQ_IN_INSTANCE, instance);
160 efx_mcdi_execute_quiet(enp, &req);
162 if (req.emr_rc != 0) {
171 * EALREADY is not an error, but indicates that the MC has rebooted and
172 * that the RXQ has already been destroyed.
175 EFSYS_PROBE1(fail1, efx_rc_t, rc);
180 #if EFSYS_OPT_RX_SCALE
181 static __checkReturn efx_rc_t
182 efx_mcdi_rss_context_alloc(
184 __in efx_rx_scale_context_type_t type,
185 __in uint32_t num_queues,
186 __out uint32_t *rss_contextp)
189 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN,
190 MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
191 uint32_t rss_context;
192 uint32_t context_type;
195 if (num_queues > EFX_MAXRSS) {
201 case EFX_RX_SCALE_EXCLUSIVE:
202 context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE;
204 case EFX_RX_SCALE_SHARED:
205 context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
212 req.emr_cmd = MC_CMD_RSS_CONTEXT_ALLOC;
213 req.emr_in_buf = payload;
214 req.emr_in_length = MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN;
215 req.emr_out_buf = payload;
216 req.emr_out_length = MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN;
218 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
219 EVB_PORT_ID_ASSIGNED);
220 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_TYPE, context_type);
223 * For exclusive contexts, NUM_QUEUES is only used to validate
224 * indirection table offsets.
225 * For shared contexts, the provided context will spread traffic over
226 * NUM_QUEUES many queues.
228 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, num_queues);
230 efx_mcdi_execute(enp, &req);
232 if (req.emr_rc != 0) {
237 if (req.emr_out_length_used < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) {
242 rss_context = MCDI_OUT_DWORD(req, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
243 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
248 *rss_contextp = rss_context;
261 EFSYS_PROBE1(fail1, efx_rc_t, rc);
265 #endif /* EFSYS_OPT_RX_SCALE */
267 #if EFSYS_OPT_RX_SCALE
269 efx_mcdi_rss_context_free(
271 __in uint32_t rss_context)
274 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_FREE_IN_LEN,
275 MC_CMD_RSS_CONTEXT_FREE_OUT_LEN);
278 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
283 req.emr_cmd = MC_CMD_RSS_CONTEXT_FREE;
284 req.emr_in_buf = payload;
285 req.emr_in_length = MC_CMD_RSS_CONTEXT_FREE_IN_LEN;
286 req.emr_out_buf = payload;
287 req.emr_out_length = MC_CMD_RSS_CONTEXT_FREE_OUT_LEN;
289 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID, rss_context);
291 efx_mcdi_execute_quiet(enp, &req);
293 if (req.emr_rc != 0) {
303 EFSYS_PROBE1(fail1, efx_rc_t, rc);
307 #endif /* EFSYS_OPT_RX_SCALE */
309 #if EFSYS_OPT_RX_SCALE
311 efx_mcdi_rss_context_set_flags(
313 __in uint32_t rss_context,
314 __in efx_rx_hash_type_t type)
316 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
318 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN,
319 MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN);
322 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_TCP_LBN ==
323 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN);
324 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_TCP_WIDTH ==
325 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH);
326 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_LBN ==
327 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN);
328 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_WIDTH ==
329 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH);
330 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_TCP_LBN ==
331 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN);
332 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_TCP_WIDTH ==
333 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH);
334 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_LBN ==
335 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN);
336 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_WIDTH ==
337 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH);
339 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
344 req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_FLAGS;
345 req.emr_in_buf = payload;
346 req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN;
347 req.emr_out_buf = payload;
348 req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN;
350 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID,
354 * If the firmware lacks support for additional modes, RSS_MODE
355 * fields must contain zeros, otherwise the operation will fail.
357 if (encp->enc_rx_scale_additional_modes_supported == B_FALSE)
358 type &= EFX_RX_HASH_LEGACY_MASK;
360 MCDI_IN_POPULATE_DWORD_10(req, RSS_CONTEXT_SET_FLAGS_IN_FLAGS,
361 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN,
362 (type & EFX_RX_HASH_IPV4) ? 1 : 0,
363 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN,
364 (type & EFX_RX_HASH_TCPIPV4) ? 1 : 0,
365 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN,
366 (type & EFX_RX_HASH_IPV6) ? 1 : 0,
367 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN,
368 (type & EFX_RX_HASH_TCPIPV6) ? 1 : 0,
369 RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE,
370 (type >> EFX_RX_CLASS_IPV4_TCP_LBN) &
371 EFX_MASK32(EFX_RX_CLASS_IPV4_TCP),
372 RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE,
373 (type >> EFX_RX_CLASS_IPV4_UDP_LBN) &
374 EFX_MASK32(EFX_RX_CLASS_IPV4_UDP),
375 RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE,
376 (type >> EFX_RX_CLASS_IPV4_LBN) & EFX_MASK32(EFX_RX_CLASS_IPV4),
377 RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE,
378 (type >> EFX_RX_CLASS_IPV6_TCP_LBN) &
379 EFX_MASK32(EFX_RX_CLASS_IPV6_TCP),
380 RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE,
381 (type >> EFX_RX_CLASS_IPV6_UDP_LBN) &
382 EFX_MASK32(EFX_RX_CLASS_IPV6_UDP),
383 RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE,
384 (type >> EFX_RX_CLASS_IPV6_LBN) & EFX_MASK32(EFX_RX_CLASS_IPV6));
386 efx_mcdi_execute(enp, &req);
388 if (req.emr_rc != 0) {
398 EFSYS_PROBE1(fail1, efx_rc_t, rc);
402 #endif /* EFSYS_OPT_RX_SCALE */
404 #if EFSYS_OPT_RX_SCALE
406 efx_mcdi_rss_context_set_key(
408 __in uint32_t rss_context,
409 __in_ecount(n) uint8_t *key,
413 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN,
414 MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN);
417 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
422 req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_KEY;
423 req.emr_in_buf = payload;
424 req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN;
425 req.emr_out_buf = payload;
426 req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN;
428 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
431 EFSYS_ASSERT3U(n, ==, MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
432 if (n != MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN) {
437 memcpy(MCDI_IN2(req, uint8_t, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY),
440 efx_mcdi_execute(enp, &req);
442 if (req.emr_rc != 0) {
454 EFSYS_PROBE1(fail1, efx_rc_t, rc);
458 #endif /* EFSYS_OPT_RX_SCALE */
460 #if EFSYS_OPT_RX_SCALE
462 efx_mcdi_rss_context_set_table(
464 __in uint32_t rss_context,
465 __in_ecount(n) unsigned int *table,
469 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN,
470 MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN);
474 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
479 req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_TABLE;
480 req.emr_in_buf = payload;
481 req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN;
482 req.emr_out_buf = payload;
483 req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN;
485 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
489 MCDI_IN2(req, uint8_t, RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE);
492 i < MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN;
494 req_table[i] = (n > 0) ? (uint8_t)table[i % n] : 0;
497 efx_mcdi_execute(enp, &req);
499 if (req.emr_rc != 0) {
509 EFSYS_PROBE1(fail1, efx_rc_t, rc);
513 #endif /* EFSYS_OPT_RX_SCALE */
516 __checkReturn efx_rc_t
520 #if EFSYS_OPT_RX_SCALE
522 if (efx_mcdi_rss_context_alloc(enp, EFX_RX_SCALE_EXCLUSIVE, EFX_MAXRSS,
523 &enp->en_rss_context) == 0) {
525 * Allocated an exclusive RSS context, which allows both the
526 * indirection table and key to be modified.
528 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
529 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
532 * Failed to allocate an exclusive RSS context. Continue
533 * operation without support for RSS. The pseudo-header in
534 * received packets will not contain a Toeplitz hash value.
536 enp->en_rss_context_type = EFX_RX_SCALE_UNAVAILABLE;
537 enp->en_hash_support = EFX_RX_HASH_UNAVAILABLE;
540 #endif /* EFSYS_OPT_RX_SCALE */
545 #if EFSYS_OPT_RX_SCATTER
546 __checkReturn efx_rc_t
547 ef10_rx_scatter_enable(
549 __in unsigned int buf_size)
551 _NOTE(ARGUNUSED(enp, buf_size))
554 #endif /* EFSYS_OPT_RX_SCATTER */
556 #if EFSYS_OPT_RX_SCALE
557 __checkReturn efx_rc_t
558 ef10_rx_scale_context_alloc(
560 __in efx_rx_scale_context_type_t type,
561 __in uint32_t num_queues,
562 __out uint32_t *rss_contextp)
566 rc = efx_mcdi_rss_context_alloc(enp, type, num_queues, rss_contextp);
573 EFSYS_PROBE1(fail1, efx_rc_t, rc);
576 #endif /* EFSYS_OPT_RX_SCALE */
578 #if EFSYS_OPT_RX_SCALE
579 __checkReturn efx_rc_t
580 ef10_rx_scale_context_free(
582 __in uint32_t rss_context)
586 rc = efx_mcdi_rss_context_free(enp, rss_context);
593 EFSYS_PROBE1(fail1, efx_rc_t, rc);
596 #endif /* EFSYS_OPT_RX_SCALE */
598 #if EFSYS_OPT_RX_SCALE
599 __checkReturn efx_rc_t
600 ef10_rx_scale_mode_set(
602 __in uint32_t rss_context,
603 __in efx_rx_hash_alg_t alg,
604 __in efx_rx_hash_type_t type,
605 __in boolean_t insert)
607 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
610 EFSYS_ASSERT3U(insert, ==, B_TRUE);
612 if ((encp->enc_rx_scale_hash_alg_mask & (1U << alg)) == 0 ||
618 if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
619 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
623 rss_context = enp->en_rss_context;
626 if ((rc = efx_mcdi_rss_context_set_flags(enp,
627 rss_context, type)) != 0)
637 EFSYS_PROBE1(fail1, efx_rc_t, rc);
641 #endif /* EFSYS_OPT_RX_SCALE */
643 #if EFSYS_OPT_RX_SCALE
644 __checkReturn efx_rc_t
645 ef10_rx_scale_key_set(
647 __in uint32_t rss_context,
648 __in_ecount(n) uint8_t *key,
653 EFX_STATIC_ASSERT(EFX_RSS_KEY_SIZE ==
654 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
656 if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
657 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
661 rss_context = enp->en_rss_context;
664 if ((rc = efx_mcdi_rss_context_set_key(enp, rss_context, key, n)) != 0)
672 EFSYS_PROBE1(fail1, efx_rc_t, rc);
676 #endif /* EFSYS_OPT_RX_SCALE */
678 #if EFSYS_OPT_RX_SCALE
679 __checkReturn efx_rc_t
680 ef10_rx_scale_tbl_set(
682 __in uint32_t rss_context,
683 __in_ecount(n) unsigned int *table,
689 if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
690 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
694 rss_context = enp->en_rss_context;
697 if ((rc = efx_mcdi_rss_context_set_table(enp,
698 rss_context, table, n)) != 0)
706 EFSYS_PROBE1(fail1, efx_rc_t, rc);
710 #endif /* EFSYS_OPT_RX_SCALE */
714 * EF10 RX pseudo-header
715 * ---------------------
717 * Receive packets are prefixed by an (optional) 14 byte pseudo-header:
719 * +00: Toeplitz hash value.
720 * (32bit little-endian)
721 * +04: Outer VLAN tag. Zero if the packet did not have an outer VLAN tag.
723 * +06: Inner VLAN tag. Zero if the packet did not have an inner VLAN tag.
725 * +08: Packet Length. Zero if the RX datapath was in cut-through mode.
726 * (16bit little-endian)
727 * +10: MAC timestamp. Zero if timestamping is not enabled.
728 * (32bit little-endian)
730 * See "The RX Pseudo-header" in SF-109306-TC.
733 __checkReturn efx_rc_t
734 ef10_rx_prefix_pktlen(
736 __in uint8_t *buffer,
737 __out uint16_t *lengthp)
739 _NOTE(ARGUNUSED(enp))
742 * The RX pseudo-header contains the packet length, excluding the
743 * pseudo-header. If the hardware receive datapath was operating in
744 * cut-through mode then the length in the RX pseudo-header will be
745 * zero, and the packet length must be obtained from the DMA length
746 * reported in the RX event.
748 *lengthp = buffer[8] | (buffer[9] << 8);
752 #if EFSYS_OPT_RX_SCALE
753 __checkReturn uint32_t
756 __in efx_rx_hash_alg_t func,
757 __in uint8_t *buffer)
759 _NOTE(ARGUNUSED(enp))
762 case EFX_RX_HASHALG_PACKED_STREAM:
763 case EFX_RX_HASHALG_TOEPLITZ:
774 #endif /* EFSYS_OPT_RX_SCALE */
776 #if EFSYS_OPT_RX_PACKED_STREAM
778 * Fake length for RXQ descriptors in packed stream mode
779 * to make hardware happy
781 #define EFX_RXQ_PACKED_STREAM_FAKE_BUF_SIZE 32
787 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
789 __in unsigned int ndescs,
790 __in unsigned int completed,
791 __in unsigned int added)
798 _NOTE(ARGUNUSED(completed))
800 #if EFSYS_OPT_RX_PACKED_STREAM
802 * Real size of the buffer does not fit into ESF_DZ_RX_KER_BYTE_CNT
803 * and equal to 0 after applying mask. Hardware does not like it.
805 if (erp->er_ev_qstate->eers_rx_packed_stream)
806 size = EFX_RXQ_PACKED_STREAM_FAKE_BUF_SIZE;
809 /* The client driver must not overfill the queue */
810 EFSYS_ASSERT3U(added - completed + ndescs, <=,
811 EFX_RXQ_LIMIT(erp->er_mask + 1));
813 id = added & (erp->er_mask);
814 for (i = 0; i < ndescs; i++) {
815 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
816 unsigned int, id, efsys_dma_addr_t, addrp[i],
819 EFX_POPULATE_QWORD_3(qword,
820 ESF_DZ_RX_KER_BYTE_CNT, (uint32_t)(size),
821 ESF_DZ_RX_KER_BUF_ADDR_DW0,
822 (uint32_t)(addrp[i] & 0xffffffff),
823 ESF_DZ_RX_KER_BUF_ADDR_DW1,
824 (uint32_t)(addrp[i] >> 32));
826 offset = id * sizeof (efx_qword_t);
827 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
829 id = (id + 1) & (erp->er_mask);
836 __in unsigned int added,
837 __inout unsigned int *pushedp)
839 efx_nic_t *enp = erp->er_enp;
840 unsigned int pushed = *pushedp;
844 /* Hardware has alignment restriction for WPTR */
845 wptr = P2ALIGN(added, EF10_RX_WPTR_ALIGN);
851 /* Push the populated descriptors out */
852 wptr &= erp->er_mask;
854 EFX_POPULATE_DWORD_1(dword, ERF_DZ_RX_DESC_WPTR, wptr);
856 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
857 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
858 wptr, pushed & erp->er_mask);
859 EFSYS_PIO_WRITE_BARRIER();
860 EFX_BAR_VI_WRITED(enp, ER_DZ_RX_DESC_UPD_REG,
861 erp->er_index, &dword, B_FALSE);
864 #if EFSYS_OPT_RX_PACKED_STREAM
867 ef10_rx_qpush_ps_credits(
870 efx_nic_t *enp = erp->er_enp;
872 efx_evq_rxq_state_t *rxq_state = erp->er_ev_qstate;
875 EFSYS_ASSERT(rxq_state->eers_rx_packed_stream);
877 if (rxq_state->eers_rx_packed_stream_credits == 0)
881 * It is a bug if we think that FW has utilized more
882 * credits than it is allowed to have (maximum). However,
883 * make sure that we do not credit more than maximum anyway.
885 credits = MIN(rxq_state->eers_rx_packed_stream_credits,
886 EFX_RX_PACKED_STREAM_MAX_CREDITS);
887 EFX_POPULATE_DWORD_3(dword,
888 ERF_DZ_RX_DESC_MAGIC_DOORBELL, 1,
889 ERF_DZ_RX_DESC_MAGIC_CMD,
890 ERE_DZ_RX_DESC_MAGIC_CMD_PS_CREDITS,
891 ERF_DZ_RX_DESC_MAGIC_DATA, credits);
892 EFX_BAR_VI_WRITED(enp, ER_DZ_RX_DESC_UPD_REG,
893 erp->er_index, &dword, B_FALSE);
895 rxq_state->eers_rx_packed_stream_credits = 0;
899 * In accordance with SF-112241-TC the received data has the following layout:
900 * - 8 byte pseudo-header which consist of:
901 * - 4 byte little-endian timestamp
902 * - 2 byte little-endian captured length in bytes
903 * - 2 byte little-endian original packet length in bytes
904 * - captured packet bytes
905 * - optional padding to align to 64 bytes boundary
906 * - 64 bytes scratch space for the host software
908 __checkReturn uint8_t *
909 ef10_rx_qps_packet_info(
911 __in uint8_t *buffer,
912 __in uint32_t buffer_length,
913 __in uint32_t current_offset,
914 __out uint16_t *lengthp,
915 __out uint32_t *next_offsetp,
916 __out uint32_t *timestamp)
921 efx_evq_rxq_state_t *rxq_state = erp->er_ev_qstate;
923 EFSYS_ASSERT(rxq_state->eers_rx_packed_stream);
925 buffer += current_offset;
926 pkt_start = buffer + EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE;
928 qwordp = (efx_qword_t *)buffer;
929 *timestamp = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_TSTAMP);
930 *lengthp = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_ORIG_LEN);
931 buf_len = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_CAP_LEN);
933 buf_len = P2ROUNDUP(buf_len + EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE,
934 EFX_RX_PACKED_STREAM_ALIGNMENT);
936 current_offset + buf_len + EFX_RX_PACKED_STREAM_ALIGNMENT;
938 EFSYS_ASSERT3U(*next_offsetp, <=, buffer_length);
939 EFSYS_ASSERT3U(current_offset + *lengthp, <, *next_offsetp);
941 if ((*next_offsetp ^ current_offset) &
942 EFX_RX_PACKED_STREAM_MEM_PER_CREDIT)
943 rxq_state->eers_rx_packed_stream_credits++;
951 __checkReturn efx_rc_t
955 efx_nic_t *enp = erp->er_enp;
958 if ((rc = efx_mcdi_fini_rxq(enp, erp->er_index)) != 0)
965 * EALREADY is not an error, but indicates that the MC has rebooted and
966 * that the RXQ has already been destroyed. Callers need to know that
967 * the RXQ flush has completed to avoid waiting until timeout for a
968 * flush done event that will not be delivered.
971 EFSYS_PROBE1(fail1, efx_rc_t, rc);
981 _NOTE(ARGUNUSED(erp))
985 __checkReturn efx_rc_t
988 __in unsigned int index,
989 __in unsigned int label,
990 __in efx_rxq_type_t type,
991 __in const efx_rxq_type_data_t *type_data,
992 __in efsys_mem_t *esmp,
995 __in unsigned int flags,
999 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1001 boolean_t disable_scatter;
1002 boolean_t want_inner_classes;
1003 unsigned int ps_buf_size;
1004 uint32_t es_bufs_per_desc = 0;
1005 uint32_t es_max_dma_len = 0;
1006 uint32_t es_buf_stride = 0;
1007 uint32_t hol_block_timeout = 0;
1009 _NOTE(ARGUNUSED(id, erp, type_data))
1011 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS == (1 << ESF_DZ_RX_QLABEL_WIDTH));
1012 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1013 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1015 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1016 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1018 if (!ISP2(ndescs) ||
1019 (ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {
1023 if (index >= encp->enc_rxq_limit) {
1029 case EFX_RXQ_TYPE_DEFAULT:
1032 #if EFSYS_OPT_RX_PACKED_STREAM
1033 case EFX_RXQ_TYPE_PACKED_STREAM:
1034 switch (type_data->ertd_packed_stream.eps_buf_size) {
1035 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M:
1036 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M;
1038 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K:
1039 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K;
1041 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K:
1042 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K;
1044 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K:
1045 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K;
1047 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K:
1048 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K;
1055 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1056 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1057 case EFX_RXQ_TYPE_ES_SUPER_BUFFER:
1060 type_data->ertd_es_super_buffer.eessb_bufs_per_desc;
1062 type_data->ertd_es_super_buffer.eessb_max_dma_len;
1064 type_data->ertd_es_super_buffer.eessb_buf_stride;
1066 type_data->ertd_es_super_buffer.eessb_hol_block_timeout;
1068 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1074 #if EFSYS_OPT_RX_PACKED_STREAM
1075 if (ps_buf_size != 0) {
1076 /* Check if datapath firmware supports packed stream mode */
1077 if (encp->enc_rx_packed_stream_supported == B_FALSE) {
1081 /* Check if packed stream allows configurable buffer sizes */
1082 if ((ps_buf_size != MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M) &&
1083 (encp->enc_rx_var_packed_stream_supported == B_FALSE)) {
1088 #else /* EFSYS_OPT_RX_PACKED_STREAM */
1089 EFSYS_ASSERT(ps_buf_size == 0);
1090 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1092 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1093 if (es_bufs_per_desc > 0) {
1094 if (encp->enc_rx_es_super_buffer_supported == B_FALSE) {
1098 if (!IS_P2ALIGNED(es_max_dma_len,
1099 EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT)) {
1103 if (!IS_P2ALIGNED(es_buf_stride,
1104 EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT)) {
1109 #else /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1110 EFSYS_ASSERT(es_bufs_per_desc == 0);
1111 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1113 /* Scatter can only be disabled if the firmware supports doing so */
1114 if (flags & EFX_RXQ_FLAG_SCATTER)
1115 disable_scatter = B_FALSE;
1117 disable_scatter = encp->enc_rx_disable_scatter_supported;
1119 if (flags & EFX_RXQ_FLAG_INNER_CLASSES)
1120 want_inner_classes = B_TRUE;
1122 want_inner_classes = B_FALSE;
1124 if ((rc = efx_mcdi_init_rxq(enp, ndescs, eep->ee_index, label, index,
1125 esmp, disable_scatter, want_inner_classes,
1126 ps_buf_size, es_bufs_per_desc, es_max_dma_len,
1127 es_buf_stride, hol_block_timeout)) != 0)
1131 erp->er_label = label;
1133 ef10_ev_rxlabel_init(eep, erp, label, type);
1135 erp->er_ev_qstate = &erp->er_eep->ee_rxq_state[label];
1140 EFSYS_PROBE(fail10);
1141 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1148 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1149 #if EFSYS_OPT_RX_PACKED_STREAM
1154 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1157 #if EFSYS_OPT_RX_PACKED_STREAM
1160 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1164 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1171 __in efx_rxq_t *erp)
1173 efx_nic_t *enp = erp->er_enp;
1174 efx_evq_t *eep = erp->er_eep;
1175 unsigned int label = erp->er_label;
1177 ef10_ev_rxlabel_fini(eep, label);
1179 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1180 --enp->en_rx_qcount;
1182 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1187 __in efx_nic_t *enp)
1189 #if EFSYS_OPT_RX_SCALE
1190 if (enp->en_rss_context_type != EFX_RX_SCALE_UNAVAILABLE)
1191 (void) efx_mcdi_rss_context_free(enp, enp->en_rss_context);
1192 enp->en_rss_context = 0;
1193 enp->en_rss_context_type = EFX_RX_SCALE_UNAVAILABLE;
1195 _NOTE(ARGUNUSED(enp))
1196 #endif /* EFSYS_OPT_RX_SCALE */
1199 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */