drivers/net/sfc/base/ef10_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2012-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
  12
  13
  14 static  __checkReturn   efx_rc_t
  15 efx_mcdi_init_rxq(
  16         __in            efx_nic_t *enp,
  17         __in            uint32_t ndescs,
  18         __in            uint32_t target_evq,
  19         __in            uint32_t label,
  20         __in            uint32_t instance,
  21         __in            efsys_mem_t *esmp,
  22         __in            boolean_t disable_scatter,
  23         __in            boolean_t want_inner_classes,
  24         __in            uint32_t ps_bufsize,
  25         __in            uint32_t es_bufs_per_desc,
  26         __in            uint32_t es_max_dma_len,
  27         __in            uint32_t es_buf_stride,
  28         __in            uint32_t hol_block_timeout)
  29 {
  30         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
  31         efx_mcdi_req_t req;
  32         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_INIT_RXQ_V3_IN_LEN,
  33                 MC_CMD_INIT_RXQ_V3_OUT_LEN);
  34         int npages = efx_rxq_nbufs(enp, ndescs);
  35         int i;
  36         efx_qword_t *dma_addr;
  37         uint64_t addr;
  38         efx_rc_t rc;
  39         uint32_t dma_mode;
  40         boolean_t want_outer_classes;
  41
  42         EFSYS_ASSERT3U(ndescs, <=, encp->enc_rxq_max_ndescs);
  43
  44         if ((esmp == NULL) ||
  45             (EFSYS_MEM_SIZE(esmp) < efx_rxq_size(enp, ndescs))) {
  46                 rc = EINVAL;
  47                 goto fail1;
  48         }
  49
  50         if (ps_bufsize > 0)
  51                 dma_mode = MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM;
  52         else if (es_bufs_per_desc > 0)
  53                 dma_mode = MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER;
  54         else
  55                 dma_mode = MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET;
  56
  57         if (encp->enc_tunnel_encapsulations_supported != 0 &&
  58             !want_inner_classes) {
  59                 /*
  60                  * WANT_OUTER_CLASSES can only be specified on hardware which
  61                  * supports tunnel encapsulation offloads, even though it is
  62                  * effectively the behaviour the hardware gives.
  63                  *
  64                  * Also, on hardware which does support such offloads, older
  65                  * firmware rejects the flag if the offloads are not supported
  66                  * by the current firmware variant, which means this may fail if
  67                  * the capabilities are not updated when the firmware variant
  68                  * changes. This is not an issue on newer firmware, as it was
  69                  * changed in bug 69842 (v6.4.2.1007) to permit this flag to be
  70                  * specified on all firmware variants.
  71                  */
  72                 want_outer_classes = B_TRUE;
  73         } else {
  74                 want_outer_classes = B_FALSE;
  75         }
  76
  77         req.emr_cmd = MC_CMD_INIT_RXQ;
  78         req.emr_in_buf = payload;
  79         req.emr_in_length = MC_CMD_INIT_RXQ_V3_IN_LEN;
  80         req.emr_out_buf = payload;
  81         req.emr_out_length = MC_CMD_INIT_RXQ_V3_OUT_LEN;
  82
  83         MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_SIZE, ndescs);
  84         MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_TARGET_EVQ, target_evq);
  85         MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_LABEL, label);
  86         MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_INSTANCE, instance);
  87         MCDI_IN_POPULATE_DWORD_9(req, INIT_RXQ_EXT_IN_FLAGS,
  88             INIT_RXQ_EXT_IN_FLAG_BUFF_MODE, 0,
  89             INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT, 0,
  90             INIT_RXQ_EXT_IN_FLAG_TIMESTAMP, 0,
  91             INIT_RXQ_EXT_IN_CRC_MODE, 0,
  92             INIT_RXQ_EXT_IN_FLAG_PREFIX, 1,
  93             INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER, disable_scatter,
  94             INIT_RXQ_EXT_IN_DMA_MODE,
  95             dma_mode,
  96             INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE, ps_bufsize,
  97             INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES, want_outer_classes);
  98         MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_OWNER_ID, 0);
  99         MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
 100
 101         if (es_bufs_per_desc > 0) {
 102                 MCDI_IN_SET_DWORD(req,
 103                     INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET,
 104                     es_bufs_per_desc);
 105                 MCDI_IN_SET_DWORD(req,
 106                     INIT_RXQ_V3_IN_ES_MAX_DMA_LEN, es_max_dma_len);
 107                 MCDI_IN_SET_DWORD(req,
 108                     INIT_RXQ_V3_IN_ES_PACKET_STRIDE, es_buf_stride);
 109                 MCDI_IN_SET_DWORD(req,
 110                     INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT,
 111                     hol_block_timeout);
 112         }
 113
 114         dma_addr = MCDI_IN2(req, efx_qword_t, INIT_RXQ_IN_DMA_ADDR);
 115         addr = EFSYS_MEM_ADDR(esmp);
 116
 117         for (i = 0; i < npages; i++) {
 118                 EFX_POPULATE_QWORD_2(*dma_addr,
 119                     EFX_DWORD_1, (uint32_t)(addr >> 32),
 120                     EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
 121
 122                 dma_addr++;
 123                 addr += EFX_BUF_SIZE;
 124         }
 125
 126         efx_mcdi_execute(enp, &req);
 127
 128         if (req.emr_rc != 0) {
 129                 rc = req.emr_rc;
 130                 goto fail2;
 131         }
 132
 133         return (0);
 134
 135 fail2:
 136         EFSYS_PROBE(fail2);
 137 fail1:
 138         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 139
 140         return (rc);
 141 }
 142
 143 static  __checkReturn   efx_rc_t
 144 efx_mcdi_fini_rxq(
 145         __in            efx_nic_t *enp,
 146         __in            uint32_t instance)
 147 {
 148         efx_mcdi_req_t req;
 149         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FINI_RXQ_IN_LEN,
 150                 MC_CMD_FINI_RXQ_OUT_LEN);
 151         efx_rc_t rc;
 152
 153         req.emr_cmd = MC_CMD_FINI_RXQ;
 154         req.emr_in_buf = payload;
 155         req.emr_in_length = MC_CMD_FINI_RXQ_IN_LEN;
 156         req.emr_out_buf = payload;
 157         req.emr_out_length = MC_CMD_FINI_RXQ_OUT_LEN;
 158
 159         MCDI_IN_SET_DWORD(req, FINI_RXQ_IN_INSTANCE, instance);
 160
 161         efx_mcdi_execute_quiet(enp, &req);
 162
 163         if (req.emr_rc != 0) {
 164                 rc = req.emr_rc;
 165                 goto fail1;
 166         }
 167
 168         return (0);
 169
 170 fail1:
 171         /*
 172          * EALREADY is not an error, but indicates that the MC has rebooted and
 173          * that the RXQ has already been destroyed.
 174          */
 175         if (rc != EALREADY)
 176                 EFSYS_PROBE1(fail1, efx_rc_t, rc);
 177
 178         return (rc);
 179 }
 180
 181 #if EFSYS_OPT_RX_SCALE
 182 static  __checkReturn   efx_rc_t
 183 efx_mcdi_rss_context_alloc(
 184         __in            efx_nic_t *enp,
 185         __in            efx_rx_scale_context_type_t type,
 186         __in            uint32_t num_queues,
 187         __out           uint32_t *rss_contextp)
 188 {
 189         efx_mcdi_req_t req;
 190         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN,
 191                 MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
 192         uint32_t rss_context;
 193         uint32_t context_type;
 194         efx_rc_t rc;
 195
 196         if (num_queues > EFX_MAXRSS) {
 197                 rc = EINVAL;
 198                 goto fail1;
 199         }
 200
 201         switch (type) {
 202         case EFX_RX_SCALE_EXCLUSIVE:
 203                 context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE;
 204                 break;
 205         case EFX_RX_SCALE_SHARED:
 206                 context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
 207                 break;
 208         default:
 209                 rc = EINVAL;
 210                 goto fail2;
 211         }
 212
 213         req.emr_cmd = MC_CMD_RSS_CONTEXT_ALLOC;
 214         req.emr_in_buf = payload;
 215         req.emr_in_length = MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN;
 216         req.emr_out_buf = payload;
 217         req.emr_out_length = MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN;
 218
 219         MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
 220             EVB_PORT_ID_ASSIGNED);
 221         MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_TYPE, context_type);
 222
 223         /*
 224          * For exclusive contexts, NUM_QUEUES is only used to validate
 225          * indirection table offsets.
 226          * For shared contexts, the provided context will spread traffic over
 227          * NUM_QUEUES many queues.
 228          */
 229         MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, num_queues);
 230
 231         efx_mcdi_execute(enp, &req);
 232
 233         if (req.emr_rc != 0) {
 234                 rc = req.emr_rc;
 235                 goto fail3;
 236         }
 237
 238         if (req.emr_out_length_used < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) {
 239                 rc = EMSGSIZE;
 240                 goto fail4;
 241         }
 242
 243         rss_context = MCDI_OUT_DWORD(req, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
 244         if (rss_context == EF10_RSS_CONTEXT_INVALID) {
 245                 rc = ENOENT;
 246                 goto fail5;
 247         }
 248
 249         *rss_contextp = rss_context;
 250
 251         return (0);
 252
 253 fail5:
 254         EFSYS_PROBE(fail5);
 255 fail4:
 256         EFSYS_PROBE(fail4);
 257 fail3:
 258         EFSYS_PROBE(fail3);
 259 fail2:
 260         EFSYS_PROBE(fail2);
 261 fail1:
 262         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 263
 264         return (rc);
 265 }
 266 #endif /* EFSYS_OPT_RX_SCALE */
 267
 268 #if EFSYS_OPT_RX_SCALE
 269 static                  efx_rc_t
 270 efx_mcdi_rss_context_free(
 271         __in            efx_nic_t *enp,
 272         __in            uint32_t rss_context)
 273 {
 274         efx_mcdi_req_t req;
 275         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_FREE_IN_LEN,
 276                 MC_CMD_RSS_CONTEXT_FREE_OUT_LEN);
 277         efx_rc_t rc;
 278
 279         if (rss_context == EF10_RSS_CONTEXT_INVALID) {
 280                 rc = EINVAL;
 281                 goto fail1;
 282         }
 283
 284         req.emr_cmd = MC_CMD_RSS_CONTEXT_FREE;
 285         req.emr_in_buf = payload;
 286         req.emr_in_length = MC_CMD_RSS_CONTEXT_FREE_IN_LEN;
 287         req.emr_out_buf = payload;
 288         req.emr_out_length = MC_CMD_RSS_CONTEXT_FREE_OUT_LEN;
 289
 290         MCDI_IN_SET_DWORD(req, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID, rss_context);
 291
 292         efx_mcdi_execute_quiet(enp, &req);
 293
 294         if (req.emr_rc != 0) {
 295                 rc = req.emr_rc;
 296                 goto fail2;
 297         }
 298
 299         return (0);
 300
 301 fail2:
 302         EFSYS_PROBE(fail2);
 303 fail1:
 304         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 305
 306         return (rc);
 307 }
 308 #endif /* EFSYS_OPT_RX_SCALE */
 309
 310 #if EFSYS_OPT_RX_SCALE
 311 static                  efx_rc_t
 312 efx_mcdi_rss_context_set_flags(
 313         __in            efx_nic_t *enp,
 314         __in            uint32_t rss_context,
 315         __in            efx_rx_hash_type_t type)
 316 {
 317         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 318         efx_mcdi_req_t req;
 319         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN,
 320                 MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN);
 321         efx_rc_t rc;
 322
 323         EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_TCP_LBN ==
 324                     MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN);
 325         EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_TCP_WIDTH ==
 326                     MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH);
 327         EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_LBN ==
 328                     MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN);
 329         EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_WIDTH ==
 330                     MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH);
 331         EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_TCP_LBN ==
 332                     MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN);
 333         EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_TCP_WIDTH ==
 334                     MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH);
 335         EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_LBN ==
 336                     MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN);
 337         EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_WIDTH ==
 338                     MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH);
 339
 340         if (rss_context == EF10_RSS_CONTEXT_INVALID) {
 341                 rc = EINVAL;
 342                 goto fail1;
 343         }
 344
 345         req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_FLAGS;
 346         req.emr_in_buf = payload;
 347         req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN;
 348         req.emr_out_buf = payload;
 349         req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN;
 350
 351         MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID,
 352             rss_context);
 353
 354         /*
 355          * If the firmware lacks support for additional modes, RSS_MODE
 356          * fields must contain zeros, otherwise the operation will fail.
 357          */
 358         if (encp->enc_rx_scale_additional_modes_supported == B_FALSE)
 359                 type &= EFX_RX_HASH_LEGACY_MASK;
 360
 361         MCDI_IN_POPULATE_DWORD_10(req, RSS_CONTEXT_SET_FLAGS_IN_FLAGS,
 362             RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN,
 363             (type & EFX_RX_HASH_IPV4) ? 1 : 0,
 364             RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN,
 365             (type & EFX_RX_HASH_TCPIPV4) ? 1 : 0,
 366             RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN,
 367             (type & EFX_RX_HASH_IPV6) ? 1 : 0,
 368             RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN,
 369             (type & EFX_RX_HASH_TCPIPV6) ? 1 : 0,
 370             RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE,
 371             (type >> EFX_RX_CLASS_IPV4_TCP_LBN) &
 372             EFX_MASK32(EFX_RX_CLASS_IPV4_TCP),
 373             RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE,
 374             (type >> EFX_RX_CLASS_IPV4_UDP_LBN) &
 375             EFX_MASK32(EFX_RX_CLASS_IPV4_UDP),
 376             RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE,
 377             (type >> EFX_RX_CLASS_IPV4_LBN) & EFX_MASK32(EFX_RX_CLASS_IPV4),
 378             RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE,
 379             (type >> EFX_RX_CLASS_IPV6_TCP_LBN) &
 380             EFX_MASK32(EFX_RX_CLASS_IPV6_TCP),
 381             RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE,
 382             (type >> EFX_RX_CLASS_IPV6_UDP_LBN) &
 383             EFX_MASK32(EFX_RX_CLASS_IPV6_UDP),
 384             RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE,
 385             (type >> EFX_RX_CLASS_IPV6_LBN) & EFX_MASK32(EFX_RX_CLASS_IPV6));
 386
 387         efx_mcdi_execute(enp, &req);
 388
 389         if (req.emr_rc != 0) {
 390                 rc = req.emr_rc;
 391                 goto fail2;
 392         }
 393
 394         return (0);
 395
 396 fail2:
 397         EFSYS_PROBE(fail2);
 398 fail1:
 399         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 400
 401         return (rc);
 402 }
 403 #endif /* EFSYS_OPT_RX_SCALE */
 404
 405 #if EFSYS_OPT_RX_SCALE
 406 static                  efx_rc_t
 407 efx_mcdi_rss_context_set_key(
 408         __in            efx_nic_t *enp,
 409         __in            uint32_t rss_context,
 410         __in_ecount(n)  uint8_t *key,
 411         __in            size_t n)
 412 {
 413         efx_mcdi_req_t req;
 414         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN,
 415                 MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN);
 416         efx_rc_t rc;
 417
 418         if (rss_context == EF10_RSS_CONTEXT_INVALID) {
 419                 rc = EINVAL;
 420                 goto fail1;
 421         }
 422
 423         req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_KEY;
 424         req.emr_in_buf = payload;
 425         req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN;
 426         req.emr_out_buf = payload;
 427         req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN;
 428
 429         MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
 430             rss_context);
 431
 432         EFSYS_ASSERT3U(n, ==, MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
 433         if (n != MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN) {
 434                 rc = EINVAL;
 435                 goto fail2;
 436         }
 437
 438         memcpy(MCDI_IN2(req, uint8_t, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY),
 439             key, n);
 440
 441         efx_mcdi_execute(enp, &req);
 442
 443         if (req.emr_rc != 0) {
 444                 rc = req.emr_rc;
 445                 goto fail3;
 446         }
 447
 448         return (0);
 449
 450 fail3:
 451         EFSYS_PROBE(fail3);
 452 fail2:
 453         EFSYS_PROBE(fail2);
 454 fail1:
 455         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 456
 457         return (rc);
 458 }
 459 #endif /* EFSYS_OPT_RX_SCALE */
 460
 461 #if EFSYS_OPT_RX_SCALE
 462 static                  efx_rc_t
 463 efx_mcdi_rss_context_set_table(
 464         __in            efx_nic_t *enp,
 465         __in            uint32_t rss_context,
 466         __in_ecount(n)  unsigned int *table,
 467         __in            size_t n)
 468 {
 469         efx_mcdi_req_t req;
 470         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN,
 471                 MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN);
 472         uint8_t *req_table;
 473         int i, rc;
 474
 475         if (rss_context == EF10_RSS_CONTEXT_INVALID) {
 476                 rc = EINVAL;
 477                 goto fail1;
 478         }
 479
 480         req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_TABLE;
 481         req.emr_in_buf = payload;
 482         req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN;
 483         req.emr_out_buf = payload;
 484         req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN;
 485
 486         MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
 487             rss_context);
 488
 489         req_table =
 490             MCDI_IN2(req, uint8_t, RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE);
 491
 492         for (i = 0;
 493             i < MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN;
 494             i++) {
 495                 req_table[i] = (n > 0) ? (uint8_t)table[i % n] : 0;
 496         }
 497
 498         efx_mcdi_execute(enp, &req);
 499
 500         if (req.emr_rc != 0) {
 501                 rc = req.emr_rc;
 502                 goto fail2;
 503         }
 504
 505         return (0);
 506
 507 fail2:
 508         EFSYS_PROBE(fail2);
 509 fail1:
 510         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 511
 512         return (rc);
 513 }
 514 #endif /* EFSYS_OPT_RX_SCALE */
 515
 516
 517         __checkReturn   efx_rc_t
 518 ef10_rx_init(
 519         __in            efx_nic_t *enp)
 520 {
 521 #if EFSYS_OPT_RX_SCALE
 522
 523         if (efx_mcdi_rss_context_alloc(enp, EFX_RX_SCALE_EXCLUSIVE, EFX_MAXRSS,
 524                 &enp->en_rss_context) == 0) {
 525                 /*
 526                  * Allocated an exclusive RSS context, which allows both the
 527                  * indirection table and key to be modified.
 528                  */
 529                 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
 530                 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
 531         } else {
 532                 /*
 533                  * Failed to allocate an exclusive RSS context. Continue
 534                  * operation without support for RSS. The pseudo-header in
 535                  * received packets will not contain a Toeplitz hash value.
 536                  */
 537                 enp->en_rss_context_type = EFX_RX_SCALE_UNAVAILABLE;
 538                 enp->en_hash_support = EFX_RX_HASH_UNAVAILABLE;
 539         }
 540
 541 #endif /* EFSYS_OPT_RX_SCALE */
 542
 543         return (0);
 544 }
 545
 546 #if EFSYS_OPT_RX_SCATTER
 547         __checkReturn   efx_rc_t
 548 ef10_rx_scatter_enable(
 549         __in            efx_nic_t *enp,
 550         __in            unsigned int buf_size)
 551 {
 552         _NOTE(ARGUNUSED(enp, buf_size))
 553         return (0);
 554 }
 555 #endif  /* EFSYS_OPT_RX_SCATTER */
 556
 557 #if EFSYS_OPT_RX_SCALE
 558         __checkReturn   efx_rc_t
 559 ef10_rx_scale_context_alloc(
 560         __in            efx_nic_t *enp,
 561         __in            efx_rx_scale_context_type_t type,
 562         __in            uint32_t num_queues,
 563         __out           uint32_t *rss_contextp)
 564 {
 565         efx_rc_t rc;
 566
 567         rc = efx_mcdi_rss_context_alloc(enp, type, num_queues, rss_contextp);
 568         if (rc != 0)
 569                 goto fail1;
 570
 571         return (0);
 572
 573 fail1:
 574         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 575         return (rc);
 576 }
 577 #endif /* EFSYS_OPT_RX_SCALE */
 578
 579 #if EFSYS_OPT_RX_SCALE
 580         __checkReturn   efx_rc_t
 581 ef10_rx_scale_context_free(
 582         __in            efx_nic_t *enp,
 583         __in            uint32_t rss_context)
 584 {
 585         efx_rc_t rc;
 586
 587         rc = efx_mcdi_rss_context_free(enp, rss_context);
 588         if (rc != 0)
 589                 goto fail1;
 590
 591         return (0);
 592
 593 fail1:
 594         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 595         return (rc);
 596 }
 597 #endif /* EFSYS_OPT_RX_SCALE */
 598
 599 #if EFSYS_OPT_RX_SCALE
 600         __checkReturn   efx_rc_t
 601 ef10_rx_scale_mode_set(
 602         __in            efx_nic_t *enp,
 603         __in            uint32_t rss_context,
 604         __in            efx_rx_hash_alg_t alg,
 605         __in            efx_rx_hash_type_t type,
 606         __in            boolean_t insert)
 607 {
 608         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 609         efx_rc_t rc;
 610
 611         EFSYS_ASSERT3U(insert, ==, B_TRUE);
 612
 613         if ((encp->enc_rx_scale_hash_alg_mask & (1U << alg)) == 0 ||
 614             insert == B_FALSE) {
 615                 rc = EINVAL;
 616                 goto fail1;
 617         }
 618
 619         if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
 620                 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
 621                         rc = ENOTSUP;
 622                         goto fail2;
 623                 }
 624                 rss_context = enp->en_rss_context;
 625         }
 626
 627         if ((rc = efx_mcdi_rss_context_set_flags(enp,
 628                     rss_context, type)) != 0)
 629                 goto fail3;
 630
 631         return (0);
 632
 633 fail3:
 634         EFSYS_PROBE(fail3);
 635 fail2:
 636         EFSYS_PROBE(fail2);
 637 fail1:
 638         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 639
 640         return (rc);
 641 }
 642 #endif /* EFSYS_OPT_RX_SCALE */
 643
 644 #if EFSYS_OPT_RX_SCALE
 645         __checkReturn   efx_rc_t
 646 ef10_rx_scale_key_set(
 647         __in            efx_nic_t *enp,
 648         __in            uint32_t rss_context,
 649         __in_ecount(n)  uint8_t *key,
 650         __in            size_t n)
 651 {
 652         efx_rc_t rc;
 653
 654         EFX_STATIC_ASSERT(EFX_RSS_KEY_SIZE ==
 655             MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
 656
 657         if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
 658                 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
 659                         rc = ENOTSUP;
 660                         goto fail1;
 661                 }
 662                 rss_context = enp->en_rss_context;
 663         }
 664
 665         if ((rc = efx_mcdi_rss_context_set_key(enp, rss_context, key, n)) != 0)
 666                 goto fail2;
 667
 668         return (0);
 669
 670 fail2:
 671         EFSYS_PROBE(fail2);
 672 fail1:
 673         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 674
 675         return (rc);
 676 }
 677 #endif /* EFSYS_OPT_RX_SCALE */
 678
 679 #if EFSYS_OPT_RX_SCALE
 680         __checkReturn   efx_rc_t
 681 ef10_rx_scale_tbl_set(
 682         __in            efx_nic_t *enp,
 683         __in            uint32_t rss_context,
 684         __in_ecount(n)  unsigned int *table,
 685         __in            size_t n)
 686 {
 687         efx_rc_t rc;
 688
 689
 690         if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
 691                 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
 692                         rc = ENOTSUP;
 693                         goto fail1;
 694                 }
 695                 rss_context = enp->en_rss_context;
 696         }
 697
 698         if ((rc = efx_mcdi_rss_context_set_table(enp,
 699                     rss_context, table, n)) != 0)
 700                 goto fail2;
 701
 702         return (0);
 703
 704 fail2:
 705         EFSYS_PROBE(fail2);
 706 fail1:
 707         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 708
 709         return (rc);
 710 }
 711 #endif /* EFSYS_OPT_RX_SCALE */
 712
 713
 714 /*
 715  * EF10 RX pseudo-header
 716  * ---------------------
 717  *
 718  * Receive packets are prefixed by an (optional) 14 byte pseudo-header:
 719  *
 720  *  +00: Toeplitz hash value.
 721  *       (32bit little-endian)
 722  *  +04: Outer VLAN tag. Zero if the packet did not have an outer VLAN tag.
 723  *       (16bit big-endian)
 724  *  +06: Inner VLAN tag. Zero if the packet did not have an inner VLAN tag.
 725  *       (16bit big-endian)
 726  *  +08: Packet Length. Zero if the RX datapath was in cut-through mode.
 727  *       (16bit little-endian)
 728  *  +10: MAC timestamp. Zero if timestamping is not enabled.
 729  *       (32bit little-endian)
 730  *
 731  * See "The RX Pseudo-header" in SF-109306-TC.
 732  */
 733
 734         __checkReturn   efx_rc_t
 735 ef10_rx_prefix_pktlen(
 736         __in            efx_nic_t *enp,
 737         __in            uint8_t *buffer,
 738         __out           uint16_t *lengthp)
 739 {
 740         _NOTE(ARGUNUSED(enp))
 741
 742         /*
 743          * The RX pseudo-header contains the packet length, excluding the
 744          * pseudo-header. If the hardware receive datapath was operating in
 745          * cut-through mode then the length in the RX pseudo-header will be
 746          * zero, and the packet length must be obtained from the DMA length
 747          * reported in the RX event.
 748          */
 749         *lengthp = buffer[8] | (buffer[9] << 8);
 750         return (0);
 751 }
 752
 753 #if EFSYS_OPT_RX_SCALE
 754         __checkReturn   uint32_t
 755 ef10_rx_prefix_hash(
 756         __in            efx_nic_t *enp,
 757         __in            efx_rx_hash_alg_t func,
 758         __in            uint8_t *buffer)
 759 {
 760         _NOTE(ARGUNUSED(enp))
 761
 762         switch (func) {
 763         case EFX_RX_HASHALG_PACKED_STREAM:
 764         case EFX_RX_HASHALG_TOEPLITZ:
 765                 return (buffer[0] |
 766                     (buffer[1] << 8) |
 767                     (buffer[2] << 16) |
 768                     (buffer[3] << 24));
 769
 770         default:
 771                 EFSYS_ASSERT(0);
 772                 return (0);
 773         }
 774 }
 775 #endif /* EFSYS_OPT_RX_SCALE */
 776
 777 #if EFSYS_OPT_RX_PACKED_STREAM
 778 /*
 779  * Fake length for RXQ descriptors in packed stream mode
 780  * to make hardware happy
 781  */
 782 #define EFX_RXQ_PACKED_STREAM_FAKE_BUF_SIZE 32
 783 #endif
 784
 785                                 void
 786 ef10_rx_qpost(
 787         __in                    efx_rxq_t *erp,
 788         __in_ecount(ndescs)     efsys_dma_addr_t *addrp,
 789         __in                    size_t size,
 790         __in                    unsigned int ndescs,
 791         __in                    unsigned int completed,
 792         __in                    unsigned int added)
 793 {
 794         efx_qword_t qword;
 795         unsigned int i;
 796         unsigned int offset;
 797         unsigned int id;
 798
 799         _NOTE(ARGUNUSED(completed))
 800
 801 #if EFSYS_OPT_RX_PACKED_STREAM
 802         /*
 803          * Real size of the buffer does not fit into ESF_DZ_RX_KER_BYTE_CNT
 804          * and equal to 0 after applying mask. Hardware does not like it.
 805          */
 806         if (erp->er_ev_qstate->eers_rx_packed_stream)
 807                 size = EFX_RXQ_PACKED_STREAM_FAKE_BUF_SIZE;
 808 #endif
 809
 810         /* The client driver must not overfill the queue */
 811         EFSYS_ASSERT3U(added - completed + ndescs, <=,
 812             EFX_RXQ_LIMIT(erp->er_mask + 1));
 813
 814         id = added & (erp->er_mask);
 815         for (i = 0; i < ndescs; i++) {
 816                 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
 817                     unsigned int, id, efsys_dma_addr_t, addrp[i],
 818                     size_t, size);
 819
 820                 EFX_POPULATE_QWORD_3(qword,
 821                     ESF_DZ_RX_KER_BYTE_CNT, (uint32_t)(size),
 822                     ESF_DZ_RX_KER_BUF_ADDR_DW0,
 823                     (uint32_t)(addrp[i] & 0xffffffff),
 824                     ESF_DZ_RX_KER_BUF_ADDR_DW1,
 825                     (uint32_t)(addrp[i] >> 32));
 826
 827                 offset = id * sizeof (efx_qword_t);
 828                 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
 829
 830                 id = (id + 1) & (erp->er_mask);
 831         }
 832 }
 833
 834                         void
 835 ef10_rx_qpush(
 836         __in    efx_rxq_t *erp,
 837         __in    unsigned int added,
 838         __inout unsigned int *pushedp)
 839 {
 840         efx_nic_t *enp = erp->er_enp;
 841         unsigned int pushed = *pushedp;
 842         uint32_t wptr;
 843         efx_dword_t dword;
 844
 845         /* Hardware has alignment restriction for WPTR */
 846         wptr = P2ALIGN(added, EF10_RX_WPTR_ALIGN);
 847         if (pushed == wptr)
 848                 return;
 849
 850         *pushedp = wptr;
 851
 852         /* Push the populated descriptors out */
 853         wptr &= erp->er_mask;
 854
 855         EFX_POPULATE_DWORD_1(dword, ERF_DZ_RX_DESC_WPTR, wptr);
 856
 857         /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
 858         EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
 859             wptr, pushed & erp->er_mask);
 860         EFSYS_PIO_WRITE_BARRIER();
 861         EFX_BAR_VI_WRITED(enp, ER_DZ_RX_DESC_UPD_REG,
 862             erp->er_index, &dword, B_FALSE);
 863 }
 864
 865 #if EFSYS_OPT_RX_PACKED_STREAM
 866
 867                         void
 868 ef10_rx_qpush_ps_credits(
 869         __in            efx_rxq_t *erp)
 870 {
 871         efx_nic_t *enp = erp->er_enp;
 872         efx_dword_t dword;
 873         efx_evq_rxq_state_t *rxq_state = erp->er_ev_qstate;
 874         uint32_t credits;
 875
 876         EFSYS_ASSERT(rxq_state->eers_rx_packed_stream);
 877
 878         if (rxq_state->eers_rx_packed_stream_credits == 0)
 879                 return;
 880
 881         /*
 882          * It is a bug if we think that FW has utilized more
 883          * credits than it is allowed to have (maximum). However,
 884          * make sure that we do not credit more than maximum anyway.
 885          */
 886         credits = MIN(rxq_state->eers_rx_packed_stream_credits,
 887             EFX_RX_PACKED_STREAM_MAX_CREDITS);
 888         EFX_POPULATE_DWORD_3(dword,
 889             ERF_DZ_RX_DESC_MAGIC_DOORBELL, 1,
 890             ERF_DZ_RX_DESC_MAGIC_CMD,
 891             ERE_DZ_RX_DESC_MAGIC_CMD_PS_CREDITS,
 892             ERF_DZ_RX_DESC_MAGIC_DATA, credits);
 893         EFX_BAR_VI_WRITED(enp, ER_DZ_RX_DESC_UPD_REG,
 894             erp->er_index, &dword, B_FALSE);
 895
 896         rxq_state->eers_rx_packed_stream_credits = 0;
 897 }
 898
 899 /*
 900  * In accordance with SF-112241-TC the received data has the following layout:
 901  *  - 8 byte pseudo-header which consist of:
 902  *    - 4 byte little-endian timestamp
 903  *    - 2 byte little-endian captured length in bytes
 904  *    - 2 byte little-endian original packet length in bytes
 905  *  - captured packet bytes
 906  *  - optional padding to align to 64 bytes boundary
 907  *  - 64 bytes scratch space for the host software
 908  */
 909         __checkReturn   uint8_t *
 910 ef10_rx_qps_packet_info(
 911         __in            efx_rxq_t *erp,
 912         __in            uint8_t *buffer,
 913         __in            uint32_t buffer_length,
 914         __in            uint32_t current_offset,
 915         __out           uint16_t *lengthp,
 916         __out           uint32_t *next_offsetp,
 917         __out           uint32_t *timestamp)
 918 {
 919         uint16_t buf_len;
 920         uint8_t *pkt_start;
 921         efx_qword_t *qwordp;
 922         efx_evq_rxq_state_t *rxq_state = erp->er_ev_qstate;
 923
 924         EFSYS_ASSERT(rxq_state->eers_rx_packed_stream);
 925
 926         buffer += current_offset;
 927         pkt_start = buffer + EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE;
 928
 929         qwordp = (efx_qword_t *)buffer;
 930         *timestamp = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_TSTAMP);
 931         *lengthp   = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_ORIG_LEN);
 932         buf_len    = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_CAP_LEN);
 933
 934         buf_len = P2ROUNDUP(buf_len + EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE,
 935                             EFX_RX_PACKED_STREAM_ALIGNMENT);
 936         *next_offsetp =
 937             current_offset + buf_len + EFX_RX_PACKED_STREAM_ALIGNMENT;
 938
 939         EFSYS_ASSERT3U(*next_offsetp, <=, buffer_length);
 940         EFSYS_ASSERT3U(current_offset + *lengthp, <, *next_offsetp);
 941
 942         if ((*next_offsetp ^ current_offset) &
 943             EFX_RX_PACKED_STREAM_MEM_PER_CREDIT)
 944                 rxq_state->eers_rx_packed_stream_credits++;
 945
 946         return (pkt_start);
 947 }
 948
 949
 950 #endif
 951
 952         __checkReturn   efx_rc_t
 953 ef10_rx_qflush(
 954         __in    efx_rxq_t *erp)
 955 {
 956         efx_nic_t *enp = erp->er_enp;
 957         efx_rc_t rc;
 958
 959         if ((rc = efx_mcdi_fini_rxq(enp, erp->er_index)) != 0)
 960                 goto fail1;
 961
 962         return (0);
 963
 964 fail1:
 965         /*
 966          * EALREADY is not an error, but indicates that the MC has rebooted and
 967          * that the RXQ has already been destroyed. Callers need to know that
 968          * the RXQ flush has completed to avoid waiting until timeout for a
 969          * flush done event that will not be delivered.
 970          */
 971         if (rc != EALREADY)
 972                 EFSYS_PROBE1(fail1, efx_rc_t, rc);
 973
 974         return (rc);
 975 }
 976
 977                 void
 978 ef10_rx_qenable(
 979         __in    efx_rxq_t *erp)
 980 {
 981         /* FIXME */
 982         _NOTE(ARGUNUSED(erp))
 983         /* FIXME */
 984 }
 985
 986         __checkReturn   efx_rc_t
 987 ef10_rx_qcreate(
 988         __in            efx_nic_t *enp,
 989         __in            unsigned int index,
 990         __in            unsigned int label,
 991         __in            efx_rxq_type_t type,
 992         __in_opt        const efx_rxq_type_data_t *type_data,
 993         __in            efsys_mem_t *esmp,
 994         __in            size_t ndescs,
 995         __in            uint32_t id,
 996         __in            unsigned int flags,
 997         __in            efx_evq_t *eep,
 998         __in            efx_rxq_t *erp)
 999 {
1000         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1001         efx_rc_t rc;
1002         boolean_t disable_scatter;
1003         boolean_t want_inner_classes;
1004         unsigned int ps_buf_size;
1005         uint32_t es_bufs_per_desc = 0;
1006         uint32_t es_max_dma_len = 0;
1007         uint32_t es_buf_stride = 0;
1008         uint32_t hol_block_timeout = 0;
1009
1010         _NOTE(ARGUNUSED(id, erp, type_data))
1011
1012         EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS == (1 << ESF_DZ_RX_QLABEL_WIDTH));
1013         EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1014         EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1015
1016         if (index >= encp->enc_rxq_limit) {
1017                 rc = EINVAL;
1018                 goto fail1;
1019         }
1020
1021         switch (type) {
1022         case EFX_RXQ_TYPE_DEFAULT:
1023                 ps_buf_size = 0;
1024                 break;
1025 #if EFSYS_OPT_RX_PACKED_STREAM
1026         case EFX_RXQ_TYPE_PACKED_STREAM:
1027                 if (type_data == NULL) {
1028                         rc = EINVAL;
1029                         goto fail2;
1030                 }
1031                 switch (type_data->ertd_packed_stream.eps_buf_size) {
1032                 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M:
1033                         ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M;
1034                         break;
1035                 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K:
1036                         ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K;
1037                         break;
1038                 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K:
1039                         ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K;
1040                         break;
1041                 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K:
1042                         ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K;
1043                         break;
1044                 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K:
1045                         ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K;
1046                         break;
1047                 default:
1048                         rc = ENOTSUP;
1049                         goto fail3;
1050                 }
1051                 break;
1052 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1053 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1054         case EFX_RXQ_TYPE_ES_SUPER_BUFFER:
1055                 if (type_data == NULL) {
1056                         rc = EINVAL;
1057                         goto fail4;
1058                 }
1059                 ps_buf_size = 0;
1060                 es_bufs_per_desc =
1061                     type_data->ertd_es_super_buffer.eessb_bufs_per_desc;
1062                 es_max_dma_len =
1063                     type_data->ertd_es_super_buffer.eessb_max_dma_len;
1064                 es_buf_stride =
1065                     type_data->ertd_es_super_buffer.eessb_buf_stride;
1066                 hol_block_timeout =
1067                     type_data->ertd_es_super_buffer.eessb_hol_block_timeout;
1068                 break;
1069 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1070         default:
1071                 rc = ENOTSUP;
1072                 goto fail5;
1073         }
1074
1075 #if EFSYS_OPT_RX_PACKED_STREAM
1076         if (ps_buf_size != 0) {
1077                 /* Check if datapath firmware supports packed stream mode */
1078                 if (encp->enc_rx_packed_stream_supported == B_FALSE) {
1079                         rc = ENOTSUP;
1080                         goto fail6;
1081                 }
1082                 /* Check if packed stream allows configurable buffer sizes */
1083                 if ((ps_buf_size != MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M) &&
1084                     (encp->enc_rx_var_packed_stream_supported == B_FALSE)) {
1085                         rc = ENOTSUP;
1086                         goto fail7;
1087                 }
1088         }
1089 #else /* EFSYS_OPT_RX_PACKED_STREAM */
1090         EFSYS_ASSERT(ps_buf_size == 0);
1091 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1092
1093 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1094         if (es_bufs_per_desc > 0) {
1095                 if (encp->enc_rx_es_super_buffer_supported == B_FALSE) {
1096                         rc = ENOTSUP;
1097                         goto fail8;
1098                 }
1099                 if (!IS_P2ALIGNED(es_max_dma_len,
1100                             EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT)) {
1101                         rc = EINVAL;
1102                         goto fail9;
1103                 }
1104                 if (!IS_P2ALIGNED(es_buf_stride,
1105                             EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT)) {
1106                         rc = EINVAL;
1107                         goto fail10;
1108                 }
1109         }
1110 #else /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1111         EFSYS_ASSERT(es_bufs_per_desc == 0);
1112 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1113
1114         /* Scatter can only be disabled if the firmware supports doing so */
1115         if (flags & EFX_RXQ_FLAG_SCATTER)
1116                 disable_scatter = B_FALSE;
1117         else
1118                 disable_scatter = encp->enc_rx_disable_scatter_supported;
1119
1120         if (flags & EFX_RXQ_FLAG_INNER_CLASSES)
1121                 want_inner_classes = B_TRUE;
1122         else
1123                 want_inner_classes = B_FALSE;
1124
1125         if ((rc = efx_mcdi_init_rxq(enp, ndescs, eep->ee_index, label, index,
1126                     esmp, disable_scatter, want_inner_classes,
1127                     ps_buf_size, es_bufs_per_desc, es_max_dma_len,
1128                     es_buf_stride, hol_block_timeout)) != 0)
1129                 goto fail11;
1130
1131         erp->er_eep = eep;
1132         erp->er_label = label;
1133
1134         ef10_ev_rxlabel_init(eep, erp, label, type);
1135
1136         erp->er_ev_qstate = &erp->er_eep->ee_rxq_state[label];
1137
1138         return (0);
1139
1140 fail11:
1141         EFSYS_PROBE(fail11);
1142 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1143 fail10:
1144         EFSYS_PROBE(fail10);
1145 fail9:
1146         EFSYS_PROBE(fail9);
1147 fail8:
1148         EFSYS_PROBE(fail8);
1149 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1150 #if EFSYS_OPT_RX_PACKED_STREAM
1151 fail7:
1152         EFSYS_PROBE(fail7);
1153 fail6:
1154         EFSYS_PROBE(fail6);
1155 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1156 fail5:
1157         EFSYS_PROBE(fail5);
1158 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1159 fail4:
1160         EFSYS_PROBE(fail4);
1161 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1162 #if EFSYS_OPT_RX_PACKED_STREAM
1163 fail3:
1164         EFSYS_PROBE(fail3);
1165 fail2:
1166         EFSYS_PROBE(fail2);
1167 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1168 fail1:
1169         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1170
1171         return (rc);
1172 }
1173
1174                 void
1175 ef10_rx_qdestroy(
1176         __in    efx_rxq_t *erp)
1177 {
1178         efx_nic_t *enp = erp->er_enp;
1179         efx_evq_t *eep = erp->er_eep;
1180         unsigned int label = erp->er_label;
1181
1182         ef10_ev_rxlabel_fini(eep, label);
1183
1184         EFSYS_ASSERT(enp->en_rx_qcount != 0);
1185         --enp->en_rx_qcount;
1186
1187         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1188 }
1189
1190                 void
1191 ef10_rx_fini(
1192         __in    efx_nic_t *enp)
1193 {
1194 #if EFSYS_OPT_RX_SCALE
1195         if (enp->en_rss_context_type != EFX_RX_SCALE_UNAVAILABLE)
1196                 (void) efx_mcdi_rss_context_free(enp, enp->en_rss_context);
1197         enp->en_rss_context = 0;
1198         enp->en_rss_context_type = EFX_RX_SCALE_UNAVAILABLE;
1199 #else
1200         _NOTE(ARGUNUSED(enp))
1201 #endif /* EFSYS_OPT_RX_SCALE */
1202 }
1203
1204 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */