1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
8 * This is NOT the original source file. Do NOT edit it.
9 * To update the tlv layout, please edit the copy in
10 * the sfregistry repo and then, in that repo,
11 * "make tlv_headers" or "make export" to
12 * regenerate and export all types of headers.
15 /* These structures define the layouts for the TLV items stored in static and
16 * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.).
18 * They contain the same sort of information that was kept in the
19 * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures
20 * (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for
23 * These are used directly by the MC and should also be usable directly on host
24 * systems which are little-endian and do not do strange things with structure
25 * padding. (Big-endian host systems will require some byte-swapping.)
29 * Please refer to SF-108797-SW for a general overview of the TLV partition
34 * The current tag IDs have a general structure: with the exception of the
35 * special values defined in the document, they are of the form 0xLTTTNNNN,
38 * - L is a location, indicating where this tag is expected to be found:
39 * 0: static configuration
40 * 1: dynamic configuration
41 * 2: firmware internal use
42 * 3: license partition
43 * 4: tsa configuration
45 * - TTT is a type, which is just a unique value. The same type value
46 * might appear in both locations, indicating a relationship between
47 * the items (e.g. static and dynamic VPD below).
49 * - NNNN is an index of some form. Some item types are per-port, some
50 * are per-PF, some are per-partition-type.
54 * As with the previous Siena structures, each structure here is laid out
55 * carefully: values are aligned to their natural boundary, with explicit
56 * padding fields added where necessary. (No, technically this does not
57 * absolutely guarantee portability. But, in practice, compilers are generally
58 * sensible enough not to introduce completely pointless padding, and it works
63 #ifndef CI_MGMT_TLV_LAYOUT_H
64 #define CI_MGMT_TLV_LAYOUT_H
67 /* ----------------------------------------------------------------------------
68 * General structure (defined by SF-108797-SW)
69 * ----------------------------------------------------------------------------
75 * (Note that this is *not* followed by length or value fields: anything after
76 * the tag itself is irrelevant.)
79 #define TLV_TAG_END (0xEEEEEEEE)
82 /* Other special reserved tag values.
85 #define TLV_TAG_SKIP (0x00000000)
86 #define TLV_TAG_INVALID (0xFFFFFFFF)
89 /* TLV partition header.
91 * In a TLV partition, this must be the first item in the sequence, at offset
95 #define TLV_TAG_PARTITION_HEADER (0xEF10DA7A)
97 struct tlv_partition_header {
101 /* 0 indicates the default segment (always located at offset 0), while other values
102 * are for RFID-selectable presets that should immediately follow the default segment.
103 * The default segment may also have preset > 0, which means that it is a preset
104 * selected through an RFID command and copied by FW to the location at offset 0. */
107 uint32_t total_length;
111 /* TLV partition trailer.
113 * In a TLV partition, this must be the last item in the sequence, immediately
114 * preceding the TLV_TAG_END word.
117 #define TLV_TAG_PARTITION_TRAILER (0xEF101A57)
119 struct tlv_partition_trailer {
127 /* Appendable TLV partition header.
129 * In an appendable TLV partition, this must be the first item in the sequence,
130 * at offset 0. (Note that, unlike the configuration partitions, there is no
131 * trailer before the TLV_TAG_END word.)
134 #define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7)
136 struct tlv_appendable_partition_header {
144 /* ----------------------------------------------------------------------------
145 * Configuration items
146 * ----------------------------------------------------------------------------
150 /* NIC global capabilities.
153 #define TLV_TAG_GLOBAL_CAPABILITIES (0x00010000)
155 struct tlv_global_capabilities {
162 /* Siena-style per-port MAC address allocation.
164 * There are <count> addresses, starting at <base_address> and incrementing
165 * by adding <stride> to the low-order byte(s).
167 * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool
168 * of contiguous MAC addresses for the firmware to allocate as it sees fit.)
171 #define TLV_TAG_PORT_MAC(port) (0x00020000 + (port))
173 struct tlv_port_mac {
176 uint8_t base_address[6];
185 * This is the portion of VPD which is set at manufacturing time and not
186 * expected to change. It is formatted as a standard PCI VPD block. There are
187 * global and per-pf TLVs for this, the global TLV is new for Medford and is
188 * used in preference to the per-pf TLV.
191 #define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf))
193 struct tlv_pf_static_vpd {
199 #define TLV_TAG_GLOBAL_STATIC_VPD (0x001f0000)
201 struct tlv_global_static_vpd {
210 * This is the portion of VPD which may be changed (e.g. by firmware updates).
211 * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs
212 * for this, the global TLV is new for Medford and is used in preference to the
216 #define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf))
218 struct tlv_pf_dynamic_vpd {
224 #define TLV_TAG_GLOBAL_DYNAMIC_VPD (0x10200000)
226 struct tlv_global_dynamic_vpd {
233 /* "DBI" PCI config space changes.
235 * This is a set of edits made to the default PCI config space values before
236 * the device is allowed to enumerate. There are global and per-pf TLVs for
237 * this, the global TLV is new for Medford and is used in preference to the
241 #define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf))
248 uint16_t byte_enables;
254 #define TLV_TAG_GLOBAL_DBI (0x00210000)
256 struct tlv_global_dbi {
261 uint16_t byte_enables;
267 /* Partition subtype codes.
269 * A subtype may optionally be stored for each type of partition present in
270 * the NVRAM. For example, this may be used to allow a generic firmware update
271 * utility to select a specific variant of firmware for a specific variant of
274 * The description[] field is an optional string which is returned in the
275 * MC_CMD_NVRAM_METADATA response if present.
278 #define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type))
280 struct tlv_partition_subtype {
284 uint8_t description[];
288 /* Partition version codes.
290 * A version may optionally be stored for each type of partition present in
291 * the NVRAM. This provides a standard way of tracking the currently stored
292 * version of each of the various component images.
295 #define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type))
297 struct tlv_partition_version {
306 /* Global PCIe configuration */
308 #define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000)
310 struct tlv_pcie_config {
313 int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */
314 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
315 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
316 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
317 #define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */
318 #define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */
321 /* Per-PF configuration. Note that not all these fields are necessarily useful
322 * as the apertures are constrained by the BIU settings (the one case we do
323 * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can
324 * tidy things up later */
326 #define TLV_TAG_PF_PCIE_CONFIG(pf) (0x10080000 + (pf))
328 struct tlv_per_pf_pcie_config {
332 uint8_t port_allocation;
333 uint16_t vectors_per_pf;
334 uint16_t vectors_per_vf;
335 uint8_t pf_bar0_aperture;
336 uint8_t pf_bar2_aperture;
337 uint8_t vf_bar0_aperture;
339 uint16_t supp_pagesz;
340 uint16_t msix_vec_base;
344 /* Development ONLY. This is a single TLV tag for all the gubbins
345 * that can be set through the MC command-line other than the PCIe
346 * settings. This is a temporary measure. */
347 #define TLV_TAG_TMP_GUBBINS (0x10090000) /* legacy symbol - do not use */
348 #define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS
350 struct tlv_tmp_gubbins {
353 /* Consumed by dpcpu.c */
354 uint64_t tx0_tags; /* Bitmap */
355 uint64_t tx1_tags; /* Bitmap */
356 uint64_t dl_tags; /* Bitmap */
358 #define TLV_DPCPU_TX_STRIPE (1) /* No longer used, has no effect */
359 #define TLV_DPCPU_BIU_TAGS (2) /* Use BIU tag manager */
360 #define TLV_DPCPU_TX0_TAGS (4) /* tx0_tags is valid */
361 #define TLV_DPCPU_TX1_TAGS (8) /* tx1_tags is valid */
362 #define TLV_DPCPU_DL_TAGS (16) /* dl_tags is valid */
363 /* Consumed by features.c */
364 uint32_t dut_features; /* All 1s -> leave alone */
365 int8_t with_rmon; /* 0 -> off, 1 -> on, -1 -> leave alone */
366 /* Consumed by clocks_hunt.c */
367 int8_t clk_mode; /* 0 -> off, 1 -> on, -1 -> leave alone */
368 /* No longer used, superseded by TLV_TAG_DESCRIPTOR_CACHE_CONFIG. */
369 int8_t rx_dc_size; /* -1 -> leave alone */
371 int16_t num_q_allocs;
374 /* Global port configuration
376 * This is now deprecated in favour of a platform-provided default
377 * and dynamic config override via tlv_global_port_options.
379 #define TLV_TAG_GLOBAL_PORT_CONFIG (0x000a0000)
381 struct tlv_global_port_config {
384 uint32_t ports_per_core;
385 uint32_t max_port_speed;
391 * This is intended for user-configurable selection of optional firmware
392 * features and variants.
394 * Initially, this consists only of the satellite CPU firmware variant
395 * selection, but this tag could be extended in the future (using the
396 * tag length to determine whether additional fields are present).
399 #define TLV_TAG_FIRMWARE_OPTIONS (0x100b0000)
401 struct tlv_firmware_options {
404 uint32_t firmware_variant;
405 #define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff)
407 /* These are the values for overriding the driver's choice; the definitions
408 * are taken from MCDI so that they don't get out of step. Include
409 * <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if
410 * you need to use these constants.
412 #define TLV_FIRMWARE_VARIANT_FULL_FEATURED MC_CMD_FW_FULL_FEATURED
413 #define TLV_FIRMWARE_VARIANT_LOW_LATENCY MC_CMD_FW_LOW_LATENCY
414 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM MC_CMD_FW_PACKED_STREAM
415 #define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE MC_CMD_FW_HIGH_TX_RATE
416 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \
417 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1
418 #define TLV_FIRMWARE_VARIANT_RULES_ENGINE MC_CMD_FW_RULES_ENGINE
419 #define TLV_FIRMWARE_VARIANT_DPDK MC_CMD_FW_DPDK
420 #define TLV_FIRMWARE_VARIANT_L3XUDP MC_CMD_FW_L3XUDP
425 * Intended for boards with A0 silicon where the core voltage may
426 * need tweaking. Most likely set once when the pass voltage is
429 #define TLV_TAG_0V9_SETTINGS (0x000c0000)
431 struct tlv_0v9_settings {
434 uint16_t flags; /* Boards with high 0v9 settings may need active cooling */
435 #define TLV_TAG_0V9_REQUIRES_FAN (1)
436 uint16_t target_voltage; /* In millivolts */
437 /* Since the limits are meant to be centred to the target (and must at least
438 * contain it) they need setting as well. */
439 uint16_t warn_low; /* In millivolts */
440 uint16_t warn_high; /* In millivolts */
441 uint16_t panic_low; /* In millivolts */
442 uint16_t panic_high; /* In millivolts */
446 /* Clock configuration */
448 #define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */
449 #define TLV_TAG_CLOCK_CONFIG_HUNT TLV_TAG_CLOCK_CONFIG
451 struct tlv_clock_config {
454 uint16_t clk_sys; /* MHz */
455 uint16_t clk_dpcpu; /* MHz */
456 uint16_t clk_icore; /* MHz */
457 uint16_t clk_pcs; /* MHz */
460 #define TLV_TAG_CLOCK_CONFIG_MEDFORD (0x00100000)
462 struct tlv_clock_config_medford {
465 uint16_t clk_sys; /* MHz */
466 uint16_t clk_mc; /* MHz */
467 uint16_t clk_rmon; /* MHz */
468 uint16_t clk_vswitch; /* MHz */
469 uint16_t clk_dpcpu; /* MHz */
470 uint16_t clk_pcs; /* MHz */
474 /* EF10-style global pool of MAC addresses.
476 * There are <count> addresses, starting at <base_address>, which are
477 * contiguous. Firmware is responsible for allocating addresses from this
478 * pool to ports / PFs as appropriate.
481 #define TLV_TAG_GLOBAL_MAC (0x000e0000)
483 struct tlv_global_mac {
486 uint8_t base_address[6];
492 #define TLV_TAG_ATB_0V9_TARGET (0x000f0000) /* legacy symbol - do not use */
493 #define TLV_TAG_ATB_0V9_TARGET_HUNT TLV_TAG_ATB_0V9_TARGET
495 /* The target value for the 0v9 power rail measured on-chip at the
496 * analogue test bus */
497 struct tlv_0v9_atb_target {
504 /* Factory settings for amplitude calibration of the PCIE TX serdes */
505 #define TLV_TAG_TX_PCIE_AMP_CONFIG (0x00220000)
506 struct tlv_pcie_tx_amp_config {
509 uint8_t quad_tx_imp2k[4];
510 uint8_t quad_tx_imp50[4];
511 uint8_t lane_amp[16];
515 /* Global PCIe configuration, second revision. This represents the visible PFs
516 * by a bitmap rather than having the number of the highest visible one. As such
517 * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG
518 * can and it should be used in place of that tag in future (but compatibility with
519 * the old tag will be left in the firmware indefinitely). */
521 #define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000)
523 struct tlv_pcie_config_r2 {
526 uint16_t visible_pfs; /**< Bitmap of visible PFs */
527 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
528 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
529 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
532 /* Dynamic port mode.
534 * Allows selecting alternate port configuration for platforms that support it
535 * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the
536 * number of externally visible ports (and, hence, PF to port mapping), so must
537 * be done at boot time.
539 * Port mode naming convention is
541 * [nports_on_cage0]x[port_lane_width]_[nports_on_cage1]x[port_lane_width]
543 * Port lane width determines the capabilities (speeds) of the ports, subject
544 * to architecture capabilities (e.g. 25G support) and switch bandwidth
546 * - single lane ports can do 25G/10G/1G
547 * - dual lane ports can do 50G/25G/10G/1G (with fallback to 1 lane)
548 * - quad lane ports can do 100G/40G/50G/25G/10G/1G (with fallback to 2 or 1 lanes)
550 * This tag supercedes tlv_global_port_config.
553 #define TLV_TAG_GLOBAL_PORT_MODE (0x10110000)
555 struct tlv_global_port_mode {
559 #define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */
561 /* Huntington port modes */
562 #define TLV_PORT_MODE_10G (0)
563 #define TLV_PORT_MODE_40G (1)
564 #define TLV_PORT_MODE_10G_10G (2)
565 #define TLV_PORT_MODE_40G_40G (3)
566 #define TLV_PORT_MODE_10G_10G_10G_10G (4)
567 #define TLV_PORT_MODE_40G_10G_10G (6)
568 #define TLV_PORT_MODE_10G_10G_40G (7)
570 /* Medford (and later) port modes */
571 #define TLV_PORT_MODE_1x1_NA (0) /* Single 10G/25G on mdi0 */
572 #define TLV_PORT_MODE_1x4_NA (1) /* Single 100G/40G on mdi0 */
573 #define TLV_PORT_MODE_NA_1x4 (22) /* Single 100G/40G on mdi1 */
574 #define TLV_PORT_MODE_1x2_NA (10) /* Single 50G on mdi0 */
575 #define TLV_PORT_MODE_NA_1x2 (11) /* Single 50G on mdi1 */
576 #define TLV_PORT_MODE_1x1_1x1 (2) /* Single 10G/25G on mdi0, single 10G/25G on mdi1 */
577 #define TLV_PORT_MODE_1x4_1x4 (3) /* Single 40G on mdi0, single 40G on mdi1 */
578 #define TLV_PORT_MODE_2x1_2x1 (5) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 */
579 #define TLV_PORT_MODE_4x1_NA (4) /* Quad 10G/25G on mdi0 */
580 #define TLV_PORT_MODE_NA_4x1 (8) /* Quad 10G/25G on mdi1 */
581 #define TLV_PORT_MODE_1x4_2x1 (6) /* Single 40G on mdi0, dual 10G/25G on mdi1 */
582 #define TLV_PORT_MODE_2x1_1x4 (7) /* Dual 10G/25G on mdi0, single 40G on mdi1 */
583 #define TLV_PORT_MODE_1x2_1x2 (12) /* Single 50G on mdi0, single 50G on mdi1 */
584 #define TLV_PORT_MODE_2x2_NA (13) /* Dual 50G on mdi0 */
585 #define TLV_PORT_MODE_NA_2x2 (14) /* Dual 50G on mdi1 */
586 #define TLV_PORT_MODE_1x4_1x2 (15) /* Single 40G on mdi0, single 50G on mdi1 */
587 #define TLV_PORT_MODE_1x2_1x4 (16) /* Single 50G on mdi0, single 40G on mdi1 */
588 #define TLV_PORT_MODE_1x2_2x1 (17) /* Single 50G on mdi0, dual 10G/25G on mdi1 */
589 #define TLV_PORT_MODE_2x1_1x2 (18) /* Dual 10G/25G on mdi0, single 50G on mdi1 */
591 /* Snapper-only Medford2 port modes.
592 * These modes are eftest only, to allow snapper explicit
593 * selection between multi-channel and LLPCS. In production,
594 * this selection is automatic and outside world should not
597 #define TLV_PORT_MODE_2x1_2x1_LL (19) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1, low-latency PCS */
598 #define TLV_PORT_MODE_4x1_NA_LL (20) /* Quad 10G/25G on mdi0, low-latency PCS */
599 #define TLV_PORT_MODE_NA_4x1_LL (21) /* Quad 10G/25G on mdi1, low-latency PCS */
600 #define TLV_PORT_MODE_1x1_NA_LL (23) /* Single 10G/25G on mdi0, low-latency PCS */
601 #define TLV_PORT_MODE_1x1_1x1_LL (24) /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */
602 #define TLV_PORT_MODE_BUG63720_DO_NOT_USE (9) /* bug63720: Do not use */
603 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
605 /* Deprecated Medford aliases - DO NOT USE IN NEW CODE */
606 #define TLV_PORT_MODE_10G_10G_10G_10G_Q (5)
607 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1 (4)
608 #define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8)
609 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 (9)
611 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
614 /* Type of the v-switch created implicitly by the firmware */
616 #define TLV_TAG_VSWITCH_TYPE(port) (0x10120000 + (port))
618 struct tlv_vswitch_type {
621 uint32_t vswitch_type;
622 #define TLV_VSWITCH_TYPE_DEFAULT (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */
623 #define TLV_VSWITCH_TYPE_NONE (0)
624 #define TLV_VSWITCH_TYPE_VLAN (1)
625 #define TLV_VSWITCH_TYPE_VEB (2)
626 #define TLV_VSWITCH_TYPE_VEPA (3)
627 #define TLV_VSWITCH_TYPE_MUX (4)
628 #define TLV_VSWITCH_TYPE_TEST (5)
631 /* A VLAN tag for the v-port created implicitly by the firmware */
633 #define TLV_TAG_VPORT_VLAN_TAG(pf) (0x10130000 + (pf))
635 struct tlv_vport_vlan_tag {
639 #define TLV_VPORT_NO_VLAN_TAG (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */
642 /* Offset to be applied to the 0v9 setting, wherever it came from */
644 #define TLV_TAG_ATB_0V9_OFFSET (0x10140000)
646 struct tlv_0v9_atb_offset {
649 int16_t offset_millivolts;
653 /* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port).
654 * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583.
655 * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while
656 * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default:
657 * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */
659 #define TLV_TAG_PRIVILEGE_MASK (0x10150000) /* legacy symbol - do not use */
661 struct tlv_privilege_mask { /* legacy structure - do not use */
664 uint32_t privilege_mask;
667 #define TLV_TAG_PRIVILEGE_MASK_ADD (0x10150000)
669 struct tlv_privilege_mask_add {
672 uint32_t privilege_mask_add;
675 #define TLV_TAG_PRIVILEGE_MASK_REM (0x10160000)
677 struct tlv_privilege_mask_rem {
680 uint32_t privilege_mask_rem;
683 /* Additional privileges given to all PFs.
684 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
686 #define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS (0x10190000)
688 struct tlv_privilege_mask_add_all_pfs {
691 uint32_t privilege_mask_add;
694 /* Additional privileges given to a selected PF.
695 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
697 #define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf) (0x101A0000 + (pf))
699 struct tlv_privilege_mask_add_single_pf {
702 uint32_t privilege_mask_add;
705 /* Turning on/off the PFIOV mode.
706 * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */
708 #define TLV_TAG_PFIOV(port) (0x10170000 + (port))
714 #define TLV_PFIOV_OFF (0) /* Default */
715 #define TLV_PFIOV_ON (1)
718 /* Multicast filter chaining mode selection.
720 * When enabled, multicast packets are delivered to all recipients of all
721 * matching multicast filters, with the exception that IP multicast filters
722 * will steal traffic from MAC multicast filters on a per-function basis.
725 * When disabled, multicast packets will always be delivered only to the
726 * recipients of the highest priority matching multicast filter.
727 * (Legacy behaviour.)
729 * The DEFAULT mode (which is the same as the tag not being present at all)
730 * is equivalent to ENABLED in production builds, and DISABLED in eftest
733 * This option is intended to provide run-time control over this feature
734 * while it is being stabilised and may be withdrawn at some point in the
735 * future; the new behaviour is intended to become the standard behaviour.
738 #define TLV_TAG_MCAST_FILTER_CHAINING (0x10180000)
740 struct tlv_mcast_filter_chaining {
744 #define TLV_MCAST_FILTER_CHAINING_DEFAULT (0xffffffff)
745 #define TLV_MCAST_FILTER_CHAINING_DISABLED (0)
746 #define TLV_MCAST_FILTER_CHAINING_ENABLED (1)
749 /* Pacer rate limit per PF */
750 #define TLV_TAG_RATE_LIMIT(pf) (0x101b0000 + (pf))
752 struct tlv_rate_limit {
758 /* OCSD Enable/Disable
760 * This setting allows OCSD to be disabled. This is a requirement for HP
761 * servers to support PCI passthrough for virtualization.
763 * The DEFAULT mode (which is the same as the tag not being present) is
764 * equivalent to ENABLED.
766 * This option is not used by the MCFW, and is entirely handled by the various
767 * drivers that support OCSD, by reading the setting before they attempt
770 * bit0: OCSD Disabled/Enabled
773 #define TLV_TAG_OCSD (0x101C0000)
779 #define TLV_OCSD_DISABLED 0
780 #define TLV_OCSD_ENABLED 1 /* Default */
783 /* Descriptor cache config.
785 * Sets the sizes of the TX and RX descriptor caches as a power of 2. It also
786 * sets the total number of VIs. When the number of VIs is reduced VIs are taken
787 * away from the highest numbered port first, so a vi_count of 1024 means 1024
788 * VIs on the first port and 0 on the second (on a Torino).
791 #define TLV_TAG_DESCRIPTOR_CACHE_CONFIG (0x101d0000)
793 struct tlv_descriptor_cache_config {
796 uint8_t rx_desc_cache_size;
797 uint8_t tx_desc_cache_size;
800 #define TLV_DESC_CACHE_DEFAULT (0xff)
801 #define TLV_VI_COUNT_DEFAULT (0xffff)
803 /* RX event merging config (read batching).
805 * Sets the global maximum number of events for the merging bins, and the
806 * global timeout configuration for the bins.
809 #define TLV_TAG_RX_EVENT_MERGING_CONFIG (0x101e0000)
811 struct tlv_rx_event_merging_config {
815 #define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
818 #define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
819 #define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
821 #define TLV_TAG_PCIE_LINK_SETTINGS (0x101f0000)
822 struct tlv_pcie_link_settings {
825 uint16_t gen; /* Target PCIe generation: 1, 2, 3 */
826 uint16_t width; /* Number of lanes */
829 /* TX event merging config.
831 * Sets the global maximum number of events for the merging bins, and the
832 * global timeout configuration for the bins, and the global timeout for
835 #define TLV_TAG_TX_EVENT_MERGING_CONFIG (0x10210000)
836 struct tlv_tx_event_merging_config {
840 #define TLV_TX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
842 uint32_t qempty_timeout_ns; /* Medford only */
844 #define TLV_TX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
845 #define TLV_TX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
846 #define TLV_TX_EVENT_MERGING_QEMPTY_TIMEOUT_NS_DEFAULT (0xffffffff)
848 #define TLV_TAG_LICENSE (0x30800000)
850 typedef struct tlv_license {
856 /* TSA NIC IP address configuration (DEPRECATED)
858 * Sets the TSA NIC IP address statically via configuration tool or dynamically
859 * via DHCP via snooping based on the mode selection (0=Static, 1=DHCP, 2=Snoop)
861 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
862 * be moved to a private partition during TSA development. It is not used in any
866 #define TLV_TAG_TMP_TSAN_CONFIG (0x10220000) /* DEPRECATED */
868 #define TLV_TSAN_IP_MODE_STATIC (0)
869 #define TLV_TSAN_IP_MODE_DHCP (1)
870 #define TLV_TSAN_IP_MODE_SNOOP (2)
871 typedef struct tlv_tsan_config {
879 uint32_t bind_retry; /* DEPRECATED */
880 uint32_t bind_bkout; /* DEPRECATED */
883 /* TSA Controller IP address configuration (DEPRECATED)
885 * Sets the TSA Controller IP address statically via configuration tool
887 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
888 * be moved to a private partition during TSA development. It is not used in any
892 #define TLV_TAG_TMP_TSAC_CONFIG (0x10230000) /* DEPRECATED */
894 #define TLV_MAX_TSACS (4)
895 typedef struct tlv_tsac_config {
899 uint32_t ip[TLV_MAX_TSACS];
900 uint32_t port[TLV_MAX_TSACS];
903 /* Binding ticket (DEPRECATED)
905 * Sets the TSA NIC binding ticket used for binding process between the TSA NIC
906 * and the TSA Controller
908 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
909 * be moved to a private partition during TSA development. It is not used in any
913 #define TLV_TAG_TMP_BINDING_TICKET (0x10240000) /* DEPRECATED */
915 typedef struct tlv_binding_ticket {
919 } tlv_binding_ticket_t;
921 /* Solarflare private key (DEPRECATED)
923 * Sets the Solareflare private key used for signing during the binding process
925 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
926 * be moved to a private partition during TSA development. It is not used in any
930 #define TLV_TAG_TMP_PIK_SF (0x10250000) /* DEPRECATED */
932 typedef struct tlv_pik_sf {
938 /* CA root certificate (DEPRECATED)
940 * Sets the CA root certificate used for TSA Controller verfication during
941 * TLS connection setup between the TSA NIC and the TSA Controller
943 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
944 * be moved to a private partition during TSA development. It is not used in any
948 #define TLV_TAG_TMP_CA_ROOT_CERT (0x10260000) /* DEPRECATED */
950 typedef struct tlv_ca_root_cert {
954 } tlv_ca_root_cert_t;
956 /* Tx vFIFO Low latency configuration
958 * To keep the desired booting behaviour for the switch, it just requires to
959 * know if the low latency mode is enabled.
962 #define TLV_TAG_TX_VFIFO_ULL_MODE (0x10270000)
963 struct tlv_tx_vfifo_ull_mode {
967 #define TLV_TX_VFIFO_ULL_MODE_DEFAULT 0
972 * Medford2 tag for selecting VI window decode (see values below)
974 #define TLV_TAG_BIU_VI_WINDOW_MODE (0x10280000)
975 struct tlv_biu_vi_window_mode {
979 #define TLV_BIU_VI_WINDOW_MODE_8K 0 /* 8k per VI, CTPIO not mapped, medford/hunt compatible */
980 #define TLV_BIU_VI_WINDOW_MODE_16K 1 /* 16k per VI, CTPIO mapped */
981 #define TLV_BIU_VI_WINDOW_MODE_64K 2 /* 64k per VI, CTPIO mapped, POWER-friendly */
986 * Medford2 tag for configuring the FastPD mode (see values below)
988 #define TLV_TAG_FASTPD_MODE(port) (0x10290000 + (port))
989 struct tlv_fastpd_mode {
993 #define TLV_FASTPD_MODE_SOFT_ALL 0 /* All packets to the SoftPD */
994 #define TLV_FASTPD_MODE_FAST_ALL 1 /* All packets to the FastPD */
995 #define TLV_FASTPD_MODE_FAST_SUPPORTED 2 /* Supported packet types to the FastPD; everything else to the SoftPD */
998 /* L3xUDP datapath firmware UDP port configuration
1000 * Sets the list of UDP ports on which the encapsulation will be handled.
1001 * The number of ports in the list is implied by the length of the TLV item.
1003 #define TLV_TAG_L3XUDP_PORTS (0x102a0000)
1004 struct tlv_l3xudp_ports {
1008 #define TLV_TAG_L3XUDP_PORTS_MAX_NUM_PORTS 16
1011 #endif /* CI_MGMT_TLV_LAYOUT_H */